AD7495BR_技术文档

1 MSPS,

12-Bit ADCs

a

AD7475/AD7495

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Fast Throughput Rate: 1 MSPS

Specified for V_DDof 2.7 V to 5.25 V

Low Power:

4.5 mW Max at 1 MSPS with 3 V Supplies

10.5 mW Max at 1 MSPS with 5 V Supplies

Wide Input Bandwidth:

V

DD

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

V

IN

REF IN

68 dB SNR at 300 kHz Input Frequency

Flexible Power/Serial Clock Speed Management

No Pipeline Delays

High-Speed Serial Interface SPI™/QSPI™/

MICROWIRE™/DSP-Compatible

On-Board Reference 2.5 V (AD7495 Only)

Standby Mode: 1 ␮A Max

SCLK

SDATA

CS

CONTROL

LOGIC

V

DRIVE

AD7475

8-Lead ␮SOIC and SOIC Packages

GND

V

APPLICATIONS

DD

Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications

Instrumentation and Control Systems

Data Acquisition Systems

High-Speed Modems

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

T/H

V

IN

REF OUT

BUF

SCLK

SDATA

CS

Optical Sensors

CONTROL

LOGIC

2.5V

REFERENCE

GENERAL DESCRIPTION

V

DRIVE

The AD7475/AD7495 are 12-bit high-speed, low-power,

successive-approximation ADCs. The parts operate from a single

2.7 V to 5.25 V power supply and feature throughput rates up to

1 MSPS. The parts contain a low-noise, wide bandwidth track/hold

amplifier that can handle input frequencies in excess of 1 MHz.

AD7495

GND

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption. The

The conversion process and data acquisition are controlled using

CS and the serial clock allowing the devices to interface with

microprocessors or DSPs. The input signal is sampled on the

falling edge of CS and conversion is also initiated at this point.

There are no pipelined delays associated with the part.

AD7475 offers 1 MSPS throughput rates with 4.5 mW

power consumption.

2. Single-supply operation with V_DRIVEfunction. The AD7475/

AD7495 operate from a single 2.7 V to 5.25 V supply. The

V

_DRIVEfunction allows the serial interface to connect directly

The AD7475/AD7495 use advanced design techniques to achieve

very low power dissipation at high throughput rates. With 3 V

supplies and 1 MSPS throughput rate, the AD7475 consumes just

1.5 mA, while the AD7495 consumes 2 mA. With 5 V supplies

and 1 MSPS, the current consumption is 2.1 mA for the AD7475

and 2.6 mA for the AD7495.

to either 3 V or 5 V processor systems independent of V_DD

.

3. Flexible power/serial clock speed management. The con-

version rate is determined by the serial clock, allowing the

conversion time to be reduced through the serial clock speed

increase. The part also features shutdown modes to maximize

power efficiency at lower throughput rates. This allows the

average power consumption to be reduced while not convert-

ing. Power consumption is 1 µA when in full shutdown.

The analog input range for the part is 0 V to REF IN. The 2.5 V

reference for the AD7475 is applied externally to the REF IN pin

while the AD7495 has an on-board 2.5 V reference. The conver-

sion time is determined by the SCLK frequency.

4. No pipeline delay. The part features a standard successive-

approximation ADC with accurate control of the sampling

instant via a CS input and once off conversion control.

MICROWIRE is a trademark of National Semiconductor Corporation.

SPI and QSPI are trademarks of Motorola, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD7475/AD7495–SPECIFICATIONS¹

(V_DD= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, REF IN = 2.5 V, f_SCLK= 20 MHz unless otherwise

noted; T_A= T_MINto T_MAX, unless otherwise noted.)

AD7475–SPECIFICATIONS¹

Parameter

A Version¹

B Version¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio

(SINAD)

Total Harmonic Distortion (THD) –75

Peak Harmonic or Spurious Noise

(SFDR)

68

dB min

f_IN= 300 kHz Sine Wave, f_SAMPLE= 1 MSPS

–75

–76

dB max

f_IN= 300 kHz Sine Wave, f_SAMPLE= 1 MSPS

_IN= 300 kHz Sine Wave, f_SAMPLE= 1 MSPS

–76

f

Intermodulation Distortion (IMD)

Second Order Terms

Third Order Terms

Aperture Delay

–78

10

–78

10

dB typ

ns typ

Aperture Jitter

50

ps typ

Full Power Bandwidth

8.3

1.3

8.3

1.3

MHz typ

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

Integral Nonlinearity

12

1.5

0.5

+1.5/–0.9

12

1

0.5

+1.5/–0.9

Bits

LSB max

LSB typ

LSB max

@ 5 V (typ @ 3 V)

@ 25°C

Differential Nonlinearity

@ 5 V Guaranteed No Missed Codes to 12 Bits

(typ @ 3 V)

@ 25°C

Typically 2.5 LSB

0.5

8

3

0.5

8

3

LSB typ

LSB max

Offset Error

Gain Error

ANALOG INPUT

Input Voltage Ranges

DC Leakage Current

Input Capacitance

0 to REF IN

Volts

µA max

pF typ

1

20

1

20

REFERENCE INPUT

REF IN Input Voltage Range

DC Leakage Current

Input Capacitance

2.5

1

20

2.5

1

20

Volts

µA max

pF typ

1% for Specified Performance

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

V_DRIVE– 1

0.4

1

V_DRIVE– 1

0.4

1

V min

V max

µA max

pF max

Typically 10 nA, V_IN= 0 V or V_DRIVE

2

Input Capacitance, C_IN

10

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

V_DRIVE– 0.2

V min

I_SOURCE= 200 µA; V_DRIVE= 2.7 V to 5.25 V

I_SINK= 200 µA

0.4

10

0.4

10

V max

µA max

pF max

Floating-State Output Capacitance²10

Output Coding

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time

800

300

325

1

ns max

16 SCLK Cycles with SCLK at 20 MHz

Sine Wave Input

Full-Scale Step Input

300

325

1

Throughput Rate

MSPS max See Serial Interface Section

POWER REQUIREMENTS

V_DD

2.7/5.25

V min/max

V_DRIVE

3

I_DD

Digital I/Ps = 0 V or V_DRIVE

V_DD= 2.7 V to 5.25 V. SCLK On or Off

Normal Mode (Static)

Normal Mode (Operational)

750

2.1

1.5

450

100

1

750

2.1

1.5

450

100

1

ꢀA typ

mA max

µA typ

µA max

V

_DD= 4.75 V to 5.25 V. f_SAMPLE= 1 MSPS

_DD= 2.7 V to 3.6 V. f_SAMPLE= 1 MSPS

Partial Power-Down Mode

Full Power-Down Mode

f_SAMPLE= 100 kSPS

(Static)

SCLK On or Off

–2–

REV. A

AD7475/AD7495

AD7475–SPECIFICATIONS (continued)

Parameter

A Version¹

B Version¹

Unit

Test Conditions/Comments

POWER REQUIREMENTS

(continued)

Power Dissipation³

Normal Mode (Operational)

10.5

4.5

500

300

5

10.5

4.5

500

300

5

mW max

ꢀW max

V_DD= 5 V. f_SAMPLE= 1 MSPS

V_DD= 3 V. f_SAMPLE= 1 MSPS

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

Partial Power-Down (Static)

Full Power-Down

3

NOTES

¹Temperature ranges as follows: A, B Versions: –40ꢁC to +85ꢁC.

²Sample tested @ 25ꢁC to ensure compliance.

³See Power Versus Throughput Rate section.

Specifications subject to change without notice.

(V_DD= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, f_SCLK= 20 MHz unless otherwise noted; T_A= T_MINto

T_MAX, unless otherwise noted.)

AD7495–SPECIFICATIONS¹

Parameter

A Version¹

B Version¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion

(SINAD)

Total Harmonic Distortion (THD) –75

Peak Harmonic or Spurious Noise –76

(SFDR)

68

dB min

f_IN= 300 kHz Sine Wave, f_SAMPLE= 1 MSPS

–75

–76

dB max

f_IN= 300 kHz Sine Wave, f_SAMPLE= 1 MSPS

Intermodulation Distortion (IMD)

Second Order Terms

Third Order Terms

Aperture Delay

–78

10

–78

10

dB typ

ns typ

Aperture Jitter

Full Power Bandwidth

50

8.3

1.3

50

8.3

1.3

ps typ

MHz typ

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

Integral Nonlinearity

12

1.5

0.5

+1.5/–0.9

12

1

0.5

+1.5/–0.9

Bits

LSB max

LSB typ

LSB max

@ 5 V (typ @ 3 V)

@ 25°C

@ 5 V Guaranteed No Missed Codes to 12 Bits

(typ @ 3 V)

Differential Nonlinearity

0.6

8

7

0.6

8

7

LSB typ

LSB max

@ 25°C

Typically 2.5 LSB

Offset Error

Gain Error

ANALOG INPUT

Input Voltage Ranges

DC Leakage Current

Input Capacitance

0 to 2.5

1

20

0 to 2.5

1

20

Volts

µA max

pF typ

REFERENCE OUTPUT

REF OUT Output Voltage

REF OUT Impedance

2.4625/2.5375 2.4625/2.5375 V min/max

10

50

Ω typ

ppm/ꢁC typ

REF OUT Temperature Coefficient 50

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

V_DRIVE– 1

0.4

1

V_DRIVE– 1

0.4

1

V min

V max

µA max

pF max

Typically 10 nA, V_IN= 0 V or V_DRIVE

2

Input Capacitance, C_IN

10

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

V_DRIVE– 0.2

0.4

10

Straight (Natural) Binary

V min

I_SOURCE= 200 µA; V_DD= 2.7 V to 5.25 V

I_SINK= 200 µA

0.4

10

V max

µA max

pF max

Floating-State Output Capacitance²10

Output Coding

REV. A

–3–

AD7475/AD7495–SPECIFICATIONS¹

AD7495–SPECIFICATIONS (continued)

Parameter

A Version¹

B Version¹

Unit

Test Conditions/Comments

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time

800

300

325

1

800

300

325

1

ns max

16 SCLK Cycles with SCLK at 20 MHz

Sine Wave Input

Full-Scale Step Input

Throughput Rate

MSPS max See Serial Interface Section

POWER REQUIREMENTS

V_DD

V_DRIVE

2.7/5.25

V min/max

I_DD

Digital I/Ps = 0 V or V_DRIVE

Normal Mode (Static)

Normal Mode (Operational)

1

2.6

2

650

230

1

2.6

2

650

230

1

mA typ

mA max

µA typ

µA max

V_DD= 2.7 V to 5.25 V. SCLK On or Off

V_DD= 4.75 V to 5.25 V. f_SAMPLE= 1 MSPS

V_DD= 2.7 V to 3.6 V. f_SAMPLE= 1 MSPS

f_SAMPLE= 100 kSPS

(Static)

(Static) SCLK On or Off

Partial Power-Down Mode

Full Power-Down Mode

Power Dissipation³

Normal Mode (Operational)

13

6

1.15

690

5

13

6

1.15

690

5

mW max

µW max

V_DD= 5 V. f_SAMPLE= 1 MSPS

V_DD= 3 V. f_SAMPLE= 1 MSPS

Partial Power-Down (Static)

Full Power-Down

V

_DD= 5 V

_DD= 3 V

V_DD= 5 V

V_DD= 3 V

3

NOTES

¹Temperature ranges as follows: A, B Versions: –40ꢁC to +85ꢁC.

²Sample tested @ 25ꢁC to ensure compliance.

³See Power Versus Throughput Rate section.

Specifications subject to change without notice.

(V_DD= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475); T_A= T_MINto T_MAX, unless

otherwise noted.)

TIMING SPECIFICATIONS¹

Limit at T_MIN, T_MAX

AD7475/AD7495

Parameter

Unit

Description

2

f_SCLK

10

kHz min

20

MHz max

t_CONVERT

16 × t_SCLK

800

100

10

22

40

0.4 t_SCLK

10

45

t_SCLK= 1/f_SCLK

f_SCLK= 20 MHz

Minimum Quiet Time Required between Conversions

CS to SCLK Setup Time

Delay from CS Until SDATA 3-State Disabled

Data Access Time after SCLK Falling Edge

SCLK Low Pulsewidth

SCLK High Pulsewidth

SCLK to Data Valid Hold Time

SCLK Falling Edge to SDATA High Impedance

CS Rising Edge to SDATA High Impedance

Power-Up Time from Full Power-Down AD7475

Power-Up Time from Full Power-Down AD7495

ns max

ns min

ns max

ns min

ns max

µs max

t_QUIET

t₂₃

t₃₃

t₄

t₅

t₆

t₇₄

t₈

4

t₉

20

650

t_POWER-UP

NOTES

¹Sample tested at 25ꢁC to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DRIVE) and timed from a voltage level of 1.6 V.

²Mark/Space ratio for the SCLK input is 40/60 to 60/40.

³Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V.

⁴t₈and t₉are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t₈and t₉, quoted in the timing characteristics are

the true bus relinquish time of the part and are independent of the bus loading.

Specifications subject to change without notice.

–4–

REV. A

AD7475/AD7495

CS

t_CONVERT

t₆

t₂

B

3

4

5

1

2

13

15

t₈

DB0

16

14

t₅

SCLK

t₇

DB10

t_QUIET

t₄

DB11

t₃

0

SDATA

DB2

DB1

THREE-STATE

FOUR LEADING ZEROS

Figure 1. Serial Interface Timing Diagram

Timing Example 1

With t₂= 10 ns min, this leaves t_acqto be 664 ns. This 664 ns

satisfies the requirement of 300 ns for t_ACQ. From Figure 2, t_ACQ

is comprised of 2.5(1/f_SCLK) + t₈+ t_QUIET, t₈= 45 ns. This allows

a value of 119 ns for t_QUIETsatisfying the minimum requirement

of 100 ns. As in this example and with other slower clock values,

the signal may already be acquired before the conversion is

complete, but it is still necessary to leave 100 ns minimum

t_QUIETbetween conversions. In Example 2 the signal should be

fully acquired at approximately Point C in Figure 2.

Having f_SCLK= 20 MHz and a throughput of 1 MSPS gives a cycle

time of t₂+ 12.5(1/f_SCLK) + t_ACQ= 1 µs. With t₂= 10 ns min, this

leaves t_ACQto be 365 ns. This 365 ns satisfies the requirement of

300 ns for t_ACQ. From Figure 2, t_ACQcomprises of 2.5(1/f_SCLK) + t₈

+ t_QUIET, where t₈= 45 ns. This allows a value of 195 ns for t_QUIET

satisfying the minimum requirement of 100 ns.

,

Timing Example 2

Having f_SCLK= 5 MHz and a throughput of 315 KSPS, gives a

cycle time of t₂+ 12.5(1/f_SCLK) + t_ACQ= 3.174 ꢀs.

CS

t_CONVERT

t₆

t₂

B

C

3

4

5

1

2

13

14

t₅

15

16

SCLK

t₈

t_QUIET

45ns

12.5 (1/f

)

SCLK

t_ACQUISITION

10ns

1/THROUGHPUT

Figure 2. Serial Interface Timing Example

200␮A

I

OL

TO OUTPUT

1.6V

C

L

50pF

200␮A

I

OH

Figure 3. Load Circuit for Digital Output Timing Specifications

REV. A

–5–

AD7475/AD7495

ABSOLUTE MAXIMUM RATINGS¹

PIN CONFIGURATIONS

(T_A= 25ꢁC unless otherwise noted)

AD7475 SOIC/␮SOIC

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

_DRIVEto GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

1

2

3

4

8

7

6

5

REF IN

V

DD

AD7475

TOP VIEW

(Not to Scale)

V

CS

IN

V

_DRIVEto DV_DD. . . . . . . . . . . . . . . . . –0.3 V to DV_DD+ 0.3 V

GND

V

DRIVE

Digital Output Voltage to GND . . . . . . –0.3 V to V_DD+ 0.3 V

REF IN to GND . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Input Current to Any Pin Except Supplies². . . . . . . ꢂ10 mA

Operating Temperature Range

SCLK

SDATA

Commercial (A, B Version) . . . . . . . . . . . . –40ꢁC to +85ꢁC

Storage Temperature Range . . . . . . . . . . . –65ꢁC to +150ꢁC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150ꢁC

SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW

ꢃ_JAThermal Impedance . . . . . . . . . . . . . . 157ꢁC/W (SOIC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9ꢁC/W (µSOIC)

ꢃ_JCThermal Impedance . . . . . . . . . . . . . . . 56ꢁC/W (SOIC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74ꢁC/W (µSOIC)

Lead Temperature, Soldering

AD7495 SOIC/␮SOIC

1

2

3

4

8

7

6

5

REF OUT

V

DD

AD7495

TOP VIEW

(Not to Scale)

V

CS

IN

GND

V

DRIVE

SCLK

SDATA

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215ꢁC

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220ꢁC

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Linearity

Package

Option²

Branding

Information

Model

Range

Error (LSB)¹

AD7495AR

AD7495BR

AD7495ARM

AD7495BRM

AD7475AR

AD7475BR

AD7475ARM

–40ꢁC to +85ꢁC

Evaluation Board

Controller Board

1.5

1

1.5

1

1.5

1

1.5

SO-8

RM-8

SO-8

RM-8

AD7495AR

AD7495BR

CCA

CCB

AD7475AR

AD7475BR

C9A

AD7475BRM

1

C9B

EVAL-AD7495CB³

EVAL-AD7475CB³

EVAL-CONTROL BRD2⁴

NOTES

¹Linearity Error here refers to Integral Linearity Error.

²SO = SOIC; RM = µSOIC.

³This can be used as a standalone evaluation board or in conjunction with the EVAL-BOARD CONTROLLER for evaluation/demonstration purposes.

⁴This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in

the CB designators.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7475/AD7495 features proprietary ESD protection circuitry, permanent damage may occur

on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions

are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–6–

AD7475/AD7495

PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

1

REF IN

Reference Input for the AD7475. An external reference must be applied to this input. The voltage range

for the external reference is 2.5 V 1% for specified performance. A cap of a least 0.1 ꢀF should be placed

on the REF IN pin.

REF OUT

Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The

internal reference can be taken from this pin but buffering is required before it is applied elsewhere in a system.

Analog Input. Single-ended analog input channel. The input range is 0 to REF IN.

Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. All analog input signals

and any external reference signal should be referred to this GND voltage.

2

3

V_IN

GND

4

5

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is

also used as the clock source for the AD7475/AD7495’s conversion process.

Data Out. Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a

serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists

of four leading zeros followed by the 12 bits of conversion data which is provided MSB first.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface

of the AD7475/AD7495 will operate.

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7475/AD7495 and also frames the serial data transfer.

Power Supply Input. The V_DDrange for the AD7475/AD7495 is from 2.7 V to 5.25 V.

SDATA

6

7

8

V_DRIVE

CS

V_DD

TERMINOLOGY

Total Harmonic Distortion

Integral Nonlinearity

Total harmonic distortion (THD) is the ratio of the rms sum of

This is the maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints of the

transfer function are zero scale, a point 1/2 LSB below the first

code transition, and full scale, a point 1/2 LSB above the last

code transition.

harmonics to the fundamental. For the AD7475/AD7495, it is

defined as:

V₂²+V₃²+V₄²+V₅²+V₆²

THD(dB) = 20log

V₁

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

where V₁is the rms amplitude of the fundamental and V₂, V₃, V₄,

V₅and V₆are the rms amplitudes of the second through the sixth

harmonics.

Offset Error

Peak Harmonic or Spurious Noise

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB.

Peak harmonic or spurious noise is defined as the ratio of the rms

value of the next largest component in the ADC output spectrum

(up to f_S/2 and excluding dc) to the rms value of the fundamental.

Normally, the value of this specification is determined by the

largest harmonic in the spectrum, but for ADCs where the har-

monics are buried in the noise floor, it will be a noise peak.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (i.e., V_REF– 1.5 LSB) after the offset

error has been adjusted out.

Track/Hold Acquisition Time

Intermodulation Distortion

The track/hold amplifier returns into track mode on the 13th

SCLK rising edge (see Serial Interface section). The Track/Hold

Acquisition Time is the minimum time required for the track-

and-hold amplifier to remain in track mode for its output to

reach and settle to within 0.5 LSB of the applied input signal,

given a step change to the input signal.

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ꢂ nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those

for which neither m nor n is equal to zero. For example, the

second order terms include (fa + fb) and (fa – fb), while the third

order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (f_S/2), excluding dc. The ratio

is dependent on the number of quantization levels in the digiti-

zation process; the more levels, the smaller the quantization noise.

The theoretical signal to (noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by:

The AD7475/AD7495 are tested using the CCIF standard where

two input frequencies near the top end of the input bandwidth are

used. In this case, the second order terms are usually distanced

in frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. The calculation of the intermodulation distortion is as per

the THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

REV. A

–7–

AD7475/AD7495

AD7475/AD7495 TYPICAL PERFORMANCE CURVES

TPC 1 shows a typical FFT plot for the AD7475 at 1 MHz

sample rate and 100 kHz input frequency.

CIRCUIT INFORMATION

The AD7475/AD7495 are fast, micropower, 12-bit, single-supply,

A/D converters. The parts can be operated from a 2.7 V to 5.25 V

supply. When operated from either a 5 V supply or a 3 V sup-

ply, the AD7475/AD7495 are capable of throughput rates of

1 MSPS when provided with a 20 MHz clock.

8192 POINT FFT

f

= 1MSPS

SAMPLE

= 100kHz

–15

–35

The AD7475/AD7495 provide the user with an on-chip track/

hold, A/D converter, and a serial interface housed in either an

8-lead SOIC or µSOIC package, which offers the user considerable

space-saving advantages over alternative solutions. The AD7495

also has an on-chip 2.5 V reference. The serial clock input accesses

data from the part but also provides the clock source for the

successive-approximation A/D converter. The analog input range

is 0 V to REF IN for the AD7475 and 0 V to REF OUT for

the AD7495.

IN

SINAD = 70.46dB

THD = –87.7dB

SFDR = –89.5dB

–55

–75

–95

The AD7475/AD7495 also feature power-down options to allow

power saving between conversions. The power-down feature is

implemented across the standard serial interface as described in

the Modes of Operation section.

–115

0

50

100 150

200 250 300

350 400 450 500

FREQUENCY – kHz

TPC 1. AD7475 Dynamic Performance

CONVERTER OPERATION

TPC 2 shows a typical FFT plot for the AD7495 at 1 MHz sample

rate and 100 kHz input frequency.

The AD7475/AD7495 are 12-bit successive approximation

analog-to-digital converters based around a capacitive DAC.

The AD7475/AD7495 can convert analog input signals in the

range 0 V to 2.5 V. Figures 4 and 5 show simplified schematics

of the ADC. The ADC comprises of Control Logic, SAR and a

Capacitive DAC, which are used to add and subtract fixed

amounts of charge from the sampling capacitor to bring the

comparator back into a balanced condition. Figure 4 shows the

ADC during its acquisition phase. SW2 is closed and SW1 is in

Position A. The comparator is held in a balanced condition and

the sampling capacitor acquires the signal on V_IN.

8192 POINT FFT

f

= 1MSPS

= 100kHz

SAMPLE

–15

–35

IN

SINAD = 69.95dB

THD = –89.2dB

SFDR = –91.2dB

–55

–75

CAPACITIVE

DAC

–95

–115

4k⍀

A

0

50

100 150

200 250 300

350 400 450 500

V

IN

FREQUENCY – kHz

B

CONTROL LOGIC

SW1

SW2

TPC 2. AD7495 Dynamic Performance

COMPARATOR

AGND

TPC 3 shows the signal-to-(noise + distortion) ratio performance

versus input frequency for various supply voltages while sampling

at 1 MSPS with an SCLK of 20 MHz.

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 5), SW2 will

open and SW1 will move to position B causing the compara-

tor to become unbalanced. The Control Logic and the Capacitive

DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The Control Logic generates the ADC

output code. Figure 6 shows the ADC transfer function.

71.0

V

= V

= 4.75V

70.5

70.0

69.5

69.0

68.5

DD

DRIVE

V

= V = 3.60V

DRIVE

DD

V

= V

= 2.70V

DD

DRIVE

CAPACITIVE

DAC

V

= V

= 5.25V

DD

DRIVE

4k⍀

A

V

IN

SW1

B

CONTROL LOGIC

SW2

COMPARATOR

10

100

INPUT FREQUENCY – kHz

1000

AGND

Figure 5. ADC Conversion Phase

TPC 3. AD7495 SINAD vs. Input Frequency at 1 MSPS

REV. A

–8–

AD7475/AD7495

5V

ADC TRANSFER FUNCTION

SERIAL

INTERFACE

SUPPLY

The output coding of the AD7475/AD7495 is straight binary.

The designed code transitions occur midway between successive

integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The LSB size

is = V_REF/4096. The ideal transfer characteristic for the AD7475/

AD7495 is shown in Figure 6 below.

0.1␮F

10␮F

V

DD

SCLK

0V TO

2.5V

INPUT

V

SDATA

IN

AD7475

␮C/␮P

CS

GND

V

DRIVE

111...111

111...110

REF IN

0.1␮F

10␮F

2.5V

AD780

111...000

0.1␮F

(MIN)

1LSB = V

/4096

REF

3V

SUPPLY

011...111

Figure 7. AD7475 Typical Connection Diagram

000...010

000...001

000...000

Analog Input

Figure 9 shows an equivalent circuit of the analog input structure

of the AD7475/AD7495. The two diodes D1 and D2 provide ESD

protection for the analog inputs. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more than

200 mV. This will cause these diodes to become forward-biased

and start conducting current into the substrate. 20 mA is the

maximum current these diodes can conduct without causing

irreversible damage to the part. The capacitor C1 in Figure 9 is

typically about 4 pF and can primarily be attributed to pin capaci-

tance. The resistor R1 is a lumped component made up of the

on resistance of a switch. This resistor is typically about 100 Ω.

The capacitor C2 is the ADC sampling capacitor and has a capaci-

tance of 16 pF typically. For ac applications, removing high

frequency components from the analog input signal is recom-

mended by use of an RC low-pass filter on the relevant analog

input pin. In applications where harmonic distortion and signal

to noise ratio are critical, the analog input should be driven from

a low impedance source. Large source impedances will signifi-

cantly affect the ac performance of the ADC. This may necessitate

the use of an input buffer amplifier. The choice of the op amp will

be a function of the particular application.

0.5LSB

0V

V

–1.5LSB

REF

ANALOG INPUT

Figure 6. AD7475/AD7495 Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 7 and Figure 8 show a typical connection diagram for the

AD7475 and AD7495 respectively. In both setups the GND pin is

connected to the analog ground plane of the system. In Figure 7

REF IN is connected to a decoupled 2.5 V supply from a reference

source, the AD780, to provide an analog input range of 0 V to

2.5 V. Although the AD7475 is connected to a V_DDof 5 V, the

serial interface is connected to a 3 V microprocessor. The V_DRIVE

pin of the AD7475 is connected to the same 3 V supply of the

microprocessor to allow a 3 V logic interface, see Digital Inputs

Section. In Figure 8, the REF OUT pin of the AD7495 is con-

nected to a buffer and then applied to a level-shifting circuit used

on the analog input to allow a bipolar signal to be applied to the

AD7495. A minimum 100 nF capacitance is required on the

REF OUT pin to GND. The conversion result from both ADCs is

output in a 16-bit word with four leading zeros followed by the

MSB of the 12-bit result. For applications where power con-

sumption is of concern, the power-down modes should be

used between conversions or bursts of several conversions to

improve power performance. See Modes of Operation section

of the data sheet.

V

DD

C2

16pF

D1

D2

R1

V

IN

C1

4pF

CONVERSION PHASE–SWITCH OPEN

TRACK PHASE–SWITCH CLOSED

Figure 9. Equivalent Analog Input Circuit

5V

SUPPLY

SERIAL

INTERFACE

0.1␮F

10␮F

V

0V TO

2.5V

INPUT

DD

R

SCLK

R

0V

V

IN

SDATA

3R

AD7495

␮C/␮P

R

CS

GND

V

DRIVE

REF OUT

0.1␮F

10␮F

0.1␮F

(MIN)

3V

SUPPLY

Figure 8. AD7495 Typical Connection Diagram

–9–

REV. A

AD7475/AD7495

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance will depend on the amount of total harmonic distortion

(THD) that can be tolerated. The THD will increase as the source

impedance increases and performance will degrade. Figure 10

shows a graph of the total harmonic distortion versus source

impedance for various analog input frequencies.

allows the ADC to easily interface to both 3 V and 5 V processors.

For example, if the AD7475/AD7495 were operated with a V_DD

of 5 V, and the V_DRIVEpin could be powered from a 3 V supply.

The AD7475/AD7495 has better dynamic performance with a

V_DDof 5 V while still being able to interface to 3 V digital parts.

Care should be taken to ensure V_DRIVEdoes not exceed V_DDby

more than 0.3 V. (See Absolute Maximum Ratings.)

Reference Section

–10

–20

An external reference source should be used to supply the 2.5 V

reference to the AD7475. Errors in the reference source will result

in gain errors in the AD7475 transfer function and will add the

specified full-scale errors on the part. A capacitor of at least 0.1 µF

should be placed on the REF IN pin. Suitable reference sources

for the AD7475 include the AD780, the AD680, and the AD1852.

–30

f

= 10kHz

IN

–40

–50

–60

f

= 500kHz

IN

f

= 200kHz

IN

The AD7495 contains an on-chip 2.5 V reference. As shown in

Figure 12, the voltage that appears at the REF OUT pin is inter-

nally buffered before being applied to the ADC, the output

impedance of this buffer is typically 10 Ω. The reference is capable

of sourcing up to 2 mA. The REF OUT pin should be decoupled

to AGND using a 100 nF or greater capacitor.

–70

–80

–90

f

= 100kHz

IN

1

10

100

1000

10000

If the 2.5 V internal reference is to be used to drive another device

that is capable of glitching the reference at critical times, then the

reference will have to be buffered before driving the device. To

ensure optimum performance of the AD7495 it is recommended

that the Internal Reference not be over driven. If the use of an

external reference is required the AD7475 should be used.

SOURCE IMPEDANCE – Ohms

Figure 10. THD vs. Source Impedance for Various Ana-

log Input Frequencies

Figure 11 shows a graph of total harmonic distortion versus analog

Input frequency for various supply voltages while sampling at

1 MSPS with an SCLK of 20 MHz.

V

REF OUT

25⍀

–75

V

= V

= 5.25V

40k⍀

–77

–79

–81

–83

–85

–87

–89

–91

–93

–95

DD

DRIVE

160k⍀

V

= V

= 2.70V

DD

DRIVE

Figure 12. AD7495 Reference Circuit

MODES OF OPERATION

V

= V

= 3.60V

DD

DRIVE

The mode of operation of the AD7475/AD7495 is selected by

controlling the (logic) state of the CS signal during a conversion.

There are three possible modes of operation, Normal Mode,

Partial Power-Down Mode, and Full Power-Down Mode. The

point at which CS is pulled high after the conversion has been

initiated will determine which power-down mode, if any, the device

will enter. Similarly, if already in a power-down mode, CS can

control whether the device will return to Normal operation or

remain in power-down. These modes of operation are designed to

provide flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio for

differing application requirements.

V

= V

= 4.75V

DD

DRIVE

10

100

INPUT FREQUENCY – kHz

1000

Figure 11. THD vs. Analog Input Frequency for Various

Supply Voltages

Digital Inputs

The digital inputs applied to the AD7475/AD7495 are not limited

by the maximum ratings which limit the analog inputs. Instead,

the digital inputs applied can go to 7 V and are not restricted by

the V_DD+ 0.3 V limit as on the analog inputs.

Normal Mode

This mode is intended for fastest throughput rate performance as

the user does not have to worry about any power-up times with

the AD7475/AD7495 remaining fully powered all the time.

Figure 13 shows the general diagram of the operation of the

AD7475/AD7495 in this mode.

Another advantage of SCLK and CS not being restricted by the

_DD+ 0.3 V limit is the fact that power supply sequencing issues

are avoided. If CS or SCLK are applied before V_DD, there is no

risk of latch-up as there would be on the analog inputs if a

V

The conversion is initiated on the falling edge of CS as described in

the Serial Interface section. To ensure the part remains fully pow-

ered up at all times, CS must remain low until at least 10 SCLK

falling edges have elapsed after the falling edge of CS. If CS is

brought high any time after the 10th SCLK falling edge, but

signal greater than 0.3 V were applied prior to V_DD

.

V_DRIVE

The AD7475/AD7495 also has the V_DRIVEfeature. V_DRIVE

controls the voltage at which the serial interface operates. V_DRIVE

REV. A

–10–

AD7475/AD7495

CS

1

10

16

SCLK

SDATA

FOUR LEADING ZEROS + CONVERSION RESULT

Figure 13. Normal Mode Operation

CS

1

2

10

16

SCLK

Figure 14. Entering Partial Power-Down Mode

THE PART BEGINS

TO POWER UP

THE PART IS FULLY

POWERED UP

CS

16

A1

1

10

SCLK

SDATA

INVALID DATA

VALID DATA

Figure 15. Exiting Partial Power-Down Mode

falling edge of CS the device will begin to power up, and will

continue to power up as long as CS is held low until after the

falling edge of the tenth SCLK. The device will be fully powered

up once 16 SCLKs have elapsed, and valid data will result from

the next conversion as shown in Figure 15. If CS is brought high

before the second falling edge of SCLK, the AD7475/AD7495

will go back into partial power-down again. This avoids accidental

power-up due to glitches on the CS line; although the device

may begin to power up on the falling edge of CS, it will power

down again on the rising edge of CS. If in partial power-down

and CS is brought high between the second and tenth falling

edges of SCLK, the device will enter full power-down mode.

before the 16th SCLK falling edge, the part will remain powered

up but the conversion will be terminated and SDATA will go

back into three-state. Sixteen serial clock cycles are required

to complete the conversion and access the conversion result. CS

may idle high until the next conversion or may idle low until some-

time prior to the next conversion (effectively idling CS low).

Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the quiet

time, t_QUIET, has elapsed by bringing CS low again.

Partial Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and then the ADC is powered

down for a relatively long duration between these bursts of several

conversions. When the AD7475 is in partial power-down, all ana-

log circuitry is powered down except for the bias current generator;

and, in the case of the AD7495, all analog circuitry is powered

down except for the on-chip reference and reference buffer.

Power-Up Time

The power-up time of the AD7475/AD7495 from partial power-

down is typically 1 µs, which means that with any frequency of

SCLK up to 20 MHz, one dummy cycle will always be suffi-

cient to allow the device to power up from partial power-down.

Once the dummy cycle is complete, the ADC will be fully pow-

ered up and the input signal will be acquired properly. The quiet

time t_QUIETmust still be allowed from the point where the bus

goes back into three-state after the dummy conversion, to the

next falling edge of CS. When running at 1 MSPS throughput

rate, the AD7475/AD7495 will power up and acquire a signal

within 0.5 LSB in one dummy cycle, i.e., 1 µs.

To enter partial power-down, the conversion process must be

interrupted by bringing CS high anywhere after the second falling

edge of SCLK and before the tenth falling edge of SCLK as shown

in Figure 14. Once CS has been brought high in this window of

SCLKs, the part will enter partial power-down, and the con-

version that was initiated by the falling edge of CS will be

terminated, and SDATA will go back into three-state. If CS

is brought high before the second SCLK falling edge, the part

will remain in Normal Mode and will not power down. This will

avoid accidental power-down due to glitches on the CS line.

When powering up from the power-down mode with a dummy

cycle, as in Figure 15, the track-and-hold that was in hold mode

while the part was powered down, returns to track mode after the

first SCLK edge the part receives after the falling edge of CS.

This is shown as Point A in Figure 15. Although at any SCLK

frequency one dummy cycle is sufficient to power the device up

and acquire V_IN, it does not necessarily mean that a full dummy

In order to exit this mode of operation and power the AD7475/

AD7495 up again, a dummy conversion is performed. On the

REV. A

–11–

AD7475/AD7495

THE PART ENTERS

PARTIAL POWER-DOWN

THE PART BEGINS

TO POWER UP

THE PART ENTERS

FULL POWER-DOWN

CS

16

1

2

1

2

10

SCLK

THREE-STATE

SDATA

INVALID DATA

Figure 16. Entering Full Power-Down Mode

THE PART IS FULLY

POWERED UP

THE PART BEGINS

TO POWER UP

t_POWER-UP

CS

16

1

10

SCLK

SDATA

INVALID DATA

VALID DATA

Figure 17. Exiting Full Power-Down Mode

cycle of 16 SCLKs must always elapse to power up the device

and fully acquire V_IN; 1 µs will be sufficient to power the device

up and acquire the input signal. If, for example, a 5 MHz SCLK

frequency was applied to the ADC, the cycle time would be 3.2 ꢀs.

In one dummy cycle, 3.2 µs, the part would be powered up and

V_INfully acquired. However, after 1 µs with a 5 MHz SCLK,

only 5 SCLK cycles would have elapsed. At this stage, the ADC

would be fully powered up and the signal acquired. So, in this

case the CS can be brought high after the tenth SCLK falling edge

and brought low again after a time t_QUIETto initiate the conversion.

long as CS is held low until after the falling edge of the tenth

SCLK. The power-up time is longer than one dummy conversion

cycle however, and this time, t_POWER-UP, must elapse before

a conversion can be initiated as shown in Figure 17. (See

Timing Specifications.)

When power supplies are first applied to the AD7475/AD7495,

the ADC may power up in either of the power-down modes or

normal mode. Because of this, it is best to allow a dummy cycle

to elapse to ensure the part is fully powered up before attempt-

ing a valid conversion. Likewise, if it is intended to keep the part

in the partial power-down mode immediately after the supplies

are applied, then two dummy cycles must be initiated. The first

dummy cycle must hold CS low until after the tenth SCLK

falling edge, Figure 13; in the second cycle CS must be brought

high before the tenth SCLK edge but after the second SCLK

falling edge, Figure 14. Alternatively, if it is intended to place

the part in full power-down mode when the supplies have been

applied, then three dummy cycles must be initiated. The first

dummy cycle must hold CS low until after the tenth SCLK

edge, Figure 13; the second and third dummy cycle place the

part in full power-down, Figure 16. See Modes of Operation

section. Once supplies are applied to the AD7475/AD7495,

enough time must be allowed, for the AD7475, for the external

reference to power up and charge the reference capacitor to its

final value. For the AD7495, enough time should be allowed for

the internal reference buffer to charge the reference capacitor.

Then, to place the AD7475/AD7495 in normal mode, a dummy

cycle, 1 µs, should be initiated. If the first valid conversion is then

performed directly after the dummy conversion, care must be

taken to ensure that adequate acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part will return to track upon the first SCLK edge

applied after the falling edge of CS. However, when the ADC

powers up initially after supplies are applied, the track-and-hold

will already be in track. This means (assuming one has the facil-

ity to monitor the ADC supply current) if the ADC powers up

Full Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required than that in the partial power-down

mode, as power up from a full power-down would not be com-

plete in just one dummy conversion. This mode is more suited to

applications where a series of conversions performed at a relatively

high throughput rate would be followed by a long period of

inactivity and hence power-down. When the AD7475/AD7495

is in full power-down, all analog circuitry is powered down.

Full power-down is entered in a way similar to partial power-down,

except the timing sequence shown in Figure 14 must be executed

twice. The conversion process must be interrupted in a similar

fashion by bringing CS high anywhere after the second falling

edge of SCLK and before the tenth falling edge of SCLK. The

device will enter partial power-down at this point. To reach full

power-down, the next conversion cycle must be interrupted

in the same way as shown in Figure 16. Once CS has been

brought high in this window of SCLKs, then the part will

power down completely.

NOTE: It is not necessary to complete the 16 SCLKs once CS

has been brought high to enter a power-down mode.

To exit full power-down, and power the AD7475/AD7495 up

again, a dummy conversion is performed as when powering

up from partial power-down. On the falling edge of CS the

device will begin to power up, and will continue to power up as

REV. A

–12–

AD7475/AD7495

in the desired mode of operation, and thus a dummy cycle is not

required to change mode, then neither is a dummy cycle required

to place the track-and-hold into track. If no current monitoring

facility is available, the relevant dummy cycle(s) should be per-

formed to ensure the part is in the required mode.

remaining 8 µs where the part is in partial power-down. With a

throughput rate of 100 kSPS, the average power dissipated during

each conversion cycle is (2/10) ꢄ (6 mW) + (8/10) ꢄ (0.69 mW)

= 1.752 mW. Figure 18 shows the power versus throughput rate

when using the partial power-down mode between conversions

with both 5 V and 3 V supplies for both the AD7475 and AD7495.

For the AD7475, partial power-down current is lower than that

of the AD7495.

POWER VERSUS THROUGHPUT RATE

By using the partial power-down mode on the AD7475/AD7495

when not converting, the average power consumption of the

ADC decreases at lower throughput rates. Figure 18 shows

how, as the throughput rate is reduced, the part remains in its

partial power-down state longer and the average power consump-

tion over time drops accordingly.

Full power-down mode is intended for use in applications with

slower throughput rates than required for the partial power-

down mode. It is necessary to leave 650 µs for the AD7495 to

be fully powered up from full power-down before initiating a

conversion. Current consumptions between conversions is typi-

cally less than 1 µA.

100

Figure 19 shows a typical graph of current versus throughput for

the AD7495 while operating in different modes. At slower

throughput rates, e.g., 10 SPS to 1 kSPS, the AD7495 was

operated in Full Power-Down mode. As the throughput rate

increased, up to 100 kSPS, the AD7495 was operated in Partial

Power-Down mode, with the part being powered down between

conversions. With throughput rates from 100 kSPS to 1 MSPS,

the part operated in Normal mode, remaining fully powered up

at all times.

AD7495 5V

SCLK = 20MHz

AD7475 5V

SCLK = 20MHz

10

1

AD7495 3V

SCLK = 20MHz

AD7475 3V

SCLK = 20MHz

0.1

0.01

2.0

V

= 5V

DD

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0.001

0

50

100

150

200

250

300

350

THROUGHPUT – kSPS

Figure 18. AD7495 Power vs. Throughput for Partial

Power-Down

For example if the AD7495 is operated in a continuous sampling

mode with a throughput rate of 100 kSPS and an SCLK of

20 MHz (V_DD= 5 V), and the device is placed in partial power-

down mode between conversions, then the power consumption

is calculated as follows. The maximum power dissipation during

normal operation is 13 mW (V_DD= 5 V). If the power-up time

from partial power-down is one dummy cycle, i.e., 1 µs, and the

remaining conversion time is another cycle, i.e., 1 µs, then the

AD7495 can be said to dissipate 13 mW for 2 µs during each

conversion cycle. For the remainder of the conversion cycle,

8 µs, the part remains in partial power-down mode. The AD7495

can be said to dissipate 1.15 mW for the remaining 8 µs of the

conversion cycle. If the throughput rate is 100 kSPS, the cycle

time is 10 µs and the average power dissipated during each cycle

is (2/10) ꢄ (13 mW) + (8/10) ꢄ (1.15 mW) = 3.52 mW. If V_DD

= 3 V, SCLK = 20 MHz and the device is again in partial power-

down mode between conversions, the power dissipated during

normal operation is 6 mW. The AD7495 can be said to dissipate

6 mW for 2 µs during each conversion cycle and 0.69 mW for the

PARTIAL

POWER-DOWN

FULL

POWER-DOWN

NORMAL

10

100

1k

10k

100k

1M

THROUGHPUT – SPS

Figure 19. Typical AD7495 Current vs. Throughput

SERIAL INTERFACE

Figure 20 shows the detailed timing diagram for serial interfacing

to the AD7475/AD7495. The serial clock provides the conversion

clock and also controls the transfer of information from the

AD7475/AD7495 during conversion.

CS initiates the data transfer and conversion process. The falling

edge of CS puts the track and hold into hold mode, takes the bus

out of three-state, and the analog input is sampled at this point.

CS

t_CONVERT

t₆

t₂

B

3

4

5

1

2

13

15

t₈

DB0

16

14

t₅

SCLK

t₇

DB10

t_QUIET

t₄

DB11

t₃

0

SDATA

DB2

DB1

THREE-STATE

FOUR LEADING ZEROS

Figure 20. Serial Interface Timing Diagram

–13–

REV. A

AD7475/AD7495

CS

t_CONVERT

t₆

t₂

B

t₉

3

4

5

1

2

13

15

16

14

SCLK

t₇

t_QUIET

t₄

t₃

0

DB11

DB10

SDATA

THREE-STATE

DB2

THREE-STATE

FOUR LEADING ZEROS

Figure 21. Serial Interface Timing Diagram—Conversion Termination

The connection diagram is shown in Figure 22. It should be noted

that for signal processing applications, it is imperative that

the frame synchronization signal from the TMS320C5x/C54x

provide equidistant sampling. The V_DRIVEpin of the AD7475/

AD7495 takes the same supply voltage as that of the TMS320C5x/

C54x. This allows the ADC to operate at a higher voltage than

the serial interface, i.e., TMS320C5x/C54x, if necessary.

The conversion is also initiated at this point and will require

16 SCLK cycles to complete. Once 13 SCLK falling edges have

elapsed, the track and hold will go back into track on the next

SCLK rising edge as shown in Figure 20 at Point B. On the

16th SCLK falling edge the SDATA line will go back into three-

state. If the rising edge of CS occurs before 16 SCLKs have

elapsed, the conversion will be terminated and the SDATA line

will go back into three-state, as shown in Figure 21, otherwise

SDATA returns to three-state on the 16th SCLK falling edge as

shown in Figure 20.

TMS320C5x/C54x*

AD7475/AD7495*

SCLK

CLKX

Sixteen serial clock cycles are required to perform the conversion

process and to access data from the AD7475/AD7495. CS going

low provides the first leading zero to be read in by the micro-

controller or DSP. The remaining data is then clocked out by

subsequent SCLK falling edges beginning with the 2nd leading

zero, thus the first falling clock edge on the serial clock has the

second leading zero provided. The final bit in the data transfer

is valid on the sixteenth falling edge, having being clocked out on

the previous (15th) falling edge.

CLKR

DR

SDATA

CS

FBX

V

DRIVE

FSR

V

DD

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Interfacing to the TMS320C5x/C54x

AD7475/AD7495 to ADSP-21xx

In applications with a slower SCLK, it may be possible to read in

data on each SCLK rising edge, although the first leading zero will

still have to be read on the first SCLK falling edge after the CS

falling edge. Therefore, the first rising edge of SCLK after the CS

falling edge would provide the second leading zero and the 15th

rising SCLK edge would have DB0 provided. This method may

not work with most Micros/DSPs, but could possibly be used

with FPGAs and ASICs.

The ADSP-21xx family of DSPs are interfaced directly to the

AD7475/AD7495 without any glue logic required. The V_DRIVEpin

of the AD7475/AD7495 takes the same supply voltage as that of

the ADSP-21xx. This allows the ADC to operate at a higher

voltage than the serial interface, i.e., ADSP-21xx, if necessary.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0,

MICROPROCESSOR INTERFACING

The serial interface on the AD7475/AD7495 allows the parts to

be directly connected to a range of many different microprocessors.

This section explains how to interface the AD7475/AD7495 with

some of the more common microcontroller and DSP serial

interface protocols.

ITFS = 1.

AD7475/AD7495 to TMS320C5x/C54x

To implement the power-down modes SLEN should be set to

1001 to issue an 8-bit SCLK burst.

The serial interface on the TMS320C5x/C54x uses a continuous

serial clock and frame synchronization signals to synchronize the

data transfer operations with peripheral devices like the AD7475/

AD7495. The CS input allows easy interfacing between the

TMS320C5x/C54x and the AD7475/AD7495 without any glue

logic required. The serial port of the TMS320C5x/C54x is set

up to operate in burst mode with internal CLKX (Tx serial clock)

and FSX (Tx frame sync). The serial port control register (SPC)

must have the following setup: FO = 0, FSM = 1, MCM = 1 and

TXM = 1. The format bit, FO, may be set to 1 to set the word

length to 8 bits, in order to implement the power-down modes

on the AD7475/AD7495.

The connection diagram is shown in Figure 23. The ADSP-

21xx has the TFS and RFS of the SPORT tied together, with

TFS set as an output and RFS set as an input. The DSP oper-

ates in Alternate Framing Mode and the SPORT control register is

set up as described. The Frame synchronizations signal generated

on the TFS is tied to CS and as with all signal processing appli-

cations equidistant sampling is necessary. However, in this

example, the timer interrupt is used to control the sampling rate

of the ADC and under certain conditions, equidistant sampling

may not be achieved.

REV. A

–14–

AD7475/AD7495

implement the power-down modes on the AD7475/AD7495

then the word length can be changed to eight bits by setting bits

WL1 = 0 and WL0 = 0 in CRA. It should be noted that for

signal processing applications, it is imperative that the frame

synchronization signal from the DSP56xxx provide equidistant

sampling. The V_DRIVEpin of the AD7475/AD7495 takes the

same supply voltage as that of the DSP56xxx. This allows the

ADC to operate at a voltage higher than the serial interface, i.e.,

DSP56xxx, if necessary.

ADSP-21xx*

SCLK

AD7475/AD7495*

SCLK

DR

SDATA

CS

RFS

TFS

V

DRIVE

V

DD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 23. Interfacing to the ADSP-21xx

DSP56xxx*

AD7475/AD7495*

SCLK

SRD

SC2

The Timer registers etc., are loaded with a value that will provide

an interrupt at the required sample interval. When an interrupt

is received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and hence the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The

DSP will wait until the SCLK has gone high, low, and high

before transmission will start. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, the data may be transmitted or it may

wait until the next clock edge.

SDATA

CS

V

DRIVE

V

DD

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. Interfacing to the DSP56xxx

AD7475/AD7495 to MC68HC16

The Serial Peripheral Interface (SPI) on the MC68HC16 is

configured for Master Mode (MSTR = 1), Clock Polarity Bit

(CPOL) = 1 and the Clock Phase Bit (CPHA) = 0. The SPI

is configured by writing to the SPI Control Register (SPCR), see

68HC16 user manual. The serial transfer will take place as a

16-bit operation when the SIZE bit in the SPCR register is

set to SIZE = 1. To implement the power-down modes with an

8-bit transfer set SIZE = 0. A connection diagram is shown in

Figure 25. The V_DRIVEpin of the AD7475/AD7495 takes the same

supply voltage as that of the MC68HC16. This allows the ADC

to operate at a higher voltage than the serial interface, i.e.,

MC68HC16, if necessary.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained, and eight master clock periods will

elapse for every 1 SCLK period. If the timer registers are loaded

with the value 803, 100.5 SCLKs will occur between interrupts

and subsequently between transmit instructions. This situation

will result in nonequidistant sampling as the transmit instruc-

tion is occurring on a SCLK edge. If the number of SCLKs

between interrupts is a whole integer figure of N, equidistant

sampling will be implemented by the DSP.

AD7475/AD7495 to DSP56xxx

The connection diagram in Figure 24 shows how the AD7475/

AD7495 can be connected to the SSI (Synchronous Serial Inter-

face) of the DSP56xxx family of DSPs from Motorola. The SSI

is operated in Synchronous Mode (SYN bit in CRB = 1) with

internally generated 1-bit clock period frame sync for both Tx

and Rx (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word

length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To

MC68HC16*

AD7475/AD7495*

SCLK

SCLK/PCM2

MISO/PMC0

SDATA

CS

SS/PMC3

V

DRIVE

V

DD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. Interfacing to the MC68HC16

REV. A

–15–

AD7475/AD7495

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

1

5

4

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

BSC

؋

45؇

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

8؇

0؇

0.050 (1.27)

0.016 (0.40)

0.020 (0.51)

0.013 (0.33)

0.0098 (0.25)

0.0075 (0.19)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

8-Lead microSOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

8

5

4

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

1

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33؇

0.018 (0.46)

0.008 (0.20)

27؇

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

–16–

REV. A


型号：	AD7495BR
厂家：	ADI
描述：	1 MSPS, 12-Bit ADCs 1 MSPS ， 12位ADC
文件：	总16页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7495BR [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E