AD75004KN [ADI]
Quad 12-Bit D/A Converter; 四通道12位D / A转换器
| 型号： | AD75004KN |
| 厂家： | 
ADI |
| 描述： | Quad 12-Bit D/A Converter |
| 文件： | 总4页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 12-Bit
D/A Converter
a
AD75004
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
4 Com plete 12-Bit D/ A Functions
Double-Buffered Latches
Sim ultaneous Update of All DACs Possible
؎5 V Output Range
V
V
REFIN
2.22k
REFOUT
+5V
VOLTAGE
REFERENCE
High Stability Bandgap Reference
Monolithic BiMOS Construction
Guaranteed Monotonic over Tem perature
3/ 4 LSB Linearity Guaranteed over Tem perature
4 s m ax Settling Tim e to 0.01%
Operates w ith ؎12 V Supplies
Low Pow er: 720 m W m ax Including Reference
TTL/ 5 V CMOS Com patible Logic Inputs
8-Bit Microprocessor Interface
INPUT
DAC
LATCHES
LATCHES
12-BIT
DAC
10k
10k
10k
12-BIT
LATCH
8 + 4-BIT
LATCHES
V
V
OUT3
OUT2
D7
D6
12-BIT
DAC
8 + 4-BIT
LATCHES
12-BIT
LATCH
D5
D4
TTL
INPUTS
8-BIT
D3
D2
D1
D0
BUS
12-BIT
DAC
12-BIT
LATCH
8 + 4-BIT
LATCHES
V
OUT1
24-Pin PDIP or 28-Lead PLCC Package
12-BIT
LATCH
8 + 4-BIT
LATCHES
12-BIT
DAC
10k
V
V
OUT0
P RO D UCT D ESCRIP TIO N
+12V
–12V
DD
CONTROL LOGIC
V
SS
T he AD75004 contains four complete, voltage output, 12-bit
digital-to-analog converters, a high stability bandgap reference,
and double-buffered input latches on a single chip. T he convert-
ers use 12 precision high speed bipolar current steering switches
and laser-trimmed thin-film resistor networks to provide fast
settling time and high accuracy.
AGND
DGND
AD75004
TTL INPUTS
CS WR A3 A2 A1 A0
T he bandgap reference on the chip has low noise, long term
stability and temperature drift characteristics comparable to
discrete reference diodes. T he absolute value of the reference is
laser trimmed to +5.00 V with 0.6% maximum error. Its tem-
perature coefficient is also laser trimmed.
Microprocessor compatibility is achieved by the on-chip
double-buffered latches. T he design of the input latches allows
direct interface to 8-bit buses. T he 12 bits of data from the first
rank of latches can then be transferred to the second rank,
avoiding generation of spurious analog output values. T he latch
responds to strobe pulses as short as 50 ns, allowing use with
fast microprocessors.
T ypical full-scale gain T C is 15 ppm/°C. With guaranteed
monotonicity over the full temperature range, the AD75004 is
well suited for wide temperature range performance.
T he functional completeness and high performance of the
AD75004 results from a combination of advanced switch de-
sign, the BiMOS II fabrication process, and proven laser trim-
ming technology. BiMOS II is an epitaxial BiCMOS process
optimized for analog and converter functions. T he AD75004 is
trimmed at the wafer level and is specified to ±1/2 LSB maxi-
mum linearity error at 25°C and ±3/4 LSB over the full operat-
ing temperature range. T he on-chip output amplifiers provide
an output range of ±5 V, with 1 LSB equal to 2.44 mV.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD75004–SPECIFICATIONS (T = +25؇C, ؎12.0 V power supplies unless otherwise noted)
A
P aram eter
Sym bol
Min
Typ
Max
Units
DIGIT AL INPUT S (D0–D7, A0–A3, CS, WR)
Logic Levels (T T L Compatible)
Input Voltage, Logic “1”
VIH
VIL
IIH
IIL
CIN
2.0
0
5.5
0.8
10
10
10
V
V
µA
µA
pF
Input Voltage, Logic “0”
Input Current, VIH = 5.5 V
Input Current, VIL = 0.8 V
Input Capacitance
ACCURACY
Resolution
12
Bits
Integral Linearity Error
±1/4
±1/2
±1/2
؎1/2
±3/4
؎3/4
LSB
LSB
LSB
Integral Linearity Error, TMIN to T MAX
Differential Linearity Error
Differential Linearity Error, TMIN to T MAX
Gain (Full-Scale) Error1
Guaranteed Monotonic
±2
±15
±1
؎10
±30
؎2
LSB
ppm/°C
LSB
1
Gain Error Drift, TMIN to TMAX
Bipolar Zero Error1
1
Bipolar Zero Error Drift, TMIN to TMAX
±3
±7
ppm/°C
CHANNEL-T O-CHANNEL MISMAT CH
Integral Linearity Error
Gain Error1
±1/2
±1
±1
؎1
؎4
؎2
LSB
LSB
LSB
Bipolar Zero Error1
DYNAMIC PERFORMANCE
Settling T ime to ±0.01% of FSR
for FSR Change, 2 kΩ || 500 pF Load
Slew Rate, 2 kΩ || 500 pF Load
Digital Input Crosstalk (Static)2
2
4
µs
V/µs
dB
5
–50
ANALOG OUT PUT S
Full-Scale Range (FSR)
Output Current
VOUT
IOUT
±5
V
mA
mA
±5
Short Circuit Limit Current
؎40
VOLT AGE REFERENCE
Reference Output Voltage
T emperature Coefficient
VREFOUT
4.97
5.00
±15
5.0
5.03
±25
V
ppm/°C
mA
V
Reference Output Currents3
Reference Input Voltage
3.0
4.5
VREFIN
IREFIN
5.0
5.5
3.0
Reference Input Current @ 5.0 V
mA
POWER SUPPLY GAIN SENSIT IVIT Y
∆Gain/∆VDD, VDD = +10.8 to +13.2 V dc1
∆Gain/∆VSS, VSS = –10.8 to –13.2 V dc1
±15
±15
؎25
؎25
ppm of FSR/%
ppm of FSR/%
POWER SUPPLY REQUIREMENT S
Voltage Range
Supply Currents
V
DD, VSS
؎10.8
±12
±25
؎13.2
؎30
V
mA
IDD, ISS
T EMPERAT URE RANGE
Specification
Storage
T
MIN, TMAX
0
–65
+70
+150
°C
°C
NOT ES
1Gain and bipolar zero errors are measured using internal voltage reference and include its errors.
2Digital crosstalk is defined as the change in any one output’s steady state value as a result of any other output being driven from VOUT MIN to VOUT MAX into a
2 kΩ || 500 pF load by means of varying the digital input code.
3T he internal voltage reference is intended to drive on-chip only; buffer it if using it externally.
4All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from
those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.
–2–
REV. A
AD75004
1
TIMING CHARACTERISTICS
TRUTH TABLE
(T = +25؇C, ؎12.0 V power supplies unless otherwise noted)
A
P aram eter
Sym bol
Min
Units
Control and Address Lines
CS WR A3 A2 A1 A0
O peration
Address Setup T ime
Address Hold T ime
Data Setup T ime
Data Hold T ime
Chip Select to Write Setup T ime
Write to Chip Select Hold T ime
Write Pulse Width
t1
t2
t3
t4
t5
t6
t7
30
10
10
45
0
ns
ns
ns
ns
ns
ns
ns
1
X
0
0
0
0
X
1
0
0
0
0
X
X
0
0
1
X
X
0
1
0
X
X
X
X
No operation
No operation
A1* A0* 8 LSBs → one input latch
A1* A0* 4 MSBs → one input latch
A1* A0* Update one DAC latch
0
50
1
1
X
X
Update all 4 DAC latches
NOT ES
NOT E
1T iming measurement reference level is 1.5 V.
*T he A1 and A0 inputs specify the relevant channel.
Specifications subject to change without notice
A1
A0
Channel
ADDRESS INPUTS
(A0–A3)
0
0
1
1
0
1
0
1
0
1
2
3
t2
t1
DATA INPUTS
(D0–D7)
t3
t4
CHIP SELECT
(CS)
t6
t5
WRITE
(WR)
t7
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise noted)
Min
Max
Units
Conditions
VDD to DGND
VSS to DGND
VDD to VSS
VREFIN to AGND
Digital Inputs to DGND
AGND to DGND
–0.3
–18
–0.3
–0.3
–0.3
–0.3
+18
V
V
V
V
V
V
+0.3
+26.4
VDD
VDD
+0.3
Short to AGND on Analog Outputs
Power Dissipation
Indefinite sec
1.0
W
T A ≤ 75°C
Specification T emperature Range
Storage T emperature
Lead T emperature
0
–65
+70
+150
+300
°C
°C
°C
Soldering, 10 seconds
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. T hese are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD75004 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Model
Tem perature Range
P ackage O ption*
AD75004KN
AD75004KP
0°C to +70°C
0°C to +70°C
N-24A
P-28A
*N = Plastic DIP; P = Plastic Leaded Chip Carrier.
REV. A
–3–
AD75004
P IN D ESCRIP TIO NS
P IN CO NFIGURATIO NS
24-P in P lastic D IP
P lastic
D IP
P in
P LCC
P in
D7
1
24
23
22
21
20
19
18
17
16
V
V
V
Nam e
D escription
DD
2
3
D6
D5
OUT3
OUT2
1
2
3
5
6
7
9
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
CS
WR
A3
A2
A1
Data Input Bit 7
Data Input Bit 6
Data Input Bit 5
Data Input Bit 4
4
5
D4
D3
D2
V
V
V
V
V
OUT1
OUT0
Data Input Bit 3 or 11 (MSB)
Data Input Bit 2 or 10
Data Input Bit 1 or 9
Data Input Bit 0 (LSB) or 8
Chip Select Input; Active Low
Write Input; Active Low
Address Input Bit 3 (MSB)
Address Input Bit 2
Address Input Bit 1
Address Input Bit 0 (LSB)
Digital Ground
AD75004KN
TOP VIEW
(Not to Scale)
6
REFIN
REFOUT
SS
D1
D0
7
10
11
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
4
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
–
CS
WR
A3
9
AGND
10
11
12
15
14
DGND
A0
A0
A2
13 A1
DGND
AGND
VSS
Analog Ground
–12 V Power Supply
+5 V Reference Output
Reference Input
Analog Output 0
Analog Output 1
Analog Output 2
Analog Output 3
+12 V Power Supply
No Internal Connection
No Internal Connection
No Internal Connection
No Internal Connection
28-P in P LCC
VREFOUT
VREFIN
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VDD
NC
4
3
2
1
28 27 26
D4
5
25 NC
D3
D2
NC
D1
D0
6
7
24
23
VOUT1
VOUT0
AD75004KP
8
12
25
–
–
–
NC
NC
NC
8
22 VREFIN
TOP VIEW
(Not to Scale)
9
21
VREFOUT
10
20 VSS
BINARY CO D E TABLE
11
19 AGND
CS
Twos Com plem ent
Value in D AC Latch
Analog O utput
Voltage
12 13 14 15 16 17 18
NC = NO CONNECT
MSB
0111
0000
0000
1111
1000
LSB
1111
0001
0000
1111
0000
1111
0000
0000
1111
0000
(2047/2048) * VREFIN
(1/2048) * VREFIN
0 V
– (1/2048) * VREFIN
–VREFIN
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N-24A)
P LCC (P -28A)
1.290 (32.77)
1.150 (29.21)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.056 (1.42)
0.042 (1.07)
24
13
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.55 (13.97)
0.53 (13.47)
0.048 (1.21)
0.042 (1.07)
4
5
26
25
PIN 1
0.021 (0.53)
0.013 (0.33)
IDENTIFIER
1
12
0.430 (10.92)
0.390 (9.91)
0.606 (15.4)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
0.16 (4.07)
0.14 (3.56)
0.060 (1.52)
0.015 (0.38)
0.594 (15.09)
PIN 1
0.032 (0.81)
0.026 (0.66)
0.2
(5.08)
MAX
11
12
19
18
SQ
SQ
0.150
(3.81)
MIN
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.456 (11.58)
0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
0.012 (0.305)
0.008 (0.203)
0.100
(2.54)
BSC
0.065 (1.66)
0.45 (1.15)
0.02 (0.508)
0.015 (0.381)
0.175 (4.45)
0.12 (3.05)
SEATING
PLANE
0.110 (2.79)
0.085 (2.16)
–4–
REV. A
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