AD7528SQ [ADI]

CMOS Dual 8-Bit Buffered Multiplying DAC; CMOS双8位缓冲乘法DAC


型号：	AD7528SQ
厂家：	ADI
描述：	CMOS Dual 8-Bit Buffered Multiplying DAC CMOS双8位缓冲乘法DAC
文件：	总8页 (文件大小：191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CMOS Dual 8-Bit

Buffered Multiplying DAC

AD7528

FEATURES

FUNCTIONAL BLOCK DIAGRAM

On-Chip Latches for Both DACs

+5 V to +15 V Operation

REF

DACs Matched to 1%

Four Quadrant Multiplication

TTL/CMOS Compatible

Latch Free (Protection Schottkys not Required)

DB0

OUT A

DATA

INPUTS

INPUT

BUFFER

LATCH

DAC A

DB7

AGND

APPLICATIONS

AD7528

Digital Control of:

Gain/Attenuation

Filter Parameters

Stereo Audio Circuits

X-Y Graphics

DAC A/

DAC B

CONTROL

LOGIC

OUT B

LATCH

DAC B

DGND

REF

GENERAL DESCRIPTION

ORDERING GUIDE¹

The AD7528 is a monolithic dual 8-bit digital/analog converter

featuring excellent DAC-to-DAC matching. It is available in

skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount

packages.

Temperature

Ranges

Relative Gain

Accuracy Error

Package

Options³

Model²

AD7528JN –40°C to +85°C

AD7528KN –40°C to +85°C

AD7528LN –40°C to +85°C

±1 LSB

±4 LSB N-20

±1/2 LSB ±2 LSB N-20

±1/2 LSB ±1 LSB N-20

Separate on-chip latches are provided for each DAC to allow

easy microprocessor interface.

AD7528JP

–40°C to +85°C

±1 LSB

±4 LSB P-20A

Data is transferred into either of the two DAC data latches via a

common 8-bit TTL/CMOS compatible input port. Control

input DAC A/DAC B determines which DAC is to be loaded.

The AD7528’s load cycle is similar to the write cycle of a ran-

dom access memory and the device is bus compatible with most

8-bit microprocessors, including 6800, 8080, 8085, Z80.

AD7528KP –40°C to +85°C

AD7528LP –40°C to +85°C

±1/2 LSB ±2 LSB P-20A

±1/2 LSB ±1 LSB P-20A

AD7528JR

–40°C to +85°C

±1 LSB

±4 LSB R-20

AD7528KR –40°C to +85°C

AD7528LR –40°C to +85°C

AD7528AQ –40°C to +85°C

AD7528BQ –40°C to +85°C

AD7528CQ –40°C to +85°C

AD7528SQ –55°C to +125°C ±1 LSB

AD7528TQ –55°C to +125°C ±1/2 LSB ±2 LSB Q-20

AD7528UQ –55°C to +125°C ±1/2 LSB ±1 LSB Q-20

±1/2 LSB ±2 LSB R-20

±1/2 LSB ±1 LSB R-20

±1 LSB

±4 LSB Q-20

±1/2 LSB ±2 LSB Q-20

±1/2 LSB ±1 LSB Q-20

The device operates from a +5 V to +15 V power supply, dis-

sipating only 20 mW of power.

±4 LSB Q-20

Both DACs offer excellent four quadrant multiplication charac-

teristics with a separate reference input and feedback resistor for

each DAC.

NOTES

¹Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts

will be marked with cerdip designator “Q.”

²Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to

part number. For further information, see Analog Devices’ 1990 Military Products

Databook.

PRODUCT HIGHLIGHTS

1. DAC-to-DAC matching: since both of the AD7528 DACs are

fabricated at the same time on the same chip, precise match-

ing and tracking between DAC A and DAC B is inherent.

The AD7528’s matched CMOS DACs make a whole new

range of applications circuits possible, particularly in the

audio, graphics and process control areas.

³N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

2. Small package size: combining the inputs to the on-chip DAC

latches into a common data bus and adding a DAC A/DAC B

select line has allowed the AD7528 to be packaged in either a

small 20-lead DIP, SOIC or PLCC.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_REFA = V_REFB = +10 V; OUT A = OUT B = O V unless otherwise noted)

AD7528–SPECIFICATIONS

V_DD= +5 V

Version¹T_A= +25°C T_MIN, T_MAX

V_DD= +15 V

Parameter

T_A= +25°C T_MIN, T_MAX

Units

Test Conditions/Comments

STATIC PERFORMANCE²

Resolution

Relative Accuracy

All

±1

±1/2

±1

±1/2

±1

±1/2

±1

±1/2

±1

Bits

J, A, S

K, B, T

L, C, U

All

LSB max

This is an Endpoint Linearity Specification

Differential Nonlinearity

Gain Error

All Grades Guaranteed Monotonic Over

Full Operating Temperature Range

Measured Using Internal R_FBA and R_FBB

Both DAC Latches Loaded with 11111111

Gain Error is Adjustable Using Circuits

of Figures 4 and 5

J, A, S

K, B, T

L, C, U

±4

±2

±1

±6

±4

±3

±4

±2

±1

±5

±3

±1

LSB max

Gain Temperature Coefficient³

∆Gain/∆Temperature

All

±0.007

±0.0035

%/°C max

Output Leakage Current

OUT A (Pin 2)

OUT B (Pin 20)

All

±50

±400

±50

±200

nA max

kΩ min

kΩ max

DAC Latches Loaded with 00000000

Input Resistance (V_REFA, V_REFB)

Input Resistance TC = –300 ppm/°C, Typical

Input Resistance is 11 kΩ

V_REFA/V_REFB Input Resistance

Match

All

±1

% max

DIGITAL INPUTS⁴

Input High Voltage

V_IH

Input Low Voltage

V_IL

All

2.4

0.8

±1

2.4

0.8

±10

13.5

1.5

±1

13.5

1.5

V min

V max

µA max

Input Current

I_IN

±10

V_IN= 0 or V_DD

Input Capacitance

DB0–DB7

WR, CS, DAC A/DAC B

All

pF max

SWITCHING CHARACTERISTICS³

See Timing Diagram

Chip Select to Write Set Up Time

t_CS

Chip Select to Write Hold Time

t_CH

DAC Select to Write Set Up Time

t_AS

DAC Select to Write Hold Time

t_AH

Data Valid to Write Set Up Time

t_DS

Data Valid to Write Hold Time

t_DH

Write Pulsewidth

t_WR

All

100

ns min

100

POWER SUPPLY

I_DD

See Figure 3

All Digital Inputs V_ILor V_IH

All Digital Inputs 0 V or V_DD

All

100

500

100

500

mA max

µA max

(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as

Output Amplifiers)

AC PERFORMANCE CHARACTERISTICS⁵

V_DD= +5 V

V_DD= +15 V

Parameter

Version¹T_A= +25°C T_MIN, T_MAXT_A= +25°C T_MIN, T_MAXUnits

Test Conditions/Comments

% per % max ∆V_DD= ±5%

DC SUPPLY REJECTION (∆GAIN/∆V_DD

CURRENT SETTLING TIME²

)

All

0.02

350

0.04

400

0.01

180

0.02

200

ns max

To 1/2 LSB. OUT A/OUT B Load = 100 Ω.

WR = CS = 0 V. DB0–DB7 = 0 V to V_DDor

V_DDto 0 V

PROPAGATION DELAY (From Digital In-

put to 90% of Final Analog Output Current) All

V_REFA = V_REFB = +10 V

220

160

270

100

ns max

OUT A, OUT B Load = 100 Ω C_EXT= 13 pF

WR = CS = 0 V DB0–DB7 = 0 V to V_DDor

V_DDto 0 V

DIGITAL-TO-ANALOG GLITCH IMPULSE All

OUTPUT CAPACITANCE

440

nV sec typ

For Code Transition 00000000 to 11111111

C_OUT

All

120

pF max

DAC Latches Loaded with 00000000

DAC Latches Loaded with 11111111

AC FEEDTHROUGH⁶

V_REFA to OUT A

V_REFB to OUT B

All

–70

–65

–70

–65

dB max

V_REFA, V_REFB = 20 V p-p Sine Wave

@ 100 kHz

–2–

REV. B

AD7528

V_DD= +5 V

V_DD= +15 V

Parameter

Version¹T_A= +25°C T_MIN, T_MAXT_A= +25°C T_MIN, T_MAXUnits

Test Conditions/Comments

CHANNEL-TO-CHANNEL ISOLATION

V_REFA to OUT B

Both DAC Latches Loaded with 11111111.

V_REFA = 20 V p-p Sine Wave @ 100 kHz

V_REFB = 0 V see Figure 6.

V_REFA = 20 V p-p Sine Wave @ 100 kHz

V_REFA = 0 V see Figure 6.

All

–77

dB typ

V_REFB to OUT A

DIGITAL CROSSTALK

All

nV sec typ

dB typ

Measured for Code Transition 00000000 to

11111111

HARMONIC DISTORTlON

NOTES

–85

V_IN= 6 V rms @ 1 kHz

¹Temperature Ranges are J, K, L Versions: –40°C to +85°C

A, B, C Versions: –40°C to +85°C

AD7528, ideal maximum output is V_REF– 1 LSB. Gain error of

both DACs is adjustable to zero with external resistance.

S, T, U Versions: –55°C to +125°C

²Specifications applies to both DACs in AD7528.

³Guaranteed by design but not production tested.

Output Capacitance

Capacitance from OUT A or OUT B to AGND.

⁴Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA.

⁵These characteristics are for design guidance only and are not subject to test.

⁶Feedthrough can be further reduced by connecting the metal lid on the ceramic package

(suffix D) to DGND.

Digital to Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the

analog output when the inputs change state. This is normally

specified as the area of the glitch in either pA-secs or nV-secs

depending upon whether the glitch is measured as a current or

voltage signal. Glitch impulse is measured with V_REFA,

V_REFB = AGND.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

(T_A= +25°C unless otherwise noted)

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

V_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V_DD+ 0.3 V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V_DD+ 0.3 V

V_PIN2, V_PIN20to AGND . . . . . . . . . . . . . . –0.3 V, V_DD+ 0.3 V

V_REFA, V_REFB to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

V_RFBA, V_RFBB to AGND . . . . . . . . . . . . . . . . . . . . . . . ±25 V

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Propagation Delay

This is a measure of the internal delays of the circuit and is

defined as the time from a digital input change to the analog

output current reaching 90% of its final value.

Channel-to-Channel Isolation

The proportion of input signal from one DAC’s reference input

which appears at the output of the other DAC, expressed as a

ratio in dB.

Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C

Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C

Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C

Digital Crosstalk

The glitch energy transferred to the output of one converter due

to a change in digital input code to the other converter. Speci-

fied in nV secs.

PIN CONFIGURATIONS

PLCC

CAUTION:

1. ESD sensitive device. The digital control inputs are diode

protected; however, permanent damage may occur on uncon-

nected devices subjected to high energy electrostatic fields.

Unused devices must be stored in conductive foam or shunts.

20 19

2. Do not insert this device into powered sockets. Remove

power before insertion or removal.

PIN 1

IDENTIFIER

REF

DGND

AD7528

TOP VIEW

(Not to Scale)

DAC A/DAC B

(MSB) DB7

DB6

TERMINOLOGY

Relative Accuracy

DB0 (LSB)

Relative accuracy or endpoint nonlinearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

adjusting for zero and full scale and is normally expressed in

LSBs or as a percentage of full scale reading.

10 11 12 13

DIP, SOIC

OUT B

AGND

OUT A

Differential Nonlinearity

REF

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB max over

the operating temperature range ensures monotonicity.

REF

DGND

AD7528

TOP VIEW

(Not to Scale)

DAC A/DAC B

(MSB) DB7

DB6

DB0 (LSB)

DB1

Gain Error

Gain error or full-scale error is a measure of the output error

between an ideal DAC and the actual device output. For the

DB2

DB5

DB4

DB3

REV. B

–3–

AD7528

INTERFACE LOGIC INFORMATION

DAC Selection:

Both DAC latches share a common 8-bit input port. The con-

trol input DAC A/DAC B selects which DAC can accept data

from the input port.

Figure 1. An inverted R-2R ladder structure is used, that is, bi-

nary weighted currents are switched between the DAC output

and AGND thus maintaining fixed currents in each ladder leg

independent of switch state.

EQUIVALENT CIRCUIT ANALYSIS

Mode Selection:

Inputs CS and WR control the operating mode of the selected

DAC. See Mode Selection Table below.

Figure 2 shows an approximate equivalent circuit for one of the

AD7528’s D/A converters, in this case DAC A. A similar

equivalent circuit can be drawn for DAC B. Note that AGND

(Pin 1) is common for both DAC A and DAC B.

Write Mode:

When CS and WR are both low the selected DAC is in the write

mode. The input data latches of the selected DAC are transpar-

ent and its analog output responds to activity on DB0–DB7.

The current source I_LEAKAGEis composed of surface and junc-

tion leakages and, as with most semiconductor devices, approxi-

mately doubles every 10°C. The resistor R_Oas shown in Figure

2 is the equivalent output resistance of the device which varies

with input code (excluding all 0s code) from 0.8 R to 2 R. R is

typically 11 kΩ. C_OUTis the capacitance due to the N-channel

switches and varies from about 50 pF to 120 pF depending

upon the digital input. g(V_REFA, N) is the Thevenin equivalent

voltage generator due to the reference input voltage V_REFA and

the transfer function of the R-2R ladder.

Hold Mode:

The selected DAC latch retains the data which was present on

DB0–DB7 just prior to CS or WR assuming a high state. Both

analog outputs remain at the values corresponding to the data in

their respective latches.

Mode Selection Table

DAC A/DAC B

DAC A

DAC B

WRITE

HOLD

WRITE

HOLD

OUT A

g(V

A, N)

OUT

REF

HOLD

LKG

AGND

L = Low State; H = High State; X = Don’t Care.

Figure 2. Equivalent Analog Output Circuit of DAC A

WRITE CYCLE TIMING DIAGRAM

CIRCUIT INFORMATION–DIGITAL SECTION

t_CH

t_CS

The input buffers are simple CMOS inverters designed such

that when the AD7528 is operated with V_DD= 5 V, the buffer

converts TTL input levels (2.4 V and 0.8 V) into CMOS logic

levels. When V_INis in the region of 2.0 volts to 3.5 volts the

input buffers operate in their linear region and pass a quiescent

current, see Figure 3. To minimize power supply currents it is

recommended that the digital input voltages be as close to the

supply rails (V_DDand DGND) as is practically possible.

CHIP SELECT

t_AH

t_AS

DAC A/DAC B

t_WR

WRITE

t_DS

t_DH

DATA IN

(DB0 – DB7)

DATA IN STABLE

The AD7528 may be operated with any supply voltage in the

range 5 ≤ V_DD≤ 15 volts. With V_DD= +15 V the input logic

levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.

NOTES:

1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED

FROM 10% TO 90% OF V

= +5V, t = t = 20ns;

= +15V, t = t = 40ns;

r f

+ V

2. TIMING MEASUREMENT REFERENCE LEVEL IS

= +15V

800

700

600

500

400

300

200

100

= +25؇C

ALL DIGITAL INPUTS

TIED TOGETHER

CIRCUIT INFORMATION—D/A SECTION

The AD7528 contains two identical 8-bit multiplying D/A con-

verters, DAC A and DAC B. Each DAC consists of a highly

stable thin film R-2R ladder and eight N-channel current steer-

ing switches. A simplified D/A circuit for DAC A is shown in

= +5V

REF

10 11 12 13 14

– Volts

OUT A

AGND

Figure 3. Typical Plots of Supply Current, I_DDvs. Logic

Input Voltage V_IN, for V_DD= +5 V and +15 V

DAC A DATA LATCHES

AND DRIVERS

Figure 1. Simplified Functional Circuit for DAC A

–4–

REV. B

AD7528

(± 10V)

Table I. Unipolar Binary Code Table

DAC Latch Contents Analog Output

MSB

LSB

(DAC A or DAC B)

255

–V_IN

DB0

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

INPUT

BUFFER

DATA

INPUTS

256

DAC A

OUTA

AGND

LATCH

OUT

DB7

129

–V_IN

AGND

256

AD7528

V_IN

128

256

DAC A/

–V_IN

= −

DAC B

CONTROL

LOGIC

127

256

OUT B

LATCH

DAC B

OUT

DGND

256

AGND

256

= 0

(± 10V)

NOTES:

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

SEE TABLE III FOR RECOMMENDED VALUES.

C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN

USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.

256

2⁻⁸

(

)

(

Note: 1 LSB =

)

(

Figure 4. Dual DAC Unipolar Binary Operation

(2 Quadrant Multiplication); See Table I

Table II. Bipolar (Offset Binary) Code Table

DAC Latch Contents Analog Output

(± 10V)

20k⍀

MSB

LSB

(DAC A or DAC B)

OUT

10k⍀

127

+V_IN

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

128

R11

5k⍀

DB0

INPUT

BUFFER

DATA

INPUTS

AGND

DAC A

OUTA

AGND

LATCH

DB7

AGND

AD7528

DAC A/

–V_IN

DAC B

CONTROL

LOGIC

128

20k⍀

LATCH

DAC B

OUT B

AGND

127

–V_IN

DGND

128

10k⍀

128

–V_IN

R10

OUT

128

20k⍀

R12

128

2⁻⁷

(

)

(

5k⍀

Note: 1 LSB =

)

(

AGND

(± 10V)

NOTES:

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

SEE TABLE III FOR RECOMMENDED VALUES.

ADJUST R1 FOR V

ADJUST R3 FOR V

MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R6, R7 AND R9, R10.

C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED

IF A1/A3 IS A HIGH SPEED AMPLIFIER.

A = 0V WITH CODE 10000000 IN DAC A LATCH.

B = 0V WITH CODE 10000000 IN DAC B LATCH.

OUT

Table III. Recommended Trim Resistor

Values vs. Grade

Trim

Resistor

Figure 5. Dual DAC Bipolar Operation

(4 Quadrant Multiplication); See Table II

J/A/S

K/B/T

L/C/U

R1; R3

R2; R4

1 k

330

500

150

200

REV. B

–5–

AD7528

APPLICATIONS INFORMATION

Application Hints

To ensure system performance consistent with AD7528 specifi-

cations, careful attention must be given to the following points:

ship between input frequency and channel to channel isolation.

Figure 7 shows a printed circuit layout for the AD7528 and the

AD644 dual op amp which minimizes feedthrough and crosstalk.

SINGLE SUPPLY APPLICATIONS

1. GENERAL GROUND MANAGEMENT: AC or transient

voltages between the AD7528 AGND and DGND can cause

noise injection into the analog output. The simplest method

of ensuring that voltages at AGND and DGND are equal is

to tie AGND and DGND together at the AD7528. In more

complex systems where the AGND–DGND intertie is on the

backplane, it is recommended that diodes be connected in

inverse parallel between the AD7528 AGND and DGND

pins (1N914 or equivalent).

2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a

code-dependent output resistance which in turn causes a

code-dependent amplifier noise gain. The effect is a code-

dependent differential nonlinearity term at the amplifier

output which depends on V_OS(V_OSis amplifier input offset

voltage). This differential nonlinearity term adds to the R/2R

differential nonlinearity. To maintain monotonic operation, it

is recommended that amplifier V_OSbe no greater than 10% of

1 LSB over the temperature range of interest.

The AD7528 DAC R-2R ladder termination resistors are con-

nected to AGND within the device. This arrangement is par-

ticularly convenient for single supply operation because AGND

may be biased at any voltage between DGND and V_DD. Figure

8 shows a circuit which provides two +5 V to +8 V analog out-

puts by biasing AGND +5 V up from DGND. The two DAC

reference inputs are tied together and a reference input voltage

is obtained without a buffer amplifier by making use of the

constant and matched impedances of the DAC A and DAC B

reference inputs. Current flows through the two DAC R-2R

ladders into R1 and R1 is adjusted until the V_REFA and V_REF

inputs are at +2 V. The two analog output voltages range from

+5 V to +8 V for DAC codes 00000000 to 11111111.

= +15V

DAC A

A = +5V TO +8V

B = +5V TO +8V

OUT

DB0

DB7

DATA

INPUTS

SUGGESTED

OP AMP:

AD644

3. HIGH FREQUENCY CONSIDERATIONS: The output

capacitance of a CMOS DAC works in conjunction with the

amplifier feedback resistance to add a pole to the open loop

response. This can cause ringing or oscillation. Stability can

be restored by adding a phase compensation capacitor in

parallel with the feedback resistor.

AD7528

DAC B

DAC A/DAC B

OUT

2 VOLTS

10k⍀

AD584J

1k⍀

GND

DYNAMIC PERFORMANCE

The dynamic performance of the two DACs in the AD7528 will

depend upon the gain and phase characteristics of the output

amplifiers together with the optimum choice of the PC board

layout and decoupling components. Figure 6 shows the relation

Figure 8. AD7528 Single Supply Operation

Figure 9 shows DAC A of the AD7528 connected in a positive

reference, voltage switching mode. This configuration is useful

in that V_OUTis the same polarity as V_INallowing single supply

operation. However, to retain specified linearity, V_INmust be in

the range 0 V to +2.5 V and the output buffered or loaded with

a high impedance, see Figure 10. Note that the input voltage is

connected to the DAC OUT A and the output voltage is taken

from the DAC V_REFA pin.

–100

= +25؇C

= +15V

–90

–80

–70

–60

–50

= 20V PEAK TO PEAK

OUT

(0V TO +2.5V)

REF

DAC A

OUT A

+15V

AD7528

20k

50k

100k

200k

500k

INPUT FREQUENCY – Hz

Figure 9. AD7528 in Single Supply, Voltage Switching Mode

Figure 6. Channel-to-Channel Isolation

PIN 8 OF TO-5 CAN (AD644)

AD644

V+

= +25؇C

= +15V

V–

NONLINEARITY

AGND

AD7528 PIN 1

C1 LOCATION

*NOTE

INPUT SCREENS

TO REDUCE

FEEDTHROUGH.

LAYOUT SHOWS

COPPER SIDE

C2 LOCATION

REF

DIFFERENTIAL

NONLINEARITY

REF

DGND

DAC A/DAC B

MSB

AD7528

(i.e., BOTTOM VIEW).

LSB

2.5

3.5

4.5

5.5

6.5

7.5

A – Volts

Figure 7. Suggested PC Board Layout for AD7528 with

AD644 Dual Op Amp

Figure 10. Typical AD7528 Performance in Single Supply

Voltage Switching Mode (K/B/T, L/C/U Grades)

–6–

REV. B

AD7528

MICROPROCESSOR INTERFACE

ADDRESS BUS

A8–A15

A**

ADDRESS BUS

A0–A15

DAC A/DAC B

ADDRESS

DECODE

LOGIC

CPU

8085

A**

DAC A

DAC A/DAC B

ADDRESS

DECODE

LOGIC

A + 1**

DB0

DB7

AD7528*

DAC A

CPU

6800

LATCH

8212

A + 1**

DAC B

ALE

AD7528*

␾2

DB0

DB7

DAC B

ADDR/DATA BUS

AD0–AD7

*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY

**A = DECODED 7528 ADDR DAC A

A + 1 = DECODED 7528 ADDR DAC B

D0–D7

DATA BUS

*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY

**A = DECODED 7528 ADDR DAC A

A + 1 = DECODED 7528 ADDR DAC B

NOTE:

8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE

BOTH DACs WITH DATA FROM H AND L REGISTERS

Figure 11. AD7528 Dual DAC to 6800 CPU Interface

Figure 12. AD7528 Dual DAC to 8085 CPU Interface

PROGRAMMABLE WINDOW COMPARATOR

In the circuit of Figure 13 the AD7528 is used to implement a

programmable window comparator. DACs A and B are loaded

with the required upper and lower voltage limits for the test,

respectively. If the test input is not within the programmed

limits, the pass/fail output will indicate a fail (logic zero).

TEST INPUT

0 TO –V

REF

1k⍀

OUT A

REF

DAC A

DB0

DB7

DATA

INPUTS

AD311

COMPARATOR

AD7528

PASS/ FAIL

OUTPUT

OUT B

DAC A/DAC B

DAC B

REF

AD311

COMPARATOR

Figure 13. Digitally Programmable Window Comparator

(Upper and Lower Limit Detector)

PROGRAMMABLE STATE VARIABLE FILTER

In this state variable or universal filter configuration (Figure 14)

DACs A1 and B1 control the gain and Q of the filter character-

istic while DACs A2 and B2 control the cutoff frequency, f_C.

DACs A2 and B2 must track accurately for the simple expres-

sion for f_Cto hold. This is readily accomplished by the AD7528.

Op amps are 2 × AD644. C3 compensates for the effects of op

amp gain bandwidth limitations.

The filter provides low pass, high pass and band pass outputs

and is ideally suited for applications where microprocessor

control of filter parameters is required, e.g., equalizer, tone

controls, etc.

Programmable range for component values shown is f_C= 0 kHz

to 15 kHz and Q = 0.3 to 4.5.

30k⍀

CIRCUIT EQUATIONS

C1= C2,R1= R2, R4 = R5

1000pF

30k⍀

47pF

10k⍀

HIGH

f_C=

LOW

PASS

2 π R1C1

OUTPUT

BAND

R3 R_F

PASS

Q =

OUTPUT

R4 R_FBB1

AD7528

DAC A1

R_F

R_S

A_O= –

DAC B1

DAC A2

DAC B2

AD7528

NOTE

DAC Equivalent Resistance

Equals

DB0–DB7

DATA 1

DB0–DB7

DATA 2

CS WR DAC A/DAC B

256 ×(DAC Ladder esistance)

DAC Digital Code

Figure 14. Digitally Controlled State Variable Filter

–7–

REV. B

AD7528

DIGITALLY CONTROLLED DUAL TELEPHONE

ATTENUATOR

In this configuration the AD7528 functions as a 2-channel digi-

tally controlled attenuator. Ideal for stereo audio and telephone

signal level control applications. Table IV gives input codes vs.

attenuation for a 0 dB to 15.5 dB range.

Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit

of Figure 15

Attn. DAC Input

Code In Attn. DAC Input

Decimal dB Code

Code In

Decimal

Code

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

1 1 1 1 1 1 1 1

1 1 1 1 0 0 1 0

1 1 1 0 0 1 0 0

1 1 0 1 0 1 1 1

1 1 0 0 1 0 1 1

1 1 0 0 0 0 0 0

1 0 1 1 0 1 0 1

1 0 1 0 1 0 1 1

1 0 1 0 0 0 1 0

1 0 0 1 1 0 0 0

1 0 0 1 0 0 0 0

1 0 0 0 1 0 0 0

1 0 0 0 0 0 0 0

0 1 1 1 1 0 0 1

0 1 1 1 0 0 1 0

0 1 1 0 1 1 0 0

255

242

228

215

203

192

181

171

162

152

144

136

128

121

114

108

88.0 0 1 1 0 0 1 1 0

88.5 0 1 1 0 0 0 0 0

89.0 0 1 0 1 1 0 1 1

89.5 0 1 0 1 0 1 1 0

10.0 0 1 0 1 0 0 0 1

10.5 0 1 0 0 1 1 0 0

11.0 0 1 0 0 1 0 0 0

11.5 0 1 0 0 0 1 0 0

12.0 0 1 0 0 0 0 0 0

12.5 0 0 1 1 1 1 0 1

13.0 0 0 1 1 1 0 0 1

13.5 0 0 1 1 0 1 1 0

14.0 0 0 1 1 0 0 1 1

14.5 0 0 1 1 0 0 0 0

15.0 0 0 1 0 1 1 1 0

15.5 0 0 1 0 1 0 1 1

102

Attenuation, dB

−

Input Code = 256 ϫ 10 exp

DAC A

OUT

DB0

DB7

DATA BUS

DAC A/DAC B

AD7528

DAC B

OUT

SUGGESTED

OP AMP: AD644

For further applications information the reader is referred to

Analog Devices Application Note on the AD7528.

Figure 15. Digitally Controlled Dual Telephone Attenuator

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Cerdip (Q-20)

20-Lead Plastic DIP (N-20)

1.07 (27.18) MAX

0.28 (7.11)

PIN 1

0.255 (6.477)

0.24 (6.1)

0.245 (6.223)

0.32 (8.128)

0.30 (7.62)

0.32 (8.128)

0.29 (7.366)

0.97 (24.64)

0.935 (23.75)

0.14 (3.56)

PIN 1

0.135 (3.429)

0.125 (3.17)

0.145 (3.683)

MIN

0.20 (5.0)

0.14 (3.56)

0.125 (3.17)

0.125 (3.175)

MIN

0.15 (3.8)

0.125 (3.18)

SEATING

PLANE

SEATING

PLANE

0.011 (0.28)

0.009 (0.23)

0.011 (0.28)

0.009 (0.23)

0.11 (2.79)

0.09 (2.28)

0.065 (1.66)

0.045 (1.15)

0.021 (0.533)

0.015 (0.381)

15؇

0؇

0.07 (1.78) 0.02 (0.5) 0.11 (2.79)

0.05 (1.27) 0.016 (0.41) 0.09 (2.28)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

15؇

0؇

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42

20-Lead SOIC (R-20)

20-Lead Plastic Leaded Chip Carrier (P-20A)

0.5118 (13.00)

0.4961 (12.60)

0.180 (4.47)

0.165 (4.19)

0.395 (10.02)

0.385 (9.78)

0.12 (3.05)

0.09 (2.29)

0.020 (0.51) MIN

0.356 (9.04)

0.350 (8.89)

0.2992 (7.60)

0.2914 (7.40)

0.048 (1.21)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

0.4193 (10.65)

0.3937 (10.00)

0.050

(1.27)

BSC

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

0.02

(0.51)

MAX

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

45؇

0.025 (0.64)

MIN

0.02 (0.51)

MAX

0.060 (1.53)

MIN

8؇

0؇

0.0500 0.0192 (0.49)

0.0118 (0.30)

0.0040 (0.10)

0.0500 (1.27)

0.0157 (0.40)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

(1.27)

BSC

0.0138 (0.35)

–8–

REV. B

AD7528SQ [ADI]

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