AD7538JR [ADI]
LC2MOS uP-Compatible 14-Bit DAC; LC2MOS向上兼容的14位DAC
| 型号： | AD7538JR |
| 厂家： | 
ADI |
| 描述： | LC2MOS uP-Compatible 14-Bit DAC |
| 文件： | 总8页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
P-Compatible 14-Bit DAC
a
AD7538
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
All Grades 14-Bit Monotonic Over the Full Tem perature
Range
Low Cost 14-Bit Upgrade for 12-Bit System s
14-Bit Parallel Load w ith Double Buffered Inputs
Sm all 24-Pin, 0.3؆ DIP and SOIC
Low Output Leakage (<20 nA) Over the Full
Tem perature Range
APPLICATIONS
Microprocessor Based Control System s
Digital Audio
Precision Servo Control
Control and Measurem ent in High Tem perature
Environm ents
P RO D UCT H IGH LIGH TS
GENERAL D ESCRIP TIO N
1. Guaranteed Monotonicity
T he AD7538 is a 14-bit monolithic CMOS D/A converter
which uses laser trimmed thin-film resistors to achieve excellent
linearity.
T he AD7538 is guaranteed monotonic to 14-bits over the
full temperature range for all grades.
2. Low Cost
T he DAC is loaded by a single 14-bit wide word using standard
Chip Select and Memory Write Logic. Double buffering, which
is optional using LDAC, allows simultaneous update in a sys-
tem containing multiple AD7538s.
T he AD7538, with its 14-bit dynamic range, affords a low
cost solution for 12-bit system upgrades.
3. Small Package Size
T he AD7538 is packaged in a small 24-pin, 0.3" DIP and a
24-pin SOIC.
A novel low leakage configuration (U.S. Patent No. 4,590,456)
enables the AD7538 to exhibit excellent output leakage current
characteristics over the specified temperature range.
4. Low Output Leakage
By tying VSS (Pin 24) to a negative voltage, it is possible to
achieve a low output leakage current at high temperatures.
T he AD7538 is manufactured using the Linear Compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts T T L or CMOS logic level inputs.
5. Wide Power Supply T olerance
T he device operates on a +12 V to +15 V VDD, with a ±5%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
2
(V = +11.4 V to +15.75 V , V = +10 V; VPIN3 = VPIN4 = 0 V,
1
DD
REF
AD7538–SPECIFICATIONS
V = –300 mV. All specifications TMIN to TMAX unless otherwise noted.)
SS
J, K
A, B
P aram eter
Versions
Versions
S Version T Version
Units
Test Conditions/Com m ents
ACCURACY
Resolution
14
±2
±1
14
±1
±1
14
±2
±1
14
±1
±1
Bits
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
+25°C
All Grades Guaranteed Monotonic
Over T emperature.
Measured Using Internal RFB DAC
Registers Loaded with All 1s.
±4
±8
±4
±5
±4
±10
±4
±6
LSB max
LSB max
T MIN to T MAX
Gain T emperature Coefficient3;
∆Gain/∆T emperature
Output Leakage Current IOUT (Pin 3)
+25°C
T MIN to T MAX
T MIN to T MAX
±2
±2
±2
±2
ppm/°C typ
±5
±10
±25
±5
±10
±25
±5
±20
±150
±5
±20
±150
nA max
nA max
nA max
All Digital Inputs 0 V
VSS = –300 mV
VSS = 0 V
REFERENCE INPUT
Input Resistance, Pin 1
3.5
10
3.5
10
3.5
10
3.5
10
kΩ min
kΩ max
T ypical Input Resistance = 6 kΩ
DIGIT AL INPUT S
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN (Input Current)
+25°C
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
V min
V max
±1
±10
7
±1
±10
7
±1
±10
7
±1
±10
7
µA max
µA max
pF max
VIN = 0 V or VDD
T MIN to T MAX
CIN (Input Capacitance)3
POWER SUPPLY
VDD Range
VSS Range
IDD
11.4/15.75
–200/–500
4
11.4/15.75
–200/–500
4
11.4/15.75 11.4/15.75
–200/–500 –200/–500
V min/V max
mV min/mV max T his Range
mA max
µA max
Specification Guaranteed Over
4
4
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
500
500
500
500
These characteristics are included for Design Guidance only and are not sub-
ject to test. (V = +11.4 V to +15.75 V, V = +10 V, VPIN3 = VPIN4 = O V, V =
O V or –300 mV, Output Amplifier is AD711 except where noted.)
DD
REF
SS
AC PERFORMANCE CHARACTERISTICS
P aram eter
TA = +25؇C TA = TMIN, TMAX
Units
Test Conditions/Com m ents
Output Current Settling T ime
1.5
µs max
T o 0.003% of Full-Scale Range.
IOUT Load= 100 Ω, CEXT = 13 pF.
DAC Register Alternately Loaded
with All 1s and All 0s. T ypical Value
of Settling T ime Is 0.8 µs.
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
20
nV-sec typ
mV p-p typ
Measured with VREF = 0 V. IOUT Load
= 100 Ω, CEXT = 13 pF. DAC Register
Alternately Loaded with All 1s and All 0s.
3
5
VREF = ±10 V, 10 kHz Sine Wave DAC
Register Loaded with All 0s.
Power Supply Rejection
∆Gain/∆VDD
±0.01
±0.02
% per % max ∆VDD = ±5%
Output Capacitance
COUT (Pin 3)
COUT (Pin 3)
260
130
260
130
pF max
pF max
DAC Register Loaded with All 1s
DAC Register Loaded with All 0s
Output Noise Voltage Density
(10 Hz–100 kHz)
15
nV√Hz typ
Measured Between RFB and IOUT
NOT ES
T emperature range as follows: J, K Versions: 0°C to +70°C
A, B Versions: –25°C to +85°C
S, T Versions: –55°C to +125°C
2Specifications are guaranteed for a VDD of +11.4 V to +15.75 V. At VDD = 5 V, the device is fully functional with degraded specifications.
3Sample tested to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
AD7538
(V = +11.4 V to +15.75 V, V = +10 V, VPIN3 = VPIN4 = 0 V, V = 0 V or –300 mV.
All specifications TMIN to TMAX unless otherwise noted. See Figure 1 for Timing Diagram.)
DD
REF
SS
1
TIMING CHARACTERISTICS
Lim it at
Lim it at
TA = +25؇C
TA = 0؇C to +70؇C
TA = –25؇C to +85؇C
Lim it at
TA = –55؇C to +125؇C
P aram eter
Units
Test Conditions/Com m ents
t1
t2
t3
t4
t5
t6
0
0
170
170
140
20
0
0
200
200
160
20
0
0
240
240
180
30
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup T ime
CS to WR Hold T ime
LDAC Pulse Width
Write Pulse Width
Data Setup T ime
Data Hold T ime
NOT ES
1T emperature range as follows: J, K Versions: 0°C to +70°C
A, B Versions: –25°C to +85°C
S, T Versions: –55°C to +125°C
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
(T A= +25°C unless otherwise stated)
Operating T emperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . . –25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
VDD (Pin 23) to DGND . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VSS (Pin 24) to AGND . . . . . . . . . . . . . . . . . . . –15 V, +0.3 V
VREF (Pin 1) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
VRFB (Pin 2) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
Digital Input Voltage (Pins 6–22)
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
VPIN3 to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Power Dissipation (Any Package)
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
T o +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . 10 mW/°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO N
D IP , SO IC
Figure 1. Tim ing Diagram
REV. A
–3–
AD7538
in Least Significant Bits. Gain error is adjustable to zero with an
external potentiometer.
TERMINO LO GY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after ad-
justing for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage of full-scale
reading.
D IGITAL-TO -ANALO G GLITCH IMP ULSE
T he amount of charge injected from the digital inputs to the
analog output when the inputs change state is called Digital-
to-Analog Glitch Impulse. T his is normally specified as the area
of the glitch in either pA-secs or nV-secs depending upon
whether the glitch is measured as a current or voltage. It is mea-
sured with VREF = AGND.
D IFFERENTIAL NO NLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
O UTP UT CAP ACITANCE
T his is the capacitance from IOUT to AGND.
O UTP UT LEAKAGE CURRENT
Output Leakage Current is current which appears at IOUT with
the DAC register loaded to all 0s.
GAIN ERRO R
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is expressed
MULTIP LYING FEED TH RO UGH ERRO R
T his is the ac error due to capacitive feedthrough from VREF
terminal to IOUT with DAC register loaded to all zeros.
O RD ERING GUID E
Relative
Tem perature
Full-Scale P ackage
Model
Range
Accuracy
Error
O ption*
AD7538JN
AD7538KN
AD7538JR
AD7538KR
AD7538AQ
AD7538BQ
AD7538SQ
AD7538T Q
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±8 LSB
±4 LSB
±8 LSB
±4 LSB
±8 LSB
±4 LSB
±8 LSB
±4 LSB
N-24
N-24
R-24
R-24
Q-24
Q-24
Q-24
Q-24
*N = Plastic DIP; Q = Cerdip; R = SOIC.
P IN FUNCTIO N D ESCRIP TIO N
P in
Mnem onic
D escription
11
VREF
Voltage Reference.
12
13
RFB
IOUT
Feedback Resistor. Used to close the loop around an external op amp.
Current Output T erminal.
14
15
6–19
20
21
AGND
DGND
DB13–DB0
LDAC
CS
Analog Ground
Digital Ground
Data Inputs. Bit 13 (MSB) to Bit 0 (LSB).
Chip Select Input. Active LOW.
Asynchronous Load DAC Input. Active LOW.
Write Input. Active LOW.
22
WR
CS
LDAC
WR
O P ERATIO N
0
1
0
1
X
1
0
0
1
1
0
X
0
X
1
Load Input Register.
Load DAC Register from Input Register.
Input and DAC Registers are T ransparent.
No Operation.
No Operation.
NOT E: X Don’t Care.
23
24
VDD
VSS
+12 V to +15 V supply input.
Bias pin for High T emperature Low Leakage configuration. T o implement low leakage
system, the pin should be at a negative voltage. See Figures 4 and 5 for recommended circuitry.
–4–
REV. A
AD7538
D /A SECTIO N
T he R-2R ladder current is 1/8 of the total reference input cur-
rent. 7/8 I flows in the parallel ladder structure. Switches A-G
steer equally weighted currents between IOUT and AGND.
Figure 2 shows a simplified circuit diagram for the AD7538
D/A section. T he three MSBs of the 14-bit Data Word are de-
coded to drive the seven switches A-G. T he 11 LSBs of the
Data Word consist of an R-2R ladder operated in a current
steering configuration.
Since the input resistance at VREF is constant, it may be driven
by a voltage source or a current source of positive or negative
polarity.
CIRCUIT INFO RMATIO N
Figure 2. Sim plified Circuit Diagram for the AD7538 D/A Section
EQ UIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent circuit for the analog section of
the AD7538 D/A converter. T he current source ILEAKAGE is
composed of surface and junction leakages. T he resistor RO
denotes the equivalent output resistance of the DAC which
varies with input code. COUT is the capacitance due to the cur-
rent steering switches and varies from about 90 pF to 180 pF
(typical values) depending upon the digital input. g(VREF, N) is
the T hevenin equivalent voltage generator due to the reference
input voltage, VREF, and the transfer function of the DAC
ladder, N.
Figure 4. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD 7538
Binary Num ber In
Figure 3. AD7538 Equivalent Analog Output Circuit
D AC Register
Analog O utput, VO UT
D IGITAL SECTIO N
MSB
LSB
T he digital inputs are designed to be both T T L and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. T o minimize power
supply currents, it is recommended that the digital input volt-
ages be driven as close as possible to 0 V and 5 V logic levels.
16383
–VIN
11 1111 1111 1111
16384
8192
16384
–VIN
–VIN
= –1/2VIN
10 0000 0000 0000
UNIP O LAR BINARY O P ERATIO N (2-Q UAD RANT
MULTIP LICATIO N)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2 quadrant multipli-
cation. T he code table for Figure 4 is given in T able I.
1
00 0000 0000 0001
00 0000 0000 0000
16384
0 V
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
REV. A
–5–
AD7538
For zero offset adjustment, the DAC register is loaded with all
0s and amplifier offset (VOS) adjusted so that VOUT is 0 V. Ad-
justing VOUT to 0 V is not necessary in many applications, but it
Table II. Bipolar Code Table for O ffset Binary Circuit of
Figure 5.
is recommended that VOS be no greater than (25 × 10–6) (VREF
)
Binary Num ber In
D AC Register
Analog O utput VO UT
to maintain specified DAC accuracy (see Applications Hints).
MSB
LSB
Full-scale trimming is accomplished by loading the DAC register
with all 1s and adjusting R1 so that VOUTA = –VIN (16383/16384).
For high temperature operation, resistors and potentiometers
should have a low T emperature Coefficient. In many applica-
tions, because of the excellent Gain T .C. and Gain Error speci-
fications of the AD7538, Gain Error trimming is not necessary.
In fixed reference applications, full scale can also be adjusted
by omitting R1 and R2 and trimming the reference voltage
magnitude.
8191
+VIN
11 1111 1111 1111
8192
1
+VIN
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
8192
0 V
BIP O LAR O P ERATIO N
(4-Q UAD RANT MULTIP LICATIO N)
T he recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used. T he code table
for Figure 5 is given in T able II.
1
–VIN
8192
8191
–VIN
00 0000 0000 0000
8192
With the DAC loaded to 10 0000 0000 0000, adjust R1 for
VO = 0 V. Alternatively, one can omit R1 and R2 and adjust the
ratio of R5 and R6 for VO = 0 V. Full-scale trimming can be
accomplished by adjusting the amplitude of VIN or by varying
the value of R7.
VSS should be tied to a voltage of approximately –0.3 V as in
Figures 4 and 5. A simple resistor divider (R3, R4) produces ap-
proximately –300 mV from –15 V. T he capacitor C2 in parallel
with R3 is an integral part of the low leakage configuration and
must be 4.7 µF or greater. Figure 6 is a plot of leakage current
versus temperature for both conditions. It clearly shows the im-
provement gained by using the low leakage configuration.
T he values given for R1, R2 are the minimum necessary to cali-
brate the system for resistors, R5, R6, R7 ratio matched to 0.1%.
System linearity error is independent of resistor ratio matching
and is affected by DAC linearity error only.
When operating over a wide temperature range, it is important
that the resistors be of the same type so that their temperature
coefficients match.
For further information sec “CMOS DAC Application Guide”,
3rd Edition, Publication Number G872b-8-1/89 available from
Analog Devices.
Figure 6. Graph of Typical Leakage Current vs.
Tem perature for AD7538
P RO GRAMMABLE GAIN AMP LIFIER
T he circuit shown in Figure 7 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
Figure 5. Bipolar Operation
LO W LEAKAGE CO NFIGURATIO N
For CMOS Multiplying D/A converters, as the device is oper-
ated at higher temperatures, the output leakage current in-
creases. For a 14-bit resolution system, this can be a significant
source of error. T he AD7538 features a leakage reduction con-
figuration (U.S. Patent No. 4,590,456) to keep the leakage cur-
rent low over an extended temperature range. One may operate
the device with or without this configuration. If VSS (Pin 24) is
tied to AGND then the DAC will exhibit normal output leakage
current at high temperatures. T o use the low leakage facility,
Figure 7. Program m able Gain Am plifier (PGA)
–6–
REV. A
AD7538
T he transfer function of Figure 7 is:
MICRO P RO CESSO R INTERFACING
T he AD7538 is designed for easy interfacing to 16-bit micro-
processors and can be treated as a memory mapped peripheral.
T his reduces the amount of external logic needed for interfacing
to a minimal.
REQ
RFB
VOUT
VIN
Gain =
= –
(1)
REQ is the equivalent transfer impedance of the DAC from the
VREF pin to the IOUT pin and can be expressed as
AD 7538-8086 INTERFACE
Figure 8 shows the 8086 processor interface to a single device.
In this setup the double buffering feature (using LDAC) of the
DAC is not used. T he 14-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
2n RIN
N
REQ
=
(2)
Where: n is the resolution of the DAC
Where: N is the DAC input code in decimal
Where: RIN is the constant input impedance
Where: of the DAC (RIN = RLAD
)
Substituting this expression into Equation 1 and assuming zero
gain error for the DAC (RIN = RFB) the transfer function simpli-
fies to
VOUT
VIN
2n
N
= –
(3)
T he ratio N/2n is commonly represented by the term D and, as
such, is the fractional representation of the digital input word.
Figure 8. AD7538-8086 Interface Circuit
In a multiple DAC system the double buffering of the AD7538
allows the user to simultaneously update all DACs. In Figure 9,
a 14-bit word is loaded to the Input Registers of each of the
DACs in sequence. T hen, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought low, updating all the
DACs simultaneously.
VOUT
VIN
–2n –1
= –
=
(4)
N
D
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. T he all 0s code is never applied. T his avoids an open-
loop condition thereby saturating the amplifier. With the all 0s
code excluded there remains 2n – 1 possible input codes allow-
ing a choice of 2n – 1 output levels. In dB terms the dynamic
range is
VOUT
VIN
20 log10
= 20 log10 (2n –1) = 84 dB.
AP P LICATIO N H INTS
O utput O ffset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. T he maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on VOS, where
VOS is the amplifier input offset voltage. T o maintain specified
accuracy with VREF at 10 V, it is recommended that VOS be no
greater than 0.25 mV, or (25 × 10–6) (VREF), over the tempera-
ture range of operation. T he AD711 is a suitable op amp. T he
op amp has a wide bandwidth and high slew rate and is recom-
mended for ac and other applications requiring fast settling.
Gener al Gr ound Managem ent: Since the AD7538 is speci-
fied for high accuracy, it is important to use a proper grounding
technique. AC or transient voltages between AGND and
DGND can cause noise injection into the analog output. T he
simplest method of ensuring that voltages at AGND and
DGND are equal is to tie AGND and DGND together at the
AD7538. In more complex systems where the AGND and
DGND intertie is on the backplane, it is recommended that two
diodes be connected in inverse parallel between the AD7538
AGND and DGND pins (1N914 or equivalent).
Figure 9. AD7538-8086 Interface: Multiple DAC System
REV. A
–7–
AD7538
AD 7538-MC68000 INTERFACE
microprocessor bus in the preceding interface configurations.
T hese inputs will be constantly changing even when the device
is not selected. T he high frequency logic activity on the bus can
feed through the DAC package capacitance to show up as noise
on the analog output. T o minimize this Digital Feedthrough
isolate the DAC from the noise source. Figure 11 shows an in-
terface circuit which uses this technique. All data inputs are
latched from the bus by the CS signal. One may also use other
means, such as peripheral interface devices, to reduce the Digi-
tal Feedthrough.
Figure 10 shows the MC68000 processor interface to a single
device. In this setup the double buffering feature of the DAC is
not used and the appropriate data is written into the DAC in
one MOVE instruction.
Figure 10. AD7538-MC68000 Interface
D IGITAL FEED TH RO UGH
T he digital inputs to the AD7538 are directly connected to the
Figure 11. AD7538 Interface Circuit Using Latches to
Minim ize Digital Feedthrough
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic Suffix (N)
24-P in Cerdip (Suffix Q)
–8–
REV. A
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