AD7608BSTZ [ADI]
8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC; 8通道DAS，内置18位，双极性，同步采样ADC
| 型号： | AD7608BSTZ |
| 厂家： | 
ADI |
| 描述： | 8-Channel DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC |
| 文件： | 总32页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel DAS with 18-Bit, Bipolar,
Simultaneous Sampling ADC
Data Sheet
AD7608
FEATURES
APPLICATIONS
8 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±± V
Single ± V analog supply and 2.3 V to ±.2± V VDRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Power line monitoring and protection systems
Multiphase motor controls
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
18-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Pin compatible solutions from 14-bits to 18-bits
Performance
7 kV ESD rating on analog input channels
98 dB SNR, −107 dB THD
Low power: 100 mW
Standby mode: 2± mW
64-lead LQFP package
COMPANION PRODUCTS
External References: ADR421, ADR431
Digital Isolators: ADuM1402, ADuM±000, ADuM±402
Voltage Regulator Design Tool: ADIsimPower, Supervisor
Parametric Search
Complete list of complements on AD7608 product page
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Single-
Ended
Resolution Inputs
True
Number of
Differential Simultaneous
Inputs
Sampling Channels
18 Bits
16 Bits
AD76081
AD7606
AD7609
8
8
6
4
8
AD7606-6
AD7606-4
AD7607
14 Bits
FUNCTIONAL BLOCK DIAGRAM
AV
CC
AV
CC
REGCAP REGCAP REFCAPB REFCAPA
R
1MΩ
FB
V1
CLAMP
CLAMP
T/H
SECOND
ORDER LPF
V1GND
2.5V
LDO
2.5V
LDO
R
R
FB
FB
1MΩ
1MΩ
REFIN/REFOUT
V2
CLAMP
CLAMP
T/H
T/H
T/H
T/H
T/H
T/H
T/H
SECOND
V2GND
ORDER LPF
R
R
FB
FB
1MΩ
1MΩ
REF SELECT
AGND
2.5V
REF
V3
CLAMP
CLAMP
OS 2
OS 1
OS 0
SECOND
ORDER LPF
V3GND
R
R
FB
FB
1MΩ
1MΩ
V4
CLAMP
CLAMP
D
D
A
B
SECOND
ORDER LPF
OUT
V4GND
SERIAL
R
R
FB
FB
1MΩ
1MΩ
OUT
8:1
MUX
PARALLEL/
SERIAL
RD/SCLK
CS
DIGITAL
FILTER
18-BIT
SAR
V5
CLAMP
CLAMP
INTERFACE
SECOND
ORDER LPF
V5GND
R
R
FB
FB
1MΩ
1MΩ
PAR/SER SEL
V
DRIVE
V6
CLAMP
CLAMP
SECOND
ORDER LPF
PARALLEL
DB[15:0]
V6GND
R
R
FB
FB
1MΩ
1MΩ
AD7608
V7
CLAMP
CLAMP
SECOND
ORDER LPF
V7GND
CLK OSC
R
R
FB
FB
1MΩ
1MΩ
BUSY
CONTROL
INPUTS
V8
CLAMP
CLAMP
SECOND
ORDER LPF
FRSTDATA
V8GND
R
FB
1MΩ
AGND
CONVST A CONVST B RESET RANGE
Figure 1.
1 Patent pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
AD7608
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Details ....................................................................... 19
Analog Input ............................................................................... 19
ADC Transfer Function............................................................. 20
Internal/External Reference...................................................... 21
Typical Connection Diagram ................................................... 22
Power-Down Modes .................................................................. 22
Conversion Control ................................................................... 23
Digital Interface.............................................................................. 24
Applications....................................................................................... 1
Companion Products....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
PAR
/SER SEL = 0)...................................... 24
Parallel Interface (
PAR
Serial Interface (
/SER SEL = 1)......................................... 25
Reading During Conversion..................................................... 25
Digital Filter ................................................................................ 26
Layout Guidelines....................................................................... 30
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
1/12—Rev. 0 to Rev. A
Changes to Analog Input Ranges Section ····································19
4/11—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
AD7608
GENERAL DESCRIPTION
The AD7608 operates from a single 5 V supply and can
The AD7608 is an 18-bit, 8-channel simultaneous sampling,
analog-to-digital data acquisition system (DAS). The part contains
analog input clamp protection, a second-order antialiasing filter,
a track-and-hold amplifier, an 18-bit charge redistribution
successive approximation analog-to-digital converter (ADC), a
flexible digital filter, a 2.5 V reference and reference buffer, and
high speed serial and parallel interfaces.
accommodate 10 V and 5 V true bipolar input signals while
sampling at throughput rates up to 200 kSPS for all channels.
The input clamp protection circuitry can tolerate voltages up
to 16.5 V. The AD7608 has 1 MΩ analog input impedance
regardless of sampling frequency. The single supply operation,
on-chip filtering, and high input impedance eliminate the need
for driver op amps and external bipolar supplies. The AD7608
antialiasing filter has a 3 dB cutoff frequency of 22 kHz and
provides 40 dB antialias rejection when sampling at 200 kSPS.
The flexible digital filter is pin driven, yields improvements in
SNR, and reduces the 3 dB bandwidth.
Rev. A | Page 3 of 32
AD7608
Data Sheet
SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)2, 3
fIN = 1 kHz sine wave unless otherwise noted
Oversampling by 16; 10 V range; fIN = 130 Hz
Oversampling by 16; 5 V range; fIN = 130 Hz
No oversampling; 10 V range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
No oversampling; 10 V range
No oversampling; 5 V range
98
99.5
97.5
90.9
90
90.5
89.5
91.5
90.5
−107
−108
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
95.5
89.5
88.5
88.5
88
Signal-to-(Noise + Distortion) (SINAD)2
Dynamic Range
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation2
−95
fa = 1 kHz, fb = 1.1 kHz
−110
−106
−95
dB
dB
dB
fIN on unselected channels up to 160 kHz
ANALOG INPUT FILTER
Full Power Bandwidth
−3 dB, 10 V range
−3 dB, 5 V range
−0.1 dB, 10 V range
−0.1 dB, 5 V range
10 V range
23
15
10
5
11
15
kHz
kHz
kHz
kHz
µs
tGROUP DELAY
5 V range
µs
DC ACCURACY
Resolution
No missing codes
18
Bits
Differential Nonlinearity2
Integral Nonlinearity2
Total Unadjusted Error (TUE)
0.75 −0.99/+2.6 LSB4
2.5
15
40
15
40
2
7.5
LSB
LSB
LSB
LSB
10 V range
5 V range
Positive Full-Scale Error2, 5
External reference
Internal reference
External reference
Internal reference
10 V range
5 V range
10 V range
5 V range
10 V range
5 V range
10 V range
5 V range
External reference
Internal reference
External reference
Internal reference
10 V range
128
LSB
Positive Full-Scale Error Drift
Positive Full-Scale Error Matching2
ppm/°C
ppm/°C
LSB
LSB
LSB
7
12
30
3.5
3.5
10
95
128
24
Bipolar Zero Code Error2,
6
48
LSB
Bipolar Zero Code Error Drift
Bipolar Zero Code Error Matching2
Negative Full-Scale Error2, 5
µV/°C
µV/°C
LSB
LSB
LSB
5
3
30
65
21
15
128
40
4
8
LSB
Negative Full-Scale Error Drift
Negative Full-Scale Error Matching2
ppm/°C
ppm/°C
LSB
12
30
95
128
5 V range
LSB
Rev. A | Page 4 of 32
Data Sheet
AD7608
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG INPUT
Input Voltage Ranges
RANGE = 1
RANGE = 0
10
5
V
V
Analog Input Current
10 V; see Figure 28
5 V; see Figure 28
5.4
2.5
5
µA
µA
pF
MΩ
Input Capacitance7
Input Impedance
1
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range
DC Leakage Current
2.475
2.5
7.5
2.49/
2.505
2.525
1
V
µA
pF
V
Input Capacitance7
REF SELECT = 1
REFIN/REFOUT
Reference Output Voltage
Reference Temperature Coefficient
LOGIC INPUTS
10
ppm/°C
Input High Voltage (VINH
)
0.9 × VDRIVE
V
Input Low Voltage (VINL
Input Current (IIN)
Input Capacitance (CIN)7
LOGIC OUTPUTS
)
0.1 × VDRIVE
2
V
µA
pF
5
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating-State Leakage Current
Floating-State Output Capacitance7
Output Coding
ISOURCE = 100 µA
ISINK = 100 µA
VDRIVE − 0.2
V
V
µA
pF
0.2
20
1
5
Twos complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
All eight channels included; see Table 3
Per channel, all eight channels included
4
1
µs
µs
kSPS
200
POWER REQUIREMENTS
AVCC
VDRIVE
4.75
2.3
5.25
5.25
V
V
ITOTAL
Digital inputs = 0 V or VDRIVE
fSAMPLE = 200 kSPS
Normal Mode (Static)
Normal Mode (Operational)8
Standby Mode
16
20
5
22
27
8
mA
mA
mA
µA
Shutdown Mode
Power Dissipation
2
11
Normal Mode (Static)
Normal Mode (Operational)8
Standby Mode
80
100
25
115.5
142
42
mW
mW
mW
µW
fSAMPLE = 200 kSPS
Shutdown Mode
10
58
1 Temperature range for B version is −40°C to +85°C.
2 See the Terminology section.
3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB
and THD by 3 dB.
4 LSB means least significant bit. With 5 V input range, 1 LSB = 38.14 µV. With 10 V input range, 1 LSB = 76.29 µV.
5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from
the external reference.
6 Bipolar zero code error is calculated with respect to the analog input voltage.
7 Sample tested during initial release to ensure compliance.
8 Operational power/current figure includes contribution when running in oversampling mode.
Rev. A | Page 5 of 32
AD7608
Data Sheet
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Parameter
Min
Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE
tCYCLE
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
Serial mode reading during conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
STBY rising edge to CONVST x rising edge; power-up time from
standby mode
5
µs
µs
5
4
10.5 µs
tCONV
3.45
7.87
16.05
33
66
133
257
4.15 µs
9.1
18.8 µs
39
µs
µs
µs
µs
µs
µs
78
158
315
100
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
30
13
ms
ms
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
50
20
20
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
40
25
25
0
2
t5FF
0.5
25
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
t6
t7
25
PARALLEL/BYTE READ
OPERATION
t8
0
0
ns
ns
CS to RD setup time
t9
CS to RD hold time
t10
RD low pulse width
16
21
25
32
15
22
ns
ns
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
t11
t12
Rev. A | Page 6 of 32
Data Sheet
AD7608
Limit at TMIN, TMAX
Min Typ Max Unit Description
Parameter
t13
Delay from CS until DB[15:0] three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
16
20
25
30
ns
ns
ns
ns
3
t14
16
21
25
32
ns
ns
ns
ns
ns
ns
ns
t15
t16
t17
6
6
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state enabled
22
SERIAL READ OPERATION
fSCLK
Frequency of serial read clock
23.5 MHz VDRIVE above 4.75 V
17 MHz VDRIVE above 3.3 V
14.5 MHz VDRIVE above 2.7 V
11.5 MHz VDRIVE above 2.3 V
t18
Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until
MSB valid
15
20
30
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
SCLK low pulse width
3
t19
F
17
23
27
34
ns
ns
ns
ns
ns
ns
t20
t21
t22
t23
0.4 tSCLK
0.4 tSCLK
7
SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
CS rising edge to DOUTA/DOUTB three-state enabled
22
ns
FRSTDATA OPERATION
t24
Delay from CS falling edge until FRSTDATA three-state disabled
15
20
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
t25
CS
falling edge until FRSTDATA high, serial mode
Delay from
15
20
25
30
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
t26
Delay from RD falling edge to FRSTDATA high
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
16
20
25
30
ns
ns
ns
ns
Rev. A | Page 7 of 32
AD7608
Data Sheet
Limit at TMIN, TMAX
Min Typ Max Unit Description
Parameter
t27
Delay from RD falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from 16th SCLK falling edge to FRSTDATA low
19
24
ns
ns
t28
17
22
24
ns
ns
ns
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from CS rising edge until FRSTDATA three-state enabled
t29
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t5
CONVST A/
CONVST B
tCYCLE
t2
CONVST A/
CONVST B
t3
tCONV
t1
BUSY
t4
CS
t7
tRESET
RESET
Figure 2.CONVST x Timing—Reading After a Conversion
t5
CONVST A/
CONVST B
tCYCLE
t2
CONVST A/
CONVST B
t3
tCONV
t1
BUSY
t6
CS
t7
tRESET
RESET
Figure 3. CONVST x Timing—Reading During a Conversion
CS
RD
t9
t8
t13
t11
t10
t16
t17
t14
V2
t15
V8
V1
[17:2]
V1
[1:0]
V2
[1:0]
V8
[1:0]
DATA:
DB[15:0]
INVALID
t24
[17:2]
[17:2]
t26
t27
t29
FRSTDATA
CS
RD
Pulses
Figure 4. Parallel Mode Separate and
Rev. A | Page 8 of 32
Data Sheet
AD7608
t12
CS, RD
t16
t13
V1
t17
V1
[1:0]
V2
[17:2]
V2
[1:0]
V7
[17:2]
V7
[1:0]
V8
[17:2]
V8
[1:0]
DATA:
DB[15:0]
[17:2]
FRSTDATA
CS
RD
Figure 5. and
Linked Parallel Mode
CS
t21
t20
SCLK
t19
t22
DB1
t23
t18
D
D
A,
B
OUT
OUT
DB17
t25
DB16
DB15
DB0
t28
t29
FRSTDATA
Figure 6. Serial Read Operation (Channel 1)
Rev. A | Page 9 of 32
AD7608
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Rating
AVCC to AGND
VDRIVE to AGND
−0.3 V to +7 V
−0.3 V to AVCC + 0.3 V
16.5 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
10 mA
Analog Input Voltage to AGND1
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
B Version
Storage Temperature Range
Junction Temperature
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec)
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.
−40°C to +85°C
−65°C to +150°C
150°C
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
64-Lead LQFP
45
11
°C /W
240 (+0)°C
Pb-Free Temperature, Soldering Reflow 260 (+0)°C
ESD CAUTION
ESD (All Pins Except Analog Inputs)
ESD (Analog Input Pins Only)
2 kV
7 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. A | Page 10 of 32
Data Sheet
AD7608
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
AV
48
AV
CC
CC
ANALOG INPUT
PIN 1
2
3
47 AGND
46
AGND
OS 0
DECOUPLING CAPACITOR PIN
POWER SUPPLY
REFGND
4
5
45
44
43
42
41
40
39
38
37
36
OS 1
OS 2
REFCAPB
REFCAPA
REFGND
REFIN/REFOUT
AGND
GROUND PIN
6
DATA OUTPUT
PAR/SER SEL
AD7608
7
STBY
TOP VIEW
DIGITAL OUTPUT
DIGITAL INPUT
(Not to Scale)
8
RANGE
9
AGND
CONVST A
CONVST B
RESET
REFERENCE INPUT/OUTPUT
10
11
12
13
REGCAP
AV
CC
AV
CC
RD/SCLK
REGCAP
CS
BUSY 14
35 AGND
FRSTDATA 15
34 REF SELECT
33 DB15
DB0
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TypeFF1 Mnemonic
Description
1, 37, 38, 48
P
AVCC
Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.
2, 26, 35,
40, 41, 47
P
AGND
Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7608. All
analog input signals and external reference signals should be referred to these pins. All six of these
AGND pins should connect to the AGND plane of a system.
5, 4, 3
6
DI
DI
OS [2: 0]
Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2
is the MSB control bit, while OS 0 is the LSB control bit. See the Digital Filter section for further
details on the oversampling mode of operation and Table 8 for oversampling bit decoding.
Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to a logic high, the serial interface is selected. In serial mode,
the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins function as
serial data outputs. When the serial interface is selected, DB[15:9] and DB[6:0] pins should be tied to
GND.
PAR/SER SEL
7
8
DI
DI
STBY
Standby Mode Input. This pin is used to place the AD7608 into one of two power-down modes: standby
mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin
as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference regulators,
and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down.
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of
the analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all
channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during
a conversion is not recommended. See the Analog Input section for more details.
RANGE
9, 10
DI
CONVST A,
CONVST B
Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to
initiate conversions on the analog input channels. For simultaneous sampling of all input channels,
CONVST A and CONVST B can be shorted together and a single convert start signal applied.
Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and
CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and
V8). This is only possible when oversampling is not switched on.
When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold
circuitry for their respective analog inputs is set to hold. This function allows a phase delay to be
created inherently between the sets of analog inputs.
Rev. A | Page 11 of 32
AD7608
Data Sheet
Pin No.
TypeFF1 Mnemonic
Description
11
DI
RESET
Reset Input. When set to logic high, the rising edge of RESET resets the AD7608. Once tWAKE-UP has
elapsed, the part should receive a RESET pulse after power up. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If
a RESET pulse is applied during a read, the contents of the output registers resets to all zeros.
12
DI
RD/SCLK
Parallel Data Read Control Input when Parallel Interface is Selected (RD)/Serial Clock Input when the
Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output
bus is enabled.
In parallel mode, two RD pulses are required to read the full 18 bits of conversion results from each
channel. The first RD pulse outputs DB[17:2], the second RD pulse outputs DB[1:0].
In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the
data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data
outputs. For further information, see the Conversion Control section.
13
14
DI
CS
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low
in parallel mode, the output bus, DB[15:0], is enabled and the conversion result is output on the
parallel data bus lines. In serial mode, the CS is used to frame the serial read transfer and clock out
the MSB of the serial output data.
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges
and indicates that the conversion process has started. The BUSY output remains high until the
conversion process for all channels is complete. The falling edge of BUSY signals that the conversion
data is being latched into the output data registers and is available to be read after a Time t4. Any
data read while BUSY is high must be complete before the falling edge of BUSY occurs. Rising edges
on CONVST A or CONVST B have no effect while the BUSY signal is high.
DO
BUSY
15
DO
DO
FRSTDATA
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in
three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling
edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high indicating that the
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS
as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS
falling edge. See the Conversion Control section for more details.
Parallel Output Data Bits, DB6 to DB0. When PAR/SER SEL = 0, these pins act as three-state parallel
digital output pins. When CS and RD are low, these pins are used to output DB8 to DB2 of the
conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER
SEL = 1, these pins should be tied to GND.
Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the host
interface (that is, DSP and FPGA).
Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER SEL = 0, this
pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to
output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTA and outputs
serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER SEL = 0, this
pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to
output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTB and
outputs serial conversion data. See the Conversion Control section for further details.
Parallel Output Data Bits, DB13 to DB9. When PAR/SER SEL = 0, these pins act as three-state parallel
digital output pins. When CS and RD are low, these pins are used to output DB15 to DB11 of the
conversion result during the first RD pulse and output zero during the second RD pulse. When
PAR/SER SEL = 1, these pins should be tied to GND.
22 to 16
DB[6:0]
VDRIVE
23
24
P
DO
DB7/DOUT
DB8/DOUT
DB[13:9]
A
25
DO
DO
B
31 to 27
32
DO/DI DB14
DO/DI DB15
Parallel Output Data Bit 14 (DB14). When PAR/SER SEL = 0, this pin act as three-state parallel digital
output pin. When CS and RD are low, this pin is used to output DB16 of the conversion result during the
first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER
SEL = 1, this pins should be tied to GND.
Parallel Output Data Bit 15 (DB15). When PAR/SER SEL = 0, this pin acts as three-state parallel digital
output pin. This pin is used to output DB17 of the conversion result during the first RD pulse and
DB1 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pins
should be tied to GND.
33
Rev. A | Page 12 of 32
Data Sheet
AD7608
Pin No.
TypeFF1 Mnemonic
Description
34
DI
REF SELECT
Internal/External Reference Selection Input. Logic input. If this pin is set to logic high then the
internal reference is selected and is enabled, if this pin is set to logic low then the internal reference
is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin.
36, 39
42
P
REGCAP
Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 μF capacitor. The voltage on these output pins is in the
range of 2.5 V to 2.7 V.
Reference Input/Reference Output. The on-chip reference of 2.5 V is available on this pin for external
use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled
by setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this
input. See the Internal/External Reference section. Decoupling is required on this pin for both the
internal or external reference options. A 10 µF capacitor should be applied from this pin to ground
close to the REFGND pins.
REF
REFIN/
REFOUT
43, 46
44, 45
REF
REF
REFGND
REFCAPA,
REFCAPB
Reference Ground Pins. These pins should be connected to AGND.
Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled
to AGND using a low ESR 10 μF ceramic capacitor.
49, 51, 53,
55, 57, 59,
61, 63
AI
V1 to V8
Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels
is determined by the RANGE pin.
50, 52, 54,
56, 58, 60,
62, 64
AI/
GND
V1GND to
V8GND
Analog Input Ground Pins. These pins correspond to the V1 to V8 analog input pins. Connect all
analog input AGND pins to the AGND plane of a system.
1 Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output.
Rev. A | Page 13 of 32
AD7608
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
3.5
AV , V
CC DRIVE
= 5V
INTERNAL REFERENCE
3.0
0
fSAMPLE = 200 kSPS
AV , V
CC DRIVE
INTERNAL REFERENCE
fSAMPLE = 200 kSPS
= 5V
2.5
T
= 25°C
A
2.0
–20
–40
±
10V RANGE
1.5
T
= 25°C
A
1.0
±10V RANGE
0.5
SNR = 91.23dB
SINAD = 91.17dB
THD = 108.69dB
16384 POINT FFT
fIN = 1kHz
0
–60
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–80
–100
–120
–140
–160
0
0
0
10k 20k 30k 40k 50k 60k 70k 80k 90k 100k
INPUT FREQUENCY (Hz)
CODE
Figure 8. FFT Plot, 10 V Range
Figure 11. Typical INL, 10 V Range
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
–20
AV , V
CC DRIVE
= 5V
INTERNAL REFERENCE
fSAMPLE = 200 kSPS
T
= 25°C
A
–40
±5V RANGE
0.1
0
SNR = 90.46dB
SINAD = 90.43dB
THD = 110.74dB
16384 POINT FFT
fIN = 1kHz
–60
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–80
–100
–120
–140
–160
AV , V
CC DRIVE
INTERNAL REFERENCE
= 5V
fSAMPLE = 200 kSPS
T
= 25°C
A
±10V RANGE
10k 20k 30k 40k 50k 60k 70k 80k 90k 100k
INPUT FREQUENCY (Hz)
CODE
Figure 9. FFT Plot, 5 V Range
Figure 12. Typical DNL, 10 V Range
4.0
3.5
AV , V
CC DRIVE
INTERNAL REFERENCE
fSAMPLE = 200 kSPS
= 5V
0
–20
3.0
AV , V
CC DRIVE
= 5V
2.5
T
= 25°C
INTERNAL REFERENCE
fSAMPLE = 12.5 kSPS
A
2.0
±5V RANGE
1.5
T
= 25°C
A
–40
1.0
±10V RANGE
0.5
SNR = 100.26dB
SINAD = 100.15dB
THD = –115.21dB
16384 POINT FFT
fIN = 131Hz
–60
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–80
–100
–120
–140
–160
1k
2k
3k
4k
5k
6k
INPUT FREQUENCY (Hz)
CODE
Figure 10. FFT Over Sampling by 16, 10 V Range
Figure 13. Typical INL, 5 V Range
Rev. A | Page 14 of 32
Data Sheet
AD7608
1.0
0.9
0.8
0.7
0.6
0.5
40
32
PFS ERROR
NFS ERROR
0.4
0.3
0.2
0.1
24
16
0
8
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
–8
AV , V
CC DRIVE
INTERNAL REFERENCE
= 5V
–16
–24
–32
–40
fSAMPLE = 200 kSPS
T
= 25°C
A
±5V RANGE
±10V RANGE
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
–40
–25
–10
5
20
35 50 65 80
TEMPERATURE (°C)
CODE
Figure 17. NFS/PFS Error Matching
Figure 14. Typical DNL, 5 V Range
10
8
80
60
40
±10V RANGE
6
20
±5V RANGE
4
0
–20
–40
–60
AV , V
= 5V
fSAMPLE = 200 kSPS
= 25°C
2
CC DRIVE
T
A
EXTERNAL REFERENCE
SOURCE RESISTANCE IS MATCHED ON
THE VxGND INPUT
0
200kSPS
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
±10V AND ±5V RANGE
–2
–80
–40
0
20k
40k
60k
80k
100k
120k
–25
–10
5
20
35 50 65 80
SOURCE RESISTANCE (Ω)
TEMPERATURE (°C)
Figure 18. PFS/NFS Error vs. Source Resistance
Figure 15. NFS Error vs. Temperature
80
105
60
40
100
95
90
85
80
20
0
±5V RANGE
±10V RANGE
–20
–40
–60
OS × 64
OS × 32
OS × 16
OS × 8
OS × 4
OS × 2
NO OS
AV , V
= 5V
fSAMPLE CHANGES WITH OS RATE
= 25°C
CC DRIVE
200kSPS
T
A
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
INTERNAL REFERENCE
±10V RANGE
–80
–40
–25
–10
5
20
35 50 65 80
100k
10
100
1k
10k
TEMPERATURE (°C)
INPUT FREQUENCY (Hz)
Figure 16. PFS Error vs. Temperature
Figure 19. SNR vs. Input Frequency for Different Oversampling Rates, 10 V Range
Rev. A | Page 15 of 32
AD7608
Data Sheet
105
100
95
4.0
3.2
2.4
1.6
0.8
0
90
±5V RANGE
–0.8
–1.6
–2.4
–3.2
–4.0
OS × 64
OS × 32
OS × 16
OS × 8
OS × 4
OS × 2
NO OS
AV , V
= 5V
fSAMPLE CHANGES WITH OS RATE
= 25°C
CC DRIVE
±10V RANGE
85
80
T
A
INTERNAL REFERENCE
±5V RANGE
200kSPS
AV , V
= 5V
CC DRIVE
EXTERNAL REFERENCE
100k
10
100
1k
10k
–40
–25
–10
5
20
35 50 65 80
INPUT FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 20. SNR vs. Input Frequency for Different Oversampling Rates, 5 V Range
Figure 23. Bipolar Zero Code Error vs. Temperature
–40
16
12
8
±10V RANGE
AV , V
= 5V
CC DRIVE
–50
–60
fSAMPLE = 200kSPS
R
MATCHED ON Vx AND VxGND INPUTS
SOURCE
±5V RANGE
±10V RANGE
–70
4
–80
0
105kΩ
48.7kΩ
23.7kΩ
10kΩ
5kΩ
1.2kΩ
100Ω
51Ω
–90
–4
–8
–12
–100
–110
–120
200kSPS
AV , V
= 5V
CC DRIVE
0Ω
EXTERNAL REFERENCE
35 50 65 80
TEMPERATURE (°C)
–16
–40
1k
10k
100k
–25
–10
5
20
INPUT FREQUENCY (Hz)
Figure 21. THD vs. Input Frequency for Various Source Impedances, 10 V Range
Figure 24. Bipolar Zero Code Error Matching Between Channels
–40
–50
±5V RANGE
AV , V
CC DRIVE
INTERNAL REFERENCE
AD7608 RECOMMENDED DECOUPLING USED
= 5V
AV , V
= 5V
fSAMPLE = 200kSPS
MATCHED ON Vx AND VxGND INPUTS
CC DRIVE
–60
–70
–50
–60
R
fSAMPLE = 150kSPS
SOURCE
T
= 25°C
A
INTERFERER ON ALL UNSELECTED CHANNELS
–80
–70
–90
±10V RANGE
±5V RANGE
–80
–100
–110
–120
–130
–140
105kΩ
48.7kΩ
23.7kΩ
10kΩ
5kΩ
1.2kΩ
100Ω
51Ω
–90
–100
–110
–120
0Ω
1k
10k
100k
0
20
40
60
80
100
120
140
160
INPUT FREQUENCY (Hz)
NOISE FREQUENCY (kHz)
Figure 22. THD vs. Input Frequency for Various Source Impedances, 5 V Range
Figure 25. Channel-to-Channel Isolation
Rev. A | Page 16 of 32
Data Sheet
AD7608
110
105
100
95
22
20
18
16
14
12
10
8
±10V RANGE
±5V RANGE
90
AV , V
CC DRIVE
= 5V
T
= 25 °C
A
AV , V = 5V
CC DRIVE
85
INTERNAL REFERENCE
fSAMPLE SCALES WITH OS RATIO
fIN SCALES WITH OS RATIO
T
= 25°C
A
INTERNAL REFERENCE
fSAMPLE VARIES WITH OS RATE
80
NO OS
OS2
OS4
OS8
OS16
OS32
OS64
NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64
OVERSAMPLING RATIO
OVERSAMPLING RATIO
Figure 29. Supply Current vs. Oversampling Rate
Figure 26. Dynamic Range vs. Oversampling Ratio
140
130
120
110
100
90
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
AV
= 5.25V
CC
AV
AV
= 5V
CC
CC
±10V RANGE
±5V RANGE
= 4.75V
80
AV , V
= 5V
INTERNAL REFERENCE
CC DRIVE
AD7608 RECOMMENDED DECOUPLING USED
70
fSAMPLE = 200kSPS
T
= 25°C
A
60
0
100 200 300 400 500 600 700 800 900 1000 1100
AV NOISE FREQUENCY (kHz)
–40
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
CC
Figure 27. Reference Output Voltage vs. Temperature for Different
Supply Voltages
Figure 30. PSRR
8
AV , V
= 5V
fSAMPLE = 200kSPS
CC DRIVE
6
4
2
0
–2
–4
–6
–8
–10
+85°C
+25°C
–40°C
–10
–8
–6
–4
–2
0
2
4
6
8
10
INPUT VOLTAGE (V)
Figure 28. Analog Input Current vs. Input Voltage Across Temperature
Rev. A | Page 17 of 32
AD7608
Data Sheet
TERMINOLOGY
Total Harmonic Distortion (THD)
The ratio of the rms sum of the harmonics to the fundamental.
For the AD7608, it is defined as
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, at ½ LSB below the first
code transition; and full scale, at ½ LSB above the last code
transition.
THD (dB) =
2
2
2
2
2
2
2
2
V2 +V3 +V4 +V5 +V6 +V7 +V8 +V9
20log
V1
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
where:
V1 is the rms amplitude of the fundamental.
V2 to V9 are the rms amplitudes of the second through ninth
Bipolar Zero Code Error
The deviation of the midscale transition (all 1s to all 0s) from
the ideal, which is 0 V − ½ LSB.
harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.
Bipolar Zero Code Error Match
The absolute difference in bipolar zero code error between any
two input channels.
Positive Full-Scale Error
The deviation of the actual last code transition from the ideal
last code transition (10 V − 1½ LSB (9.99988) and 5 V − 1½ LSB
(4.99994)) after bipolar zero code error is adjusted out. The
positive full-scale error includes the contribution from the
internal reference buffer.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m, n = 0,
1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n is equal to 0. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Positive Full-Scale Error Match
The absolute difference in positive full-scale error between any
two input channels.
Negative Full-Scale Error
The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in decibels (dB).
The deviation of the first code transition from the ideal first
code transition (−10 V + ½ LSB (−9.99996) and −5 V + ½ LSB
(−4.99998)) after the bipolar zero code error is adjusted out.
The negative full-scale error includes the contribution from
the internal reference buffer.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but not
the converter’s linearity. PSR is the maximum change in full-
scale transition point due to a change in power supply voltage
from the nominal value. The PSR ratio (PSRR) is defined as the
ratio of the power in the ADC output at full-scale frequency, f,
to the power of a 100 mV p-p sine wave applied to the ADC’s
Negative Full-Scale Error Match
The absolute difference in negative full-scale error between any
two input channels.
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2, excluding dc).
V
DD and VSS supplies of Frequency fS.
PSRR (dB) = 10 log (Pf/PfS)
where:
The ratio depends on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise.
Pf is equal to the power at Frequency f in the ADC output.
PfS is equal to the power at Frequency fS coupled onto the AVCC
supply.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between all input channels. It is measured by applying a full-scale
sine wave signal, up to 160 kHz, to all unselected input channels
and then determining the degree to which the signal attenuates
in the selected channel with a 1 kHz sine wave signal applied (see
Figure 25).
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for an 18-bit converter, the signal-to-(noise + distortion)
is 110.12 dB.
Rev. A | Page 18 of 32
Data Sheet
AD7608
THEORY OF OPERATION
Analog Input Clamp Protection
CONVERTER DETAILS
Figure 31 shows the analog input structure of the AD7608. Each
AD7608 analog input contains clamp protection circuitry. Despite
single 5 V supply operation, this analog input clamp protection
allows for an input overvoltage up to 16.5 V.
The AD7608 is a data acquisition system that employs a high
speed, low power, charge redistribution, successive approxi-
mation analog-to-digital converter (ADC) and allows the
simultaneous sampling of eight analog input channels. The
analog inputs on the AD7608 can accept true bipolar input
signals. The RANGE pin is used to select either 10 V or
5 V as the input range. The AD7608 operates from a single
5 V supply.
R
FB
1MΩ
Vx
CLAMP
CLAMP
1MΩ
VxGND
SECOND-
ORDER
LPF
The AD7608 contains input clamp protection, input signal
scaling amplifiers, a second-order antialiasing filter, track-and-
hold amplifiers, an on-chip reference, reference buffers, a high
speed ADC, a digital filter, and high speed parallel and serial
interfaces. Sampling on the AD7608 is controlled using the
CONVST x signals.
R
FB
Figure 31. Analog Input Circuitry
Figure 32 shows the voltage vs. current characteristic of the
clamp circuit. For input voltages of up to 16.5 V, no current
flows in the clamp circuit. For input voltages that are above
16.5 V, the AD7608 clamp circuitry turns on.
30
ANALOG INPUT
Analog Input Ranges
20
10
The AD7608 can handle true bipolar, single-ended input voltages.
The logic level on the RANGE pin determines the analog input
range of all analog input channels. If this pin is tied to a logic
high, the analog input range is 10 V for all channels. If this pin
is tied to a logic low, the analog input range is 5 V for all
channels. A logic change on the RANGE pin has an immediate
effect on the analog input range; how-ever, there is typically
a settling time of approximately 80 µs, in addition to the normal
acquisition time requirement. The recommended practice is to
hardwire the RANGE pin according to the desired input range
for the system signals.
0
–10
–20
AV , V
CC DRIVE
= 5V
–30
T
= 25 °C
A
–40
–25 –20 –15 –10
–5
0
5
10
15
20
25
SOURCE VOLTAGE (V)
During normal operation, the applied analog input voltage
should remain within the analog input range selected via the
range pin. A RESET pulse must be applied after power-up to
ensure the analog input channels are configured for the range
selected.
Figure 32. Input Protection Clamp Profile
A series resistor should be placed on the analog input channels
to limit the current to 10 mA for input voltages above 16.5 V.
In an application where there is a series resistance on an analog
input channel, Vx, a corresponding resistance is required on the
analog input GND channel, VxGND (see Figure 33). If there is
no corresponding resistor on the VxGND channel, an offset
error occurs on that channel.
When in a power-down mode, it is recommended to tie the
analog inputs to GND. As per the input clamp protection section,
the overvoltage clamp protection is recommended for use in
transient overvoltage conditions and should not remain active
for extended periods. Stressing the analog inputs outside of the
conditions mentioned here may degrade the Bipolar Zero Code
error and THD performance of the AD7608.
R
FB
AD7608
ANALOG
INPUT
SIGNAL
R
R
1MΩ
1MΩ
Vx
CLAMP
CLAMP
C
VxGND
Analog Input Impedance
R
The analog input impedance of the AD7608 is 1 MΩ. This is
a fixed input impedance that does not vary with the AD7608
sampling frequency. This high analog input impedance elimi-
nates the need for a driver amplifier in front of the AD7608,
allowing for direct connection to the source or sensor. With
the need for a driver amplifier eliminated, bipolar supplies
(which are often a source of noise in a system) can be
removed from the signal chain.
FB
Figure 33. Input Resistance Matching on the Analog Input
Rev. A | Page 19 of 32
AD7608
Data Sheet
Analog Input Antialiasing Filter
track-and-hold actually going into hold) is well matched, by design,
across all eight track-and-holds on one device and from device
to device. This matching allows more than one AD7608 device
to be sampled simultaneously in a system.
An analog antialiasing filter (a second-order Butterworth) is also
provided on the AD7608. Figure 34 and Figure 35 show the
frequency and phase response, respectively, of the analog
antialiasing filter. In the 5 V range, the −3 dB frequency is
typically 15 kHz. In the 10 V range, the −3 dB frequency is
typically 23 kHz.
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode, and the acquisition time
for the next set of conversions begins.
5
0
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 µs on the AD7608. The
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, parallel byte, or
serial interface after BUSY goes low; or, alternatively, data from
the previous conversion can be read while BUSY is high. Reading
data from the AD7608 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced
by ~1.5 dB when reading during a conversion.
±10V RANGE
AV , V
= 5V
fSAMPLE = 200kSPS
= 25°C
CC DRIVE
–5
–10
–15
–20
–25
–30
–35
–40
±5V RANGE
T
A
±10V RANGE 0.1dB
3dB
–40 10,303Hz 24,365Hz
+25 9619Hz
+85 9326Hz
23,389Hz
22,607Hz
±5V RANGE
0.1dB
–40 5225Hz
+25 5225Hz
+85 4932Hz
3dB
16,162Hz
15,478Hz
14,990Hz
100
1k
10k
100k
INPUT FREQUENCY (Hz)
ADC TRANSFER FUNCTION
Figure 34. Analog Antialiasing Filter Frequency Response
The output coding of the AD7608 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/262,144 for the AD7608. The ideal transfer characteristic
for the AD7608 is shown in Figure 36.
18
16
14
12
10
8
±5V RANGE
±10V RANGE
VIN
10V
VIN
5V
REF
2.5V
REF
2.5V
±10V CODE =
× 131,072 ×
±5V CODE =
× 131,072 ×
6
011...111
011...110
4
+FS – (–FS)
2
000...001
000...000
111...111
LSB =
AV , V
= 5V
fSAMPLE = 200kSPS
= 25°C
CC DRIVE
218
0
T
A
–2
100
100...010
100...001
100...000
1k
10k
100k
INPUT FREQUENCY (Hz)
–FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB
Figure 35. Analog Antialiasing Filter Phase Response
ANALOG INPUT
Track-and-Hold Amplifiers
+FS
±10V RANGE +10V
±5V RANGE +5V
MIDSCALE –FS
LSB
76.29µV
38.15µV
0V
0V
–10V
–5V
The track-and-hold amplifiers on the AD7608 allow the ADC
to accurately acquire an input sine wave of full-scale amplitude
to 18-bit resolution. The track-and-hold amplifiers sample
their respective inputs simultaneously on the rising edge of
CONVST x. The aperture time for track-and-hold (that is, the
delay time between the external CONVST x signal and the
Figure 36. AD7608 Transfer Characteristic
The LSB size is dependent on the analog input range selected.
Rev. A | Page 20 of 32
Data Sheet
AD7608
Internal Reference Mode
INTERNAL/EXTERNAL REFERENCE
One AD7608 device, configured to operate in the internal refer-
ence mode, can be used to drive the remaining AD7608 devices,
which are configured to operate in external reference mode (see
Figure 39). The REFIN/REFOUT pin of the AD7608, configured
in internal reference mode, should be decoupled using a 10 µF
ceramic decoupling capacitor. The other AD7608 devices,
configured in external reference mode, should use at least a
100 nF decoupling capacitor on their REFIN/REFOUT pins.
The AD7608 contains an on-chip 2.5 V band gap reference. The
REFIN/REFOUT pin allows access to the 2.5 V reference that
generates the on-chip 4.5 V reference internally, or it allows an
external reference of 2.5 V to be applied to the AD7608. An
externally applied reference of 2.5 V is also gained up to 4.5 V,
using the internal buffer. This 4.5 V buffered reference is the
reference used by the SAR ADC.
The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference or an external reference.
If this pin is set to logic high, the internal reference is selected
and enabled. If this pin is set to logic low, the internal reference
is disabled and an external reference voltage must be applied
to the REFIN/REFOUT pin. The internal reference buffer is
always enabled. After a reset, the AD7608 operates in the reference
mode selected by the REF SELECT pin. Decoupling is required
on the REFIN/REFOUT pin for both the internal and external
reference options. A 10 µF ceramic capacitor is required on the
REFIN/REFOUT pin.
REFIN/REFOUT
SAR
REFCAPB
BUF
10µF
REFCAPA
2.5V
REF
Figure 37. Reference Circuitry
The AD7608 contains a reference buffer configured to gain the
REF voltage up to ~4.5 V, as shown in Figure 37. The REFCAPA
and REFCAPB pins must be shorted together externally, and a
ceramic capacitor of 10 μF applied to REFGND, to ensure that
the reference buffer is in closed-loop operation. The reference
voltage available at the REFIN/REFOUT pin is 2.5 V.
AD7608
AD7608
AD7608
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
100nF
100nF
100nF
ADR421
When the AD7608 is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin. For
applications using multiple AD7608 devices, the following
configurations are recommended, depending on the application
requirements.
0.1µF
Figure 38. Single External Reference Driving Multiple AD7608 REFIN Pins
V
DRIVE
External Reference Mode
AD7608
AD7608
AD7608
One ADR421 external reference can be used to drive the
REFIN/REFOUT pins of all AD7608 devices (see Figure 38).
In this configuration, each REFIN/REFOUT pin of the AD7608
should be decoupled with at least a 100 nF decoupling capacitor.
REF SELECT
REF SELECT
REF SELECT
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
+
10µF
100nF
100nF
Figure 39. Internal Reference Driving Multiple AD7608 REFIN Pins
Rev. A | Page 21 of 32
AD7608
Data Sheet
The power-down mode is selected through the state of the
STBY
TYPICAL CONNECTION DIAGRAM
RANGE pin when the
pin is low. Table 7 shows the
Figure 40 shows the typical connection diagram for the AD7608.
There are four AVCC supply pins on the part, and each of the
four pins should be decoupled using a 100 nF capacitor at each
supply pin and a 10 µF capacitor at the supply source. The AD7608
can operate with the internal reference or an externally applied
reference. In this configuration, the AD7608 is configured to
operate with the internal reference. When using a single AD7608
device on the board, the REFIN/REFOUT pin should be
decoupled with a 10 µF capacitor. Refer to the Internal/External
Reference section when using an application with multiple
AD7608 devices. The REFCAPA and REFCAPB pins are
shorted together and decoupled with a 10 µF ceramic
capacitor.
configurations required to choose the desired power-down
mode. When the AD7608 is placed in standby mode, the
current consumption is 8 mA maximum and power-up time
is approximately 100 µs because the capacitor on the REFCAPA
and REFCAPB pins must charge up. In standby mode, the
on-chip reference and regulators remain powered up, and the
amplifiers and ADC core are powered down.
When the AD7608 is placed in shutdown mode, the current
consumption is 11 µA maximum and power-up time is approx-
imately 13 ms (external reference mode). In shutdown mode,
all circuitry is powered down. When the AD7608 is powered
up from shutdown mode, a RESET signal must be applied to
the AD7608 after the required power-up time has elapsed.
The VDRIVE supply is connected to the same supply as the pro-
cessor. The VDRIVE voltage controls the voltage value of the
output logic signals. For layout, decoupling, and grounding
hints, see the Layout Guidelines section.
Table 7. Power-Down Mode Selection
STBY
Power-Down Mode
Standby
Shutdown
RANGE
0
0
1
0
After supplies have been applied to the AD7608, apply a RESET
signal to the device to ensure it is configured for the correct
mode of operation.
POWER-DOWN MODES
There are two power-down modes available on the AD7608:
STBY
standby mode and shutdown mode. The
pin controls
whether the AD7608 is in normal mode or in one of the two
power-down modes.
ANALOG SUPPLY
VOLTAGE 5V1
DIGITAL SUPPLY
VOLTAGE +2.3V TO +5V
+
1µF
10µF
100nF
100nF
2
AV
V
DRIVE
REFIN/REFOUT
REGCAP
CC
REFCAPA
PARALLEL
INTERFACE
+
DB0 TO DB15
10µF
REFCAPB
REFGND
CONVST A, B
CS
RD
BUSY
V1
V1GND
V2
V2GND
V3
V3GND
V4
AD7608
RESET
OS 2
OS 1
OS 0
OVERSAMPLING
EIGHT ANALOG
INPUTS V1 TO V8
V4GND
V5
REF SELECT
PAR/SER SEL
V
DRIVE
V5GND
V6
V6GND
V7
V7GND
V8
V8GND
RANGE
STBY
V
DRIVE
AGND
1
DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).
CC
CC
DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV
PIN 37 AND PIN 38.
CC
2
DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
Figure 40. Typical Connection Diagram
Rev. A | Page 22 of 32
Data Sheet
AD7608
Simultaneously Sampling Two Sets of Channels
CONVERSION CONTROL
The AD7608 also allows the analog input channels to be
sampled simultaneously in two sets. This can be used in power-
line protection and measurement systems to compensate for
phase differences introduced by PT and CT transformers. In a
50 Hz system, this allows for up to 9° of phase compensation; and
in a 60 Hz system, it allows for up to 10° of phase compensation.
Simultaneous Sampling on All Analog Input Channels
The AD7608 allows simultaneous sampling of all analog input
channels. All channels are sampled simultaneously when both
CONVST x pins (CONVST A, CONVST B) are tied together.
A single CONVST x signal is used to control both CONVST x
inputs. The rising edge of this common CONVST x signal
initiates simultaneous sampling on all analog input channels.
This is accomplished by pulsing the two CONVST x pins
independently and is possible only if oversampling is not in
use. CONVST A is used to initiate simultaneous sampling of
the first set of channels (V1 to V4) and CONVST B is used
to initiate simultaneous sampling on the second set of analog
input channels (V5 to V8), as illustrated in Figure 41. On the
rising edge of CONVST A, the track-and-hold amplifiers for
the first set of channels are placed into hold mode. On the
rising edge of CONVST B, the track-and-hold amplifiers for
the second set of channels are placed into hold mode. The con-
version process begins once both rising edges of CONVST x
have occurred; therefore BUSY goes high on the rising edge of
the later CONVST x signal. In Table 3, Time t5 indicates the
maximum allowable time between CONVST x sampling points.
The AD7608 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is tCONV. The BUSY signal indicates to the user when
conversions are in progress, so when the rising edge of CONVST x
is applied, BUSY goes logic high and transitions low at the end
of the entire conversion process. The falling edge of the BUSY
signal is used to place all eight track-and-hold amplifiers back
into track mode. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus (DB[15:0]),
or the DOUTA and DOUTB serial data lines.
There is no change to the data read process when using two
separate CONVST x signals.
Connect all unused analog input channels to AGND. The results
for any unused channels are still included in the data read because
all channels are always converted.
V1 TO V4 TRACK-AND-HOLD
ENTER HOLD
V5 TO V8 TRACK-AND-HOLD
ENTER HOLD
t5
CONVST A
CONVST B
AD7608 CONVERTS
ON ALL 8 CHANNELS
BUSY
tCONV
CS, RD
V1
V2
V8
DATA: DB[15:0]
FRSTDATA
Figure 41. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode
Rev. A | Page 23 of 32
AD7608
Data Sheet
DIGITAL INTERFACE
The AD7608 provides two interface options: a parallel interface
and high speed serial interface. The required interface mode is
CS
RD
signal can be permanently tied low, and the
The
signal can be used to access the conversion results as shown
in Figure 4. A read operation of new data can take place after
the BUSY signal goes low (Figure 2), or alternatively a read
operation of data from the previous conversion process can
take place while BUSY is high (Figure 3).
PAR
selected via the
/SER SEL pin.
The operation of the interface modes is discussed in the
following sections.
PARALLEL INTERFACE (PAR/SER SEL = 0)
RD
The
results register. Two
18-bit conversion result from each channel. Applying a sequence
RD RD
pin is used to read data from the output conversion
Data can be read from the AD7608 via the parallel data bus with
RD
pulses are required to read the full
CS
RD
standard and
signals. To read the data over the parallel
PAR
CS
RD
and
bus, the
/SER SEL pin should be tied low. The
of 16
results out from each channel onto the 16-bit parallel output
RD
pulses to the AD7608
pin clocks the conversion
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
bus in ascending order. The first
goes low clocks out DB[17:2] of the V1 result, the next
falling edge updates the bus with DB[1:0] of V1 result. It takes
falling edge after BUSY
CS
RD
impedance state when both
and
are logic low.
RD
AD7608
INTERRUPT
RD
16
pulses to read the eight 18-bit conversion results from
BUSY 14
th
13
RD
clocks
the AD7608. On the AD7608, the 16 falling edge of
CS
12
RD/SCLK
DB[15:0]
DIGITAL
HOST
out the DB[1:0] conversion result for Channel V8. When the
RD
[33:24]
[22:16]
signal is logic low, it enables the data conversion result from
each channel to be transferred to the digital host (DSP, FPGA).
Figure 42. AD7608 interface diagram—One AD7608 Using the Parallel Bus;
CS RD
and
Shorted Together
When there is only one AD7608 in a system/board and it does
not share the parallel bus, data can be read using just one control
CS
The rising edge of the
and the falling edge of the
of the high impedance state.
input signal three-states the bus
CS
RD
signal from the digital host. The
together as shown in Figure 5. In this case, the data bus comes
CS RD
and
signals can be tied
CS
input signal takes the bus out
CS
is the control signal that
out of three-state on the falling edge of
/
. The combined
signal allows the data to be clocked out of the AD7608
CS
enables the data lines, it is the function that allows multiple
AD7608 devices to share the same parallel data bus.
CS RD
and
and to be read by the digital host. In this case,
is used to
CS
frame the data transfer of each data channel. In this case, 16
pulses are required to read the eight channels of data.
Rev. A | Page 24 of 32
Data Sheet
AD7608
The SCLK input signal provides the clock source for the serial
SERIAL INTERFACE (PAR/SER SEL = 1)
CS
read operation. goes low to access the data from the AD7608.
To read data back from the AD7608 over the serial interface,
CS
The falling edge of
clocks out the MSB of the 18-bit conversion result. This MSB
CS
takes the bus out of three-state and
PAR
CS
the
/SER SEL pin should be tied high. The
and SCLK
signals are used to transfer data from the AD7608. The AD7608
has two serial data output pins, DOUTA, and DOUTB. Data can be
read back from the AD7608 using one or both of these DOUT
lines. For the AD7608, conversion results from Channel V1 to
Channel V4 first appear on DOUTA while conversion results from
Channel V5 to Channel V8 first appear on DOUTB.
is valid on the first falling edge of the SCLK after the
falling
edge. The subsequent 17 data bits are clocked out of the AD7608
on the SCLK rising edge. Data is valid on the SCLK falling edge.
Eighteen clock cycles must be provided to the AD7608 to access
each conversion result.
The FRSTDATA output signal indicates when the first channel,
CS
The
falling edge takes the data output lines (DOUTA
CS
V1, is being read back. When the input is high, the FRSTDATA
and DOUTB) out of three-state and clocks out the MSB of
the conversion result. The rising edge of SCLK clocks all
subsequent data bits onto the serial data outputs, DOUTA
and DOUTB. The
serial read, or it can be pulsed to frame each channel read
of 18 SCLK cycles.
output pin is in three-state. In serial mode, the falling edge of
CS
takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
CS
input can be held low for the entire
D
OUTA output data line. The FRSTDATA output returns to a
logic low following the 18th SCLK falling edge. If all channels
are read on DOUTB, the FRSTDATA output does not go high
when V1 is output on the serial data output pin. It only goes
high when V1 is available on DOUTA (and this is when V5 is
available on DOUTB).
Figure 43 shows a read of eight simultaneous conversion results
using two DOUT lines on the AD7608. In this case, a 72 SCLK
transfer is used to access data from the AD7608 and
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using just one DOUT line, in which case DOUTA is recommended
to access all conversion data as the channel data is output in
ascending order. For the AD7608 to access all eight conversion
results on one DOUT line, a total of 144 SCLK cycles are required.
CS
is held
READING DURING CONVERSION
Data can be read from the AD7608 while BUSY is high and
conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read may be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a VDRIVE of 3.3 V to 5.25 V.
CS
These 144 SCLK cycles can be framed by one
group of 18 SCLK cycles can be individually framed by the
signal or each
CS
signal. The disadvantage of using just one DOUT line is that the
throughput rate is reduced if reading after conversion. The
unused DOUT line should be left unconnected in serial mode.
For the AD7608, if DOUTB is used as a single DOUT line, the
channel results will output in the following order: V5, V6, V7,
V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns
low once V5 is read on DOUTB.
Data can be read from the AD7608 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t6, as
outlined in Table 3, should be observed in this condition.
Figure 6 shows the timing diagram for reading one channel of
CS
data, framed by the
signal, from the AD7608 in serial mode.
CS
72
SCLK
D
D
A
B
V1
V5
V2
V6
V3
V7
V4
V8
OUT
OUT
Figure 43. AD7608 Serial Interface with two DOUT Lines
Rev. A | Page 25 of 32
AD7608
Data Sheet
Figure 44 shows that the conversion time extends as the over-
sampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 µs. Figure 44 shows OS × 2
and OS × 4; for a 10 kSPS example, there is adequate cycle time to
further increase the oversampling rate and yield greater improve-
ments in SNR performance. In an application where the initial
sampling or throughput rate is at 200 kSPS, for example, and
oversampling is turned on, the throughput rate must be reduced
to accommodate the longer conversion time and to allow for the
read. To achieve the fastest throughput rate possible when over-
sampling is turned on, the read can be performed during the
BUSY high time. The falling edge of BUSY is used to update the
output data registers with the new conversion data; therefore, the
reading of conversion data should not occur on this edge.
tCYCLE
DIGITAL FILTER
The AD7608 contains an optional digital first-order sinc filter
that should be used in applications where slower throughput
rates are used or where higher signal-to-noise ratio or dynamic
range is desirable. The oversampling ratio of the digital filter is
controlled using the oversampling pins, OS [2:0] (see Table 8).
OS 2 is the MSB control bit, and OS 0 is the LSB control bit.
Table 8 provides the oversampling bit decoding to select the
different oversample rates. The OS pins are latched on the falling
edge of BUSY. This sets the oversampling rate for the next
conversion (see Figure 45). In addition to the oversampling
function, the output result is decimated to 18-bit resolution.
If the OS pins are set to select an OS ratio of 8, the next
CONVST x rising edge takes the first sample for each channel,
and the remaining seven samples for all channels are taken with
an internally generated sampling signal. These samples are then
averaged to yield an improvement in SNR performance. Table 8
shows typical SNR performance for both the 10 V and the
5 V range. As Table 8 indicates, there is an improvement in
SNR as the OS ratio increases. As the OS ratio increases, the
3 dB frequency is reduced, and the allowed sampling frequency
is also reduced. In an application where the required sampling
frequency is 10 kSPS, an OS ratio of up to 16 can be used. In
this case, the application sees an improvement in SNR, but the
input 3 dB bandwidth is limited to ~6 kHz.
CONVST A,
CONVST B
tCONV
19µs
9µs
4µs
OS = 0 OS = 2 OS = 4
BUSY
t4
t4
t4
CS
RD
The CONVST A and CONVST B pins must be tied/driven
together when oversampling is turned on. When the over-
sampling function is turned on, the BUSY high time for the
conversion process extends. The actual BUSY high time
depends on the oversampling rate selected: the higher
the oversampling rate, the longer the BUSY high, or total
conversion time (see Table 3).
DATA:
DB[15:0]
Figure 44. No Oversampling, Oversampling × 2, and Oversampling × 4 While
Using Read After Conversion
CONVST A,
CONVST B
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
CONVERSION N
CONVERSION N + 1
BUSY
OS x
tOS_HOLD
tOS_SETUP
Figure 45. OS Pin Timing
Table 8. Oversample Bit Decoding
SNR 5 V
SNR 10 V
3 dB BW 5 V
Range (kHz)
3 dB BW 10 V
Range (kHz)
Maximum Throughput
CONVST x Frequency (kHz)
OS [2:0]
000
001
010
011
100
101
110
OS Ratio
Range (dB)1
90.5
Range (dB)1
No OS
2
4
8
16
32
64
91.2
93.4
95.7
98
100.4
102.8
103.5
15
15
13.7
10.3
6
22
22
18.5
11.9
6
200
100
50
92.5
94.45
96.5
99.1
101.7
103
25
12.5
6.25
3.125
3
1.5
3
1.5
111
Invalid
1 SNR values taken with a full scale 100 Hz input signal.
Rev. A | Page 26 of 32
Data Sheet
AD7608
3500
3000
2500
2000
1500
1000
500
Figure 46 to Figure 52 illustrates the effect of oversampling on
the code spread in a dc histogram plot. As the oversample rate
is increased, the spread of codes is reduced. (In Figure 46 to
Figure 52, AVCC = VDRIVE = 5 V and the sampling rate was scaled
with OS ratio.)
OVERSAMPLING BY 8
3027
2176
1600
1756
NO OVERSAMPLING
1377
1170 1208
1400
1200
1000
800
600
400
648
–2
1001
457
2
852
78
–3
44
3
4
2
4
708
0
–4
–1
0
1
588
CODE
411
Figure 49. Histogram of Codes—OS × 8 (9 Codes)
328
4500
4000
3500
3000
2500
2000
1500
1000
500
188
200
0
146
5
OVERSAMPLING BY 16
82
3947
66
6
35
3
21
7
3
0
9
5
8
–9 –8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
CODE
Figure 46. Histogram of Codes—No OS (18 Codes)
2703
2000
1800
1600
1400
1200
1000
800
OVERSAMPLING BY 2
1759
1524
1397
1081
–1
385
2
1065
69
–2
902
7
3
0
0
1
CODE
600
538
498
Figure 50. Histogram of Codes—OS × 16 (6 Codes)
400
6000
5000
4000
3000
2000
1000
0
208
165
200
OVERSAMPLING BY 32
5403
57
54
15
–8 –7 –6 –5 –4 –3 –2 –1
CODE
1
9
0
0
0
1
2
3
4
5
6
Figure 47. Histogram Of Codes—OS × 2 (14 Codes)
2500
2000
1500
1000
500
OVERSAMPLING BY 4
2224
1913
1460
1301
1551
17
11
–2
1072
–1
0
1
2
CODE
684
Figure 51. Histogram of Codes—OS × 32 (5 Codes)
427
199
64
40
4
14
0
–5
–4 –3 –2
–1
0
1
2
3
4
5
CODE
Figure 48. Histogram of Codes—OS × 4 (11 Codes)
Rev. A | Page 27 of 32
AD7608
Data Sheet
7000
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6489
AV
= 5V
CC
OVERSAMPLING BY 64
V
T
= 5V
DRIVE
= 25°C
6000
5000
4000
3000
2000
1000
0
A
±10V RANGE
OS BY 4
1238
465
–1
0
1
100
1k
10k
100k
1M
10M
CODE
FREQUENCY (Hz)
Figure 52. Histogram of Codes—OS × 64 (3 Codes)
Figure 54. Digital Filter Response for OS × 4
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
When the oversampling mode is selected, this has the effect
of adding a digital filter function after the ADC. The different
oversampling rates and the CONVST x sampling frequency
produces different digital filter frequency profiles.
AV
V
= 5V
CC
= 5V
DRIVE
T
= 25°C
A
±10V RANGE
OS BY 8
Figure 53 to Figure 58 show the digital filter frequency profiles
for oversampling by 2 to oversampling by 64. The combination
of the analog antialiasing filter and the oversampling digital
filter can be used to eliminate or reduce the complexity of the
design of the filter before the AD7608. The digital filtering
combines steep roll-off and linear phase response.
0
AV
= 5V
CC
V
= 5V
DRIVE
= 25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
A
100
1k
10k
100k
1M
10M
±10V RANGE
OS BY 2
FREQUENCY (Hz)
Figure 55. Digital Filter Response for OS × 8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AV
= 5V
= 5V
CC
V
DRIVE
= 25°C
T
A
±10V RANGE
OS BY 16
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 53. Digital Filter OS × 2
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 56. Digital Filter Response for OS × 16
Rev. A | Page 28 of 32
Data Sheet
AD7608
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AV
= 5V
= 5V
AV
= 5V
= 5V
CC
CC
V
V
DRIVE
= 25°C
DRIVE
T
T = 25°C
A
A
±10V RANGE
OS BY 32
±10V RANGE
OS BY 64
–100
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 57. Digital Filter Response for OS × 32
Figure 58. Digital Filter Response for OS × 64
Rev. A | Page 29 of 32
AD7608
Data Sheet
LAYOUT GUIDELINES
The printed circuit board that houses the AD7608 should be
designed so that the analog and digital sections are separated
and confined to different areas of the board.
Use at least one ground plane. It can be common or split between
the digital and analog sections. In the case of the split plane, the
digital and analog ground planes should be joined in only one
place, preferably as close as possible to the AD7608.
If the AD7608 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only one point: a star ground point should be
established as close as possible to the AD7608. Good connections
should be made to the ground plane. Avoid sharing one connec-
tion for multiple ground pins. Individual vias or multiple vias to
the ground plane should be used for each ground pin.
Figure 59. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and
REGCAP Pins
Avoid running digital lines under the devices because doing so
couples noise onto the die. Allow the analog ground plane to
run under the AD7608 to avoid noise coupling. Fast switching
signals like CONVST A, CONVST B, or clocks should be shielded
with digital ground to avoid radiating noise to other sections of
the board, and they should never run near analog signal paths.
Avoid crossover of digital and analog signals. Run traces on
layers in close proximity on the board at right angles to each
other to reduce the effect of feedthrough through the board.
The power supply lines to the AVCC and VDRIVE pins on the
AD7608 should use as large a trace as possible to provide
low impedance paths and reduce the effect of glitches on the
power supply lines. Where possible, use supply planes. Good
connections should be made between the AD7608 supply pins
and the power tracks on the board. Use a single via or multiple
vias for each supply pin.
Good decoupling is also important to lower the supply impedance
presented to the AD7608 and to reduce the magnitude of the
supply spikes. The decoupling capacitors should be placed close
to (ideally right up against) these pins and their corresponding
ground pins. Place the decoupling capacitors for the REFIN/
REFOUT pin and the REFCAPA and REFCAPB pins as close
as possible to their respective AD7608 pins and where possible
they should be placed on the same side of the board as the AD7608
device. Figure 59 shows the recommended decoupling on the
top layer of the AD7608 board. Figure 60 shows bottom layer
decoupling. Bottom layer decoupling is for the four AVCC pins
and the VDRIVE pin.
Figure 60. Bottom Layer Decoupling
Rev. A | Page 30 of 32
Data Sheet
AD7608
To ensure good device-to-device performance matching, in a
system that contains multiple AD7608 devices, a symmetrical
layout between the AD7608 devices is important.
Figure 61 shows a layout with two devices. The AVCC supply
plane runs to the right of both devices. The VDRIVE supply
track runs to the left of the two devices. The reference chip
is positioned between both the two devices and the reference
voltage track runs north to Pin 42 of U1 and south to Pin 42
to U2. A solid ground plane is used.
U2
These symmetrical layout principles can be applied to a system
that contains more than two AD7608 devices. The AD7608
devices can be placed in a north-south direction with the reference
voltage located midway between the AD7608 devices with the
reference track running in the north-south direction similar to
Figure 61.
U1
Figure 61. Layout for Multiple AD7608 Devices—Top Layer and
Supply Plane Layer
Rev. A | Page 31 of 32
AD7608
Data Sheet
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
17
32
PLANE
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 62. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7608BSTZ
AD7608BSTZ-RL
EVAL-AD7608EDZ
CED1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-64-2
ST-64-2
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board for the AD7608
Converter Evaluation Development
1 Z = RoHS Compliant Part.
©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08938-0-1/12(A)
Rev. A | Page 32 of 32
相关型号：
AD7610BCPZ
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48
ROCHESTER
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