AD7655ASTRL [ADI]
Low Cost 4-Channel 1 MSPS 16-Bit ADC; 低成本4通道1 MSPS 16位ADC
| 型号： | AD7655ASTRL |
| 厂家： | 
ADI |
| 描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 文件： | 总20页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7655*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
4-Channel, 16-Bit Resolution ADC
2 Track-and-Hold Amplifiers Throughput:
1 MSPS (Normal Mode)
888 kSPS (Impulse Mode)
Analog Input Voltage Range: 0 V to 5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
120 mW Typical,
2.6 mW @ 10 kSPS
AVDD AGND
REFGND REFx
DVDD DGND
TRACK/HOLD
ꢀ2
OVDD
OGND
INA1
INAN
INA2
A0
MUX
SERIAL
PORT
SER/PAR
SWITCHED
CAP DAC
EOC
MUX
INB1
INBN
INB2
PD
BUSY
D[15:0]
CS
MUX
16
PARALLEL
INTERFACE
CLOCK AND
CONTROL LOGIC
RD
RESET
A/B
Package: 48-Lead Quad Flat Pack (LQFP) or
48-Lead Frame Chip Scale Pack (LFCSP)
Pin-to-Pin Compatible with the AD7654
Low Cost
AD7655
BYTESWAP
IMPULSE
CNVST
PulSAR Selection
APPLICATIONS
4-Channel Data Acquisition
Type/kSPS
100–250
500–570
800–1000
Pseudo
Differential
AD7651
AD7650/AD7652 AD7653
GENERAL DESCRIPTION
AD7660/AD7661 AD7664/AD7666 AD7667
The AD7655 is a low cost, 4-channel, 16-bit, charge redistribution
SAR, analog-to-digital converter that operates from a single 5 V
power supply. It contains two low noise, wide bandwidth track-and-
hold amplifiers that allow simultaneous sampling, a high speed
1 MSPS 16-bit sampling ADC, an internal conversion clock,
error correction circuits, and both serial and parallel system
interface ports. Each track-and-hold has a multiplexer in front
to provide a 4-channel input ADC.
True Bipolar
AD7663
AD7665
AD7676
AD7679
AD7671
AD7677
AD7674
True Differential AD7675
18-Bit
AD7678
Multichannel/
Simultaneous
AD7654
AD7655
PRODUCT HIGHLIGHTS
1. Multichannel ADC
The AD7655 features a very high sampling rate mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput. It is available
in 48-lead LQFP or 48-lead LFCSP packages with operation
specified from –40∞C to +85∞C.
The AD7655 features 4-channel inputs with two sample-
and-hold circuits that allow simultaneous sampling.
2. Fast Throughput
The AD7655 is a very high speed (1 MSPS in normal mode
and 888 kSPS in impulse mode), charge redistribution, 16-bit
SAR ADC that avoids pipeline delay.
3. Single-Supply Operation
The AD7655 operates from a single 5 V supply and dissipates
only 120 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and a power-
down mode.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
*Patent pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(–40ꢁC to +85ꢁC, VREF = 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V,
AD7655–SPECIFICATIONS unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
Common-mode Input Voltage
Analog Input CMRR
Input Current
VINx – VINxN
VINxN
fIN = 100 kHz
1 MSPS Throughput
0
–0.1
2 VREF
+0.5
V
dB
mA
55
45
Input Impedance
See Analog Input Section
THROUGHPUT SPEED
Complete Cycle (2 channels)
Throughput Rate
Complete Cycle (2 channels)
Throughput Rate
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
2
1
2.25
888
ms
0
0
MSPS
ms
kSPS
DC ACCURACY
Integral Linearity Error
No Missing Codes
–6
15
+6
LSB1
Bits
Transition Noise
0.8
±0.25
±2
LSB
Full-Scale Error2
TMIN to TMAX
±0.5
% of FSR
ppm/ЊC
% of FSR
ppm/ЊC
LSB
Full-Scale Error Drift2
Unipolar Zero Error2
Unipolar Zero Error Drift2
Power Supply Sensitivity
TMIN to TMAX
±0.25
±0.8
±0.8
AVDD = 5 V ± 5%
AC ACCURACY
Signal-to-Noise
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
f
IN = 100 kHz
86
98
–96
86
dB3
dB
dB
dB
fIN = 100 kHz
fIN = 100 kHz
f
IN = 100 kHz
fIN = 100 kHz,
–60 dB Input
fIN = 100 kHz
30
–92
10
dB
dB
MHz
Channel-to-Channel Isolation
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay4
2
30
5
ns
ps
ps rms
ns
Aperture Delay Matching4
Aperture Jitter4
Transient Response
Full-Scale Step
250
REFERENCE
External Reference Voltage Range
External Reference Current Drain
2.3
2.5
180
AVDD/2
V
mA
1 MSPS Throughput
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
–1
+0.8
OVDD + 0.3
+1
+1
V
V
mA
mA
IIH
–1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Parallel or Serial 16-Bit Straight Binary Coding
Conversion Results Available Immediately
after Completed Conversion
0.4
VOL
VOH
ISINK = 1.6 mA
ISOURCE = –500 mA
V
V
OVDD – 0.2
–2–
REV. 0
AD7655
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.25
5
5
5.25
5.25
5.255
V
V
V
DVDD
OVDD
Operating Current6
AVDD
1 MSPS Throughput
15.5
8.5
100
120
2.6
mA
mA
mA
mW
mW
mW
DVDD
OVDD
Power Dissipation
1 MSPS Throughput6
20 kSPS Throughput7
888 kSPS Throughput7
135
125
114
TEMPERATURE RANGE8
Specified Performance
TMIN to TMAX
–40
+85
∞C
NOTES
1LSB means least significant bit. With the 0 V to 5 V input range, one LSB is 76.294 mV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4Sample tested during initial release.
5The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
6In Normal Mode.
7In Impulse Mode.
8Contact factory for extended temperature range.
Specifications subject to change without notice.
(–40ꢁC to +85ꢁC, VREF = 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 8 and 9
Convert Pulsewidth
t1
t2
t3
t4
5
ns
ms
ns
ms
Time Between Conversions (Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Normal Mode/Impulse Mode)
Aperture Delay
End of Conversions to BUSY LOW Delay
Conversion Time (Normal Mode/Impulse Mode)
Acquisition Time
2/2.25
32
1.75/2
t5
t6
t7
t8
t9
t10
t11
2
ns
ns
ms
ns
ns
ns
ms
10
1.75/2
250
10
RESET Pulsewidth
CNVST LOW to EOC HIGH Delay
EOC HIGH for Channel A Conversion
(Normal Mode/Impulse Mode)
EOC LOW after Channel A Conversion
EOC HIGH for Channel B Conversion
Channel Selection Setup Time
Channel Selection Hold Time
30
1/1.25
t12
t13
t14
t15
45
ns
ms
ns
ns
0.75
30
250
Refer to Figures 10, 11, 12, 13, and 14 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t16
t17
t18
t19
t20
1.75/2
ms
ns
ns
ns
ns
14
5
40
15
40
A/B LOW to Data Valid Delay
REV. 0
–3–
AD7655
TIMING SPECIFICATIONS (CONTINUED)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 15 and 16 (Master Serial Interface Modes)
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Read during Convert)
(Normal Mode/Impulse Mode)
t21
t22
t23
t24
10
10
10
ns
ns
ns
ns
250/500
SYNC Asserted to SCLK First Edge Delay*
Internal SCLK Period*
Internal SCLK HIGH*
Internal SCLK LOW*
SDOUT Valid Setup Time*
SDOUT Valid Hold Time*
SCLK Last Edge to SYNC Delay*
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
(Normal Mode/Impulse Mode)
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
3
ns
ns
ns
ns
ns
ns
23
12
7
4
2
40
1
10
10
10
ns
ns
ns
See Table I
CNVST LOW to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t36
t37
0.75/1
25
ms
ns
Refer to Figures 17 and 18 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t38
t39
t40
t41
t42
t43
t44
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
External SCLK HIGH
External SCLK LOW
*In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Symbol
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
t25
t26
t26
t27
t28
t29
t30
t31
t35
t35
3
17
50
70
22
21
18
4
3
4.25
4.5
17
17
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
25
40
12
7
4
2
1
3.25
3.5
100
140
50
49
18
30
30
6.25
6.5
200
280
100
99
18
80
80
10.75
11
–4–
REV. 0
AD7655
ABSOLUTE MAXIMUM RATINGS1
I
1.6mA
OL
Analog Inputs
INAx2, INBx2, REFx, INxN, REFGND
AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
TO OUTPUT
PIN
1.4V
C
L
*
60pF
I
500ꢂA
OH
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . .2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range
*
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
L
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
2V
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C
0.8V
tDELAY
NOTES
tDELAY
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 See Analog Input section.
2V
2V
0.8V
0.8V
Figure 2. Voltage Reference Levels for Timing
3 Specification is for device in free air: 48-Lead LQFP: JA = 91∞C/W, JC = 30∞C/W.
4 Specification is for device in free air: 48-Lead LFCSP:
JA = 26∞C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7655AST
AD7655ASTRL
AD7655ACP
AD7655ACPRL
EVAL-AD7655CB1
EVAL-CONTROL BRD22
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale Pack (LFCSP)
Chip Scale Pack (LFCSP)
Evaluation Board
ST-48
ST-48
CP-48
CP-48
Controller Board
NOTES
1This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7655 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD7655
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
AGND
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
DVDD
PIN 1
IDENTIFIER
CNVST
PD
3
A0
4
BYTESWAP
RESET
5
A/B
DGND
CS
AD7655
6
RD
TOP VIEW
7
IMPULSE
EOC
BUSY
D15
D14
D13
D12
(Not to Scale)
8
SER/PAR
D0
9
10
11
12
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic
Type Description
1, 47, 48 AGND
P
Analog Power Ground Pin.
2
3
AVDD
A0
P
Input Analog Power Pin. Nominally 5 V.
DI
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously,
then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then
converted.
4
5
BYTESWAP
DI
DI
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
A/B
Data Channel Selection. In parallel mode, when LOW, the data from channel B is read.
When HIGH, the data from channel A is read. In serial mode, when HIGH, channel A is
output first followed by channel B. When LOW, channel B is output first followed by channel A.
6, 20
7
DGND
Digital Power Ground Pin.
IMPULSE
DI
Mode Selection. When HIGH, this input selects a reduced power mode, IMPULSE. In this
mode, the power dissipation is approximately proportional to the sampling rate. When LOW,
the mode NORMAL is selected.
8
SER/PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
11, 12
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs
are in high impedance.
D[2:3] or
DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1]
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW which is the serial master
read after convert mode, these inputs, part of the serial port, are used to slow down if desired the
internal serial clock which clocks the data output. In the other serial modes, these inputs are not used.
13
14
D[4]
or EXT/INT
DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock, called respectively, master and slave mode. With
EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
HIGH, output data is synchronized to an external clock signal connected to the SCLK input.
D[5]
or INVSYNC
DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
–6–
REV. 0
AD7655
PIN FUNCTION DESCRIPTIONS
Pin
Number Mnemonic
Type Description
15
D[6]
or INVSCLK
DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
16
D[7]
or RDC/SDIN
DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is
HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from
two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19, 36
21
DVDD
P
Digital Power. Nominally at 5 V.
D[8]
or SDOUT
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655
provides the two conversion results, MSB first, from its internal shift register. The order of channel
outputs is controlled by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22
23
D[9]
or SCLK
DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data
SDOUT is updated depends upon the logic state of the INVSCLK pin.
D[10]
or SYNC
DO
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames
SDOUT. After the first channel is output, SYNC is pulsed LOW.
When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains
LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH.
24
D[11]
or RDERROR
DO
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as a incomplete read error flag. In slave mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
D[12:15]
BUSY
DO
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs
are in high impedance.
29
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
two conversions are complete and the data are latched into the on-chip shift register. The falling
edge of BUSY could be used as a data ready clock signal.
30
31
32
EOC
RD
DO
DI
End of Convert Output. Going low at each channel conversion.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion if any is aborted.
If not used, this pin could be tied to DGND.
REV. 0
–7–
AD7655
PIN FUNCTION DESCRIPTIONS (continued)
Pin
Number Mnemonic
Type Description
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE HIGH), if CNVST is held low when the
acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a
conversion is immediately started.
37
REF
AI
AI
AI
This input pin is used to provide a reference to the converter.
Reference Input Analog Ground
38
REFGND
INB1, INB2
39, 41
42, 43
40, 45
44, 46
NOTES
Analog Inputs
REFB, REFA AI
INBN, INAN AI
These inputs are the references applied to Channel A and Channel B, respectively.
Analog input ground senses. Allow to sense each channel ground independently.
Analog Inputs
INA2, INA1
AI
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
DEFINITION OF SPECIFICATIONS
Effective Number of Bits (ENOB)
Integral Nonlinearity Error (INL)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from the
middle of each code to the true straight line.
ENOB = S / N + D
– 1.76 / 6.02
)
[
]
(
)
dB
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Full-Scale Error
The last transition (from 111 . . . 10 to 111 . . . 11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The full-scale error
is the deviation of the actual level of the last transition from the
ideal level.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Unipolar Zero Error
In unipolar mode, the first transition should occur at a level 1/2
LSB above analog ground. The unipolar zero error is the devia-
tion of the actual transition from that point.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signals are held for a conversion.
Spurious Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Transient Response
The time required for the AD7655 to achieve its rated accuracy
after a full-scale step function is applied to its input.
–8–
REV. 0
Typical Performance Characteristics–AD7655
5
4
3
2
1
3
2
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
0
32768
CODE
0
32768
CODE
16384
16384
49152
65536
49152
65536
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
9000
8000
7000
8000
8480
7059
6894
7000
6000
5000
6000
5000
4000
3000
2000
4000
3000
2000
3505
3396
1230
1094
739
108
1000
0
1000
0
0
5
220
104
39
0
0
0
77
29
0
0
102
103
105
106
107
109
10A
101 102 103 104 105 106 107 108 109 10A
CODE IN HEX
CODE IN HEX
TPC 2. Histogram of 16,384 Conversions of a DC
Input at the Code Transition
TPC 5. Histogram of 16,384 Conversions of a DC
Input at the Code Center
–90
0
96
93
90
8192 POINT FFT
f
f
= 500MHz
= 100kHz, –0.5dB
S
IN
–20
SNR = 85.8dB
–40
–60
–94
THD = –91.4dB
SFDR = 93.6dB
S/[N+D] = 84.5dB
–80
–98
THD
–100
–120
–140
87
84
–102
–106
R
SNR
–160
–180
25
50
100 125 150 175 200
FREQUENCY – kHz
225 250
0
75
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE – ؇C
TPC 3. FFT Plot
TPC 6. SNR, THD vs. Temperature
REV. 0
–9–
AD7655
100
16.0
15.5
100
10
NORMAL AVDD
95
90
85
80
75
NORMAL DVDD
IMPULSE AVDD
15.0
14.5
14.0
13.5
13.0
1
SNR
IMPULSE DVDD
0.1
0.01
SINAD
ENOB
0.001
0.0001
OVDD 2.7V
70
1
10
100
FREQUENCY – kHz
1000
1
10
SAMPLING RATE – kSPS
100
1000
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
TPC 10. Operating Currents vs. Sample Rate
50
–75
OVDD = 2.7V @ 85ꢁC
–80
OVDD = 2.7V @ 25ꢁC
SFDR
40
–85
30
CROSSTALK B TO A
–90
–95
OVDD = 5V @ 85ꢁC
CROSSTALK A TO B
THD
20
OVDD = 5V @ 25ꢁC
–100
–105
THIRD HARMONIC
SECOND HARMONIC
10
0
–110
0
50
100
– pF
150
1000
10
100
FREQUENCY – kHz
1
1000
C
L
TPC 8. THD, Harmonics, Crosstalk and SFDR
vs. Frequency
TPC 11. Typical Delay vs. Load Capacitance CL
5
4
3
FULL SCALE
2
OFFSET DRIFT
1
0
–1
–2
–3
–4
–5
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE – ꢁC
TPC 9. Full Scale and Zero Error vs. Temperature
–10–
REV. 0
AD7655
CIRCUIT INFORMATION
The AD7655 is a very fast, low power, single-supply, precise
4-channel 16-bit analog-to-digital converter (ADC).
111...111
111...110
111...101
The AD7655 provides the user with two on-chip track-and-hold,
successive approximation ADCs that do not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
The AD7655 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP or in a tiny 48-lead LFCSP package that combines
space savings and allows flexible configurations as either serial
or parallel interface. The AD7655 is pin-to-pin compatible with
PulSAR ADCs.
000...010
000...001
000...000
–FS
–FS + 1 LSB
+FS – 1 LSB
–FS + 0.5 LSB
+FS – 1.5 LSB
ANALOG INPUT
Modes of Operation
The AD7655 features two modes of operation, normal and impulse.
Each of these modes is more suitable for specific applications.
Figure 3. ADC Ideal Transfer Function
The normal mode is the fastest mode (1 MSPS). Except when
it is powered down (PD HIGH), the power dissipation is almost
independent of the sampling rate.
Table II. Output Codes and Ideal Input Voltages
Analog
Digital Output
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput in
this mode is 888 kSPS. When operating at 20 kSPS, for example,
it typically consumes only 2.6 mW. This feature makes the
AD7655 ideal for battery-powered applications.
D
escription
Input VREF = 2.5 V
Code (Hex)
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
4.999924 V
4.999847 V
2.500076 V
2.5 V
2.499924 V
–76.29 mV
0 V
FFFF1
FFFE
8001
8000
Transfer Functions
The AD7655 data format is straight binary. The ideal transfer
characteristic for the AD7655 is shown in Figure 3 and Table II.
7FFF
0001
00002
NOTES
1This is also the code for overrange analog input (VINx – VINxN above
2 ϫ (VREF – VREFGND)).
2This is also the code for underrange analog input (VINx below VINxN).
REV. 0
–11–
AD7655
DVDD
ANALOG
SUPPLY
(5V)
30ꢃ
DIGITAL SUPPLY
(3.3V OR 5V)
NOTE 6
+
+
+
100nF
10ꢂF
10ꢂF
100nF
100nF
10ꢂF
AD780
AVDD
AGND
DGND
OVDD
OGND
DVDD
REF A/
REF B/
REF
SERIAL PORT
2.5V REF
NOTE 1
SCLK
1Mꢃ
100nF
C
+
REF
50kꢃ
1ꢂF
SDOUT
NOTE 2
REFGND
INA1
NOTE 3
50ꢃ
BUSY
ꢂC/ꢂP/DSP
50ꢃ
–
15ꢃ
CNVST
D
NOTE 4
U1
+
ANALOG INPUT A1
NOTE 7
C
2.7nF
C
AD7655
NOTE 5
AD8021
SER/PAR
DVDD
A/B
A0
50ꢃ
–
U2
+
CLOCK
CS
15ꢃ
NOTE 4
INA2
INAN
RD
ANALOG INPUT A2
2.7nF
BYTESWAP
RESET
PD
C
C
NOTE 5
AD8021
50ꢃ
–
U1
15ꢃ
NOTE 4
INB1
+
ANALOG INPUT B1
2.7nF
C
C
NOTE 5
AD8021
50ꢃ
–
U2
15ꢃ
NOTE 4
INB2
INBN
+
ANALOG INPUT B2
2.7nF
C
C
NOTE 5
AD8021
NOTES
1. SEEVOLTAGE REFERENCE INPUT SECTION.
2. WITHTHE RECOMMENDEDVOLTAGE REFERENCES, C
IS 47ꢂF. SEEVOLTAGE REFERENCE INPUT SECTION.
REF
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUTS SECTION.
6. OPTION, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
Figure 4. Typical Connection Diagram (Serial Interface)
–12–
REV. 0
AD7655
TYPICAL CONNECTION DIAGRAM
It could significantly differ from the settling time at a 16-bit
level and, therefore, it should be verified prior to the driver
selection. The tiny op amp AD8021, which combines ultra-
low noise and a high gain bandwidth, meets this settling time
requirement even when used with a high gain of up to 13.
Figure 4 shows a typical connection diagram for the AD7655.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
Figure 5 shows a simplified analog input section of the AD7655.
∑
∑
The noise generated by the driver amplifier needs to be kept
as low as possible in order to preserve the SNR and transition
noise performance of the AD7655. The noise coming from
the driver is filtered by the AD7655 analog input circuit
one-pole low-pass filter made by RA, RB, and CS.
AVDD
R
= 500ꢃ
A
INA1
INA2
The driver needs to have a THD performance suitable to
that of the AD7655.
C
S
S
INAN
INBN
C
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
INB1
INB2
R
= 500ꢃ
B
AGND
The AD8022 could also be used where a dual version is needed
and a gain of 1 is used.
Figure 5. Simplified Analog Input
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
The diodes shown in Figure 5 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs. This will cause
these diodes to become forward-biased and start conducting
current. These diodes can handle a forward-biased current of
120 mA maximum. This condition could eventually occur when
the input buffer’s (U1) or (U2) supplies are different from AVDD.
In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
The AD8610 is also an option where low bias current is needed
in low frequency applications.
Voltage Reference Input
The AD7655 requires an external 2.5 V reference. The reference
input should be applied to REF, REFA for Channel A, and to
REFB for Channel B. The voltage reference input REF of the
AD7655 has a dynamic input impedance; it should therefore be
driven by a low impedance source with an efficient decoupling.
This decoupling depends on the choice of the voltage reference
but usually consists of a 1 mF ceramic capacitor and a low ESR
tantalum capacitor connected to the REFA, REFB, and REFGND
inputs with minimum parasitic inductance. 47 mF is an appro-
priate value for the tantalum capacitor when using one of the
recommended reference voltages:
This analog input structure allows the sampling of the differential
signal between INx and INxN. Unlike other converters, the INxN is
sampled at the same time as the INx input. By using these differ-
ential inputs, small signals common to both inputs are rejected.
During the acquisition phase, for ac signals, the AD7655 behaves
like a one-pole RC filter consisting of the equivalent resistance
RA, RB, and CS. The resistors RA and RB are typically 500 W and
are a lumped component made up of some serial resistance and the
on resistance of the switches. The capacitor CS is typically 32 pF
and is mainly the ADC sampling capacitor. This one-pole filter
with a typical –3 dB cutoff frequency of 10 MHz reduces unde-
sirable aliasing effects and limits the noise coming from the inputs.
∑
∑
The low noise, low temperature drift AD780 voltage reference
The low cost AD1582 voltage reference
For applications using multiple AD7655s, it is more effective to
buffer the reference voltage using the internal buffer. Each ADC
should be decoupled individually.
Because the input impedance of the AD7655 is very high, the
AD7655 can be driven directly by a low impedance source without
gain error. As shown in Figure 4, that allows an external one-pole
RC filter between the output of the amplifier output and the
ADC analog inputs to even further improve the noise filtering
done by the AD7655 analog input circuit. However, the source
impedance has to be kept low because it affects the ac perfor-
mances, especially the total harmonic distortion. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD degrades with
the increase of the source impedance.
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference, which directly affects the full-scale
accuracy if this parameter is applicable. For instance, a ±15 ppm/∞C
tempco of the reference changes the full scale by ±1 LSB/∞C.
Power Supply
The AD7655 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.7 V and DVDD
+ 0.3 V. To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply, as shown in Figure 5. The AD7655 is independent
of power supply sequencing, once OVDD does not exceed DVDD
by more than 0.3 V, and thus is free from supply voltage induced
latchup. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 6.
Driver Amplifier Choice
Although the AD7655 is easy to drive, the driver amplifier needs
to meet at least the following requirements:
∑
The driver amplifier and the AD7655 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data sheet,
the settling at 0.1% or 0.01% is more commonly specified.
REV. 0
–13–
AD7655
t2
70
t1
65
60
55
50
45
CNVST
t15
t14
A0
BUSY
t3
t4
t10
EOC
t13
t11
t12
t6
t5
40
1
10
100
1000
10000
MODE
CONVERT B
ACQUIRE
CONVERT A
ACQUIRE
t8
CONVERT
FREQUENCY – kHz
t7
Figure 6. PSRR vs. Frequency
Figure 8. Conversion Control
POWER DISSIPATION
In impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7655 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping CNVST low, the AD7655 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7655 could sometimes
run slightly faster than the guaranteed limits in the impulse
mode of 888 kSPS. This feature does not exist in normal mode.
In impulse mode, the AD7655 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 7. This feature makes the AD7655
ideal for very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
1000
For applications where the SNR is critical, the CNVST signal should
have a very low jitter. Some solutions to achieve this are to use a
dedicated oscillator for CNVST generation or, at least, to clock
it with a high frequency low jitter clock, as shown in Figure 4.
NORMAL
100
IMPULSE
t9
10
RESET
1
BUSY
0.1
1
10
100
1000
DATA BUS
SAMPLING RATE – kSPS
Figure 7. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
t8
CNVST
Figure 8 shows the detailed timing diagrams of the conversion
process. The AD7655 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of the
CS and RD signals. The A0 signal is the MUX select signal that
chooses which input signal is to be sampled. When high, INx1 is
chosen and when low, INx2 is chosen, where x is either A or B.
It should be noted that this signal should not be changed during
the acquisition phase of the converter.
Figure 9. Reset Timing
DIGITAL INTERFACE
The AD7655 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7655 digital interface also accommodates either 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7655
to the host system interface digital supply.
–14–
REV. 0
AD7655
Signals CS and RD control the interface. When at least one of
these signals is high, the interface outputs are in high impedance.
Usually, CS allows the selection of each AD7655 in multicircuit
applications and is held low in a single AD7655 design. RD is
generally used to enable the conversion result on the data bus.
In parallel mode, signal A/B allows the choice of reading either
the output of Channel A or Channel B, whereas in serial mode,
signal A/B controls which channel is output first.
PARALLEL INTERFACE
The AD7655 is configured to use the parallel interface (Figure 10)
when SER/PAR is held low. The data can be read either after each
conversion, which is during the next acquisition phase or during
the other channel’s conversion, or during the following conversion
as shown, respectively, in Figures 11 and 12. When the data is
read during the conversion, however, it is recommended that it is
read only during the first half of the conversion phase. That avoids
any potential feedthrough between voltage transients on the
digital interface and the most critical analog conversion circuitry.
CS = RD = 0
t1
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0].
CNVST
t16
BUSY
t4
t3
t17
EOC
t10
PREVIOUS CHANNEL B
OR NEW A
NEW A
OR B
PREVIOUS CHANNEL A
OR B
CS
RD
DATA BUS
Figure 10. Master Parallel Data Timing for Reading
(Continuous Read)
BYTE
CS
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
PINS D[15:8]
PINS D[7:0]
t18
t18
t19
HI-Z
RD
LOW BYTE
HIGH BYTE
BUSY
Figure 13. 8-Bit Parallel Interface
CURRENT
DATA BUS
CONVERSION
CS
t18
t19
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
RD
CS = 0
A/B
t1
CNVST, RD
HI-Z
HI-Z
DATA BUS
CHANNEL A
t18
CHANNEL B
t12
t10
t20
t13
t11
EOC
Figure 14. A/B Channel Reading
BUSY
t4
The detailed functionality of A/B is explained in Figure 14.
When high, the data from Channel A is available on the data bus.
When low, the data bus now carries output from Channel B.
Note that Channel A can be read immediately after conversion
is done (EOC), while Channel B is still in its converting phase.
t3
PREVIOUS
DATA BUS
CONVERSION
t18
t19
SERIAL INTERFACE
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
The AD7655 is configured to use the serial interface when
SER/PAR is held high. The AD7655 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/B. When HIGH, Channel A is output
first; when LOW, Channel B is output first. Unlike in parallel
mode, Channel A data is updated only after Channel B conversion.
This data is synchronized with the 32 clock pulses provided on
the SCLK pin.
REV. 0
–15–
AD7655
MASTER SERIAL INTERFACE
Internal Clock
Figures 15 and 16 show the detailed timing diagrams of these
two modes.
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The AD7655
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired.
Usually, because the AD7655 is used with a fast throughput, the
mode master, read during conversion is the most recommended
serial mode when it can be used.
In read after conversion mode, it should be noted that unlike in
other modes, the signal BUSY returns low after the 32 data bits
are pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of this mode is
The output data is valid on both the rising and falling edge of
the data clock. Depending on RDC/SDIN input, the data can be
read after each conversion or during the following conversion.
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
A/B = 1
EXT/INT = 0
CS, RD
t3
CNVST
t35
BUSY
t12
EOC
t13
t37
t36
t32
SYNC
t21
t25
t26
t31
t27
t28
2
t33
17
1
16
30
31
32
SCLK
t22
t34
CH A
D15
CH A
D14
CH B
D2
CH B
D1
X
CH B D0
SDOUT
t23
t30
t29
Figure 15. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0
INVSCLK = INVSYNC = 0
A/B = 1
RDC/SDIN = 1
CS, RD
t1
CNVST
t3
BUSY
t12
EOC
t10
t13
t11
t24
t32
SYNC
t21
t26
t27 t28
t31
t33
t22
SCLK
1
2
16
1
2
16
t25
t34
CH B
D15
CH B
D14
CH A
D15
CH A
D14
SDOUT
CH B D0
CH A D0
X
t23
t30
t29
Figure 16. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
–16–
REV. 0
AD7655
that it can accommodate slow digital hosts because the serial
clock can be slowed down by using DIVSCLK.
The external clock can be either a continuous or discontinuous
clock. A discontinuous clock can be either normally high or
normally low when inactive. Figures 17 and 18 show the detailed
timing diagrams of these methods.
In read during conversion mode, the serial clock and data toggle at
appropriate instants, which minimizes potential feedthrough between
digital activity and the critical conversion decisions. The SYNC
signal goes low after the LSB of each channel has been output.
While the AD7655 is performing a bit decision, it is important
that voltage transients do not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
of each channel because the AD7655 provides error correction
circuitry that can correct for an improper bit decision made during
the first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that is toggling only when BUSY is low or,
more importantly, that it does not transition during the latter
half of EOC high.
SLAVE SERIAL INTERFACE
External Clock
The AD7655 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/INT pin is held high.
In this mode, several methods can be used to read the data. The
external serial clock is gated by CS and the data are output when
both CS and RD are low. Thus, depending on CS, the data can
be read after each conversion or during the following conversion.
EXT/INT = 1
INVSCLK = 0
RD = 0
A/B = 1
CS
EOC
BUSY
t42
t43 t44
1
2
3
30
31
32
33
34
SCLK
t38
t39
CH A
D15
CH A
D14
CH A
D13
X CH A X CH A
D15 D14
CH B D1 CH B D0
X
SDOUT
t23
t41
X CH A
D15
X CH A
D14
X CH B
D1
X CH B
D0
Y CH A Y CH A
D15 D14
X CH A
D13
SDIN
t40
Figure 17. Slave Serial Data Timing for Reading (Read after Convert)
INVSCLK = 0
A/B = 1
EXT/INT = 1
RD = 0
CS
t10
CNVST
t12
t13
t11
EOC
BUSY
t3
t42
t43
t44
SCLK
1
2
3
31
32
t38
t39
SDOUT
X
CH A D15 CH A D14 CH A D13
CH B D1
CH B D0
t23
Figure 18. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
–17–
REV. 0
AD7655
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning low,
the results of this conversion can be read while both CS and RD
are low. The data from both channels are shifted out, MSB first,
with 32 clock pulses and are valid on both the rising and falling
edge of the clock.
prevent incomplete data reading. There is no daisy-chain feature
in this mode, and RDC/SDIN input should always be tied either
high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process.
BUSY
OUT
BUSY
BUSY
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
AD7655
AD7655
#2 (UPSTREAM)
#1 (DOWNSTREAM)
Finally, in this mode only, the AD7655 provides a daisy-chain
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired, as it is for
instance in isolated multiconverter applications.
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift
out the data on SDOUT. Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
SCLK IN
CS IN
CNVST IN
Figure 19. Two AD7655s in a Daisy-Chain Configuration
MICROPROCESSOR INTERFACING
The AD7655 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The AD7655
is designed to interface either with a parallel 8-bit or 16-bit wide
interface or with a general-purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used with
the AD7655 to prevent digital noise from coupling into the ADC.
The following section illustrates the use of the AD7655 with an
SPI equipped DSP, the ADSP-219x.
External Clock Data Read during Conversion
Figure 18 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 32 clock pulses, and is valid on both rising and
falling edges of the clock. The 32 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
–18–
REV. 0
AD7655
SPI Interface (ADSP-219x)
coupling. Fast switching signals like CNVST or clocks should be
shielded with digital ground to avoid radiating noise to other sec-
tions of the board, and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided. Traces
on different but close layers of the board should run at right
angles to each other. This will reduce the effect of feedthrough
through the board. The power supply lines to the AD7655 should
use as large a trace as possible to provide low impedance paths
and reduce the effect of glitches on the power supply lines. Good
decoupling is also important to lower the supply’s impedance
presented to the AD7655 and reduce the magnitude of the supply
spikes. Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply’s pins, AVDD, DVDD, and OVDD
close to and ideally right up against these pins and their corre-
sponding ground pins. Additionally, low ESR 10 mF capacitors
should be located in the vicinity of the ADC to further reduce
low frequency ripple.
Figure 20 shows an interface diagram between the AD7655 and an
SPI equipped DSP, ADSP-219x. To accommodate the slower
speed of the DSP, the AD7655 acts as a slave device and data
must be read after conversion. This mode also allows the daisy
chain feature. The convert command could be initiated in response
to an internal timer interrupt. The 32-bit output data are read
with two SPI 16-bit wide access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY going
low) using an interrupt line of the DSP. The serial peripheral
interface (SPI) on the ADSP-219x is configured for master mode
(MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit
(CPHA) = 1 by writing to the SPI control register (SPICLTx).
DVDD
ADSP-219x*
AD7655*
SER/PAR
EXT/INT
The DVDD supply of the AD7655 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is recom-
mended if there is no separate supply available to connect the
DVDD digital supply to the analog supply AVDD through an
RC filter, as shown in Figure 5, and connect the system supply
to the interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system supply, it is
useful to insert a bead to further reduce high frequency spikes.
BUSY
CS
PFx
SPIxSEL (PFx)
MISOx
SDOUT
SCLK
CNVST
RD
SCKx
PFx or TFSx
INVSCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing the AD7655 to SPI Interface
APPLICATION HINTS
The AD7655 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most internal
ADC analog signals are referenced. This ground must be con-
nected with the least resistance to the analog ground plane. DGND
must be tied to the analog or digital ground plane depending on
the configuration. OGND is connected to the digital system ground.
Layout
The AD7655 has very good immunity to noise on the power
supplies, as seen in Figure 5. However, care should still be taken
with regard to grounding layout.
The printed circuit board that houses the AD7655 should be
designed so the analog and digital sections are separated and con-
fined to certain areas of the board. This facilitates the use of ground
planes that can be easily separated. Digital and analog ground
planes should be joined in only one place, preferably underneath
the AD7655, or at least as close as possible to the AD7655. If the
AD7655 is in a system where multiple devices require analog to
digital ground connections, the connection should still be made
at one point only, a star ground point, which should be estab-
lished as close as possible to the AD7655.
The layout of the decoupling of the reference voltage is impor-
tant. The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
Evaluating the AD7655 Performance
A recommended layout for the AD7655 is outlined in the documen-
tation of the evaluation board for the AD7655. The evaluation
board package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from a PC via the Eval-Control BRD2.
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7655 to avoid noise
REV. 0
–19–
AD7655
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7ꢁ
3.5ꢁ
0ꢁ
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90ꢁ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
48-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
0.60 MAX
BSC SQ
0.60 MAX
PIN 1
INDICATOR
37
48
1
36
PIN 1
INDICATOR
5.25
5.10 SQ
4.95
6.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
0.50
0.40
0.30
25
24
12
13
5.50
REF
1.00 MAX
0.65 NOM
1.00
0.90
0.80
12ꢁ MAX
0.05 MAX
0.02 NOM
0.20
REF
0.50 BSC
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
–20–
REV. 0
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