AD7671 [ADI]
16-Bit 1 MSPS SAR Unipolar ADC with Ref; 16位1 MSPS SAR ADC单极与参考
| 型号： | AD7671 |
| 厂家： | 
ADI |
| 描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 文件： | 总23页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARYTECHNICALDATA
a
16-Bit 1 MSPS SAR Unipolar ADC with Ref
AD7667*
Preliminary Technical Data
FEATURES
F U N C T IO N AL BLO C K D IAG RAM
Throughput:
1 MSPS (Warp Mode)
800 kSPS (Normal Mode)
INL: 2.ꢀ LSB Max ( 0.0038ꢁ of Full Scale)
16 Bits Resolution with No Missing Codes
Analog Input Voltage Range: 0 V to 2.ꢀ V
No Pipeline Delay
REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
OVDD
OGND
AD7667
2.5 V REF
SERIAL
PORT
16
IN
SWITCHED
CAP DAC
DATA[15:0]
BUSY
INGND
Parallel and Serial ꢀ V/3 V Interface
SPITM/QSPITM/MICROWIRETM/DSP Compatible
Single ꢀ V Supply Operation
Power Dissipation
112 mW Typ without REF, 122 mW Typ with REF
1ꢀ ꢀW @ 100 SPS
PARALLEL
INTERFACE
PDREF
RD
PDBUF
PD
CLOCK
CS
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
SER/PAR
RESET
OB/2C
BYTESWAP
Power-Down Mode: 7 ꢀW Max
Package: 48-Lead Quad Flat Pack (LQFP);
48-Lead Chip Scale Package (LFCSP);
Pin-to-Pin Compatible with PulSAR ADCs
WARP IMPULSE CNVST
PulSAR Selection
APPLICATIONS
Data Acquisition
T ype / kSPS
100 - 250
500 - 570
1000
Instrumentation
Pseudo
Differential
AD7651
AD7660/61
AD7650/52
AD7664/66
AD7653
AD7667
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
T rue Bipolar
AD7663
AD7675
AD7665
AD7676
AD7671
AD7677
T rue
Differential
PRODUCT HIGHLIGHTS
1. Fast T hroughput
GENERAL DESCRIPT ION
T he AD7667 is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
T he AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V
power supply. T he part contains a high-speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports.
2. Internal Reference
The AD7667 has an internal reference and allows for an
external reference to be used.
3. Superior INL
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced power
mode (Impulse) where the power is scaled with the through-
put.
T he AD7667 has a maximum integral nonlinearity of 2.5
LSB with no missing 16-bit code.
4. Single-Supply Operation
The AD7667 operates from a single 5 V supply and dissipates
a typical of 112 mW. In impulse mode, its power dissi-
pation decreases with the throughput. It consumes 7 µW
maximum when in power-down.
It is fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process, with correspondingly low cost and is available in a
48-lead LQFP and a tiny 48-lead LFCSP with operation speci-
fied from –40°C to +85°C.
5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
*Patent pending.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE ia a trademark of National Semiconductor Corporation
REV. PrA
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties that
m ay result from its use. No license is granted by im plication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
PRELIMINARYTECHNICALDATA
–SPECIFICATIONS (–40ꢁC to +85ꢁC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
AD7667
Parameter
Conditions
Min
Typ
Max
Unit
RESOLU T ION
16
Bits
ANALOG INPUT
Voltage Range
VIN – VINGND
VIN
0
VREF
+3
+0.5
V
Operating Input Voltage
–0.1
–0.1
V
VINGND
V
dB
µA
Analog Input CMRR
Input Current
Input Impedance
fIN = 10 kHz
1 MSPS T hroughput
T BD
11
See Analog Input Section
T HROUGHPUT SPEED
Complete Cycle
T hroughput Rate
T ime Between Conversions
Complete Cycle
T hroughput Rate
Complete Cycle
T hroughput Rate
In Warp Mode
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
1
µs
1
1000
1
kSPS
ms
1.25
800
1.5
666
µs
0
0
kSPS
µs
kSPS
DC ACCURACY
Integral Linearity Error
No Missing Codes
T ransition Noise
–2.5
16
+2.5
LSB1
Bits
0.7
LSB
Full-Scale Error2
REF = 2.5 V
± T BD
± T BD
% of FSR
LSB
LSB
Unipolar Zero Error2
Power Supply Sensitivity
± T BD
± T BD
AVDD = 5 V ± 5%
AC ACCURACY
Signal-to-N oise
fIN = 100 kHz
90
dB
Spurious Free Dynamic Range
T otal Harmonic Distortion
fIN = 100 kHz
100
-100
-100
90
dB
fIN = 45 kHz
dB
fIN = 100 kHz
dB
Signal-to-(N oise+D istortion)
–3 dB Input Bandwidth
fIN = 100 kHz
dB
–60 dB Input, fIN = 100 kHz
30
T BD
dB
M H z
SAM PLIN G D YN AM ICS
Aperture Delay
2
5
ns
ps rms
ns
Aperture Jitter
T ransient Response
Full-Scale Step
250
REFEREN C E
Internal Reference Voltage
Internal Reference Source Current
Internal Reference T emp Drift
Internal Reference T emp Drift
T urn-on Settling T ime
External Reference Voltage Range
External Reference Current Drain
T emperature Pin
@
25ꢁC
T BD
2.3
2.5
T BD
TBD
T BD
V
µA
ppm/ꢁC
ppm/ꢁC
–40ꢁC to +85ꢁC
0ꢁC to +70ꢁC
TBD
T BD
2.5
AVDD – 1.85
V
µA
1 MSPS T hroughput
T BD
Voltage Output @ 25ꢁC
T emperature Sensitivity
Output Resistance
313
1
4.3
mV
mV/ꢁC
kꢀ
DIGIT AL INPUT S
Logic Levels
VIL
VIH
IIL
–0.3
2.0
–1
+0.8
V
OVDD + 0.3
V
+1
+1
µA
µA
IIH
–1
DIGIT AL OUT PUT S
Data Format
Parallel or Serial 16-Bits
Conversion Results Available
Immediately after
Completed Conversion
0.4
Pipeline Delay
VOL
VOH
ISINK = 1.6 mA
ISOURCE = –500 µA
V
V
OVDD – 0.6
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
5.25
5.259
V
V
V
DVDD
O VD D
–2–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
Parameter
Conditions
1 MSPS T hroughput
Min
Typ
Max
Unit
Operating Current4
AVD D 5
T BD
T BD
T BD
112
m A
m A
µA
m W
µW
µW
m W
m W
µW
D VD D 5
OVD D 5
Power Dissipation5 without REF
1
MSPS T hroughput
100 SPS T hroughput6
15
In Power-Down Mode7
T BD
Power Dissipation5 with REF
1
MSPS T hroughput
122
10.015
100 SPS T hroughput6
In Power-Down Mode7
T BD
+85
T EMPERAT URE RAN GE8
Specified Performance
T MIN to TMAX
–40
°C
NOT ES
1LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2See Definition of Specifications section. T hese specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. T ested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4In warp mode.
5T ested in parallel reading mode using external reference.
6In impulse mode with external REF.
7With all digital inputs forced to DVDD or DGND respectively.
8Contact factory for extended temperature range.
9T he max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.
TIMING SPECIFICATIONS (–40ꢁC to +85ꢁC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Sym bol
M in
T yp
M ax
U nit
REFER T O FIGURES 11 AND 12
Convert Pulsewidth
T ime Between Conversions
t1
t2
5
ns
µs
1/1.25/1.5
Note 1
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t3
t4
30
ns
µs
0.75/1/1.25
t5
t6
t7
2
ns
ns
µs
End of Conversion to BUSY LOW Delay
Conversion T ime
10
0.75/1/1.25
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition T ime
RESET Pulsewidth
t8
t9
250
10
ns
ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DAT A Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DAT A Valid to BUSY LOW Delay
Bus Access Request to DAT A Valid
Bus Relinquish T ime
t10
0.75/1/1.25
µs
t11
t12
t13
45
5
ns
ns
ns
40
15
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
t15
t16
t17
10
10
10
ns
ns
ns
ns
CS LOW to Internal SCLK Valid Delay2
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
25/275/525
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period3
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
3
ns
ns
ns
ns
ns
ns
25
12
7
4
2
40
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup T ime3
SDOUT Valid Hold T ime3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
3
10
10
10
ns
ns
ns
µs
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
See T able I
0.75/1/1.25
25
t29
t30
µs
ns
–3–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
Sym bol
M in
T yp
M ax
18
U nit
REFER T O FIGURES 18 AND 20 (Slave Serial Interface Modes)2
External SCLK Setup T ime
External SCLK Active Edge to SDOUT Delay
SDIN Setup T ime
SDIN Hold T ime
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
External SCLK HIGH
External SCLK LOW
NOT ES
1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master read during convert mode. See T able I for serial master read after convert mode.
Specifications subject to change without notice.
Table I. Ser ial clock tim ings in Master Read after Conver t
DIVSCLK[1]
0
0
1
1
unit
DIVSCLK[0]
0
1
0
1
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period minimum
Internal SCLK Period typical
t18
t19
t19
t20
t21
t22
t23
t24
t24
t24
t24
3
17
50
70
22
21
18
4
60
2
2.25
2.5
17
100
140
50
49
18
30
140
3
17
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
25
40
12
7
4
2
200
280
100
99
18
89
300
5.25
5.55
5.75
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup T ime Minimum
SDOUT Valid Hold T ime Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Warp)
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
3
1.5
1.75
2
3.25
3.5
–4–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
ABSOLUT E MAXIMUM RAT INGS*
1.6mA
I
OL
IN2, TEMP2,REF, REFBUFIN, INGND, REFGND to AGND
. . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
TO OUTPUT
PIN
1.4V
C
L
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
60pF*
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . -0.3V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . -0.3V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 3.0 V
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range
I
OH
500ꢀA
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
*
C
L
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOT ES
2V
0.8V
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2See Analog Input section.
tDELAY
tDELAY
2V
2V
0.8V
0.8V
Figure 2. Voltage Reference Levels for Timing
3Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W
4Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W
ORDERING GUIDE
T emperature
Range
Model
Package Description
Package Option
AD7667AST
AD7667AST RL
AD7667ACP
AD7667ACPRL
EVAL-AD7667CB1
EVAL-CONT ROL BRD22
–40°C to +85°C Quad Flatpack (LQFP)
–40°C to +85°C Quad Flatpack (LQFP)
–40°C to +85°C Chip Scale (LFCSP)
–40°C to +85°C Chip Scale (LFCSP)
ST-48
ST-48
CP-48
CP-48
Evaluation Board
Controller Board
NOT ES
1T his board can be used as a standalone evaluation board or in conjunction with the EVAL-CONT ROL BRD2 for evaluation/demonstration purposes.
2T his board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD 7667 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrA
–5–
PRELIMINARYTECHNICALDATA
AD7667
PIN CONFIGURATION
48-Lead LQFP
(ST -48)
48 47 46 45 44 43 42 41 40 39 38 37
1
AGND
AVDD
36 AGND
35 CNVST
34 PD
PIN 1
IDENTIFIER
2
NC
BYTESWAP
OB/2C
3
4
5
6
7
33
RESET
32 CS
AD7667
TOP VIEW
(Not to Scale)
WARP
31
RD
IMPULSE
SER/PAR
30
DGND
8
29
BUSY
D0
D1
9
28 D15
27 D14
26 D13
25 D12
10
11
12
D2/SCLK0
D3/SCLK1
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
D escription
Pin No.
Mnemonic
T ype
1
2
AG N D
AVD D
P
P
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
3, 40–42, N C
44
4
5
6
BYT ESWAP
D I
D I
D I
Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].
Straight Binary/Binary T wo’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
OB/2C
WARP
7
IM PULSE
SER/PAR
D I
D I
D I
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DAT A bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these
outputs are in high impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus. When SER/PAR is HIGH, EXT /INT is LOW, and RDC/SDIN is
LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used
8
9,10
11,12
DAT A[0:1]
D AT A[2:3]or D I/O
DIVSCLK[0:1]
13
14
D AT A[4]
D I/O
D I/O
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus.
or EXT /INT
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT /INT tied LOW, the internal
clock is selected on SCLK output. With EXT /INT set to a logic HIGH, output data is syn
chronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus.
D AT A[5]
or INVSYNC
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active
–6–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
Pin No.
15
Mnemonic
T ype
D escription
state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC
is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output
Bus.
D AT A[6]
D I/O
D I/O
or INVSCLK
D AT A[7]
16
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external
data input or a read mode selection input depending on the state of EXT /INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver-
sion results from two or more ADCs onto a single SDOUT line. The digital data level on
SDIN is output on DAT A with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT /INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply than the supply of
the host interface (5 V or 3 V).
17
18
OG N D
OVD D
P
P
19
20
21
D VD D
D G N D
DAT A[8]
or SDOUT
P
P
D O
Digital Power. Nominally at 5 V.
Digital Power Ground
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data out
put synchronized to SCLK. Conversion results are stored in an on-chip register. T he
AD7667 provides the conversion result, MSB first, from its internal shift register. T he
DAT A format is determined by the logic level of OB/2C. In serial mode, when EXT /INT
is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT /INT is HIGH:
If IN VSCLK is LOW, SD OUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising
edge.
22
23
D AT A[9]
or SCLK
D I/O
D O
When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port D ata
Output Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock
input or output, dependent upon the logic state of the EXT /INT pin. T he active edge
where the data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output
frame synchronization for use with the internal data clock (EXT /INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and
remains HIGH while SDOUT output is valid. When a read sequence is initiated and
INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is
valid.
DAT A[10]
or SYNC
24
DAT A[11]
D O
When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output
Bus.
or RDERROR
When SER/PAR is H IGH and EXT /INT is H IGH , this output, part of the serial port,
is used as a incomplete read error flag. In slave mode, when a data read is started and
not complete when the following conversion is complete, the current data is lost and
RDERROR is pulsed high.
25–28
29
DAT A[12:15] D O
Bit 12 to Bit 15 of the Parallel Port Data output bus. T hese pins are always outputs regard
less of the state of SER/PAR.
Busy Output. T ransitions HIGH when a conversion is started, and remains HIGH until
the conversion is complete and the data is latched into the on-chip shift register. T he fall
ing edge of BUSY could be used as a data ready clock signal.
Must Be T ied to Digital Ground
BU SY
D O
30
31
DGND
RD
P
D I
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
32
CS
D I
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external clock.
REV. PrA
–7–
PRELIMINARYTECHNICALDATA
AD7667
Pin No.
33
Mnemonic
RESET
T ype
D I
D escription
Reset Input. When set to a logic HIGH, reset the AD7667. Current conversion if any is
aborted. If not used, this pin could be tied to DGND.
34
35
PD
D I
D I
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver
sions are inhibited after the current one is completed.
CNVST
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state
and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold
is put into the hold state and a conversion is immediately started.
Must Be T ied to Analog Ground
Reference Input Voltage
Reference Input Analog Ground
Analog Input Ground
Primart Analog Input with a Range of 0 to 2.5 V.
36
37
38
39
43
45
46
47
AGND
REF
REFG N D
IN GN D
IN
T EMP
REFBUFIN
PD REF
P
AI
AI
AI
AI
AO
AI/O
DI
T emperature sensor voltage output.
Reference Input Voltage. T he reference output and the reference buffer input.
Allows choice of Internal or External voltage reference. When HIGH, the internal refer-
ence is switched off and an external reference must be used. When low,the on-chip refer
ence is turned on.
48
PDBUF
DI
Allows choice of buffering internal reference. When LOW, the buffer is selected. When
HIGH, the buffer is switched off.
N OT ES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
–8–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
ENOB = (S/[N+D]dB – 1.76)/6.02
and is expressed in bits.
DEFINIT ION OF SPECIFICAT IONS
INT EGRAL NONLINEARIT Y ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive full
scale.” T he point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
T OT AL HARMONIC DIST ORT ION (T HD)
TH D is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
SIGNAL-T O-NOISE RAT IO (SNR)
DIFFERENT IAL NONLINEARIT Y ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differen-
tial nonlinearity is the maximum deviation from this ideal
value. It is often specified in terms of resolution for which no
missing codes are guaranteed.
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. T he value for SNR is
expressed in decibels.
SIGNAL T O (NOISE + DIST ORT ION) RAT IO
(S/[N +D ])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. T he
value for S/(N+D) is expressed in decibels.
FULL-SC ALE ERROR
T he last transition (from 011 . . . 10 to 011 . . . 11 in two’s
complement coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.49994278 V for the 0 V–2.5 V
range). T he full-scale error is the deviation of the actual level of
the last transition from the ideal level.
APERT URE D ELAY
UNIPOLAR ZERO ERROR
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
T he first transition should occur at a level 1/2 LSB above analog
ground (19.073 µV for the 0 V–2.5 V range). Unipolar zero error is
the deviation of the actual transition from that point.
T RANSIENT RESPONSE
T he time required for the AD7667 to achieve its rated accu-
racy after a full-scale step function is applied to its input.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
T he difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
OVERVOLT AGE RECOVERY
EFFECT IVE NUMBER OF BIT S (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
T he time required for the ADC to recover to full accuracy
after an analog input signal 150% of full-scale is reduced to
50% of the full-scale value.
REV. PrA
–9–
PRELIMINARYTECHNICALDATA
AD7667
0
-20
0
-20
-40
-40
-60
TO BE
-60
-80
TO BE
-80
SUPPLIED
SUPPLIED
-100
-120
-140
-160
-100
-120
-140
-160
1
1
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
0
-20
0
-20
-40
-40
-60
TO BE
-60
TO BE
-80
SUPPLIED
-80
SUPPLIED
-100
-120
-140
-160
-100
-120
-140
-160
1
1
TPC 2. Histogram of 16,384 Conversions of a DC Input at
the Code Transition
TPC 5. Histogram of 16,384 Conversions of a DC Input at
the Code Center
0
-20
-40
0
-20
-40
-60
TO BE
-60
TO BE
-80
SUPPLIED
-80
SUPPLIED
-100
-120
-140
-100
-120
-140
-160
1
-160
1
TPC 6. SNR, THD vs. Temperature
TPC 3. FFT Plot
–10–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
0
-20
0
-20
-40
-40
-60
TO BE
-60
-80
TO BE
-80
SUPPLIED
SUPPLIED
-100
-120
-140
-160
-100
-120
-140
-160
1
1
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
TPC 10. THD, Harmonics, and SFDR vs. Frequency
0
-20
0
-20
-40
-40
-60
TO BE
-60
TO BE
-80
SUPPLIED
-80
SUPPLIED
-100
-120
-140
-160
-100
-120
-140
1
-160
1
TPC 8. SNR and S/(N+D) vs. Input Level
(Referred to Full Scale)
TPC 11. Typical Delay vs. Load Capacitance CL
0
0
-20
-40
-20
-40
-60
TO BE
-60
-80
TO BE
-80
SUPPLIED
SUPPLIED
-100
-120
-140
-160
-100
-120
-140
-160
1
1
TPC 9. Operating Currents vs. Sample Rate
TPC 12. Power-Down Operating Currents vs. Temperature
REV. PrA
–11–
PRELIMINARYTECHNICALDATA
AD7667
C IRC UIT INFO RMATIO N
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
T he AD 7667 is a very fast, low power, single supply, pre-
cise 16-bit analog-to-digital converter (AD C). T he
AD 7667 features different modes to optimize performances
according to the applications.
Modes of O per ation
The AD7667 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
In warp mode, the AD 7667 is capable of converting
1,000,000 samples per second (1MSPS).
The Warp mode allows the fastest conversion rate up to 1
MSPS. However, in this mode, and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con-
secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. This
mode makes the AD7667 ideal for applications where both high
accuracy and fast sample rate are required.
T he AD 7667 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
T he AD 7667 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed
in either a 48-lead LQFP package or a 48-lead LFCSP that
saves space and allows flexible configurations as either serial or
parallel interface. T he AD7667 is a pin-to-pin compatible
upgrade of the AD7661/64/66.
The normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode
makes the AD7667 ideal for asynchronous applications such as
data acquisition systems, where both high accuracy and fast
sample rate are required.
C O NVE RTE R O P E RATIO N
The AD7667 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to a
“dummy” capacitor of the same value as the capacitive DAC
array.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 15 µW. This feature
makes the AD7667 ideal for battery-powered applications.
Tr ansfer Functions
Using the OB/2C digital input, the AD7667 offers two output
codings: straight binary and two’s complement. The LSB size is
VREF/65536, which is about 38.15 µV. The ideal transfer charac-
teristic for the AD7667 is shown in Figure 4 and Table I.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
1 LSB = V
/65536
REF
111...111
When the CNVST input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SWA and SWB are
opened first. The capacitor array and the “dummy” capacitor are
then disconnected from the inputs and connected to the REF-
GND input. Therefore, the differential voltage between IN and
INGND captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4, . . . VREF/65536).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
111...110
111...101
000...010
000...001
000...000
0V
0.5 LSB
1 LSB
V
› 1 LSB
REF
V
REF
› 1.5 LSB
ANALOG INPUT
Figure 4. ADC Ideal Transfer Function
IN
REF
REFGND
SWITCHES
CONTROL
MSB
32,768C 16,384C
LSB
SW
A
4C
2C
C
C
BUSY
CONTROL
LOGIC
COMP
INGND
OUTPUT
CODE
65,536C
SW
B
CNVST
Figure 3. ADC Simplified Schematic
–12–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
Table I. O utput Codes and Ideal Input Voltages
TYP IC AL C O NNE C TIO N D IAGRAM
Figure 5 shows a typical connection diagram for the AD7667.
D igital O utput Code
H exa
Analog Input
Figure 6 shows an equivalent circuit of the input structure of
the AD 7667.
Analog
Input
Str aight
Binar y
Two’s
Com ple-
D
escr iption
m ent
AVDD
D1
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
2.499962 V
2.499923 V
1.250038 V
1.25 V
1.249962 V
38 µV
FFFF1
FFFE
8001
7FFF1
7FFE
0001
C2
R1
IN
OR INGND
C1
D2
8000
0000
AGND
7FFF
0001
FFFF
8001
0 V
00002
80002
Figure 6. Equivalent Analog Input Circuit
NOT ES
The two diodes D 1 and D 2 provide ESD protection for
the analog inputs IN and INGND. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V. T his will cause these diodes to
become forward-biased and start conducting current.
T hese diodes can handle a forward-biased current of 100
mA maximum. For instance, these conditions could eventu-
ally occur when the input buffer’s (U1) supplies are
1T his is also the code for overrange analog input (VIN – VINGND above
VREF – VREFGND).
2T his is also the code for underrange analog input (VIN below VINGND).
ANALOG
SUPPLY
(5V)
100ꢂ
DIGITAL SUPPLY
(3.3V OR 5V)
10ꢀF
100nF
10ꢀF
100nF
100nF
10ꢀF
AVDD AGND
DGND
DVDD
OVDD
OGND
SERIAL
PORT
SCLK
REF
REFBUFIN
SDOUT
100 nF
1
47ꢀF
REFGND
BUSY
ꢀC/ ꢀP/DSP
AD7667
CNVST
3
D
15ꢂ
2
U1
IN
ANALOG INPUT
(0V TO 2.5V)
OB/2C
SER/PAR
DVDD
2.7nF
C
C
WARP
BYTESWAP
INGND
IMPULSE
PDREF PD PDBUF
RESET
CS
RD
CLOCK
NOTES:
1
THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER
THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL LOW JITTER CNVST.
2
3
Figure 5. Typical Connection Diagram
REV. PrA
–13–
PRELIMINARYTECHNICALDATA
AD7667
Source Resistance
different from AVDD. In such case, an input buffer with a
short circuit current limitation can be used to protect the
part.
D r iver Am plifier C h oice
Although the AD7667 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
T his analog input structure allows the sampling of the
differential signal between IN and INGND. Unlike other
converters, the INGND input is sampled at the same time as
the IN input. By using this differential input, small signals
common to both inputs are rejected, as shown in Figure 7,
which represents the typical CMRR over frequency. For in-
stance, by using INGND to sense a remote signal ground,
difference of ground potentials between the sensor and the
local ADC ground are eliminated.
−
The driver amplifier and the AD7667 analog input circuit
must be able together to settle for a full-scale step the capaci-
tor array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, the settling at 0.1% to 0.01% is more commonly speci-
fied. It could significantly differ from the settling time at 16
bit level and it should therefore be verified prior to the
driver selection. The tiny op amp AD8021, which com-
bines ultralow noise and a high-gain bandwidth, meets
this settling time requirement even when used with high
gain up to 13.
0
-20
-40
−
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7667. The noise
coming from the driver is filtered by the AD7667 analog
input circuit one-pole low-pass filter made by R1 and C2
or the external filter if any is used. The SNR degredation
due to the amplifier is:
-60
TO BE
-80
SUPPLIED
-100
-120
-140
-160
1
28
Figure 7. Analog Input CMR vs. Frequency
SNRLOSS = 20 LOG
2
)
During the acquisition phase, the impedance of the analog
input IN can be modeled as a parallel combination of ca-
pacitor C1 and the network formed by the series connection
of R1 and C2. Capacitor C1 is primarily the pin capacitance.
T he resistor R1 is typically 183 ꢂ and is a lumped compo-
nent made up of some serial resistors and the on resistance of
the switches. The capacitor C2 is typically 60 pF and is mainly
the ADC sampling capacitor. During the conversion phase, where
the switches are opened, the input impedance is limited to C1. The
R1, C2 makes a one-pole low-pass filter that reduces undesir-
able aliasing effect and limits the noise.
ꢁ f
2
(
N e
)
(
784 +
-3dB
N
where
f–3dB is the –3 dB input bandwidth of the AD7667 in MHz
(14.5) or the cutoff frequency of the input filter if
any used.
N
is the noise gain of the amplifier (1 if in buffer
configuration).
e N is the equivalent input noise voltage of the op amp
in
nV/
(H z)1/2
.
When the source impedance of the driving circuit is low,
the AD 7667 can be driven directly. Large source imped-
ances will significantly affect the ac performances,
especially the total harmonic distortion. T he maximum
source impedance depends on the amount of total harmonic
distortion (T HD) that can be tolerated. T he T HD degrades
in function of the source impedance and the maximum input
frequency as shown in Figure T BD.
For instance, a driver like the AD8021, with an equivalent
input noise of 2 nV/ Hz and configured as a buffer, thus with
a noise gain of 1, the SNR degrades by only 0.13 dB with the
filter used in figure 5.
−
The driver needs to have a THD performance suitable to that
of the AD7667.
T he AD8021 meets these requirements and is usually appro-
priate for almost all applications. T he AD8021 needs an
external compensation capacitor of 10 pF. T his capacitor
should have good linearity as an NPO ceramic or mica type.
0
-20
-40
-60
TO BE
T he AD8022 could also be used where dual version is needed
and gain of 1 is used.
-80
SUPPLIED
-100
-120
-140
-160
1
Figure 8. THD vs. Analog Input Frequency and
–14–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
T he AD829 is another alternative where high-frequency
(above 100 kHz) performance is not required. In gain of
1, it requires an 82 pF compensation capacitor.
For the external reference, the voltage reference input REF
of the AD7667 has a dynamic input impedance; it should
therefore be driven by a low-impedance source with an
efficient decoupling between REF and REFGND inputs.
T his decoupling depends on the choice of the voltage refer-
ence but usually consists of a 1 µF ceramic capacitor and a
low ESR tantalum capacitor connected to the REF and
REFGN D inputs with minimum parasitic inductance. 47
µF is an appropriate value for the tantalum capacitor when
using either the internal reference of one of the recom-
mended reference voltages:
T he AD8610 is another option where low bias current is
needed in low-frequency applications.
Voltage Refer en ce In pu t
T he AD7667 allows the choice of either an internal 2.5 V
voltage reference or an external 2.5 V reference.
T o use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. T his will pro-
duce a voltage on REFBUFIN of 1.25 V and the buffer’s
gain will be 2, resulting in a 2.5 V reference on REF pin.
− T he low noise, low temperature drift ADR421 and
AD780 voltage references
T o use an external reference along with the internal
buffer, PDREF should be HIGH and PDBUF should be
LOW. T his powers down the internal reference and allows
for the 2.5 V reference to be applied to REFBUFIN. In
this mode the buffer’s gain is 1.
− T he low power ADR291 voltage reference
− T he low cost AD1582 voltage reference
For applications using multiple AD7667s, it is more effective
to buffer the reference voltage using the internal buffer. T o
do so, PDREF should be HIGH, and PDBUF should be low.
T o use both external reference, PDREF and PDBUF
should both be HIGH. T he reference input should be
applied to REF.
Care should also be taken with the reference temperature
coefficient of the voltage reference which directly affects the
full-scale accuracy if this parameter matters. For instance, a
±15 ppm/°C tempco of the reference changes the full scale by
±1 LSB/°C.
It is useful to decouple the REFBUFIN pin with a 100 nF
ceramic capacitor. T he output impedance of the REFBUFIN
pin is 4 kꢂ. T hus, the 100 nF capacitor provides an RC filter
for noise reduction.
VREF , as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of VREF, this would essentially increase the
range to make it a 0 to 3 V input range with an AVDD above
4.85 V. One of the benefits here is the additional SNR ob-
tained as a result of this increase. The theoretical
improvement as a result of this increase in reference is 1.58
dB (20 log [3/2.5]). Due to the theoretical quantization
noise, however, the observed improvement is approximately
1 dB. T he AD780 can be selected with a 3 V reference
voltage.
It should be noted that the internal reference and internal
buffer are independent of the power down (PD ) pin of the
part. Powering down the part does not power down the inter-
nal reference or the internal buffer. Furthermore, powering
down the internal reference and internal buffer, as well as
powering them up, requires time. T his is due to the fact that
we have charging and discharging capacitors on the REF
which require some settling time. T herefore, for applications
requiring low power, there will always be a typical of 10 mW
of power dissipated when using the internal reference and
internal buffer even during times with no conversions.
T he T EMP pin, which measures the temperature of the
AD7667, can be used as follows. Refer to figure T BD to
see the connectivity. T he output of the T EMP pin is ap-
plied to one of the inputs of the analog switch (ADG779).
T he other input, as shown is the analog signal. T he output
of the switch is connected to the AD8021 which is config-
ured as a follower. T he output of the op-amp is applied to
the IN pin. Refer to the Specification T able for the appro-
priate values related to the T EMP pin. T his configuration
could be very useful to improve the calibration accuracy
over the temperature range.
T he internal reference is temperature compensated to
2.5V ± T BD mV. T he reference is trimmed to provide
a typical drift of T BD ppm/ꢂC. T his typical drift char-
acteristic is shown in Figure T BD . For improved drift
performance, an external reference such as the AD 780
can be used
.
0
-20
-40
-60
TO BE
TEMP
-80
ADG779
SUPPLIED
-100
-120
-140
-160
temperature
sensor
ANALOG INPUT
(UNIPOLAR)
IN
C
AD8021
C
AD7667
IN
1
Figure TBD
REV. PrA
–15–
PRELIMINARYTECHNICALDATA
AD7667
Figur e TBD
t2
t1
CNVST
P ower Supply
The AD7667 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. T he OVDD supply
allows direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. To reduce the number of supplies needed,
the digital core (D VD D ) can be supplied through a simple
RC filter from the analog supply as shown in Figure 5. The
AD7667 is independent of power supply sequencing, once
OVDD does not exceed DVDD by more than 0.3V, and thus
free from supply voltage induced latchup.
BUSY
MODE
t4
t3
t5
t6
ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
Figure 11. Basic Conversion Timing
In impulse mode, conversions can be automatically initi-
ated. If CNVST is held low when BUSY is low, the
AD7667 controls the acquisition phase and then automati-
cally initiates a new conversion. By keeping CNVST low,
the AD7667 keeps the conversion process running by itself.
It should be noted that the analog input has to be settled
when BUSY goes low. Also, at power-up, CNVST
should be brought low once to initiate the conversion pro-
cess. In this mode, the AD7667 could sometimes run
slightly faster then the guaranteed limits in the impulse mode
of 666 kSPS. This feature does not exist in warp or normal
m odes.
P O WE R D ISSIP ATIO N Vs. TH RO UGH P UT
Operating currents are very low during the acquisition phase,
which allows a significant power saving when the conversion rate
is reduced as shown in Figure 10. This power saving depends on
the mode used. In impulse mode, the AD7667 automatically
reduces its power consumption at the end of each conversion
phase. This feature makes the AD7667 ideal for very low power
battery applications. It should be noted that the digital interface
remains active even during the acquisition phase. To reduce the
operating digital supply currents even further, the digital inputs
need to be driven close to the power supply rails (i.e., DVDD or
DGND) and OVDD should not exceed DVDD by more than
0.3V.
t9
RESET
0
-20
-40
BUSY
DATA
-60
TO BE
-80
SUPPLIED
-100
-120
-140
t8
-160
CNVST
1
Figure12. RESETTiming
Figure 10. Power Dissipation vs. Sample Rate
Although CNVST is a digital signal, it should be de-
signed with special care with fast, clean edges, and levels
with minimum overshoot and undershoot or ringing.
C O NVE R S IO N C O NT R O L
Figure 11 shows the detailed timing diagrams of the conver-
sion process. T he AD7667 is controlled by the signal CNVST
which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input PD, until
the conversion is complete. T he CNVST signal operates
independently of CS and RD signals.
It is a good thing to shield the CNVST trace with ground and
also to add a low value serial resistor (i.e., 50 ꢀ) termination
close to the output of the component that drives this line.
For applications where the SN R is critical, CNVST signal
should have a very low jitter. Some solutions to achieve that is
to use a dedicated oscillator for CNVST generation or, at least,
to clock it with a high-frequency low-jitter clock as shown in
Figure 5.
D IG IT AL INT E R F AC E
T he AD7667 has a versatile digital interface; it can be
interfaced with the host system by using either a serial or
–16–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
parallel interface. T he serial interface is multiplexed on
the parallel data bus. T he AD7667 digital interface also
accommodates both 3 V or 5 V logic by simply connecting
the OVDD supply pin of the AD7667 to the host system
interface digital supply. Finally, by using the OB/2C in-
put pin, both two’s complement or straight binary coding
can be used.
low in a single AD7667 design. RD is generally used to
enable the conversion result on the data bus.
T he two signals CS and RD control the interface. CS and RD
have a similar effect because they are OR’d together inter-
nally. When at least one of these signals is high, the interface
outputs are in high impedance. Usually, CS allows the selec-
tion of each AD7667 in multicircuits applications and is held
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
CS, RD
t3
CNVST
BUSY
t28
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
2
t26
1
3
14
15
16
SCLK
t15
t27
D15
D14
t23
D2
D1
D0
SDOUT
X
t16
t22
Figure 16. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
CNVST
BUSY
t1
t3
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
14
15
16
t18
t27
SDOUT
X
D15
D14
t23
D2
D1
D0
t16
t22
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
REV. PrA
–17–
PRELIMINARYTECHNICALDATA
AD7667
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
BUSY
t35
t36 t37
SCLK
1
2
3
14
15
16
17
18
t31
t32
X
SDOUT
D15
D14
D13
X13
D1
D0
X0
X15
Y15
X14
Y14
t16
t34
SDIN
X15
X14
X1
t33
Figure 18. Slave Serial Data Timing for Reading (Read After Convert)
CS = RD = 0
CNVST
CS
t1
RD
t10
BUSY
t4
t3
BUSY
t11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
DATA
BUS
CURRENT
CONVERSION
t12
t13
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
Figure 14. Slave Parallel Data Timing for Reading
(Read After Convert)
P ARALLE L INTE RFAC E
T he AD7667 is configured to use the parallel interface when
the SER/PAR is held low. T he data can be read either after
each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figure 14 and Figure 15. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. T hat avoids
any potential feedthrough between voltage transients on the
digital interface and the most critical analog conversion cir-
cuitry.
T he BYT ESWAP pin allows a glueless interface to a 8 bits
bus. As shown in Figure T BD, the LSB byte is output on
D[7:0] and the MSB is output on D[15:8] when
BYT ESWAP is low. When BYT ESWAP is high, the LSB and
MSB bytes are swapped and the LSB is output on D[15:8]
and the MSB is output on D[7:0]. By connecting
BYT ESWAP to an address line, the 16 bits data can be read
in 2 bytes on either D[15:8] or D[7:0].
–18–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
RD = 0
EXT/INT = 1
INVSCLK = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
14
15
16
t31
t32
D14
SDOUT
X
D15
D13
D1
D0
t16
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
M AST E R SE RIAL INT E RF AC E
Inter nal C lock
CS
RD
The AD7667 is configured to generate and provide the serial
data clock SCLK when the EXT /INT pin is held low. T he
AD7667 also generates a SYNC signal to indicate to the host
when the serial data is valid. T he serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on RDC/
SDIN input, the data can be read after each conversion or
during the following conversion. Figure 16 and Figure 17
BYTE
HI-Z
HI-Z
Pins D[15:8]
Pins D[7:0]
HIGH BYTE
LOW BYTE
LOW BYTE
show the detailed timing diagrams of these two modes.
t
t
t
12
12
HIGH BYTE
13
Usually, because the AD7667 is used with a fast throughput,
the mode master, read during conversion is the most recom-
mended serial mode when it can be used.
HI-Z
HI-Z
In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical conver-
sion decisions.
Figure TBD, 8-bit Parallel Interface
CS = 0
t1
CNVST
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
,
RD
BUSY
t4
SLAVE SERIAL INTERFACE
t3
E xter nal C lock
T he AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT /INT pin is
held high. In this mode, several methods can be used to read
the data. T he external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion
or during the following conversion. The external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when inac-
tive. Figure 18 and Figure 20 show the detailed timing diagrams
of these methods.
DATA
BUS
PREVIOUS
CONVERSION
t12
t13
Figure 15. Slave Parallel Data Timing for Reading
(Read During Convert)
SE RIAL INTE RFAC E
T he AD7667 is configured to use the serial interface when
the SER/PAR is held high. T he AD7667 outputs 16 bits of
data, MSB first, on the SDOUT pin. T his data is synchro-
nized with the 16 clock pulses provided on SCLK pin. T he
output data is valid on both the rising and falling edge of the
data clock.
While the AD7667 is performing a bit decision, it is impor-
tant that voltage transients not occur on digital input/output
pins or degradation of the conversion result could occur.
T his is particularly important during the second half of the
conversion phase because the AD7667 provides error cor-
rection circuitry that can correct for an improper bit
REV. PrA
–19–
PRELIMINARYTECHNICALDATA
AD7667
decision made during the first half of the conversion
phase. For this reason, it is recommended that when an
external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is low or, more
importantly, that it does not transition during the latter
half of BUSY high.
valid on both rising and falling edge of the clock. T he 16
bits have to be read before the current conversion is com-
plete. If that is not done, RDERROR is pulsed high and
can be used to interrupt the host interface to prevent
incomplete data reading. T here is no “daisy chain”
feature in this mode and RD C/SD IN input should al-
ways be tied either high or low.
E xter n al D iscon tin u ou s C lock D ata Read After C on ver -
sion
T o reduce performance degradation due to digital activity, a
fast discontinuous clock of, at least 25 MHz, when impulse mode is
used, 32 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is
also possible to begin to read the data after conversion and
continue to read the last bits even after a new conversion has
been initiated. T hat allows the use of a slower clock speed like
18 MHz in impulse mode, 21 MHz in normal mode and 26
MHz in warp mode.
T hough the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 18 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the result of this conversion can be read while
both CS and RD are low. T he data is shifted out, MSB first,
with 16 clock pulses and is valid on both rising and falling
edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
MIC RO P RO C E SSO R INT E RF AC ING
T he AD 7667 is ideally suited for traditional dc measure-
ment applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
The AD7667 is designed to interface either with a parallel 16-
bit-wide interface or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7667 to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the
AD7667 with an SPI-equipped microcontroller, the AD SP-
21065L and AD SP-218x signal processors.
Another advantage is to be able to read the data at any speed
up to 40 MHz which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7667 provides a “daisy-
chain” feature using the RDC/SDIN input pin for cascading
multiple converters together. This feature is useful for reducing
component count and wiring connections when desired as, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a com-
mon CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.
SP I Inter face (MC 68H C 11)
Figure 21 shows an interface diagram between the AD7667
and an SPI-equipped microcontroller like the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7667 acts as a slave device and data must be read after
conversion. T his mode allows also the “daisy chain” feature.
The convert command could be initiated in response to
an internal timer interrupt. T he reading of output data,
one byte at a time, if necessary, could be initiated in
response to the end-of-conversion signal (BUSY going
low) using to an interrupt line of the microcontroller. T he
Serial Peripheral Interface (SPI) on the M C 68H C 11 is
configured for master mode (MST R = 1), Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI Interrupt Enable (SPIE = 1) by writing to the SPI Con-
trol Register (SPCR). T he IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPT ION
register).
BUSY
OUT
BUSY
BUSY
AD7667
#2
(UPSTREAM)
AD7667
#1
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
SCLK IN
CS IN
CNVST IN
Figure 19. Two AD7667s in a “Daisy-Chain” Configuration
E xter n al C lock D ata Read D u r in g C on ver sion
Figure 20 shows the detailed timing diagrams of this
method. During a conversion, while both CS and RD are
both low, the result of the previous conversion can be read.
T he data is shifted out, MSB first, with 16 clock pulses and is
–20–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
Figure 23 shows a connection diagram which allows
that. C omponents values required and resulting full-
scale ranges are shown in T able II.
DVDD
DVDD
AD7667*
MC68HC11*
SER/PAR
For applications where accurate gain and offset are de-
sired, they can be calibrated by acquiring a ground and a
voltage reference using an analog multiplexer, U2, as
shown for bipolar input ranges in Figure 23.
EXT/INT
IRQ
BUSY
SDOUT
SCLK
CS
RD
MISO/SDI
SCK
CNVST
INVSCLK
I/O PORT
C
F
*ADDITIONAL PINS OMITTED FOR CLARITY
R1
Figure 21. Interfacing the AD7667 to SPI Interface
AD SP -21065L in Master Ser ial Inter face
R2
ANALOG
INPUT
As shown in Figure 22, the AD 7667 can be interfaced to
the ADSP-21065L using the serial interface in master mode
without any glue logic required. T his mode combines the
advantages of reducing the number of wire connections and
being able to read the data during or after conversion at user
convenience.
IN
U1
AD7667
U2
100nF
100nF
R3
R4
INGND
REF
T he AD7667 is configured for the internal clock mode (EXT/
INT low) and acts, therefore, as the master device. T he con-
vert command can be generated by either an external low
jitter oscillator or, as shown, by a FLAG output of the ADSP-
21065L or by a frame output TFS of one serial port of the
ADSP-21065L which can be used as a timer. T he serial port
on the ADSP-21065L is configured for external clock (IRFS
= 0), rising edge active (CKRE = 1), external late framed
sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active
high (LRFS = 0). T he serial port of the ADSP-21065L is
configured by writing to its receive control register
C
REF
REFGND
Figure 23. Using the AD7667 in 16-Bit Bipolar and/or
Wider Input Ranges
Table II. Com ponent Values and Input Ranges
(SRCT L)—see AD SP-2106x SH ARC User’s Manual. Be-
cause the serial port within the ADSP-21065L will be seeing a
discontinuous clock, an initial word reading has to be done after
the ADSP-21065L has been reset to ensure that the serial
port is properly synchronized to this clock during each follow-
ing data read operation.
Input Range
R1
R2
R3
R4
±10 V
±5 V
0 V to –5 V
250 ꢂ
500 ꢂ
1 kꢂ
2 kꢂ
2 kꢂ
2 kꢂ
10 kꢂ
10 kꢂ
N one
8 kꢂ
6.67 kꢂ
0 ꢂ
L a yo u t
DVDD
T he AD7667 has very good immunity to noise on the
power supplies as can be seen in Figure 9. However, care
should still be taken with regard to grounding layout.
AD7667*
ADSP-21065L*
DVDD
SHARC
SER/PAR
T he printed circuit board that houses the AD7667 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. T his facilitates the use
of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7667, or, at least, as close as
possible to the AD7667. If the AD7667 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point, which should be established as close as possible
to the AD7667.
RDC/SDIN
RD
EXT/INT
RFS
DR
SYNC
SDOUT
SCLK
CS
INVSYNC
INVSCLK
RCLK
CNVST
FLAG OR TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the ADSP-21065L Using the
Serial Master Mode
AP P LIC ATIO N H INTS
It is recommended to avoid running digital lines under
the device as these will couple noise onto the die. The ana-
log ground plane should be allowed to run under the
AD7667 to avoid noise coupling. Fast switching signals
like CNVST or clocks should be shielded with digital
ground to avoid radiating noise to other sections of the
board, and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run
Bipolar and Wider Input Ranges
In some applications, it is desired to use a bipolar or wider
analog input range like, for instance, ±10 V, ±5 V or 0 V to 5 V.
Although the AD7667 has only one unipolar range, by simple
modifications of the input driver circuitry, bipolar and wider
input ranges can be used without any performance degradation.
REV. PrA
–21–
PRELIMINARYTECHNICALDATA
AD7667
at right angles to each other. T his will reduce the effect of
feedthrough through the board.
T he power supplies lines to the AD7667 should use as
large trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supplies lines.
Good decoupling is also important to lower the supplies
impedance presented to the AD7667 and reduce the magni-
tude of the supply spikes. Decoupling ceramic capacitors,
typically 100 nF, should be placed on each power supplies
pins AVDD, DVDD, and OVDD close to, and ideally right
up against, these pins and their corresponding ground pins.
Additionally, low ESR 10 µF capacitors should be located in
the vicinity of the ADC to further reduce low frequency
ripple.
The DVDD supply of the AD7667 can be either a separate
supply or come from the analog supply AVDD or the digi-
tal interface supply OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is
recommended that if no separate supply available, connect
the DVDD digital supply to the analog supply, AVD D ,
through an RC filter as shown in Figure 5, and connect
the system supply to the interface digital supply, OVDD,
and the remaining digital circuitry. When DVDD is powered
from the system supply, it is useful to insert a bead to fur-
ther reduce high-frequency spikes.
The AD7667 has five different ground pins: INGND, REF-
GND, AGND, DGND, and OGND. INGND is used to
sense the analog input signal. REFGN D senses the refer-
ence voltage and should be a low impedance return to the
reference because it carries pulsed currents. AGN D is the
ground to which most internal ADC analog signals are
referenced. T his ground must be connected with the least
resistance to the analog ground plane. DGND must be
tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system
ground.
E va lu a tin g th e AD 7667 P er for m a n ce
A recommended layout for the AD 7667 is outlined in the
evaluation board for the AD7667. T he evaluation board
package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from a PC via the Eval-Control Board.
–22–
REV. PrA
PRELIMINARYTECHNICALDATA
AD7667
OUT LINE DIMENSIONS
D imensions shown in inches and (mm).
48-Lead Quad Flatpack (LQFP)
(ST -48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
25
12
0ꢁ
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7ꢁ
0ꢁ
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
48-Lead Frame Chip Scale Package (LQFP)
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.276 (7.0)
BSC SQ
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
37
48
36
1
PIN 1
INDICATOR
0.215 (5.45)
0.209 (5.30) SQ
0.203 (5.15)
0.266 (6.75)
BSC SQ
TOP
VIEW
BOTTOM
VIEW
12
25
0.020 (0.50)
24
13
0.016 (0.40)
0.012 (0.30)
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.031 (0.80) MAX
0.026 (0.65) NOM
12ꢁ MAX
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
0.039 (1.00) MAX
0.033 (0.85) NOM
0.020 (0.50)
BSC
Pad Connected to AGND
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. PrA
–23–
相关型号：
AD7671ACPZRL
4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, MO-220VKKD-2, LFCSP-48
ADI
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