AD7674_17 [ADI]
18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC;
| 型号： | AD7674_17 |
| 厂家： | 
ADI |
| 描述： | 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC |
| 文件： | 总29页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC
Data Sheet
AD7674
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PDBUF
REF
REFGND
DVDD DGND
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range:
Throughput
AGND
AVDD
OVDD
OGND
AD7674
VREF (VREF up to 5 V)
SERIAL
PORT
REFBUFIN
18
IN+
IN–
800 kSPS (warp mode)
666 kSPS (normal mode)
570 kSPS (impulse mode)
INL: 2.5 LSB max ( 9.5 ppm of full scale)
Dynamic range : 103 dB typ (VREF = 5 V)
SINAD: 100 dB typ at 2 kHz (VREF = 5 V)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3 V interface
SPI/QSPI™/MICROWIRE/DSP compatible
On-board reference buffer
SWITCHED
CAP DAC
D[17:0]
BUSY
PARALLEL
INTERFACE
RD
CS
CLOCK
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
MODE0
MODE1
RESET
CNVST
IMPULSE
WARP
03083–0–001
Single 5 V supply operation
Figure 1.
Power dissipation
98 mW typ at 800 kSPS
Table 1. PulSARTM Selection
100 kSPS to 500 kSPS to
800 kSPS to
1000 kSPS
78 mW typ at 500 kSPS (impulse mode)
160 µW at 1 kSPS (impulse mode)
48-lead LQFP or 48-lead LFCSP
Pin-to-pin compatible upgrade of AD7676, AD7678,
and AD7679
Type
250 kSPS
570 kSPS
Pseudo-
Differential
AD7651,
AD7660/
AD7661
AD7650/AD7652, AD7653,
AD7664/AD7666
AD7667
True Bipolar
AD7663
AD7665
AD7671
AD7677
AD7674
True Differential AD7675
AD7676
APPLICATIONS
18-Bit
AD7678
AD7679
CT scanners
Multichannel/
Simultaneous
AD7654, AD7655
High dynamic data acquisition
Geophone and hydrophone sensors
∑-∆ replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput. The AD7674 is an
800 kSPS, charge redistribution, 18-bit, SAR ADC (no
latency).
GENERAL DESCRIPTION
2. Excellent Accuracy. The AD7674 has a maximum integral
nonlinearity of 2.5 LSB with no missing 18-bit codes.
The AD7674 is an 18-bit, 800 kSPS, charge redistribution,
successive approximation register (SAR) fully differential
analog-to-digital converter (ADC) that operates on a single 5 V
power supply. The device contains a high speed, 18-bit sampling
ADC, an internal conversion clock, an internal reference buffer,
error correction circuits, and both serial and parallel system
interface ports.
3. Serial or Parallel Interface. Versatile parallel (18-, 16- or
8-bit bus) or 3-wire serial interface arrangement
compatible with both 3 V and 5 V logic.
The device is available in a 48-lead LQFP or a 48-lead LFCSP
with operation specified from −40°C to +85°C.
Rev. B
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Technical Support
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AD7674* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD7674 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7674 Evaluation Kit
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD7674 EngineerZone Discussions.
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
Data Sheet
SAMPLE AND BUY
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• AD7674: 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC Data
Sheet
TECHNICAL SUPPORT
Product Highlight
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number.
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DOCUMENT FEEDBACK
REFERENCE MATERIALS
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Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
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AD7674
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 16
Typical Connection Diagram ................................................... 17
Power Dissipation versus Throughput .................................... 20
Conversion Control ................................................................... 20
Digital Interface.......................................................................... 20
Parallel Interface......................................................................... 21
Serial Interface............................................................................ 21
Master Serial Interface............................................................... 21
Slave Serial Interface .................................................................. 23
Microprocessor Interfacing....................................................... 24
Applications Information.............................................................. 25
Layout .......................................................................................... 25
Evaluating AD7674 Performance............................................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Table of Contents.............................................................................. 2
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information........................................................................ 16
REVISION HISTORY
6/2016—Rev. A to Rev. B
Changed CP-48-1 to CP-48-4 and ADSP-219x to
ADSP-2191M ................................................................. Throughout
Changes to Figure 4 and Table 6..................................................... 8
Added Figure 5; Renumbered Sequentially .................................. 8
Changes to Serial Peripheral Interface (SPI) Section................. 24
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
6/2009—Rev. 0 to Rev. A
Changes to Zero Error, TMIN to TMAX Parameter........................... 3
Changes to Gain Error, TMIN to TMAX Parameter........................... 3
Changes to Endnote 3 ...................................................................... 4
Changes to Pin Configuration Section.......................................... 8
Changes to Evaluating the AD7674’s Performance Section...... 25
Changes to Ordering Guide .......................................................... 26
7/2003—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
AD7674
SPECIFICATIONS
−40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
VIN+, VIN− to AGND
fIN = 100 kHz
−VREF
−0.1
+VREF
AVDD
V
V
dB
µA
Operating Input Voltage
Analog Input CMRR
Input Current
65
100
800 kSPS throughput
Input Impedance1
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Zero Error, TMIN to TMAX
Zero Error, TMIN to TMAX
Zero Error Temperature Drift
In warp mode
In warp mode
In warp mode
In normal mode
In normal mode
In impulse mode
In impulse mode
1.25
800
1
µs
kSPS
ms
µs
kSPS
µs
1
1.5
0
0
666
1.75
570
kSPS
−2.5
−1
18
+2.5
+1.75
LSB2
LSB
Bits
LSB
LSB
LSB
ppm/°C
% of FSR
% of FSR
ppm/°C
LSB
VREF = 5 V
In warp mode
In normal mode or impulse mode
All modes
In warp mode
In normal mode or impulse mode
All modes
AVDD = 5 V 5%
0.7
0.5
−25
−85
+25
+85
3
Gain Error, TMIN to TMAX
Gain Error, TMIN to TMAX
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
−0.034
−0.048
+0.034
+0.048
3
1.6
4
Signal-to-Noise
fIN = 2 kHz, VREF = 5 V
VREF = 4.096 V
fIN = 10 kHz, VREF = 4.096 V
fIN = 100 kHz, VREF = 4.096 V
VIN+ = VIN− = VREF/2 = 2.5 V
fIN = 2 kHz
fIN = 10 kHz
fIN = 100 kHz
fIN = 2 kHz
fIN = 10 kHz
101
99
98
dB4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
97.5
97
Dynamic Range
Spurious-Free Dynamic Range
103
120
118
105
−115
−113
−98
98
Total Harmonic Distortion
fIN = 100 kHz
fIN = 2 kHz, VREF = 4.096 V
fIN = 2 kHz, −60 dB input
Signal-to-Noise-and-Distortion Ratio
40
26
−3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
2
5
ns
ps rms
ns
Full-scale step
250
250
ns
Rev. B | Page 3 of 28
AD7674
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
REFERENCE
External Reference Voltage Range
REF Voltage with Reference Buffer
Reference Buffer Input Voltage Range
REFBUFIN Input Current
REF
3
4.096
4.096
2.5
AVDD + 0.1
4.15
2.6
V
V
V
µA
µA
REFBUFIN = 2.5 V
REFBUFIN
4.05
1.8
−1
+1
REF Current Drain
800 kSPS throughput
330
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
−0.3
+2.0
−1
+0.8
DVDD + 0.3
+1
+1
V
V
µA
µA
−1
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL
ISINK = 1.6 mA
ISOURCE = −500 µA
0.4
V
V
VOH
OVDD − 0.6
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current8
4.75
4.75
2.7
5
5
5.25
5.25
DVDD + 0.37
V
V
V
800 kSPS throughput
AVDD
16
6.5
50
mA
mA
µA
DVDD9
OVDD9
POWER DISSIPATION9
PDBUF high at 500 kSPS10
PDBUF high at 1 kSPS10
PDBUF high at 800 kSPS8
PDBUF low at 800 kSPS8
78
90
mW
µW
mW
mW
160
114
126
126
138
TEMPERATURE RANGE11
Specified Performance
TMIN to TMAX
−40
+85
°C
1 See the Analog Inputs section.
2 LSB means least significant bit. With the 4.096 V input range, 1 LSB is 31.25 µV.
3 See the Terminology section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These
specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
5 Data format parallel or serial 18-bit.
6 Conversion results are available immediately after completed conversion.
7 The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8 In warp mode.
9 Tested in parallel reading mode.
10 In impulse mode.
11 Contact factory for extended temperature range.
Rev. B | Page 4 of 28
Data Sheet
AD7674
TIMING SPECIFICATIONS
−40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 3.
Parameter
Symbol Min
Typ
Max
Unit
Refer to Figure 35 and Figure 36
Convert Pulse Width
t1
t2
t3
10
ns
µs
ns
Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
1.25/1.5/1.75
CNVST Low to BUSY High Delay
35
BUSY High All Modes Except Master Serial Read After Convert (Warp Mode/
Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t4
t5
t6
t7
t8
t9
1/1.25/1.5 µs
2
ns
ns
10
1/1.25/1.5 µs
250
10
ns
ns
RESET Pulse Width
Refer to Figure 37, Figure 38, and Figure 39 (Parallel Interface Modes)
CNVST Low to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode)
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
t10
t11
t12
t13
1/1.25/1.5 µs
ns
20
5
45
15
ns
ns
Refer to Figure 41 and Figure 42 (Master Serial Interface Modes) 2
CS Low to SYNC Valid Delay
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low to Internal SCLK Valid Delay
CS Low to SDOUT Delay
CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
25/275/525
3
25
12
7
4
2
40
Internal SCLK High3
Internal SCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
3
CS High to SYNC High-Z
10
10
10
ns
ns
ns
CS High to Internal SCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Asserted Delay (Warp Mode/Normal Mode/
Impulse Mode)
Table 4
t29
t30
1/1.25/1.5
25
µs
ns
SYNC Deasserted to BUSY Low Delay
Refer to Figure 43 and Figure 44 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
External SCLK High
External SCLK Low
1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Rev. B | Page 5 of 28
AD7674
Data Sheet
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum (Warp Mode)
BUSY High Width Maximum (Normal Mode)
BUSY High Width Maximum (Impulse Mode)
t18
t19
t19
t20
t21
t22
t23
t24
t28
t28
t28
3
17
60
80
22
21
18
4
60
2.5
2.75
3
17
120
160
50
49
18
30
140
4
17
25
40
12
7
4
2
3
1.75
2
240
320
100
99
18
89
300
7
7.25
7.5
4.25
4.5
2.25
Rev. B | Page 6 of 28
Data Sheet
AD7674
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7674 Absolute Maximum Ratings
I
1.6mA
OL
Parameter
Rating
Analog Inputs
IN+1, IN−1, REF, REFBUFIN, REFGND
to AGND
TO OUTPUT
PIN
1.4V
C
L
1
AGND − 0.3 V to
AVDD + 0.3 V
60pF
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
I
500µA
OH
0.3 V
NOTE
1
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
C
L
−0.3 V to +7 V
7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V
700 mW
2.5 W
150°C
−65°C to +150°C
300°C
03083–0–002
Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK
Outputs, CL = 10 pF
Digital Inputs
Internal Power Dissipation2
Internal Power Dissipation3
Junction Temperature
Storage Temperature Range
2V
0.8V
tDELAY
tDELAY
2V
2V
Lead Temperature Range
(Soldering 10 sec)
0.8V
0.8V
03083–0–003
1See the Analog Inputs section.
Figure 3. Voltage Reference Levels for Timing
2Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θ
JC = 30°C/W.
3 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 7 of 28
AD7674
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AGND
AVDD
AGND
CNVST
PD
1
2
3
4
5
6
7
8
9
36 AGND
35
CNVST
34 PD
AGND
AVDD
MODE0
MODE1
D0/OB/2C
WARP
IMPULSE
D1/A0
D2/A1
3
MODE0
33
RESET
4
AD7674
TOP VIEW
(Not to Scale)
32 CS
31 RD
30 DGND
29 BUSY
28 D17
27 D16
MODE1
RESET
CS
5
D0/OB/2C
WARP
AD7674
TOP VIEW
(Not to Scale)
6
RD
7
IMPULSE
D1/A0
DGND
BUSY
D17
10
11
12
D3
8
D4/DIVSCLK[0]
D5/DIVSCLK[1]
26
D15
25 D14
D2/A1
9
10
11
12
D3
D16
D4/DIVSCLK[0]
D5/DIVSCLK[1]
D15
D14
13 14 15 16
18
20 21
17
19
22 24
23
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. DNC = DO NOT CONNECT.
3. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS
CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF
THE SYSTEM.
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. DNC = DO NOT CONNECT.
Figure 4. 48-Lead LQFP Pin Configuration
Figure 5. 48-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
1, 44
2, 47
3
AGND
AVDD
MODE0
MODE1
P
P
DI
DI
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
Data Output Interface Mode Selection.
Data Output Interface Mode Selection:
4
Interface Mode No.
MODE1
MODE0
Description
0
1
2
3
0
0
1
1
0
1
0
1
18-bit interface
16-bit interface
Byte interface
Serial interface
5
6
7
D0/OB/2C
WARP
DI/O
DI
In Mode 0, 18-bit interface mode, this pin is Bit 0 of the parallel port data output bus and the data
coding is straight binary. In all other modes, this pin allows a choice of straight binary/binary twos
complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted,
resulting in a twos complement output from its internal shift register.
Conversion Mode Selection. When this input is high and the IMPULSE pin is low, WARP selects the
fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be
applied to guarantee full specified accuracy. When low, full accuracy is maintained independent of
the minimum conversion rate.
IMPULSE
DI
Conversion Mode Selection. When this input is high and the WARP pin is low, IMPULSE selects a
reduced power mode. In this mode, the power dissipation is approximately proportional to the
sampling rate. When the WARP pin and the IMPULSE pin are low, the normal mode is selected.
8
D1/A0
D2/A1
D3
DI/O
DI/O
DO
In Mode 0, 18-bit interface mode, this pin is Bit 1 of the parallel port data output bus. In all other
modes, this input pin controls the form in which data is output, as shown in Table 7.
In Mode 0, 18-bit interface mode, or Mode 1, 16-bit interface mode, this pin is Bit 2 of the parallel port data
output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
In all modes except Mode 3, this output is used as Bit 3 of the parallel port data output bus. This pin is
always an output, regardless of the interface mode.
9
10
Rev. B | Page 8 of 28
Data Sheet
AD7674
Pin No. Mnemonic
Type1 Description
D4/DIVSCLK[0], DI/O In all modes except Mode 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. In
11, 12
D5/DIVSCLK[1]
Mode 3, serial interface mode, when EXT/INT is low and RDC/SDIN is low (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial
clock that clocks the data output. In other serial modes, these pins are not used.
13
D6/EXT/INT
DI/O
In all modes except Mode 3, this output is used as Bit 6 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used as a digital select input for choosing the
internal data clock or an external data clock. With EXT/INT tied low, the internal clock is selected on
the SCLK output. With EXT/INT set to a logic high, the output data is synchronized to an external clock
signal connected to the SCLK input.
14
15
16
D7/INVSYNC
D8/INVSCLK
D9/RDC/SDIN
DI/O
DI/O
DI/O
In all modes except Mode 3, this output is used as Bit 7 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used to select the active state of the
SYNC signal. When low, SYNC is active high. When high, SYNC is active low.
In all modes except Mode 3, this output is used as Bit 8 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave mode.
In all modes except Mode 3, this output is used as Bit 9 of the parallel port data output bus. In Mode 3,
serial interface mode, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT. When EXT/INT is high, RDC/SDIN can be
used as a data input to daisy-chain the conversion results from two or more ADCs onto a single
SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after
the initiation of the read sequence. When EXT/INT is low, RDC/SDIN is used to select the read mode.
When RDC/SDIN is high, the data is output on SDOUT during conversion. When RDC/SDIN is low, the
data can be output on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19
20
21
DVDD
DGND
D10/SDOUT
P
P
DO
Digital Power. Nominally at 5 V.
Digital Power Ground.
In all modes except Mode 3, this output is used as Bit 10 of the parallel port data output bus. In Mode 3,
serial interface mode, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion
result, MSB first, from its internal shift register. The data format is determined by the logic level of
OB/2C. In serial mode when EXT/INT is low, SDOUT is valid on both edges of SCLK. In serial mode
when EXT/INT is high and INVSCLK is low, SDOUT is updated on the SCLK rising edge and is valid on
the next falling edge; if INVSCLK is high, SDOUT is updated on the SCLK falling edge and is valid on the
next rising edge.
22
23
D11/SCLK
D12/SYNC
DI/O
DO
In all modes except Mode 3, this output is used as Bit 11 of the parallel port data output bus. In Mode 3,
serial interface mode, this pin, part of the serial port, is used as a serial data clock input or output,
dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends upon the logic state of the INVSCLK pin.
In all modes except Mode 3, this output is used as Bit 12 of the parallel port data output bus. In Mode 3,
serial interface mode, this output, part of the serial port, is used as a digital output frame synchronization
for use with the internal data clock (EXT/INT = logic low). When a read sequence is initiated and INVSYNC is
low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is
initiated and INVSYNC is high, SYNC is driven low and remains low while SDOUT output is valid.
24
D13/RDERROR
DO
In all modes except Mode 3, this output is used as Bit 13 of the parallel port data output bus. In
Mode 3, serial interface mode, and when EXT/INT is high, this output, part of the serial port, is used as
an incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to
28
29
D14 to D17
BUSY
DO
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
Busy Output. Transitions high when a conversion is started. Remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data ready clock signal.
30
31
DGND
RD
P
DI
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Rev. B | Page 9 of 28
AD7674
Data Sheet
Pin No. Mnemonic
Type1 Description
32
33
34
35
CS
DI
DI
DI
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
Reset Input. When set to a logic high, reset the AD7674. Current conversion, if any, is aborted. If not
used, this pin can be tied to DGND.
Power-Down Input. When set to a logic high, power consumption is reduced and conversions are
inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE high, WARP low), if CNVST is held low when the
acquisition phase (t8) is complete, the internal sample/hold is put into hold and a conversion is
immediately started.
RESET
PD
CNVST
36
37
AGND
REF
P
AI
Must Be Tied to Analog Ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if
the internal reference buffer is not used. Should be decoupled effectively with or without the internal
buffer.
38
39
40 to
42
REFGND
IN–
NIC
AI
AI
Reference Input Analog Ground.
Differential Negative Analog Input.
No Internal Connection.
43
45
46
IN+
DNC
REFBUFIN
AI
Differential Positive Analog Input.
Do Not Connect. Do not connect to this pin.
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V
typically when 2.5 V is applied on this pin.
Allows Choice of Buffering Reference. When low, buffer is selected. When high, buffer is switched off.
Exposed Pad. The exposed pad is internally connected to AGND. This connection is not required to
meet the electrical performances. However, for increased reliability of the solder joints, it is
recommended that the pad be soldered to the analog ground of the system.
AI
DI
48
0
PDBUF
EPAD
1AI = Analog Input; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Table 7. Data Bus Interface Definitions1
Mode MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0
1
1
2
2
2
2
3
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
R[0]
R[1]
R[2]
R[2]
R[3] R[4:9]
R[3] R[4:9]
R[1]
R[10:11]
R[10:11]
R[12:15]
R[12:15]
R[16:17]
R[16:17]
18-bit parallel
16-bit high word
16-bit low word
8-bit high byte
8-bit mid byte
8-bit low byte
8-bit low byte
Serial interface
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
A0:0
A0:1
A0:0
A0:0
A0:1
A0:1
R[0]
All zeros
A1:0
All high-Z
All high-Z
All high-Z
All high-Z
R[10:11]
R[2:3]
R[12:15]
R[4:7]
R[16:17]
R[8:9]
A1:1
A1:0
R[0:1]
All zeros
R[0:1]
A1:1
All zeros
Serial interface
All high-Z
1 R[0:17] is the 18-bit ADC value stored in its output register.
Rev. B | Page 10 of 28
Data Sheet
AD7674
TERMINOLOGY
Integral Nonlinearity Error (INL)
Total Harmonic Distortion (THD)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−4.095991 V for the 4.09ꢀ V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage 1½ LSB
below the nominal full scale (4.095977 V for the 4.09ꢀ V
range). The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the ideal levels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the
input to when
CNVST
Zero Error
the input signal is held for a conversion.
The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Transient Response
Transient response is the time required for the AD7ꢀ74 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to SINAD by the
following formula:
ENOB = (SINADdB – 1.7ꢀ)/ꢀ.02
Rev. B | Page 11 of 28
AD7674
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
0
65536
131072
CODE
196608
262144
0
65536
131072
CODE
196608
262144
03083-0-008
03083-0-005
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
70000
60000
50000
40000
30000
20000
10000
0
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
V
= 5V
REF
V
= 5V
REF
28939
59121
58556
26939
25964
7165
5073
87
793
627
0
0
47
0
0
0
1
8
0
2004C2004D2004E 2004F 20050 20051 20052 20053 20054 20055
2004D 2004E 2004F 20050 20051 20052 20053 20054 20055
CODE IN HEX
CODE IN HEX
03083-0-009
03083-0-006
Figure 7. Histogram of 131,072 Conversions of a
DC Input at the Code Transition
Figure 10. Histogram of 131,072 Conversions of a
DC Input at the Code Center
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
0
–2.5
–2.0
–1.5
1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
NEGATIVE INL (LSB)
POSITIVE INL (LSB)
03083-0-010
03083-0-007
Figure 11. Typical Negative INL Distribution (424 Units)
Figure 8. Typical Positive INL Distribution (424 Units)
Rev. B | Page 12 of 28
Data Sheet
AD7674
120
100
80
250
200
150
100
50
60
40
20
0
0
0
–2.0
2.0
0.5
1.0
1.5
–1.5
–1.0
–0.5
0
POSITIVE DNL (LSB)
NEGATIVE DNL (LSB)
03083-0-011
03083-0-014
Figure 12. Typical Positive DNL Distribution (424 Units)
Figure 15. Typical Negative DNL Distribution (424 Units)
16.5
16.0
15.5
15.0
14.5
14.0
13.5
102
99
96
93
90
87
84
81
78
75
0
f
f
V
= 800kSPS
= 10kHz
S
–20
–40
IN
= 4.096V
REF
SNR = 98.4dB
THD = 119.1dB
SFDR = 120.4dB
SINAD = 98.4dB
SNR
–60
–80
SINAD
ENOB
–100
–120
–140
–160
–180
1
10
100
1000
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
FREQUENCY (kHz)
03083-0-012
03083-0-015
Figure 16. SNR, SINAD, and ENOB vs. Frequency
Figure 13. FFT (10 kHz Tone)
140
120
100
80
–60
–70
0
–20
f
f
V
= 800kSPS
= 100kHz
= 4.096V
S
IN
SFDR
REF
SNR = 98.8dB
–40
THD = 104.3dB
SFDR = 104.9dB
SINAD = 97.8dB
–80
–60
–90
–80
THIRD
HARMONIC
60
–100
–110
–120
–130
–100
–120
–140
–160
–180
THD
40
SECOND
HARMONIC
20
0
1000
1
10
100
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
FREQUENCY (kHz)
03083-0-016
03083-0-013
Figure 17. THD, SFDR, and Harmonics vs. Frequency
Figure 14. FFT (100 kHz Tone)
Rev. B | Page 13 of 28
AD7674
Data Sheet
105
104
103
102
101
100
99
100000
10000
1000
100
AVDD, WARP/NORMAL
V
= 4.096V
REF
DVDD, WARP/NORMAL
AVDD, IMPULSE
10
SNR
DVDD, IMPULSE
SINAD
1
98
PDBUF HIGH
0.1
97
OVDD, ALL MODES
0.01
0.001
96
95
–60
–50
–40
–30
–20
–10
0
1
100
1k
10k
100k
1M
10
INPUT LEVEL (dB)
SAMPLING RATE (SPS)
03083-0-017
03083-0-020
Figure 18. SNR and SINAD vs. Input Level
Figure 21. Operating Current vs. Sampling Rate
16.5
16.0
15.5
15.0
100
800
700
600
500
400
300
100
0
V
= 4.096V
REF
SNR
99
SINAD
DVDD
ENOB
98
97
96
AVDD
OVDD
14.5
125
–55
–35
–15
5
25
45
65
85
105
–55
–35
–15
5
25
45
65
C)
85
105
125
TEMPERATURE (C)
TEMPERATURE (
03083-0-018
03083-0-021
Figure 19. SNR, SINAD, and ENOB vs. Temperature
Figure 22. Power-Down Operating Currents vs. Temperature
–100
25
20
15
–110
–120
–130
–140
THD
NEGATIVE
10
FULL SCALE
5
THIRD
HARMONIC
ZERO ERROR
0
–5
SECOND
HARMONIC
POSITIVE
FULL SCALE
–10
–15
–20
–25
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
C)
85
105
125
TEMPERATURE (C)
03083-0-019
TEMPERATURE (
03083-0-022
Figure 20. THD and Harmonics vs. Temperature
Figure 23. Zero Error, Positive Full Scale, and Negative Full Scale vs.
Temperature
Rev. B | Page 14 of 28
Data Sheet
AD7674
30
20
10
0
50
40
30
20
10
0
OVDD = 2.7V @ 85°C
POSITIVE
FULL SCALE
ZERO ERROR
OVDD = 2.7V @ 25°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
10
20
NEGATIVE
FULL SCALE
–30
4.50
4.75
5.00
5.25
5.50
0
50
100
(pF)
150
200
AVDD (V)
C
L
03083-0-023
03083-0-024
Figure 24. Zero Error, Positive Full Scale, and Negative Full Scale vs. Supply
Figure 25. Typical Delay vs. Load Capacitance (CL)
Rev. B | Page 15 of 28
AD7674
Data Sheet
CIRCUIT INFORMATION
IN+
SWITCHES
CONTROL
SW+
MSB
LSB
262,144C 131,072C
4C
2C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
OUTPUT
CODE
REFGND
4C
2C
C
C
262,144C 131,072C
MSB
LSB
SW–
CNVST
03083–0–025
IN–
Figure 26. ADC Simplified Schematic
The AD7ꢀ74 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
the IN+ and IN– inputs captured at the end of the acquisition
phase is applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4, ... VREF/2ꢀ2144). The
control logic toggles these switches, starting with the MSB first,
to bring the comparator back into a balanced condition. After
completing this process, the control logic generates the ADC
output code and brings the BUSY output low.
The linearity and dynamic range of the AD7ꢀ74 are similar
to or better than many ∑-Δ ADCs. With the advantages of its
successive architecture, which ease multiplexing and reduce
power with throughput, it can be advantageous in applications
that normally use ∑-Δ ADCs.
The AD7ꢀ74 features different modes to optimize performance
according to the applications. In warp mode, the AD7ꢀ74 is
capable of converting 800,000 samples per second (800 kSPS).
Modes of Operation
The AD7ꢀ74 features three modes of operation: warp, normal,
and impulse. Each mode is more suited for specific applications.
The AD7ꢀ74 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
Warp mode allows conversion rates up to 800 kSPS. However,
in this mode and this mode only, the full specified accuracy is
guaranteed only when the time between conversions does not
exceed 1 ms. If the time between two consecutive conversions is
longer than 1 ms (for example, after power-up), the first conversion
result should be ignored. This mode makes the AD7ꢀ74 ideal
for applications where a fast sample rate is required.
The AD7ꢀ74 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
and allows for flexible configurations as either a serial or
parallel interface. The AD7ꢀ74 is a pin-to-pin compatible
upgrade of the AD7ꢀ7ꢀ, AD7ꢀ78, and AD7ꢀ79.
Normal mode is the fastest mode (ꢀꢀꢀ kSPS) without any
limitation on the time between conversions. This mode makes
the AD7ꢀ74 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
CONVERTER OPERATION
The AD7ꢀ74 is a successive approximation ADC based on a
charge redistribution DAC. Figure 2ꢀ shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors that are
connected to the two comparator inputs.
Impulse mode, the lowest power dissipation mode, allows power
saving between conversions. The maximum throughput in this
mode is 570 kSPS. When operating at 1 kSPS, for example, it
typically consumes only 13ꢀ μW. This feature makes the
AD7ꢀ74 ideal for battery-powered applications.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to AGND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the
input goes
CNVST
low, a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
Rev. B | Page 16 of 28
Data Sheet
AD7674
Table 8. Output Codes and Ideal Input Voltages
Straight Twos
Transfer Functions
Except in 18-bit interface mode, the AD7ꢀ74 offers straight
binary and twos complement output coding when using OB/
See Figure 27 and Table 8 for the ideal transfer characteristic.
Analog Input
VREF = 4.096 V
Binary
(Hex)
Complement
(Hex)
.
2C
Description
FSR − 1 LSB
FSR − 2 LSB
4.095962 V
4.095924 V
3FFFF1
3FFFE
20001
20000
1FFFF
00001
000002
1FFFF1
1FFFE
00001
00000
3FFFF
20001
200002
Midscale + 1 LSB 31.25 μV
Midscale 0 V
Midscale − 1 LSB −31.25 μV
111...111
111...110
111...101
−FSR + 1 LSB
−FSR
−4.095962 V
−4.096 V
1 This is also the code for overrange analog input (VIN+ – VIN− above VREF
VREFGND).
–
2 This is also the code for underrange analog input (VIN+ – VIN− below –VREF
VREFGND).
+
000...010
000...001
000...000
TYPICAL CONNECTION DIAGRAM
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
Figure 28 shows a typical connection diagram for the AD7ꢀ74.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.
–FS + 0.5 LSB
ANALOG INPUT
03083-0-026
Figure 27. ADC Ideal Transfer Function
DVDD
ANALOG
SUPPLY
20
DIGITAL SUPPLY
(3.3V OR 5V)
+
NOTE 5
(5V)
+
+
100nF
10F
10 F
100nF
100nF
10F
ADR421
AVDD
AGND
DGND
DVDD
OVDD
OGND
REFBUFIN
SERIAL PORT
2.5V REF
NOTE 1
SCLK
1M
50k
100nF
100nF
SDOUT
NOTE 2
REF
C
REF
BUSY
47F
NOTE 1
C/P/DSP
REFGND
50
CNVST
D
50
NOTE 6
–
U1
+
15
NOTE 3
MODE1
MODE0
OB/2C
IN+
AD7674
ANALOG INPUT+
DVDD
C
2.7nF
C
AD8021
NOTE 4
CLOCK
PDBUF
CS
50
RD
–
U2
+
15
NOTE 3
IN–
RESET
PD
ANALOG INPUT–
C
2.7nF
C
AD8021
NOTE 4
NOTES
1. SEEVOLTAGE REFERENCE INPUT SECTION.
2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
3.
.
THE AD8021 IS RECOMMENDED SEE DRIVER AMPLIFIER CHOICE SECTION.
4. SEE ANALOG INPUTS SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
03083-0-027
Figure 28. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)
Rev. B | Page 17 of 28
AD7674
Data Sheet
Analog Inputs
filter between the amplifier output and the ADC analog inputs,
as shown in Figure 28, to improve the noise filtering done by the
AD7674 analog input circuit. However, the source impedance has
to be kept low because it affects the ac performance, especially
the total harmonic distortion (THD). The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD degrades as a function of source impedance and the
maximum input frequency, as shown in Figure 31.
–95
Figure 29 shows a simplified analog input section of the AD7674.
The diodes shown in Figure 29 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input signal
never exceeds the absolute ratings on these inputs. This causes
these diodes to become forward biased and start conducting
current. These diodes can handle a forward-biased current of
120 mA max. This condition can eventually occur when the U1
or U2 supplies of the input buffer are different from AVDD. In
such a case, an input buffer with a short-circuit current
limitation can be used to protect the device.
20kHz
–100
AVDD
–105
10kHz
R+ = 102Ω
IN+
–110
C
S
C
2kHz
S
IN–
–115
R– = 102Ω
–120
15
45
75
105
AGND
03083-0-028
INPUT RESISTANCE (Ω)
03083-0-030
Figure 29. Simplified Analog Input
Figure 31. THD vs. Analog Input Frequency and Source Resistance
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 30, which represents typical
CMRR over frequency.
Driver Amplifier Choice
Although the AD7674 is easy to drive, the driver amplifier
needs to meet the following requirements:
66
•
The driver amplifier and the AD7674 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier data sheet,
settling at 0.1% or 0.01% is more commonly specified. This
can differ significantly from the settling time at an 18-bit
level and, therefore, should be verified prior to driver
selection. The tiny op amp AD8021, which combines
ultralow noise and high gain-bandwidth, meets this
settling time requirement.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7674. The noise coming from
the driver is filtered by the AD7674 analog input circuit 1-
pole low-pass filter made by R+, R–, and CS. The SNR
degradation due to the amplifier is
64
62
60
58
56
54
52
50
•
1
10
100
1000
10000
FREQUECY (kHz)
03083-0-029
Figure 30. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the AD7674 behaves
like a 1-pole RC filter consisting of the equivalent resistance R+,
R–, and CS. The R+ and R– resistors are typically 102 Ω and are
lumped components made up of a serial resistor and the on
resistance of the switches. CS is typically 60 pF and mainly
consists of the ADC sampling capacitor. This 1-pole filter with a
−3 dB cutoff frequency of 26 MHz typ reduces any undesirable
aliasing effect and limits the noise coming from the inputs.
25
SNRLOSS = 20 log
2
f
625 + π –3dB (NeN )
where:
f
–3dB is the –3 dB input bandwidth in MHz of the AD7674
(26 MHz) or the cutoff frequency of the input filter, if used.
N is the noise factor of the amplifiers (1 if in buffer
configuration).
Because the input impedance of the AD7674 is very high, the
device can be driven directly by a low impedance source without
gain error. This allows the user to put an external 1-pole RC
eN is the equivalent input noise voltage of each op amp in
nV/√Hz.
Rev. B | Page 18 of 28
Data Sheet
AD7674
For instance, for a driver with an equivalent input noise of
Voltage Reference
2 nV/√Hz (for example, the AD8021) configured as a buffer,
thus with a noise gain of +1, the SNR degrades by only 0.34 dB
with the filter in Figure 28, and by 1.8 dB without it.
The driver needs to have a THD performance suitable to
that of the AD7674.
The AD7674 allows the use of an external voltage reference
either with or without the internal reference buffer.
Using the internal reference buffer is recommended when
sharing a common reference voltage between multiple ADCs is
desired.
•
The AD8021 meets these requirements and is usually appropriate
for almost all applications. The AD8021 needs a 10 pF external
compensation capacitor, which should have good linearity as an
NPO ceramic or mica type.
However, the advantages of using the external reference voltage
directly are:
•
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (5 V) instead of a typical 4.096 V reference
when the internal buffer is used.
The AD8022 can be used if a dual version is needed and gain of
1 is present. The AD829 is an alternative in applications where
high frequency (above 100 kHz) performance is not required. In
gain of 1 applications, it requires an 82 pF compensation capacitor.
The AD8610 is another option when low bias current is needed
in low frequency applications.
•
The power saving when the internal reference buffer is
powered down (PDBUF High)
To use the internal reference buffer, PDBUF should be LOW. A
2.5 V reference voltage applied on the REFBUFIN input results
in a 4.096 V reference on the REF pin.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver allows for a differential input into the device.
The schematic is shown in Figure 32. When provided an input
signal of 0 to VREF, this configuration produces a differential
In both cases, the voltage reference input REF has a dynamic
input impedance and therefore requires an efficient decoupling
between REF and REFGND inputs, The decoupling consists of
a low ESR 47 µF tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance.
V
REF with midscale at VREF/2.
If the application can tolerate more noise, the AD8138
differential driver can be used.
Care should also be taken with the reference temperature
coefficient of the voltage reference, which directly affects the
full-scale accuracy if this parameter matters. For instance, a
4 ppm/°C temperature coefficient of the reference changes the
full scale by 1 LSB/°C.
U1
ANALOG INPUT
AD8021
10pF
(UNIPOLAR
0V TO 4.096V)
Power Supply
590Ω
590Ω
15Ω
IN+
IN–
The AD7674 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines
the output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 28. The AD7674 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in
Figure 33.
2.7nF
AD7674
15Ω
U2
1.82kΩ
8.25kΩ
REFBUFIN
REF
10
2.7nF
AD8021
10pF
µ
F
100nF
2.5V
03083-0-031
Figure 32. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
Rev. B | Page 19 of 28
AD7674
Data Sheet
70
65
60
55
50
45
t2
t1
CNVST
BUSY
t4
t3
t5
t6
MODE ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
03083-0-034
Figure 35. Basic Conversion Timing
40
1
Although
is a digital signal, it should be designed with
CNVST
10
100
1000
10000
FREQUECY (kHz)
03083-0-032
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
Figure 33. PSRR vs. Frequency
For applications where SNR is critical, the
signal should
CNVST
have very low jitter. This may be achieved by using a dedicated
oscillator for generation, or to clock it with a high
POWER DISSIPATION VERSUS THROUGHPUT
In Impulse mode, the AD7674 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows for a significant power savings when the conversion rate
is reduced, as shown in Figure 34. This feature makes the AD7674
ideal for very low power battery applications. It should be noted
that the digital interface remains active even during the acquisition
phase. To reduce the operating digital supply currents even
further, the digital inputs need to be driven close to the power
rails (DVDD and DGND), and OVDD should not exceed
DVDD by more than 0.3 V.
CNVST
frequency low jitter clock, as shown in Figure 28.
In Impulse mode, conversions can be initiated automatically. If
is held low when BUSY goes low, the AD7674 controls
CNVST
the acquisition phase and automatically initiates a new conversion.
By keeping low, the AD7674 keeps the conversion process
CNVST
running by itself. Note that the analog input has to be settled
when BUSY goes low. Also, at power-up, should be
CNVST
brought low once to initiate the conversion process. In this
mode, the AD7674 can sometimes run slightly faster than the
guaranteed limits of 570 kSPS in Impulse mode. This feature
does not exist in Warp or Normal modes.
1000000
WARP/NORMAL
100000
DIGITAL INTERFACE
10000
1000
The AD7674 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7674 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the OVDD supply pin of the AD7674
to the host system interface digital supply. Finally, by using the
100
IMPULSE
10
1
PDBUFHIGH
OB/ input pin in any mode but 18-bit interface mode, both
2C
twos complement and straight binary coding can be used.
0.1
1
100
1k
10k
100k
1M
10
The two signals,
and
, control the interface. When at least
RD
CS
one of these signals is high, the interface outputs are in high
impedance. Usually, allows the selection of each AD7674 in
SAMPLING RATE (SPS)
03083-0-033
CS
multicircuit applications, and is held low in a single AD7674
design. is generally used to enable the conversion result on
Figure 34. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
RD
the data bus.
Figure 35 shows the detailed timing diagrams of the conversion
process. The AD7674 is controlled by the signal, which
CNVST
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by PD, until the conversion is complete. The
signal operates independently of
and
signals.
CNVST
CS
RD
Rev. B | Page 20 of 28
Data Sheet
AD7674
CS = 0
t9
t1
RESET
CNVST,
RD
BUSY
t4
BUSY
t3
PREVIOUS
CONVERSION
DATA
BUS
DATA
BUS
t12
t13
03083-0-038
t8
Figure 39. Slave Parallel Data Timing for Reading (Read During Convert)
CNVST
CS
RD
03083-0-035
Figure 36. RESET Timing
CS = RD = 0
CNVST
t1
A0, A1
t10
HI-Z
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
PINS D[15:8]
PINS D[7:0]
t4
BUSY
t12
LOW BYTE
t12
HIGH BYTE
t13
HI-Z
t3
t11
DATA
BUS
03083-0-039
PREVIOUS CONVERSION DATA
NEW DATA
Figure 40. 8-Bit and 16-Bit Parallel Interface
03083-0-036
SERIAL INTERFACE
Figure 37. Master Parallel Data Timing for Reading (Continuous Read)
The AD7674 is configured to use the serial interface when MODE0
and MODE1 are held high. The AD7674 outputs 18 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 18 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
PARALLEL INTERFACE
The AD7674 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 38 and Figure 39, respectively. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage transients
on the digital interface and the most critical analog conversion
circuitry. Refer to Table 7 for a detailed description of the
different options available.
MASTER SERIAL INTERFACE
Internal Clock
The AD7674 is configured to generate and provide the serial
data clock SCLK when the EXT/
pin is held low. The AD7674
INT
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. Depending on the RDC/SDIN input,
the data can be read after each conversion or during the following
conversion. Figure 41 and Figure 42 show the detailed timing
diagrams of these two modes.
CS
RD
Usually, because the AD7674 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode.
BUSY
DATA
BUS
CURRENT
CONVERSION
In read during conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential feedthrough
between digital activity and critical conversion decisions.
t12
t13
03083-0-037
Figure 38. Slave Parallel Data Timing for Reading (Read After Convert)
In read after conversion mode, note that unlike in other modes,
the BUSY signal returns low after the 18 data bits are pulsed out
and not at the end of the conversion phase, which results in a
longer BUSY width. To accommodate slow digital hosts, the
serial clock can be slowed down by using DIVSCLK.
Rev. B | Page 21 of 28
AD7674
Data Sheet
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
t3
CNVST
BUSY
t28
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
t26
1
2
3
16
17
18
SCLK
t15
t27
X
D17
D16
t23
D2
D1
D0
SDOUT
t16
t22
03083-0-040
Figure 41. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
t1
CNVST
BUSY
t3
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
16
17
18
t18
t27
X
D17
D16
t23
D2
D1
D0
SDOUT
t16
t22
03083-0-046
Figure 42. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. B | Page 22 of 28
Data Sheet
AD7674
External Discontinuous Clock Data Read after
Conversion
SLAVE SERIAL INTERFACE
External Clock
Though maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 43 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
The AD7674 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
pin is
INT
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by . When and
CS
CS
low, the result of this conversion can be read while both
and
CS
are both low, the data can be read after each conversion or
RD
are low. Data is shifted out MSB first with 18 clock pulses,
RD
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 43 and Figure 44 show the detailed timing
diagrams of these methods.
and is valid on the rising and falling edge of the clock.
Among the advantages of this method, the conversion performance
is not degraded because there are no voltage transients on the
digital interface during the conversion process. Also, data can
be read at speeds up to 40 MHz, accommodating both slow
digital host interface and the fastest serial reading.
While the AD7674 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result can occur. This is particularly
important during the second half of the conversion phase
because the AD7674 provides error correction circuitry that can
correct for an improper bit decision made during the first half
of the conversion phase. For this reason, it is recommended that
when an external clock is being provided, it is a discontinuous
clock that only toggles when BUSY is low or, more importantly,
that it does not transition during the latter half of BUSY high.
Finally, in this mode only, the AD7674 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing component
count and wiring connections when desired (for instance, in
isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 45. Simultaneous sampling is possible by using a common
signal. It should be noted that the RDC/SDIN input is
CNVST
latched on the edge of SCLK opposite the one used to shift out
data on SDOUT. Thus, the MSB of the upstream converter follows
the LSB of the downstream converter on the next SCLK cycle.
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
BUSY
t35
t36
t37
SCLK
1
2
3
16
17
18
19
20
t31
t32
SDOUT
X
D17
D16
D15
X15
D1
X1
D0
X17
Y17
X16
Y16
t16
t34
SDIN
X17
X16
X0
t33
03083-0-042
Figure 43. Slave Serial Data Timing for Reading (Read After Convert)
Rev. B | Page 23 of 28
AD7674
Data Sheet
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
16
17
18
t31
t32
SDOUT
X
D17
D16
D15
D1
D0
t16
03083-0-043
Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
BUSY
OUT
input/output ports on a microcontroller. A variety of external
buffers can be used with the AD7674 to prevent digital noise
from coupling into the ADC. The Serial Peripheral Interface
(SPI) section illustrates the use of the AD7674 with an SPI
equipped DSP, the ADSP-2191M.
BUSY
BUSY
AD7674
AD7674
#2 (UPSTREAM)
#1 (DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
Serial Peripheral Interface (SPI)
CNVST
CS
CNVST
CS
The AD7674 digital interface is compatible with SPI. As an
example, Figure 46 shows an interface diagram between the
AD7674 and the SPI equipped ADSP-2191M. To accommodate
the slower speed of the DSP, the AD7674 acts as a slave device,
and data must be read after conversion. This mode also allows
the daisy-chain feature. The convert command can be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process can be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-2191M is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbps, which allows it to read an ADC result in
about 1.1 µs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.
SCLK
SCLK
SCLK IN
CS IN
CNVST IN
03083-0-044
Figure 45. Two AD7674 Devices in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 44 shows the detailed timing diagrams of this method.
During a conversion, while both
and
are low, the result
CS
RD
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode, and the RDC/SDIN input should always be tied
either high or low.
DVDD
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
ADSP-2191M*
AD7674*
SER/PAR
EXT/INT
BUSY
CS
PFx
SPIxSEL (PFx)
MISOx
MICROPROCESSOR INTERFACING
RD
SDOUT
SCLK
CNVST
INVSCLK
SCKx
The AD7674 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7674 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
PFx or TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. Interfacing the AD7674 to an SPI Interface
Rev. B | Page 24 of 28
Data Sheet
AD7674
APPLICATIONS INFORMATION
RC filter (see Figure 28) and connect the system supply to the
interface digital supply OVDD and the remaining digital circuitry.
When DVDD is powered from the system supply, it is useful to
insert a bead to further reduce high frequency spikes.
LAYOUT
The AD7674 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The AD7674 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The printed circuit board that houses the AD7674 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This calls for the use
of ground planes, which can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7674, or at least as close to the AD7674 as
possible. If the AD7674 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point that
should be established as close to the AD7674 as possible.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.
The user should avoid running digital lines under the device, as
these couple noise onto the die. The analog ground plane should
be allowed to run under the AD7674 to avoid noise coupling.
EVALUATING AD7674 PERFORMANCE
Fast switching signals like
or clocks should be shielded
CNVST
An evaluation board for the AD7674 allows a quick means
to measure both DC (histograms and time domain) and AC
(time and frequency domain) performances of the converter.
The EVAL-AD7674CBZ is an evaluation board package that
includes a fully assembled and tested evaluation board,
documentation, and software. The accompanying software
requires the use of a capture board which must be ordered
separately from the evaluation board (see the Ordering Guide
for information). The evaluation board can also be used in a
standalone configuration and does not use the software when in
this mode. Refer to the EVAL-AD76XXEDZ and EVAL-
AD76XXCBZ for evaluation board details.
with digital ground to avoid radiating noise to other sections of
the board, and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided. Traces
on different but close layers of the board should run at right
angles to each other. This reduces the effect of feedthrough through
the board. The power supply lines to the AD7674 should use
as large a trace as possible to provide low impedance paths and
reduce the effect of glitches on the power supply lines. Good
decoupling is also important to lower the impedance of the supply
presented to the AD7674 and to reduce the magnitude of the
supply spikes. Decoupling ceramic capacitors, typically 100 nF,
should be placed close to and ideally right up against each
power supply pin (AVDD, DVDD, and OVDD) and their
corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.
Two types of data capture boards can be used with the EVAL-
AD7674CBZ:
•
•
USB based (EVAL-CED1Z recommended)
Parallel port based (EVAL-CONTROL BRD3Z not
recommended as many newer PCs do not include parallel
ports any longer)
The DVDD supply of the AD7674 can be a separate supply or
can come from the analog supply, AVDD, or the digital
interface supply, OVDD. When the system digital supply is
noisy or when fast switching digital signals are present, and if
no separate supply is available, the user should connect the
DVDD digital supply to the analog supply AVDD through an
The recommended board layout for the AD7674 is outlined in
the evaluation board data sheet.
Rev. B | Page 25 of 28
AD7674
Data Sheet
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
SEATING
PLANE
10°
6°
2°
7.00
BSC SQ
TOP VIEW
(PINS DOWN )
1.45
1.40
1.35
0.20
0.09
VIEW A
7°
3.5°
0°
25
12
0.15
0.05
24
13
SEATING
PLANE
0.10 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90
°
CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
7.00
BSC SQ
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
48
37
36
1
0.50
BSC
EXPOSED
PAD
5.20
5.10 SQ
5.00
12
13
25
24
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
AD7674ASTZ
AD7674ASTZL
AD7674ACPZ
AD7674ACPZRL
EVAL-AD7674CBZ
EVAL-CED1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-48
ST-48
CP-48-4
CP-48-4
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
USB Data Capture Board
EVAL-CONTROL BRD2Z
EVAL-CONTROL BRD3Z
Parallel Port Capture Board, 32 k RAM
Parallel Port Capture Board, 128 k RAM
1 Z = RoHS Compliant Part.
2The EVAL-AD7674CBZ can be used as a standalone evaluation board or in conjunction with a capture board for evaluation/demonstration purposes.
3 The capture boards allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL
BRD2Z/EVAL-CONTROL BRD3Z.
Rev. B | Page 26 of 28
Data Sheet
NOTES
AD7674
Rev. B | Page 27 of 28
AD7674
NOTES
Data Sheet
©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03083-0-6/16(B)
Rev. B | Page 28 of 28
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ADI
AD7675ACPZRL
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48
ADI
AD7676ACP
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, MO-220VKKD-2, LFCSP-48
ADI
AD7676ACPRL
IC 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48, MO-220VKKD-2, LFCSP-48, Analog to Digital Converter
ADI
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