AD7687BRM [ADI]
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10, MO-187BA, MSOP-10;
| 型号： | AD7687BRM |
| 厂家： | 
ADI |
| 描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10, MO-187BA, MSOP-10 光电二极管 转换器 |
| 文件： | 总15页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
250kSPS16-BITDifferentialADCinꢀSO
a
PreliminaryTechnicalData
AD7687*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
16 Bits Resolution with No Missing 16-Bit Codes
Throughput: 250 kSPS
INL: ꢁ 1.5LSB Max (ꢁ0.0023 % of Full-Scale)
S/(N+D): 93 dB Typ @ 10 kHz
VDD REF
OVDD
SDI
AD7687
IN+
IN-
SWITCHED
CAP DAC
SCK
THD: –100 dB Typ @ 10 kHz
CONTROL
LOGIC
True Differential Analog input range: ꢁVREF
0V to VREF with VREF up to VDD on both Inputs
No Pipeline Delay
SDO
CNV
CLOCK
GND
Single Supply Operation 5V and 2.7V
with 2.5V/3V/5V logic interface
Multiple ADCs Daisy Chain and Busy Indicator
Serial Interface SPI/QSPI/ꢀWire/DSP compatible
20 mW @ 5V/250ksps, TBD @ 3V Typical Power
Dissipation,
ꢀSO/SOT23 16 Bit ADC
80 ꢀW @ 1 kSPS
Stand-by current ( acquisition phase ): 1 ꢀA Max
ꢀ-SOIC Package ( ꢀ-SO8 size )
Pin-to-Pin Compatible with the AD7685, AD7686,
AD7688
Type / kSPS 100 kSPS
250 kSPS
AD7687
380 - 550 kSPS
AD7688
True
AD7684
AD7683
AD7680
Differential
Pseudo
AD7685
AD7686
Differential
Unipolar
Battery Powered Equipment
Data Acquisition
Instrumentation
MedicalInstruments
ProcessControl
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Superior INL
The AD7687 has a maximum integral non linearity of
1.5 LSB with no missing 16-bit code.
The AD7687 is a 16-bit, 250 kSPS, charge redistribution
successive-approximation, truly differential Analog-to-
Digital Converter which operates from a single power
supply. It contains a high-speed 16-Bit sampling ADC
with no missing codes, an internal conversion clock, error
correction circuits and a flexible serial interface port. The
part also contain a low noise, wide bandwidth, very short
aperture delay track/hold circuit which can sample a
ꢁVREF analog input range. The reference voltage REF is
applied externally and can be set up to the supply voltage.
2. 2.7V or 5V Single Supply Operation
The AD7687 operates from a single supply, dissipates
only TBD mW typical, and even lower when a reduced
throughput is used. It consumes 1 µA maximum during
the acquisition phase.
3.Fast Throughput.
The AD7687 is a high speed 250 kSPS, charge redistribu-
tion, 16-Bit SAR ADC with no pipeline delay.
The serial interface features the capability to “Daisy
chain” several ADCs on a single 3 wire bus and provides
an optional Busy indicator.
The AD7687 is hardware factory calibrated. It is fabri-
cated using CMOS process and is housed in 10-lead
ꢀSOIC package with operation specified from –40°C to
+85°C.
4. Serial Interface with OVDD, Daisy Chain and Busy
2.5V, 3 V or 5 V logic 3-wire serial interface arrangement
compatible with SPI and DSP host.
*Patent pending.
REV. Pr F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
(TA = -40ꢂC to +85ꢂC, VREF = 5V, VDD = 5 V, OVDD = 2.3V to 5.25V, unless otherwise
noted.)
AD7687–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
R E S O L U T I O N
1 6
Bits
ANALOG INPUT
Voltage Range
Absolute Input Voltage
IN+ - IN-
I N +
I N -
-VREF
–0.1
–0.1
+VREF
V D D + 0 . 3
V D D + 0 . 3
V
V
V
Analog Input CMRR
Leakage Current at 25 ꢂC
Input Impedance
fIN = TBD kHz
250kSPS Throughput
T B D
T B D
d B
n A
See Analog Input Section
THROUGHPUT
Complete Cycle
Throughput Rate
SPEED
4
250
µ s
k S P S
0
DC ACCURACY
No Missing Codes
1 6
–1.5
Bits
Integral Linearity Error
Transition Noise
+1.5
T B D
T B D
LSB1
0.4
L S B
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
REF = 5 V
% of FSR
ppm/°C
L S B
ppm/°C
L S B
T B D
T B D
T B D
T B D
VDD = 5 V
5%
AC ACCURACY
Signal-to-Noise
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
fIN = TBD kHz
fIN = TBD kHz
fIN = TBD kHz
fIN = TBD kHz
9 2
9 2
9 3
dB3
d B
d B
d B
100
–100
9 3
T B D
fIN = TBD kHz,
–60 dB Input
3 3
d B
Intermodulation Distortion
Second Order Terms
Third Order Terms
T B D
T B D
2
d B
d B
M H z
–3 dB Input Bandwidth
SAMPLING
Aperture Delay
Aperture Jitter
DYNAMICS
T B D
T B D
ns
ps rms
µ s
Transient Response
Full-Scale Step
1.5
R E F E R E N C E
External Reference Voltage
0.5
V D D + 0 . 3
V
External Reference Current Drain 250kSPS Throughput
T B D
µ A
DIGITAL INPUTS
Logic Levels
VIL
VIH
–0.3
+2.0
+1.7
– 1
+0.8
V
V
V
µ A
µ A
OVDD = 2.7V to 5.25V
OVDD = 2.3V to 5.25V
OVDD + 0.3
OVDD + 0.3
+ 1
IIL
IIH
– 1
+ 1
DIGITAL
Data Format
Pipeline Delay
OUTPUTS
Serial 16-Bits Twos’s Complement
Conversion Results Available Immediately
After Completed Conversion
0.4
VOL
VOH
ISINK = 500 µA
ISOURCE = –500 µA
V
V
OVDD – 0.3
NOTES
1LSB means Least Significant Bit. With the 5 V input range, one LSB is 152.6 µV.
2SeeDefinitionofSpecificationssection. Thesespecificationsdoincludefulltemperaturerangevariationbutdonotincludetheerrorcontributionfromtheexternalreference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
Specifications subject to change without notice.
REV. Pr F
–2–
PRELIMINARY TECHNICAL DATA
AD7687
Parameter
Conditions
Min
Typ
Max
Unit
POWER
V D D
SUPPLIES
Specified Performance
4.75
2.7
2.7
5
5.25
5.25
5.25
V
V
V
VDD Range
O V D D
Operating Current
V D D
250 kSPS Throughput
VDD = 5V
T B D
T B D
2 0
m A
µ A
m W
µ W
µ W
O V D D
Power Dissipation (VDD = 5V) 250 kSPS Throughput4
T B D
T B D
1
kSPS Throughput4
8 0
During acquisition phase4
TEMPERATURE
Specified Performance
RANGE5
TMIN to TMAX
– 4 0
+ 8 5
° C
N O T E S
4With all digital inputs forced to OVDD or GND respectively.
5Contact factory for extended temperature range.
Specifications subject to change without notice.
(–40OC to +85OC, VDD = 4.75 V to 5.25V, OVDD = 2.7 V to 5.25 V, unless otherwise stated)
TIMING SPECIFICATIONS
Symbol
tCONV
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data available
Acquisition Time
1.1
1.5
4
2.5
µs
µs
µs
ns
ns
ns
ns
ns
tACQ
tCYC
Time Between Conversions
CNV Pulse width ( CS mode )
tCNVH
tSCK
tSCKH
tSCKL
tHSDO
tDSDO
5
15
7
7
5
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data remains Valid
SCK Falling Edge to Data Valid delay
OVDD above 4.75V
13
20
27
ns
ns
ns
OVDD above 3V
OVDD above 2.7V
CNV or SDI Low to SDO D15 MSB Valid (CS mode)
tEN
OVDD above 4.75V
15
30
ns
ns
OVDD above 2.7V
CNV or SDI High or last SCK Falling Edge
to SDO High Impedance (CS mode)
SDI valid Setup Time from CNV rising edge (CS mode)
SDI valid Hold Time from CNV rising edge (CS mode)
SCK valid Setup Time from CNV rising edge (Chain mode)
SCK valid Hold Time from CNV rising edge (Chain mode)
SDI valid Setup Time from SCK falling edge (Chain mode)
SDI valid Hold Time from SCK falling edge (Chain mode)
SDI High to SDO High (Chain mode with Busy indicator)
OVDD above 4.75V
tDIS
30
ns
ns
ns
ns
ns
ns
ns
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
8
0
8
5
8
0
15
30
ns
ns
OVDD above 2.7V
Specifications subject to change without notice.
REV. Pr F
–3–
PRELIMINARY TECHNICAL DATA
AD7687–SPECIFICATIONS
Internal Power Dissipation3 . . . . . . . . . . . . . . . . 325 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Lead Temperature Range
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
IN+2, IN-2, REF, . . . . . GND –0.3 V to VDD + 0.3 V
Supply Voltages
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
VDD, OVDD to GND . . . . . . . . . . . . . . . . -0.3 V to 7 V
VDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital Inputs to GND . . . . . . –0.3 V to OVDD + 0.3 V
Digital Outputs to GND . . . . –0.3 V to OVDD + 0.3 V
NOTES
1StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanent
damage to the device. This is a stress rating only; functional operation of the device
attheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthis
specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectdevicereliability.
2See Analog Input section.
3Specification is for device in free air:ꢀSOIC-10: θJA = 200°C/W.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option Brand
AD7687BRM
–40°C to +85°C
–40°C to +85°C
ꢀ SOIC-10
ꢀ SOIC-10
Evaluation Board
Controller Board
Controller Board
RM-10
RM-10 (reel)
C 0 3
C 0 3
AD7687BRMRL7
EVAL-AD7687CB1
EVAL-CONTROL
EVAL-CONTROL
BRD22
BRD32
N O T E S
1This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration
purposes.
2These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
AD7687 PIN CONFIGURATION
500µA
I
OL
1
2
3
4
5
10
OVDD
SDI
REF
VDD
IN+
+1.4V
To SDO
9
8
7
6
C
L
SCK
SDO
AD7687
IN-
50pF
GND
CNV
500µA
I
OH
Figure 1. Load Circuit for Digital Interface Timing.
2V
0.8V
tDELAY
tDELAY
2V
2V
0.8V
0.8V
Figure 2. Voltage Reference Levels for Timing.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7687 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ING!
ESD SENSITIVE DEVICE
REV. Pr F
–4–
PRELIMINARY TECHNICAL DATA
AD7687
PIN FUNCTION DESCRIPTIONS
Pin # Mnemonic
Function
1
R E F
A I
Reference Input Voltage. The REF range is from TBD to VDD. It is referred to the
GND ground. This pin should be decoupled closely to the pin with a TBD ꢀFcapacitor.
Input Power Supply.
Differential Positive Analog Input.
Differential Positive Analog Input.
2
3
4
5
6
V D D
I N +
I N -
G N D
C N V
P
A I
A I
P
Power Supply Ground.
D I
Convert Input. This input has multiple functions. On its leading edge, it initiates the
conversions, it selects the interface mode of the part, Chain or CS mode, and in chain
mode, it enables the busy indicator feature if SCK is high. In CS mode, it can enable the
serial output signal when low. In Chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result or the programming configuration word are
ouput on this pin. It is synchronized to SCK.
7
S D O
D O
8
9
S C K
S D I
D I
D I
Serial Data Clock Input.
Serial Data Input. This input provides multiple features. It selects the interface mode of
the ADC as follows:
The Chain mode is selected if SDI is low during the CNV rising edge. In this Chain
mode, SDI could be used as a data input to daisy chain the conversion results from two or
more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with
a delay of 16 SCK cycles.
The CS mode is selected if SDI is high during the CNV rising edge. In this CS mode,
either SDI or CNV can enable the serial output signals when low and if SDI or CNV is
low when the conversion is complete, the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply than the host inter
face (2.5V, 3V or 5V).
1 0
O V D D
P
N O T E S
AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
REV. Pr F
–5–
PRELIMINARY TECHNICAL DATA
AD7687
DEFINITION OF SPECIFICATIONS
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is a measurement of the resolution with a sine
wave input. It is related to S/(N+D) by the following for-
mula:
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale”. The point used as “negative full
scale” occurs 1/2 LSB before the first code transition.
“Positive full scale” is defined as a level 1 1/2 LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
ENOB = (S/[N+D]dB – 1.76)/6.02)
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first five har-
monic components to the rms value of a full-scale input
signal and is expressed in decibels.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential nonlinearity is the maximum deviation from this
ideal value. It is often specified in terms of resolution for
which no missing codes are guaranteed.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The
value for SNR is expressed in decibels.
GAIN ERROR
The last transition (from 111 . . . 10 to 111 . . . 11)
should occur for an analog voltage 1 1/2 LSB below the
nominal full scale (4.999886 V for the 0 V to 5 V range).
The gain error is the deviation of the actual level of the
last transition from the ideal level after the offset has been
adjusted out.
SIGNAL TO (NOISE + DISTORTION) RATIO
(S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/(N+D) is expressed in deci-
bels.
OFFSET ERROR
The first transition should occur at a level 1/2 LSB above
analog ground (38.1 ꢀV for the 0 V to 5 V range). The
offset error is the deviation of the actual transition from
that point.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance
and is measured from the rising edge of the CNV input to
when the input signal is held for a conversion.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms ampli-
tude of the input signal and the peak spurious signal.
TRANSIENT RESPONSE
The time required for the AD7687 to achieve its rated
accuracy after a full-scale step function is applied to its
input.
REV. Pr F
–6–
PRELIMINARY TECHNICAL DATA
AD7687
IN+
SWITCHES CONTROL
SW
+
MSB
LSB
32,768C 16,384C
4C
2C
2C
C
C
BUSY
CONTROL
LOGIC
REF
COMP
OUTPUT CODE
GND
32,768C
16,384C
MSB
4C
C
C
SW
-
LSB
CNV
IN -
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
When the conversion phase begins, SW+ and SW- are
opened first. The two capacitor arrays are then discon-
nected from the inputs and connected to the GND input.
Therefore, the differential voltage between the inputs IN+
and IN- captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the
capacitor array between GND or REF, the comparator
input varies by binary weighted voltage steps (VREF/2,
VREF/4 . . . VREF/65536). The control logic toggles these
switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the
completion of this process, the control logic generates the
ADC output code and a BUSY signal indicator.
The AD7687 is a fast, low-power, single-supply, precise
16-bit analog-to-digital converter (ADC). The AD7687 is
capable of converting 250,000 samples per second (250
kSPS) and allow power saving between conversions. When
operating at 1kSPS, for example, it consumes typically
48 ꢀW with a 3V supply, ideal for battery-powered appli-
cations.
The AD7687 provides the user with an on-chip
track/hold, successive approximation ADC that does not
exhibit any pipeline or latency, making it ideal for mul-
tiple multiplexed channel applications.
The AD7687 can be operated from a single 2.7 V to 5.5V
supply and be interfaced to either 5 V or 3.3 V or 2.5 V
digital logic. It is housed in a 10-lead ꢀSO package that
combines space savings and allows flexible configurations.
The AD7687 is pin-to-pin-compatible with the AD7685,
the AD7686 and the AD7688.
Transfer Functions
The ideal transfer characteristic for the AD7687 is shown
in Figure 4 and Table I.
The CNV rising edge is used as a sampling edge. It puts
the track and hold in hold position and initiates the con-
version process. Because the AD7687 has an on board
conversion clock, the serial clock SCK is not required for
the conversion process. When the conversion is complete
and whatever the CNV state is, the part returns automati-
cally in a power-down mode with the track and hold in
track position.
011...111
011...110
011...101
CONVERTER OPERATION
100...010
100...001
100...000
The AD7687 is a successive approximation analog-to-
digital converter based on a charge redistribution DAC.
Figure 3 shows the simplified schematic of the ADC.
The capacitive DAC consists of two identical arrays of 16
binary weighted capacitors which are connected to the two
comparator inputs.
-FS
-FS+1 LSB
+FS-1 LSB
+FS-1.5 LSB
ANALOG INPUT
-FS+0.5 LSB
Figure 4. ADC Ideal Transfer Function
During the acquisition phase, terminals of the array tied to
the comparator’s input are connected to GND via SW+
and SW-. All independent switches are connected to the
analog inputs. Thus, the capacitor arrays are used as sam-
pling capacitors and acquire the analog signal on IN+ and
IN- inputs. When the acquisition phase is complete and
the CNV input goes high, a conversion phase is initiated.
REV. Pr F
–7–
PRELIMINARY TECHNICAL DATA
AD7687
Table I. Output Codes and Ideal Input Voltages
D
escription
Analog
Input
Digital Output Code
Hexa
VREF = 5V
FSR –1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
4.999847 V
152.6µV
0 V
-152.6µV
-4.999847V
-5 V
7FFF1
0001
0000
F F F F
8001
80002
N O T E S
1This is also the code for overrange analog input (VIN+ – VIN- above
VREF
– VGND).
2This is also the code for underrange analog input (VIN+ – VIN- below
VGND – VREF ).
REV. Pr F
–8–
PRELIMINARY TECHNICAL DATA
AD7687
DIGITAL INTERFACE
Though the AD7687 has a reduced number of pins, it
offers flexibility in its serial interface modes:
CS MODE 3 wires without Busy indicator
This mode is usually used when a single AD7687 is con-
nected to an SPI compatible digital host. The connection
diagram is shown in figure 5 and the corresponding tim-
ing is given in figure 6.
The AD7687, used in “CS mode”, is compatible to SPI,
QSPI digital hosts and DSPs (e.g.:Blackfin ADSP-BF53x
or ADSP-219x). This interface can use either 3 or 4
wires. Three wires interface using CNV, SCK and SDO
signals, minimizes wiring connections useful, for instance,
in isolated applications. Four wires interface using SDI,
CNV, SCK and SDO signals allows CNV, used to initiate
the conversions, to be independent of the reading timing
(SDI). That is useful in, low jitter sampling or simulta-
neous sampling applications.
With SDI tied to OVDD, a rising edge on CNV initiates
a conversion, selects the CS mode and forces SDO in
high impedance. Once a conversion is initiated, it will be
processed until completion whatever the state of CNV is.
For instance, it could be useful to bring CNV low to se-
lect other SPI devices such as analog multiplexers but
CNV must be returned high before the minimum conver-
sion time and held high until the maximum conversion
time to avoid the generation of the busy signal indicator.
When the conversion is complete, the AD7687 enters in
acquisition phase and in reduced power mode. When CNV
goes low, the MSB is output on SDO. The remaining
data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host
with acceptable hold time using the SCK falling edge will
allow a faster reading rate. After the 16th SCK falling
edge or when CNV goes high, whichever is the earliest,
SDO returns to high impedance.
The AD7687, used in “Chain mode”, provides a “daisy
chain” feature using the SDI input for cascading multiple
ADCs on a single data line.
The mode in which the part operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high and the chain mode is selected if
SDI is low. The SDI hold time is such that when SDI and
CNV are connected together, the chain mode is always
selected.
The AD7687 also offers the possibility, as an option and
with both modes, to force a start bit in front of the 16 data
bits. This start bit can be used as a busy signal indicator to
interrupt the digital host and trigger the data reading.
CONVERT
OVDD
CNV
Digital Host
AD7687
OVDD
47k⍀
SDI
SDO
DATA IN
CLK
The busy indicator is output or not depending on the
mode as follows:
In CS mode, the busy indicator occurs if CNV or SDI is
low when the ADC conversion ends.
SCK
In Chain mode, the busy indicator will be outputed if
SCK is high during the CNV rising edge.
Figure 5. CS mode 3 wires without busy indicator Connec-
tion Diagram ( SDI high ).
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
tSCKH
15
16
D0
tHSDO
tDSDO
tDIS
tEN
SDO
D15
D14
D13
D1
Figure 6. CS mode 3 wires without busy indicator Serial InterfaceTiming ( SDI high ).
REV. Pr F
–9–
PRELIMINARY TECHNICAL DATA
AD7687
host. The AD7687 also enters in acquisition phase and in
reduced power mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be
used to capture the data, a digital host with acceptable
hold time using the SCK falling edge will allow a faster
reading rate. After the 17th optional SCK falling edge or
when CNV goes high whichever is the earliest, SDO re-
turns to high impedance.
CS MODE 3 wires with Busy indicator
This mode is usually used when a single AD7687 is con-
nected to an SPI compatible digital host having an
interrupt input.
The connection diagram is shown in figure 7 and the cor-
responding timing is given in figure 8.
With SDI tied to OVDD, a rising edge on CNV initiates
a conversion, selects the CS mode and forces SDO in
high impedance. SDO is maintained in high impedance
until the completion of the conversion whatever the state
of CNV is. Prior to the minimum conversion time, CNV
could be used to select other SPI devices such as analog
multiplexers but CNV must be returned low before the
minimum conversion time and held low until the maxi-
mum conversion time to guarantee the generation of the
busy signal indicator. When the conversion is complete,
SDO goes from high impedance to low. With a pull-up
on SDO line, this transition can be used as an interrupt
signal to trigger the data reading controlled by the digital
CONVERT
OVDD
CNV
Digital Host
AD7687
OVDD
47k⍀
SDI
SDO
DATA IN
IRQ
SCK
CLK
Figure 7. CS mode 3 wires with busy indicator Connection
Diagram ( SDI high ).
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
15
tSCKH
16
17
tHSDO
tDSDO
tDIS
SDO
D15
D14
D1
D0
Figure 8. CS mode 3 wires with busy indicator Serial Interface Timing ( SDI high ).
REV. Pr F
–10–
PRELIMINARY TECHNICAL DATA
AD7687
SDO. The remaining data bits are then clocked by subse-
quent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the
data, a digital host with acceptable hold time using the
SCK falling edge will allow a faster reading rate and more
AD7687s on a single SPI port. After the 16th SCK falling
edge or when SDI goes high whichever is the earliest,
SDO returns to high impedance and another AD7687 can
be read.
CS MODE 4 wires without Busy indicator
This mode is usually used when multiple AD7687’s are
connected to an SPI compatible digital host.
A connection diagram example using two AD7687’s is
shown in figure 9 and the corresponding timing is given in
figure 10.
With SDI high, a rising edge on CNV initiates a conver-
sion, selects the CS mode and forces SDO in high
impedance. In this mode, CNV is held high during the
conversion phase and the subsequent data reading. SDI
must be high before the minimum conversion time and
held high until the maximum conversion time to avoid the
generation of the busy signal indicator. When the conver-
sion is complete, the AD7687 enters in acquisition phase
and in reduced power mode. Each ADC result can be read
by bringing low its SDI input which outputs the MSB on
CS2
CS1
CONVERT
CNV
CNV
OVDD
47k⍀
AD7687
AD7687
Digital Host
SDI
SDO
SDI
SDO
SCK
SCK
DATA IN
CLK
Figure 9. CS mode 4 wires without busy indicator Connection Diagram.
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
SCK
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tDSDO
D13
tDIS
tEN
SDO
D15
D14
D1
D0
D15
D14
D1
D0
Figure 10. CS mode 4 wires without busy indicator Serial InterfaceTiming.
REV. Pr F
–11–
PRELIMINARY TECHNICAL DATA
AD7687
CS MODE 4 wires with Busy indicator
When the conversion is complete, SDO goes from high
impedance to low. With a pull-up on SDO line, this tran-
sition can be used as an interrupt signal to trigger the data
reading controlled by the digital host. The AD7687 also
enters in acquisition phase and in reduced power mode.
The data bits are then clocked out, MSB first, by subse-
quent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the
data, a digital host with acceptable hold time using the
SCK falling edge will allow a faster reading rate. After the
optional 17th SCK falling edge or SDI goes high which-
ever is the earliest, the SDO returns to high impedance.
This mode is usually used when a single AD7687 is con-
nected to an SPI compatible digital host having an
interrupt input and it is desired to keep CNV, used to
sample the analog input, independent of the signal used to
select the data reading. This requirement is particularly
important in applications where low jitter on CNV is de-
sired.
The connection diagram is shown in figure 11 and the
corresponding timing is given in figure 12.
With SDI high, a rising edge on CNV initiates a conver-
sion, selects the CS mode and forces SDO in high
impedance. In this mode, CNV is held high during the
conversion phase and the subsequent data reading. Prior to
the minimum conversion time, SDI could be used to se-
lect other SPI devices such as analog multiplexers but
SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator.
CS1
CONVERT
OVDD
CNV
47k⍀
AD7687
Digital Host
DATA IN
SDI
SDO
SCK
IRQ
CLK
Figure 11. CS mode 4 wires with busy indicator Connection
Diagram .
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
tEN
D15
D14
D1
D0
Figure 12. CS mode 4 wires with busy indicator Serial Interface Timing.
REV. Pr F
–12–
PRELIMINARY TECHNICAL DATA
AD7687
Chain MODE without Busy indicator
AD7687 enters in acquisition phase and in reduced power
mode. The remaining data bits stored in the internal out-
put data shift register are then clocked by subsequent SCK
falling edges. This internal output data shift register is
also filled in on each SCK falling edge by the SDI data.
By connecting SDO output of an “upstream” device to the
SDI input of a “downstream” device, after the 16th SCK
falling edge, the MSB of the “upstream” device is output
on SDO and, consequently, the result of all devices in the
chain is output serially on the SDO output of the last
“downstream” device. The data is valid on both SCK
edges. Although the rising edge can be used to capture the
data, a digital host with acceptable hold time using the
SCK falling edge will allow a faster reading rate and more
AD7687s in the chain. For instance, with a 5ns digital
host set-up time and 5V interface, up to five AD7687’s
running at the maximum conversion rate of 250 kSPS can
be “daisy-chain” to a single 3 wire port.
This mode can be used to “daisy-chain” multiple
AD7687’s on a single 3 wire serial interface. This feature
is useful for reducing component count and wiring con-
nections when desired as, for instance, in isolated
multiconverter application or for systems with a limited
capacity for interfacing to a large number of converters.
A connection diagram example using two AD7687’s is
shown in figure 13 and the corresponding timing is given
in figure 14.
With SDI tied to ground, SDO is low when CNV is low.
With SCK low, a rising edge on CNV initiates a conver-
sion, selects the Chain mode and disables the busy
indicator. In this mode, CNV is held high during the con-
version phase and the subsequent data reading. When the
conversion is complete, the MSB is output on SDO, the
CONVERT
CNV
CNV
Digital Host
DATA IN
AD7687
AD7687
B
SDO
A
SDI
SDO
SDI
SCK
SCK
CLK
Figure 13. Chain mode without busy indicator Connection Diagram .
SDI = 0
A
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
14
15
16
17
18
30
31
32
tHSCKCNV
tSSDISCK
tHSDISC
tSCKH
tEN
SDO = SDI
D
15
15
D
14
14
D
13
13
D
1
1
D
0
0
A
B
A
A
A
A
A
tHSDO
tDSDO
SDO
D
D
D
D
D
B
D
15
D
14
D
1
D 0
A
B
B
B
B
B
A
A
A
Figure 14. Chain mode without busy indicator Serial InterfaceTiming.
–13–
REV. Pr F
PRELIMINARY TECHNICAL DATA
AD7687
phase and in reduced power mode. The data bits stored in
the internal output data shift register are then clocked out,
MSB first, by subsequent SCK falling edges. This internal
output data shift register is also filled in by the SDI data
on each SCK falling edge except the first one. By con-
necting SDO output of an “upstream” device to the SDI
input of a “downstream” device, after the 17th SCK fall-
ing edge, the MSB of the “upstream” device is output on
SDO and, consequently, the result of all devices in the
chain is output serially on the SDO output of the last
“downstream” device. Similarly, the busy indicator propa-
gates through the chain such that SDO goes high only
when all upstream devices conversions are complete. Al-
though the rising edge can be used to capture the data, a
digital host with acceptable hold time using the SCK fall-
ing edge will allow a faster reading rate and more
Chain MODE with Busy indicator
This mode can also be used to “daisy-chain” multiple
AD7687’s on a single 3 wire serial interface while provid-
ing a busy indicator.
A connection diagram example using three AD7687’s is
shown in figure 15 and the corresponding timing is given
in figure 16.
With SDI and CNV tied together, SDO is low when CNV
is low. With SCK high, a rising edge on CNV/SDI ini-
tiates a conversion, selects the Chain mode and enables
the busy indicator feature. In this mode, CNV is held high
during the conversion phase and the subsequent data read-
ing. When the conversion is complete and SDI is high,
SDO goes high, this transition on SDO can be used as an
interrupt signal to trigger the data reading controlled by
the digital host. The AD7687 also enters in acquisition
AD7687s in the chain. For instance, with a 5ns digital
host set-up time and 5V interface, up to five AD7687’s
running at the maximum conversion rate of 250 kSPS can
be “daisy-chain” to a single 3 wire port.
CONVERT
CNV
CNV
CNV
Digital Host
AD7687
AD7687
A
AD7687
B
C
SDI
SDO
SDI
SDO
SDI
SDO
DATA IN
IRQ
SCK
SCK
SCK
CLK
Figure 15. Chain mode with busy indicator Connection Diagram .
tCYC
CNV = SDI
A
tACQ
ACQUISITION
tCONV
ACQUISITION
CONVERSION
tSCK
tSCKH
tSSCKCNV
SCK
1
2
3
4
15
16
D
17
D
18
19
31
32
33
34
35
47
48
49
tHSCKCNV
tSSDISCK
tHSDISC
tSCKL
tEN
SDO = SDI
D
15
15
D
14
14
D
D
13
1
0
0
A
B
A
A
A
A
A
tHSDO
tDSDO
SDO = SDI
B
D
D
13
D
1
D
D
15
D
14
D
1
D 0
A
C
B
B
B
B
B
A
A
A
tDSDOSDI
SDO
D
15
D
14
D
13
D
1
D
0
D
15
D
14
D
1
D
0
D
15
D
14
D
1
D 0
A
C
C
C
C
C
C
B
B
B
B
A
A
A
Figure 16. Chain mode with busy indicator Serial Interface Timing.
–14–
REV. Pr F
PRELIMINARY TECHNICAL DATA
AD7687
OUTLINE DIMENSIONS
Dimensionsshownininchesand(mm).
10-Lead ꢀSOIC
(RM-10)
0.124 (3.15)
0.112 (2.84)
10
6
0.124 (3.15)
0.112 (2.84)
0.199 (5.05)
0.187 (4.75)
1
5
PIN 1
0.0197 (0.50) BSC
0.122 (3.10)
0.110 (2.79)
0.120 (3.05)
0.112 (2.84)
0.038 (0.97)
0.030 (0.76)
0.043 (1.09)
0.037 (0.94)
6˚
0˚
SEATING
PLANE
0.016 (0.41)
0.006 (0.15)
0.006 (0.15)
0.002 (0.05)
0.022 (0.56)
0.021 (0.53)
0.011 (0.28)
0.003 (0.08)
REV. Pr F
–15–
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