AD7701TQ [ADI]
LC2MOS 16-Bit A/D Converter; LC2MOS 16位A / D转换器
| 型号： | AD7701TQ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 16-Bit A/D Converter |
| 文件： | 总16页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
16-Bit A/D Converter
a
AD7701
FEATURES
Monolithic 16-Bit ADC
FUNCTIO NAL BLO CK D IAGRAM
AVDD DVDD AVSS DVSS
15
SC1
4
SC2
17
0.0015% Linearity Error
14
7
6
On-Chip Self-Calibration Circuitry
Program m able Low -Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or ؎2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
AD7701
CALIBRATION
CALIBRATION
SRAM
13
CAL
MICROCONTROLLER
16-BIT A/D CONVERTER
AIN
9
12
11
BP/UP
SLEEP
Ultralow Pow er
6-POLE GAUSSIAN
LOW-PASS
DIGITAL FILTER
ANALOG
MODULATOR
VREF
10
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrum entation
Rem ote Data Acquisition
AGND
DGND
8
5
20 SDATA
SCLK
CLOCK
GENERATOR
SERIAL INTERFACE
LOGIC
19
3
2
1
16
18
DRDY
CLKIN CLKOUT MODE
CS
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7701 is a 16-bit ADC which uses a sigma-delta conver-
sion technique. T he analog input is continuously sampled by an
analog modulator whose mean output duty cycle is proportional
to the input signal. T he modulator output is processed by an
on-chip digital filter with a six-pole Gaussian response, which
updates the output data register with 16-bit binary words at
word rates up to 4 kHz. T he sampling rate, filter corner fre-
quency and output word rate are set by a master clock input
that may be supplied externally, or by a crystal-controlled on-
chip clock oscillator.
1. T he AD7701 offers 16-bit resolution coupled with outstand-
ing 0.0015% accuracy.
2. No missing codes ensures true, usable, 16-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. T he effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to
remove system offsets and gain errors.
4. A flexible synchronous/asynchronous interface allows the
AD7701 to interface directly to UART s or to the serial ports
of industry-standard microcontrollers.
T he inherent linearity of the ADC is excellent, and endpoint
accuracy is ensured by self-calibration of zero and full scale
which may be initiated at any time. T he self-calibration scheme
can also be extended to null system offset and gain errors in the
input channel.
5. Low operating power consumption and an ultralow power
standby mode make the AD7701 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
T he output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UART s and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction insures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 µW.
REV. D
© Analog Devices, Inc., 1996
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T = +25؇C; AV = DV = +5 V; AV = DV = –5 V; V = +2.5 V; fCLKIN
=
A
DD
DD
SS
SS
REF
4.096 MHz; Bipolar Mode: MODE = +5 V; A Source Resistance = 1k ⍀1 with 1 nF to
IN
AGND at A , unless otherwise noted.)
AD7701–SPECIFICATIONS
IN
P aram eter
A, S Versions2
B, T Versions2
Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
16
16
Bits
Integral Nonlinearity
T MIN to T MAX
±0.0007
±0.0015
% FSR typ
% FSR max
±0.003
Differential Nonlinearity
T MIN to T MAX
±0.125
±0.5
±0.13
±0.5
±1.2 (±2.3 S Version)
±0.25
±1
±1.6 (+3/–25 S Version)
±0.25
±1
±0.8 (+1.5/–12.5 S Version) ±0.8 (+1.5/–12.5 T Version) LSB typ
±0.5
±0.125
±0.5
±0.13
±0.5
±1.2 (±2.3 T Version)
±0.25
±1
±1.6 (+3/–25 T Version)
±0.25
± 1
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
LSB max
Guaranteed No Missing Codes
Positive Full-Scale Error3
Full-Scale Drift4
Unipolar Offset Error3
Unipolar Offset Drift4
Bipolar Zero Error3
Bipolar Zero Drift4
Bipolar Negative Full-Scale Error3
±0.5
LSB typ
±2
±2
LSB max
LSB typ
LSB rms typ
Bipolar Negative Full-Scale Drift4
Noise (Referred to Output)
±0.6 (±1.2 S Version)
0.1
±0.6 (±1.2 T Version)
0.1
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Output Update Rate, fOUT
Filter Corner Frequency, f–3 dB
Settling T ime to ±0.0007% FS
fCLKIN/256
fCLKIN/256
Hz
Hz
Hz
sec
fCLKIN/1024
fCLKIN/409,600
507904/fCLKIN
fCLKIN/1024
fCLKIN/409,600
507904/fCLKIN
For Full-Scale Input Step
SYST EM CALIBRAT ION
Positive Full-Scale Overrange
Positive Full-Scale Overrange
Negative Full-Scale Overrange
Maximum Offset Calibration Range5, 6
Unipolar Input Range
Applies to Unipolar and
Bipolar Ranges. After Cali-
bration, If AIN > VREF, the
Device Will Output All 1s
If AIN < 0 (Unipolar) or
–VREF (Bipolar), the Device
Will Output All 0s.
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
VREF + 0.1
VREF + 0.1
–(VREF + 0.1)
V max
V max
V max
–(VREF + 0.1)
–0.4 VREF to +0.4 VREF
0.8 VREF
–(VREF + 0.1)
–0.4 VREF to +0.4 VREF
0.8 VREF
V max
V max
V min
V max
Bipolar Input Range
Input Span7
2 VREF + 0.2
2 VREF + 0.2
ANALOG INPUT
Unipolar Input Range
Bipolar Input Range
Input Capacitance
Input Bias Current1
0 to +2.5
±2.5
10
0 to +2.5
±2.5
10
Volts
Volts
pF typ
nA typ
1
1
LOGIC INPUT S
All Inputs Except CLKIN
VINL, Input Low Voltage
VINH, Input High Voltage
CLKIN
0.8
2.0
0.8
2.0
V max
V min
VINL, Input Low Voltage
VINH, Input High Voltage
IIN, Input Current
0.8
3.5
10
0.8
3.5
10
V max
V min
µA max
LOGIC OUT PUT S
VOL, Output Low Voltage
VOH , Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
0.4
DVDD – 1
±10
9
0.4
DVDD – 1
±10
9
V max
V min
µA max
pF typ
ISINK = 1.6 mA
ISOURCE = 100 µA
–2–
REV. D
AD7701
P aram eter
A, S Versions2
B, T Versions2
Units
Test Conditions/Com m ents
POWER REQUIREMENT S8
Power Supply Voltages
Analog Positive Supply (AVDD
Digital Positive Supply (DVDD
)
)
)
4.5/5.5
4.5/5.5
V min/V max
V min/V max
V min/V max
V min/V max
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
4.5/AVDD
–4.5/–5.5
–4.5/–5.5
Analog Negative Supply (AVSS
Digital Negative Supply (DVSS
Calibration Memory Retention
Power Supply Voltage
)
2.0
2.0
V min
DC Power Supply Currents8
Analog Positive Supply (AIDD
Digital Positive Supply (DIDD
Analog Negative Supply (AISS
Digital Negative Supply (DISS
Power Supply Rejection9
Positive Supplies
)
)
)
)
3.2
1.5
3.2
0.1
3.2
1.5
3.2
0.1
mA max
mA max
mA max
mA max
T ypically 2 mA
T ypically 1 mA
T ypically 2 mA
T ypically 0.03 mA
70
75
70
75
dB typ
dB typ
Negative Supplies
Power Dissipation
Normal Operation
40
40
mW max
SLEEP = Logic 1,
T ypically 25 mW
SLEEP = Logic 0,
T ypically 10 µW
Standby Operation10
20 (40 S Version)
20 (40 T Version)
µW max
NOT ES
11T he AIN pin presents a very high impedance dynamic load which varies with clock frequency.
12T emperature ranges are as follows: A, B Versions; –40°C to +85°C; S, T Versions; –55°C to +125°C.
13Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
14T otal drift over the specified temperature range since calibration at power-up at +25 °C. T his is guaranteed by design and/or characterization. Recalibration at any
temperature will remove these errors.
15In unipolar mode the offset can have a negative value (–VREF) such that the unipolar mode can mimic bipolar mode operation.
16T he specifications for input overrange and for input span apply additional constraints on the offset calibration range.
17For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative
full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF +0.1)
18All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
19Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
Industrial Cerdip (A, B Versions) . . . . . . . –40°C to +85°C
(T A = +25°C unless otherwise noted)
Extended Cerdip (S, T Versions) . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V
Analog Input
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2T ransient currents of up to 100 mA will not cause SCR latch-up.
Voltage to AGND . . . . . . . . AVSS – 0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA
Operating T emperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD7701
P IN FUNCTIO N D ESCRIP TIO N
P in
Mnem onic D escription
1
MODE
Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the asynchronous
communications (ac) mode. T he SCLK pin is configured as an input, and data is transmitted in two bytes,
each with one start bit and two stop bits. If MODE is tied to DGND, the synchronous external clocking
(SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the
MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the synchronous self-clocking (SSC)
mode. SCLK is configured as an output, with a clock frequency of fCLKlN/4 and 25% duty-cycle.
2
CLKOUT
Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.
If an external clock is used, CLKOUT is not connected.
3
CLKIN
Clock Input for External Clock.
4, 17
SC1, SC2
System Calibration Pins. T he state of these pins, when CAL is taken high, determines the type of calibration
performed.
5
DGND
DVSS
AVSS
AGND
AIN
Digital Ground. Ground reference for all digital signals.
Digital Negative Supply, –5 V nominal.
Analog Negative Supply, –5 V nominal.
Analog Ground. Ground reference for all analog signals.
Analog Input.
6
7
8
9
10
VREF
Voltage Reference Input, +2.5 V nominal. T his determines the value of positive full-scale in the unipolar
mode and of both positive and negative full-scale in the bipolar mode.
11
12
13
SLEEP
BP/UP
CAL
Sleep mode pin. When this pin is taken low, the AD7701 goes into a low-power mode with typically 10 µW
power consumption.
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a unipolar input range going
from AGND to VREF. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ±VREF
.
Calibration Mode Pin. When CAL is taken high for more than 4 cycles, the AD7701 is reset and performs a
calibration cycle when CAL is brought low again. T he CAL pin can also be used as a strobe to synchronize
the operation of several AD7701s.
14
15
16
AVDD
DVDD
CS
Analog Positive Supply, +5 V nominal.
Digital Positive Supply, +5 V nominal.
Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format deter-
mined by the state of the MODE pin.
18
19
20
DRDY
SCLK
Data Ready output. DRDY is low when valid data is available in the output register. It goes high after transmission
of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the out-
put register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not.
Serial Clock Input/Output. T he SCLK pin in configured as an input or output, dependent on the type of se-
rial data transmission that has been selected by the MODE pin. When configured as an output in the syn-
chronous self-clocking mode, it has a frequency of fCLKIN/4 and a duty cycle of 25%.
SDAT A
Serial Data Output. T he AD7701’s output data is available at this pin as a 16-bit serial word. T he transmis-
sion format is determined by the state of the MODE pin.
O RD ERING GUID E
P IN CO NFIGURATIO NS
D IP , Cer dip, SO IC
SSO P
Tem perature
Linearity
P ackage
Model
Range
Error (% FSR) O ptions*
20
1
2
1
2
MODE
SDATA
28
27
26
25
24
23
22
21
MODE
SDATA
SCLK
19 SCLK
CLKOUT
CLKOUT
AD7701AN
AD7701BN
AD7701AR
AD7701BR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0.003
0.0015
0.003
0.0015
0.003
0.003
0.0015
N-20
N-20
R-20
R-20
RS-28
Q-20
Q-20
Q-20
Q-20
3
18
3
DRDY
CLKIN
SC1
DRDY
SC2
CS
CLKIN
SC1
17
4
4
SC2
AD7701
TOP VIEW
16
5
5
CS
DGND
DVSS
AVSS
DGND
NC
15
6
6
DVDD
NC
(Not to Scale)
AD7701
14 AVDD
7
7
NC
NC
NC
AD7701ARS –40°C to +85°C
TOP VIEW
(Not to Scale)
13
8
8
DV
SS
CAL
AGND
AIN
AD7701AQ
AD7701BQ
AD7701SQ
AD7701T Q
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C 0.003
–55°C to +125°C 0.0015
12
9
20 DV
19 AV
9
NC
BP/UP
DD
DD
AV
SS
11
VREF
10
10
SLEEP
18
NC 11
12
NC
17
CAL
AGND
16
15
A
13
14
BP/UP
SLEEP
IN
NOT ES
V
REF
*N = Plastic DIP; Q = Cerdip; R = SOIC; RS = SSOP.
NC = NO CONNECT
–4–
REV. D
AD7701
(AV = DV = +5 V ؎ 10%; AV = DV = –5 V ؎ 10%; AGND = DGND = O V;
DD
DD
SS
SS
1, 2
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV )
TIMING CHARACTERISTICS
DD
Lim it at TMIN, TMAX
Lim it at TMIN, TMAX
(S, T Versions)
P aram eter
(A, B Versions)
Units
Conditions/Com m ents
Master Clock Frequency: Internal Gate Oscillator
3, 4
fCLKIN
200
5
200
5
kHz min
MHz max T ypically 4.096 MHz
200
5
50
50
0
200
5
50
50
0
kHz min
MHz max
ns max
ns max
ns min
Master Clock Frequency: Externally Supplied
5
tr
Digital Output Rise T ime. T ypically 20 ns
Digital Output Fall T ime. T ypically 20 ns
SC1, SC2 to CAL High Setup T ime
tf5
t1
t2
t3
50
1000
50
1000
ns min
ns min
SC1, SC2 Hold T ime After CAL Goes High
SLEEP High to CLKIN High Setup T ime
6
SSC Mode
7
t4
t5
t6
t7
3/fCLKIN
100
250
300
790
3/fCLKIN
100
250
300
790
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access T ime (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup T ime. T ypically 380 ns
SCLK High Pulse Width. T ypically 240 ns
SCLK Low Pulse Width. T ypically 730 ns
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
t88
t9
l/fCLKIN +200
(4/fCLKIN) +200
l/fCLKIN +200
(4/fCLKIN) +200
8, 9
t10
SEC Mode
fSCLK
t11
5
35
5
35
MHz
Serial Clock Input Frequency
SCLK Input High Pulse Width
SCLK Low Pulse Width
Data Access Time (CS Low to Data Valid). Typically 80 ns
SCLK Falling Edge to Data Valid Delay. T ypically 75 ns
CS High to Hi-Z Delay
ns min
ns min
ns max
ns max
ns max
ns max
t12
t13
t14
t15
160
160
150
250
200
160
160
150
250
200
7, 10
11
8
8
t16
SCLK Falling Edge to Hi-Z Delay. T ypically 100 ns
AC Mode
t17
t18
t19
40
180
200
40
180
200
ns min
ns max
ns max
CS Setup T ime. T ypically 20 ns
Data Delay T ime. T ypically 90 ns
SCLK Falling Edge to Hi-Z Delay. T ypically 100 ns
NOT ES
11Sample tested at +25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
12See Figures 1 to 6.
13CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
14T he AD7701 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
15Specified using 10% and 90% points on waveform of interest.
16In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.
17t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
18t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. T his means that the time quoted in the T iming Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.
19If CS is returned high before all 16 bits are output, the SDAT A and SCLK outputs will complete the current data bit and then go to high impedance.
10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. T he propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. T o guarantee proper clocking of SDAT A when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.
11SDAT A is clocked out on the falling edge of the SCLK input.
REV. D
–5–
AD7701
I
OL
1.6mA
CAL
CLKIN
SLEEP
TO
OUTPUT
PIN
+
2.1V
t2
SC1,SC2 VALID
t1
t3
C
L
100pF
SC1, SC2
I
OH
200µA
Figure 1. Load Circuit for Access
Tim e and Bus Relinquish Tim e
Figure 2a. Calibration Control Tim ing
Figure 2b. SLEEP Mode Tim ing
DRDY
CS
CS
CS
t12
t15
t11
t10
HI-Z
SCLK
DATA
SDATA
HI-Z
VALID
DATA
SDATA
t13
t16
VALID
t14
HI-Z
HI-Z
DB15 DB14
DB0
SDATA
DB1
Figure 4b. SEC Mode Tim ing Diagram
Figure 4a. SEC Mode Data Hold Tim e
Figure 3. SSC Mode Data Hold
Tim e
CLKIN
CS
DRDY
CS
t7
t17
t8
HI-Z
SCLK
SCLK
t9
t4
t6
t5
t18
t19
START
HI-Z
HI-Z
SDATA
STOP 1
DB8
DB7
DB9
STOP 2
HI-Z
HI-Z
DB15
LOW BYTE
SDATA
DB14
HIGH BYTE
DB1
DB0
Figure 6. AC Mode Tim ing Diagram
Figure 5. SSC Mode Tim ing Diagram
TERMINO LO GY
LINEARITY ERRO R
BIP O LAR ZERO ERRO R
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he
endpoints of the transfer function are Zero-Scale (not to be
confused with Bipolar Zero), a point 0.5 LSB below the first
code transition (000 . . . 000 to 000 . . . 001) and Full-Scale, a
point 1.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). T he error is expressed as a percentage of full
scale.
T his is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when
operating in the bipolar mode. It is expressed in microvolts.
BIP O LAR NEGATIVE FULL-SCALE ERRO R
T his is the deviation of the first code transition from the ideal
(–VREF + 0.5 LSB), when operating in the bipolar mode. It is
expressed in microvolts.
P O SITIVE FULL-SCALE O VERRANGE
D IFFERENTIAL LINEARITY ERRO R
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages greater than +VREF ( for example,
noise peaks or excess voltages due to system gain errors in
system calibration routines) without introducing errors due to
overloading the analog modulator or overflowing the digital
filter. It is expressed in millivolts.
T his is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees monotonicity.
P O SITIVE FULL-SCALE ERRO R
Positive Full-Scale Error is the deviation of the last code
transition (111 . . . 110 to 111 . . . 111) from the ideal (VREF
–3/2 LSBs). It applies to both positive and negative analog input
ranges and it is expressed in microvolts.
NEGATIVE FULL-SCALE O VERRANGE
T his is the amount of overhead available to handle voltages
below –VREF without overloading the analog modulator or
overflowing the digital filter. Note that the analog input will
accept negative voltage peaks even in the unipolar mode. T he
overhead is expressed in millivolts.
UNIP O LAR O FFSET ERRO R
Unipolar Offset Error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the uni-
polar mode. It is expressed in microvolts.
–6–
REV. D
AD7701
O FFSET CALIBRATIO N RANGE
T he AD7701 can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. A calibration cycle may be initiated at any time
using the CAL control input.
In the system calibration modes (SC2 low) the AD7701
calibrates its offset with respect to the AIN pin. T he Offset
Calibration Range specification defines the range of voltages,
expressed as a percentage of VREF that the AD7701 can accept
and still calibrate offset accurately.
Other system components may also be included in the
calibration loop to remove offset and gain errors in the input
channel.
FULL-SCALE CALIBRATIO N RANGE
T his is the range of voltages that the AD7701 can accept in the
system calibration mode and still calibrate full-scale correctly.
For battery operation, the AD7701 also offers a standby mode
that reduces idle power consumption to typically 10 µW.
TH EO RY O F O P ERATIO N
INP UT SP AN
T he general block diagram of a sigma-delta ADC is shown in
Figure 8. It contains the following elements.
In system calibration schemes, two voltages applied in sequence
to the AD7701’s analog input define the analog input range.
T he input span specification defines the minimum and maxi-
mum input voltages from zero to full-scale that the AD7701 can
accept and still calibrate gain accurately. T he input span is ex-
pressed as a percentage of VREF.
1. A sample-hold amplifier.
2. A differential amplifier or subtracter.
3. An analog low-pass filter.
4. A 1-bit A/D converter (comparator).
5. A 1-bit DAC.
GENERAL D ESCRIP TIO N
T he AD7701 is a 16-bit A/D converter with on-chip digital
filtering, intended for the measurement of wide dynamic range,
low frequency signals such as those representing chemical,
physical or biological processes. It contains a charge-balancing
(sigma-delta) ADC, calibration microcontroller with on-chip
static RAM, a clock oscillator and a serial communications port.
6. A digital low-pass filter.
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. T he filtered difference
signal is fed to the comparator, whose output samples the
difference signal at a frequency many times that of the analog
signal sampling frequency (oversampling).
T he analog input signal to the AD7701 is continuously sampled
at a rate determined by the frequency of the master clock,
CLKIN. A charge-balancing A/D converter (Sigma-Delta
Modulator) converts the sampled signal into a digital pulse train
whose duty cycle contains the digital information. A six-pole
Gaussian digital low-pass filter processes the output of the
modulator and updates the 16-bit output register at a 4 kHz
rate. T he output data can be read from the serial port randomly
or periodically at any rate up to 4 kHz.
S/H AMP
COMPARATOR
ANALOG
LOW-PASS
DIGITAL
FILTER
FILTER
DIGITAL DATA
DAC
+5V
ANALOG
SUPPLY
Figure 8. General Sigm a-Delta ADC
0.1µF
10µF
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC:
AVDD
DVDD
SNR = (6.02 × number of bits + 1.76) dB
0.1µF
SLEEP
MODE
2.5V
VOLTAGE
REFERENCE
VREF
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
DATA
T he AD7701 samples the input signal at 16 kHz, which spreads
the quantization noise from 0 to 8 kHz. Since the specified
analog input bandwidth of the AD7701 is only 0 to 10 Hz, the
noise energy in this bandwidth would be only 1/800 of the total
quantization noise, even if the noise energy was spread evenly
throughout the spectrum. It is reduced still further by analog
filtering in the modulator loop, which shapes the quantization
noise spectrum to move most of the noise energy to frequencies
above 10 Hz. T he SNR performance in the 0 to 10 Hz range is
conditioned to the 16-bit level in this fashion.
DRDY
CS
READY
READ
(TRANSMIT)
RANGE
SELECT
BP/UP
CAL
SERIAL
CLOCK
SERIAL
DATA
SCLK
CALIBRATE
SDATA
AD7701
CLKIN
ANALOG
INPUT
AIN
CLKOUT
SC1
SC2
ANALOG
GROUND
AGND
AVSS
DGND
T he output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. T he digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data word using a
digital filter.
0.1µF
0.1µF
DVSS
–5V
ANALOG
SUPPLY
0.1µF
10µF
Figure 7. Typical System Connection Diagram
REV. D
–7–
AD7701
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first order sigma-
delta ADC is shown in Figure 9. T his contains only a first-order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: Charge-Balancing ADCs.
FILTER CH ARACTERISTICS
T he cutoff frequency of the digital filter is fCLK /409600. At the
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the output rate is 4 kHz.
Figure 10 shows the filter frequency response. T his is a 6-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
s-domain pole-zero plot of the filter is shown in Figure 11.
C
CLOCK
R
A
IN
TO DIGITAL
FILTER
T he response of the filter is defined by:
INTEGRATOR
H(x) = [1+ 0.693x2 + 0.240x4 + 0.0555x6 + 0.00962x8
STROBED
COMPARATOR
–0.5
+ 0.00133x10 + 0.000154x12]
R
where:
+V
–V
REF
x = f/f3 dB, f3 dB = fCLKIN/409600,
and
REF
1-BIT DAC
f is the frequency of interest.
Figure 9. SEC Basic Charge-Balancing ADC
20
T he term charge-balancing comes from the fact that this system
is a negative feedback loop that tries to keep the net charge on
the integrator capacitor at zero, by balancing charge injected by
the input voltage with charge injected by the 1-bit DAC. When
the analog input is zero, the only contribution to the integrator
output comes from the 1-bit DAC. For the net charge on the
integrator capacitor to be zero, the DAC output must spend half
its time at +1 V and half its time at –1 V. Assuming ideal
components, the duty cycle of the comparator will be 50%.
0
f
= 4MHz
CLK
–20
–40
–60
f
= 2MHz
CLK
–80
–100
–120
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +1 V, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
f
= 1MHz
CLK
–140
–160
1
100
10
FREQUENCY – Hz
T he AD7701 uses a second-order sigma-delta modulator and a
sophisticated digital filter that provides a rolling average of the
sampled output. After power-up or if there is a step change in
the input voltage, there is a settling time that must elapse before
valid data is obtained.
Figure 10. Frequency Response of AD7701 Filter
jw
j2
j1
D IGITAL FILTERING
S1,2 = –1.4663 + j1.8191
T he AD7701’s digital filter behaves like a similar analog filter,
with a few minor differences.
s
S3,4 = –1.7553 + j1.0005
S5,6 = –1.8739 + j0.32272
0
–2
–1
First, since digital filtering occurs after the A to D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
–j1
–j2
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. T o alleviate this problem, the AD7701 has over-
range headroom built into the sigma-delta modulator and digital
filter which allows overrange excursions of 100 mV. If noise
signals are larger than this, consideration should be given to
analog input filtering, or to reducing the gain in the input
channel so that a full-scale input (2.5 V) gives only a half-scale
input to the AD7701 (1.25 V). T his will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Figure 11. Norm alized Pole-Zero Plot of AD7701 Filter
Since the AD7701 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data will be invalid after a step change until the settling time has
elapsed. T he AD7701 is therefore unsuitable for high speed
multiplexing, where channels are switched and converted se-
quentially at high rates, as switching between channels can
cause a step change in the input. Rather, it is intended for dis-
tributed converter systems using one ADC per channel.
However, slow multiplexing of the AD7701 is possible, provided
that the settling time is allowed to elapse before data for the new
channel is accessed.
–8–
REV. D
AD7701
T he output settling of the AD7701 in response to a step input
change is shown in Figure 12. T he Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
±0.0007% (±0.5 LSB) is 125 ms with a 4.096 MHz master
clock frequency.
T he input sampling frequency, output data rate, filter character-
istics and calibration time are all directly related to the master
clock frequency fCLKIN by the ratios given in the specification
table. T herefore, the first step in system design with the
AD7701 is to select a master clock frequency suitable for the
bandwidth and output data rate required by the application.
ANALO G INP UT RANGES
100
80
60
40
20
0
T he AD7701 performs conversion relative to an externally
supplied reference voltage, which allows easy interfacing to
ratiometric systems. In addition, either unipolar or bipolar input
voltage range may be selected using the BP/UP input. With BP/
UP tied low, the input range is unipolar and the span is 0 to
+VREF. With BP/UP tied high, the input range is bipolar and the
span is ±VREF. In the bipolar mode both positive and negative
full scale are directly determined by VREF. T his offers superior
tracking of positive and negative full scale and better midscale
(bipolar zero) stability than bipolar schemes that simply scale
and offset the input range.
0
40
80
120
160
TIME – ms
T he digital output coding for the unipolar range is Unipolar
Binary; for the bipolar range it is Offset Binary. Bit weights for
the unipolar and bipolar modes are shown in T able I. T he input
voltages and output codes for unipolar and bipolar ranges, using
the recommended +2.5 V reference, are shown in T able II.
Figure 12. AD7701 Step Response
USING TH E AD 7701
SYSTEM D ESIGN CO NSID ERATIO NS
T he AD7701 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the sig-
nal continuously, like a tracking ADC, there is no need for a
start convert command. T he 16-bit output register is updated at
a 4 kHz rate, and the output can be read at any time, either syn-
chronously or asynchronously.
Table I. Bit Weight Table (2.5 V Reference Voltage)
Unipolar Mode
Bipolar Mode
LSBs % FS
V LSBs % FS
ppm FS
ppm FS
CLO CKING
10
19
38
76
0.26
0.5
1.00
2.00
0.0004
0.0008
0.0015
0.0031
0.0061
4
8
15
31
61
0.13
0.26
0.5
1.00
2.00
0.0002
0.0004
0.0008
0.0015 15
0.0031 31
2
4
8
T he AD7701 requires a master clock input, which may be an
external T T L/CMOS compatible clock signal applied to the
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the
correct frequency can be connected between CLKIN and
CLKOUT , when the clock circuit will function as a crystal-
controlled oscillator.
153 4.00
Table II. O utput Coding
Unipolar Mode
Input Relative to
FS and AGND
Bipolar Mode
Input Relative to
FS and AGND
Input in Volts
Input in Volts
O utput D ata
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
+VREF – 1.5 LSB
+VREF – 2.5 LSB
+VREF – 3.5 LSB
+2.499943
+2.499905
+2.499867
+VREF – 1.5 LSB
+VREF – 2.5 LSB
+VREF – 3.5 LSB
+2.499886
+2.499810
+2.499733
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
+VREF/2 + 0.5 LSB
+VREF/2 – 0.5 LSB
+VREF/2 – 1.5 LSB
+1.250019
+1.249981
+1.249943
AGND + 0.5 LSB
AGND – 0.5 LSB
AGND – 1.5 LSB
+0.000038
–0.000038
–0.000114
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
AGND + 2.5 LSB
AGND + 1.5 LSB
AGND + 0.5 LSB
+0.000095
+0.000057
+0.000019
–VREF + 2.5 LSB
–VREF + 1.5 LSB
–VREF + 0.5 LSB
–2.499810
–2.499886
–2.499962
NOT ES
1VREF = +2.5 V
2AGND = 0 V
3Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V
4Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V
5Inputs are voltages at code transitions.
REV. D
–9–
AD7701
INP UT SIGNAL CO ND ITIO NING
An RC filter may be added in front of the AD7701 to reduce
high frequency noise. With an external capacitor added from
AIN to AGND, the following equation will specify the maximum
allowable source resistance:
Reference voltages from +1 V to +3 V may be used with the
AD7701, with little degradation in performance. Input ranges
that cannot be accommodated by this range of reference voltages
may be achieved by input signal conditioning. T his may take the
form of gain to accommodate a smaller signal range, or passive
attenuation to reduce a larger input voltage range.
62
RS (Max)
=
100 mV × CIN / (CIN + CEXT
)
fCLKIN ×(CIN
+ CEXT ) × ln
VE
Sour ce Resistance
If passive attenuators are used in front of the AD7701, care
must be taken to ensure that the source impedance is suffi-
ciently low. T he AD7701 has an analog input with over 1 GΩ
dc input resistance. In parallel with this there as a small dy-
namic load which varies with the clock frequency (see Figure
13). Each time the analog input is sampled, a 10 pF capacitor
draws a charge packet of maximum 1 pC (10 pF × 100 mV)
T he practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source.
Vn = √4 kTRf Volts
in = √4 kTf / R Amperes
where:
A
IN
R1
k is Boltzmann’s constant (1.38 × 10–23 J/K)
and
AD7701
R2
T is temperature in degrees Kelvin (°C + 273).
C
EXT
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. T heir open
loop output resistance is normally only tens of ohms and, in any
case, most modern general purpose op amps have sufficiently
fast closed loop settling time for this not to be a problem. Offset
voltage in op amps can be eliminated in a system calibration
routine. With the wide dynamic range and small LSB size of the
AD7701, noise can also be a problem, but the digital filter will
reject most broadband noise above its cutoff frequency. How-
ever, in certain applications there may be a need for analog
input filtering.
C
10pF
IN
V
≤100mV
OS
AGND
Figure 13. Equivalent Input Circuit and Input Attenuator
from the analog source with a frequency fCLKIN/256. For a
4.096 MHz CLKIN, this yields an average current draw of
16 nA. After each sample the AD7701 allows 62 clock periods
for the input voltage to settle. T he equation which defines
settling time is:
Antialias Consider ations
VO = VIN [1 – e–t/RC
]
T he digital filter of the AD7701 does not provide any rejection
at integer multiples of the sampling frequency (nfCLKlN/256,
where n = 1, 2, 3 . . . ).
where:
VO is the final settled value,
VIN is the value of the input signal,
With a 4.096 MHz master clock there are narrow (±10 Hz)
bands at 16 kHz, 32 kHz, 48 kHz, etc., where noise passes
unattenuated to the output.
R
C
t
is the value of the input source resistance,
is the 10 pF sample capacitor,
is equal to 62/fCLKIN
.
However, due to the AD7701’s high oversampling ratio of 800
(16 kHz to 20 Hz) these bands occupy only a small fraction of
the spectrum, and most broadband noise is filtered. T he
reduction in broadband noise is given by:
From this, the following equation can be developed which gives
the maximum allowable source resistance, RS(MAX), for an error
of VE:
62
eOUT = eIN 2 fC / f S = 0.035 eIN
RS (MAX )
=
fCLKIN ×(10 pF ) × ln (100mV /VE )
where:
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. T hese
can be calibrated in system calibration schemes.
elN and eOUT are rms noise terms referred to the input
fC
is the filter –3 dB corner frequency
(fCLKIN/409600)
and
If a limit of 10 µV (0.25 LSB at 16 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
160 kΩ from the above equation, assuming that there is no
external stray capacitance.
fS
is the sampling frequency (fCLKIN/256).
Since the ratio of fS to fCLKIN is fixed, the digital filter reduces
broadband white noise by 96.5% independent of the master
clock frequency.
–10–
REV. D
AD7701
VO LTAGE REFERENCE CO NNECTIO NS
GRO UND ING AND SUP P LY D ECO UP LING
T he voltage applied to the VREF pin defines the analog input
range. T he specified reference voltage is 2.5 V, but the AD7701
will operate with reference voltages from 1 V to 3 V with little
degradation in performance.
AGND is the ground reference voltage for the AD7701, and is
completely independent of DGND. Any noise riding on the
AGND input with respect to the system analog ground will
cause conversion errors. AGND should therefore be used as the
system ground and also as the ground for the analog input and
the reference voltage.
T he reference input presents exactly the same dynamic load as
the analog input, but in the case of the reference input, source
resistance and long settling time introduce gain errors rather
than offset errors. Fortunately, most precision references have
sufficiently low output impedance and wide enough bandwidth
to settle to 10 µV within 62 clock cycles.
T he analog and digital power supplies to the AD7701 are
independent and separately pinned out, to minimize coupling
between analog and digital sections of the device. T he digital
filter will provide rejections of broadband noise on the power
supplies, except at integer multiples of the sampling frequency.
T herefore, the two analog supplies should be decoupled to
AGND using 100 nF ceramic capacitors to provide power
supply noise rejections at these frequencies. T he two digital
supplies should similarly be decoupled to DGND.
AVDD
+5V
LT1019
AD7701
VREF
ACCURACY AND AUTO CALIBRATIO N
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no-missing-codes performance. T he AD7701 achieves excellent
linearity (±0.0007%) by the use of high quality, on-chip silicon
dioxide capacitors, which have a very low capacitance/voltage
coefficient.
AGND
Figure 14. Typical External Reference Connections
T he digital filter of the AD7701 removes noise from the
reference input, just as it does with noise at the analog input,
and the same limitations apply regarding lack of noise rejection
at integer multiples of the sampling frequency. If reference noise
is a problem, some voltage references offer noise reduction
schemes using an external capacitor. Alternatively, a simple RC
filter may be used, as shown in Figure 15.
T he AD7701 offers two self-calibration modes using the on-chip
calibration microcontroller and SRAM. T able III is a truth table
for the calibration control inputs SC1 and SC2.
In the self-calibration mode, zero-scale is calibrated against the
AGND pin and full scale is calibrated against the VREF pin, to
remove internal errors.
AVDD
Note that in the bipolar mode the AD7701 calibrates positive
full scale and midscale (bipolar zero).
+5V
AD580
AD7701
RF
13kΩ
In the system-calibration mode, the AD7701 calibrates its zero
and full scale to voltages present on the analog input pin in two
sequential steps. T his allows system offsets and/or gain errors to
be nulled out.
VREF
CF
100pF
AGND
MICRO
AD7701
COMPUTER
SYSTEM
REF HI
SCLK
Figure 15. Filtered Reference Input
SDATA
CAL
T he same considerations apply to this filter as to a filter at the
analog input. In this case:
ANALOG
MUX
SIGNAL
CONDITIONING
AIN
SC1
SYSTEM
REF LO
SC2
A1
A0
62
[RF (CF +10 pF )]=
100 mV ×CIN (CIN +CF )
fCLKIN ×ln
VFSE
Figure 16. Typical Connections for System Calibration
where:
A typical system calibration scheme is shown in Figure 16. In
normal operation the analog signal is fed to the AD7701 via an
analog multiplexer. When the system is to be calibrated, AIN is
first switched to the system REF LO via the multiplexer and
CAL is strobed high, with SC1 and SC2 both high. AIN is then
switched to the system REF HI and CAL is strobed, with SC1
low and SC2 high. In this way, the effect of all error sources
fCLKIN is the master clock frequency
and
VFSE is the maximum desired error in volts.
REV. D
–11–
AD7701
Table III. Calibration Truth Table
CAL
SC1 SC2 CAL TYP E
ZERO REFERENCE FS REFERENCE
SEQUENCE
CALIBRATIO N TIME
0
1
0
1
0
1
1
0
Self-Cal
AGND
AIN
–
VREF
–
AIN
VREF
One Step
1st Step
2nd Step
One Step
3,145,655 Clock Cycles
1,052,599 Clock Cycles
1,068,813 Clock Cycles
2,117,389 Clock Cycles
System Offset
System Gain
System Offset
AIN
NOT E
DRDY remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7701 has settled to the analog input. In all other modes
DRDY falls as the device begins to settle.
between the multiplexer and the AD7701 is removed. Op amps
and other signal conditioning circuits may be used in front of
the AD7701, without worrying about their absolute gain or
offset errors. Note that the absolute value of the reference
supplied to the AD7701 is no longer important, provided it has
adequate short-term stability between calibration cycles, as full
scale is calibrated to the system reference.
T he type of calibration cycle initiated by CAL is determined by
the SC1 and SC2 inputs, in accordance with T able III.
T he power dissipation and temperature drift of the AD7701 are
low and no warm-up time is required before the initial calibra-
tion is performed. However, the system reference must have
stabilized before calibration is initiated.
If system offset errors are important but system gain errors are
not, then a one step system calibration may be performed with
SC1 high and SC2 low. In this case, offset is calibrated against
P O WER SUP P LY SEQ UENCING
T he positive digital supply (DVDD) must never exceed the
positive analog supply (AVDD) by more than 0.3 V. Power
supply sequencing is therefore important. If separate analog and
digital supplies are used, care must be taken to ensure that the
analog supply is powered up first.
AIN, which should be connected to system REF LO during
calibration, but full scale is calibrated against the AD7701’s
VREF input.
System calibration schemes will yield better accuracy than self-
calibration, even if there are no system errors. Using self-
calibration, errors arise due to the mismatch in source impedances
It is also important that power is applied to the AD7701 before
signals at VREF, AIN or the logic input pins in order to avoid any
possibility of latch-up. If separate supplies are used for the
AD7701 and the system digital circuitry, then the AD7701
should be powered up first.
between the references during calibration (AGND and VREF
)
and the analog input during normal operation. In system cali-
bration, the source impedances inherently remain identical,
such that the theoretical limit to system accuracy is calibration
resolution. T he practical limit is the noise floor of the AD7701.
A typical scheme for powering the AD7701 from a single set of
±5 V rails is shown in the system connection diagram, Figure 7.
In this circuit AVDD and DVDD are brought along separate
tracks from the same +5 V supply. T hus, there is no possibility
of the digital supply coming up before the analog supply.
Note that in system calibration, “REF LO” does not necessarily
mean the system ground or zero volts. T he AD7701 can be
calibrated to measure between any two voltages that lie within
its calibration range by deliberately making REF LO nonzero.
For example, if REF LO is +0.5 V and REF HI is +2.5 V, the
unipolar span will be between these limits.
GRO UND ING
T he AD7701 uses the analog ground connection, AGND, as the
measurement reference node. It should be used as the reference
node for both the analog input signal and the reference voltage
at the VREF pin.
CALIBRATIO N RANGE
When designing system calibration schemes, care must be taken
to ensure that the worst-case system errors do not cause the
overrange headroom of the AD7701 to be exceeded. Although
the measurement error caused by offset and gain errors can be
nulled out, the actual error voltages will still be present at the
analog input and can cause overloading of the analog modulator
or overflow of the digital filter. With a 2.5 V reference, the
maximum input voltage is (+VREF + 100 mV), and the minimum
input voltage is (–VREF – 100 mV).
T he analog and digital power supplies to the AD7701 die are
pinned out separately to minimize coupling between the analog
and digital sections of the chip. All four supplies should be
decoupled separately to their respective grounds as shown in
Figure 7. T he on-chip digital filtering of the AD7701 further
enhances power supply rejection by attenuating noise injected
into the conversion process.
SINGLE SUP P LY O P ERATIO N
Figure 17 shows a circuit to power the AD7701 from a single
+10 V supply, using an op amp to provide a half supply refer-
ence point for AGND and DGND. As the digital I/O pins are
referenced to this point, level shifting is required for external
digital communications. If galvanic isolation is required in the
system, level shifting and isolation can both be provided by
opto-isolators.
P O WER-UP AND CALIBRATIO N
A calibration cycle must be carried out after power-up to initial-
ize the device to a consistent starting condition and correct cali-
bration. T he CAL pin must be held high for at least four clock
cycles, after which calibration is initiated on the falling edge of
CAL and takes a maximum of 3,145,655 clock cycles (approxi-
mately 768 ms, with a 4.096 MHz clock). See T able III.
–12–
REV. D
AD7701
SYNCH RO NO US SELF-CLO CKING MO D E (SSC)
0.1µF
T he SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. T his mode allows interfacing to 74XX299
Universal Shift registers without any additional decoding. T he
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
0.1µF
AVDD
VREF
DVDD
10kΩ
REF
AD7701
DGND
AD707
10V ± 1V
AGND
AVSS
Figure 18 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. T he AD7701
divides each sampling interval into sixteen distinct periods.
Eight periods of 64 clock pulses are for analog settling and eight
periods of 64 clock pulses are for digital computation. T he
status of CS is polled at the beginning of each digital computation
period. If it is low at any of these times then SCLK will become
active and the data word currently in the output register will be
transmitted, MSB first. After the LSB has been transmitted
DRDY goes high and SDAT A goes three-state. If CS, having
been brought low, is taken high again at any time during data
transmission, SDAT A and SCLK will go three-state after the
current bit finishes. If CS is subsequently brought low,
DVSS
10kΩ
0.1µF
0.1µF
Figure 17. Single Supply Operation
SLEEP MO D E
T he low power standby mode is initiated by taking the SLEEP
input low, which shuts down all analog and digital circuits and
reduces power consumption to 10 µW. T he calibration coeffi-
cients are still retained in memory, but as the converter has been
quiescent, it is necessary to wait for the filter settling time
(507,904 cycles) before accessing the output data.
transmission will resume with the next bit during the sub-
sequent digital computation period. If transmission has not been
initiated and completed by the time the next data word is
available, DRDY will go high for four clock cycles then low
again as the new word is loaded into the output register.
D IGITAL INTERFACE
T he AD7701’s serial communications port allows easy inter-
facing to industry-standard microprocessors. T hree different
modes of operations are available, optimized for different types
of interface.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 19. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.
1024 CLKIN CYCLES
64 CLKIN CYCLES
ANALOG SETTLING
64 CLKIN CYCLES
INTERNAL
STATUS
DIGITAL COMPUTATION
DIGITAL COMPUTATION
72 CLKIN CYCLES
DRDY (O)
CS POLLED
CS (I)
HI-Z
HI-Z
HI-Z
HI-Z
SCLK (O)
MSB
LSB
SDATA (O)
Figure 18. Tim ing Diagram for SSC Data Transm ission Mode
REV. D
–13–
AD7701
If CS is taken high at any time during data transmission,
SDAT A and SCLK will go three-state immediately. If CS re-
turns low, the AD7701 will continue transmission with the same
data bit. If transmission has not been initiated and completed by
the time the next data word becomes available, and if CS is
high, DRDY will return high for four clock cycles, then fall as
the new word is loaded into the output register.
SYNCH RO NO US EXTERNAL CLO CK MO D E (SEC)
T he SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry-standard
microprocessors such as the COPS series, 68HC11 and
68HC05. T he SEC mode also allows customized interfaces,
using I/O port pins, to microprocessors that do not have a direct
fit with the AD7701’s other modes.
As shown in Figure 20, a falling edge on CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK.
After the LSB has been transmitted, DRDY goes high and
SDAT A goes three-state. If CS is low and the AD7701 is still
transmitting data when a new data word becomes available, the
old data word continues to be transmitted and the new data is
lost.
CLKIN (I)
72 CLKIN
CYCLES
DRDY (O)
CS (I)
HI-Z
HI-Z
SDATA (O)
SCLK (O)
DB15 (MSB)
DB14
DB0 (LSB)
DB2
DB1
HI-Z
HI-Z
Figure 19. SSC Mode Showing Data Tim ing Relative to SCLK
DRDY (O)
CS (I)
SCLK (I)
HI-Z
HI-Z
DB0
(LSB)
DB15
(MSB)
SDATA (O)
DB14
DB13
DB1
Figure 20. Tim ing Diagram for the SEC Mode
–14–
REV. D
AD7701
ASYNCH RO NO US CO MMUNICATIO NS (AC) MO D E
T he AC mode (MODE pin tied to –5 V) offers a UART -
compatible interface which allows the AD7701 to transmit data
asynchronously from remote locations. An external SCLK sets
the baud rate and data is transmitted in two bytes in UART -
compatible format. Using the AC mode, the AD7701 can be
interfaced direct to microprocessors with UART interfaces, such
as the 8051 and T MS70X2.
D IGITAL NO ISE AND O UTP UT LO AD ING
As mentioned earlier, the AD7701 divides its internal timing
into two distinct phases, analog sampling and settling and digital
computation. In the SSC mode, data is transmitted only during
the digital computation periods, to minimize the effects of
digital noise on analog performance. In the SEC and AC modes
data transmission is externally controlled, so this automatic
safeguard does not exist.
Data transmission is initiated by CS going low. If CS is low on a
falling edge of SCLK, the AD7701 begins transmitting an 8-bit
data byte (DB8–DB15) with one start bit and two stop bits, as
in Figure 21. T he SDAT A output will then go three-state. T he
second byte is transmitted by bringing CS low again and DB0 to
DB7 are transmitted in the same format as the first byte.
Whatever mode of operation is used, resistive and capacitive
loads on digital outputs should be minimized in order to reduce
crosstalk between analog and digital portions of the circuit. For
this reason connection to low-power CMOS logic such as one of
the 4000 series or 74C families is recommended.
It is especially important to minimize the load on SDAT A in the
AC mode, as transmission in this mode is inherently asynchro-
nous. In the SEC mode the AD7701 should be synchronized to
the digital system clock via CLKIN.
UART baud rates are typically low compared to the AD7701’s
4 kHz output update rate. If CS is low and data is still being
transmitted when a new data word becomes available, the new
data will be ignored. However, if CS has been taken high
between bytes, when a new data word becomes available, the
AD7701 could update the output register before the second byte
is transmitted. In this case, the UART would receive the first
byte of the new word instead of the second byte of the old word.
When using the AC mode, care must obviously be taken to
ensure that this does not occur.
SCLK (I)
DRDY (O)
CS (I)
HI-Z
START
BIT
STOP
STOP
START
BIT
STOP STOP
BIT BIT
DB14 DB15
DB6
DB8
DB9
SDATA (O)
DB0
DB1
DB7
BIT
BIT
Figure 21. Tim ing Diagram for Asynchronous Com m unications Mode
REV. D
–15–
AD7701
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-P in P lastic D IP (N-20)
20-Lead SO IC (R-20)
20
11
0.280 (7.11)
0.240 (6.10)
10
20
11
PIN 1
1
0.2992 (7.60)
0.2914 (7.40)
1.060 (26.90)
0.925 (23.50)
0.325 (8.25)
0.300 (7.62)
0.4193 (10.65)
0.3937 (10.00)
10
0.060 (1.52)
0.015 (0.38)
1
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.1043 (2.65)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.5118 (13.00)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.4961 (12.60)
x 45
°
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
20-P in Cer dip (Q -20)
28-Lead SSO P
(RS-28)
0.005 (0.13) MIN
0.098 (2.49) MAX
0.407 (10.34)
20
0.397 (10.08)
11
0.310 (7.87)
PIN 1
0.220 (5.59)
1
10
28
15
14
0.320 (8.13)
1.060 (26.92) MAX
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
1
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
°
0.07 (1.79)
0.078 (1.98)
0.068 (1.73)
PIN 1
0
°
0.100
(2.54)
BSC
0.066 (1.67)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–16–
REV. D
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