AD7703BRZ_技术文档

2

LC MOS

20-Bit A/D Converter

a

AD7703

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

Monolithic 20-Bit ADC

0.0003% Linearity Error

AV_SS

DV_SS

SC1

SC2

17

20-Bit No Missed Codes

On-Chip Self-Calibration Circuitry

Program m able Low -Pass Filter

0.1 Hz to 10 Hz Corner Frequency

0 to +2.5 V or +2.5 V Analog Input Range

4 kSPS Output Data Rate

Flexible Serial Interface

Ultralow Pow er

7

6

4

AD7703

15

14

DV_DD

AV_DD

CALIBRATION

MICROCONTROLLER

CALIBRATION

SRAM

13

CAL

20-BIT CHARGE BALANCE A/D

CONVERTER

A_IN

9

12

11

BP/UP

SLEEP

6-POLE GAUSSIAN

ANALOG

MODULATOR

V_REF

10

LOW-PASS

DIGITAL FILTER

APPLICATIONS

Industrial Process Control

Weigh Scales

Portable Instrum entation

Rem ote Data Acquisition

AGND

DGND

8

5

20 SDATA

19

CLOCK

SERIAL INTERFACE

GENERATOR

LOGIC

SCLK

3

2

1

16

18

MODE

CLKIN CLKOUT

CS

DRDY

GENERAL D ESCRIP TIO N

P RO D UCT H IGH LIGH TS

T he AD7703 is a 20-bit ADC which uses a sigma delta conver-

sion technique. T he analog input is continuously sampled by an

analog modulator whose mean output duty cycle is proportional

to the input signal. T he modulator output is processed by an

on-chip digital filter with a six-pole Gaussian response, which

updates the output data register with 20-bit binary words at

word rates up to 4 kHz. T he sampling rate, filter corner fre-

quency and output word rate are set by a master clock input

that may be supplied externally, or by an on-chip gate oscillator.

1. T he AD7703 offers 20-bit resolution coupled with

outstanding 0.0003% accuracy.

2. No missing codes ensures true, usable, 20-bit dynamic range,

removing the need for programmable gain and level-setting

circuitry.

3. T he effects of temperature drift are eliminated by on-chip

self-calibration, which removes zero and gain error. External

circuits can also be included in the calibration loop to remove

system offsets and gain errors.

T he inherent linearity of the ADC is excellent, and endpoint

accuracy is ensured by self-calibration of zero and full scale

which may be initiated at any time. T he self-calibration scheme

can also be extended to null system offset and gain errors in the

input channel.

4. A flexible synchronization allows the AD7703 to interface

directly to the serial ports of industry standard

microcontrollers and DSP processors.

5. Low operating power consumption and an ultralow power

standby mode make the AD7703 ideal for loop powered

remote sensing applications, or battery-powered portable

instruments.

T he output data is accessed through a serial port, which has two

synchronous modes suitable for interfacing to shift registers or

the serial ports of industry standard microcontrollers.

CMOS construction ensures low power dissipation, and a power

down mode reduces the idle power consumption to only 10 ␮W.

REV. D

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

(T = +25؇C; AV = DV = +5 V; AV = DV = –5 V; V = +2.5 V; f_CLKIN= 4.096 MHz;

AD7703–SPECIFICATIONS

A

DD

SS

REF

BP/UP = +5 V; MODE = +5 V; A Source Resistance = 1 k⍀¹with 1 nF to AGND at A unless otherwise noted.)

IN

P aram eter

A/S Versions²

B Version ²

C Version²

Units

Test Conditions/Com m ents

ST AT IC PERFORMANCE

Resolution

20

Bits

Integral Nonlinearity, T _MINto T _MAX

+25°C

T _MINto T _MAX

±0.0015

±0.003

±0.0007

±0.0015

±0.5

±4

±0.0003

±0.0008

±0.0012

±0.5

±4

% FSR typ

% FSR max

LSB typ

Differential Nonlinearity, T_MINto T_MAX± 0.5

Guaranteed No Missing Codes

Positive Full-Scale Error³

±4

LSB typ

±16

±19/±37

±4

±16

±19

±4

±16

±19

±4

LSB max

LSB typ

Full-Scale Drift⁴

Unipolar Offset Error³

±16

±26

±67 +48/–400

±4

±16

±26

±67

±4

±16

±26

±67

±4

LSB max

LSB typ

Unipolar Offset Drift⁴

Bipolar Zero Error³

T emp Range: 0°C to +70°C

Specified T emp Range

LSB typ

±16

±13

±34 +24/–200

±8

±16

±13

±34

±8

±16

±13

±34

±8

LSB max

LSB typ

Bipolar Zero Drift⁴

T emp Range: 0°C to +70°C

Specified T emp Range

Bipolar Negative Full-Scale Errors³

LSB typ

±32

±10/±20

1.6

±32

±10

1.6

±32

±10

1.6

LSB max

LSB typ

LSB rms typ

Bipolar Negative Full-Scale Drift⁴

Noise (Referred to Output)

DYNAMIC PERFORMANCE

Sampling Frequency, f_S

Output Update Rate, f_OUT

Filter Corner Frequency, f_{–3 dB}

Settling T ime to ±0.0007% FS

f_CLKIN/256

Hz

sec

f_CLKIN/1024

f_CLKIN/409,600

507904/f_CLKIN

f_CLKIN/1024

f_CLKIN/409,600

507904/f_CLKIN

f_CLKIN/1024

f_CLKIN/409,600

507904/f_CLKIN

For Full-Scale Input Step

SYST EM CALIBRAT ION

Positive Full-Scale Calibration Range

Positive Full-Scale Overrange

V_REF+ 0.1

V max

System Calibration Applies to

Unipolar and Bipolar Ranges.

Negative Full-Scale Overrange

Maximum Offset Calibration Ranges^{5, 6}

Unipolar Input Range

–(V_REF+ 0.1)

V max

After Calibration, if A_IN> V_REF

the Device Will Output All 1s.

If A_IN< 0 (Unipolar) or –V_REF

(Bipolar), the Device Will

Output all 0s

,

Bipolar Input Range

–0.4 V_REFto +0.4 V_REF–0.4 V_REFto +0.4 V_REF–0.4 V_REFto +0.4 V_REFV max

0.8 V_REF

2 V_REF+ 0.2

Input Span⁷

0.8 V_REF

2 V_REF+ 0.2

0.8 V_REF

2 V_REF+ 0.2

V min

V max

ANALOG INPUT

Unipolar Input Range

Bipolar Input Range

Input Capacitance

Input Bias Current¹

0 to +2.5

±2.5

20

0 to +2.5

±2.5

20

0 to +2.5

±2.5

20

Volts

pF typ

nA typ

1

LOGIC INPUT S

All Inputs except CLKIN

V_INL, Input Low Voltage

V_INH, Input High Voltage

CLKIN

0.8

2.0

0.8

2.0

0.8

2.0

V max

V min

V

_INL, Input Low Voltage

0.8

3.5

10

0.8

3.5

10

0.8

3.5

10

V max

V min

µA max

V_INH, Input High Voltage

I_IN, Input Current

LOGIC OUT PUT S

V_OL, Output Low Voltage

V_OH, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance

0.4

DV_DD–1

±10

9

0.4

DV_DD–1

±10

9

0.4

DV_DD–1

±10

9

V max

V min

µA max

pF typ

I_SINK= 1.6 mA

I_SOURCE= 100 µA

POWER REQUIREMENT S

Power Supply Voltages

Analog Positive Supply (AV_DD

Digital Positive Supply (DV_DD

Analog Negative Supply (AV_SS

Digital Negative Supply (DV_SS

Calibration Memory Retention

Power Supply Voltage

)

4.5/5.5

V min/V max For Specified Performance

V min/V max

4.5/AV_DD

–4.5/–5.5

4.5/AV_DD

–4.5/–5.5

4.5/AV_DD

–4.5/–5.5

V min/V max

2.0

V min

–2–

REV. D

AD7703

P aram eter

A/S Versions²

B Version²

C Version²

Units

Test Conditions/Com m ents

ST AT IC PERFORMANCE

DC Power Supply Currents⁸

Analog Positive Supply (AI_DD

Digital Positive Supply (DI_DD

Analog Negative Supply (AI_SS

Digital Negative Supply (DI_SS

Power Supply Rejection⁹

Positive Supplies

)

3.2

1.5

3.2

0.1

3.2

1.5

3.2

0.1

3.2

1.5

3.2

0.1

mA max

T ypically 2 mA

T ypically 1 mA

T ypically 2 mA

T ypically 0.03 mA

70

75

70

75

70

75

dB typ

Negative Supplies

Power Dissipation

Normal Operation

40

mW rnax

SLEEP = Logic 1,

T ypically 25 mW

SLEEP = Logic 0,

T ypically 10 µW

Standby Operations¹⁰

A, B, C

S

20

40

20

40

20

40

µW max

NOT ES

¹T he A_INpin presents a very high impedance dynamic load which varies with clock frequency. A ceramic 1 nF capacitor from the A _INto AGND is necessary. Source

resistance should be 750 Ω or less.

²T emperature Ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.

³Applies after calibration at the temperature of interest. Full-Scale Error applies for both unipolar and bipolar input ranges.

⁴T otal drift over the specified temperature range after calibration at power-up at +25 °C. T his is guaranteed by design and/or characterization. Recalibration at any

temperature will remove these errors.

⁵In unipolar mode the offset can have a negative value (–V_REF) such that the unipolar mode can mimic bipolar mode operation.

⁶T he specifications for input overrange and for input span apply additional constraints on the offset calibration range.

⁷For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative

full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V_REF+ 0.1).

⁸All digital outputs unloaded. All digital inputs at 5 V CMOS levels.

⁹Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.

¹⁰CLKIN is stopped. All digital inputs are grounded.

Specifications subject to change without notice.

ABSO LUTE MAXIMUM RATINGS*

(T _A= +25°C unless otherwise noted)

O RD ERING GUID E

Linearity

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV_DDto AV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DV_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

AV_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Analog Input Voltage to AGND . . . . . . . . . . . AV_SS– 0.3 V to

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies¹. . . . . . . . ±10 mA

Operating T emperature Range

Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (DIP Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

Power Dissipation (SOIC Package) to +75°C . . . . . . 250 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 15 mW/°C

Tem perature

Range

Error

(% FSR)

P ackage

O ptions*

Model

AD7703AN

AD7703BN

AD7703CN

AD7703AR

AD7703BR

AD7703CR

AD7703AQ

AD7703BQ

AD7703CQ

AD7703SQ

–40°C to +85°C

–55°C to +125°C

0.003

N-20

R-20

Q-20

0.0015

0.0012

0.003

0.0015

0.0012

0.003

0.0015

0.0012

0.003

*N = Plastic DIP; R = SOIC; Q = Cerdip.

NOT ES

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

¹T ransient currents of up to 100 mA will not cause SCR latch-up.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although this device features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. D

–3–

AD7703

TIMING CHARACTERISTICS

(AV = DV = +5 V ؎ 10%; AV = DV = –5 V ؎ 10%; AGND = DGND = 0 V; f_CLKIN

=

1, 2

DD

SS

4.096 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV ; unless otherwise noted.)

DD

Lim it at T_MIN, T_MAXLim it at T_MIN, T_MAX

P aram eter

(A, B, C Versions)

(S Version)

Units

Conditions/Com m ent⁶

Master Clock Frequency: Internal Gate Oscillator

3, 4

f_CLKIN

200

5

200

5

kHz min

MHz max T ypically 4096 kHz

200

5

50

0

200

5

50

0

kHz min

MHz max

ns max

ns min

Master Clock Frequency: Externally Supplied

5

t_r

Digital Output Rise T ime. T ypically 20 ns

Digital Output Fall T ime. T ypically 20 ns

SC1, SC2 to CAL High Setup T ime

t_f⁵

t₁

t₂₆

50

1000

50

1000

ns min

SC1, SC2 Hold T ime After CAL Goes High

SLEEP High to CLKIN High Setup T ime

t₃

SSC MODE

7

t₄

3/f_CLKIN

100

250

300

790

3/f_CLKIN

100

250

300

790

ns max

ns min

ns max

Data Access T ime (CS Low to Data Valid)

SCLK Falling Edge to Data Valid Delay (25 ns typ)

MSB Data Setup T ime. T ypically 380 ns

SCLK High Pulse Width. T ypically 240 ns

SCLK Low Pulse Width. T ypically 730 ns

SCLK Rising Edge to Hi-Z Delay (1/f_CLKIN+ 100 ns typ)

CS High to Hi-Z Delay

t₅

t₆

t₇

t₈

t₉

l/f_CLKIN+ 200

4/f_CLKIN+ 200

l/f_CLKIN+ 200

4/f_CLKIN+ 200

8, 9

t₁₀

SEC MODE

f_SCLK

t₁₁

5

35

5

35

MHz max Serial Clock Input Frequency

ns min

ns max

SCLK High Pulse Width

SCLK Low Pulse Width

Data Access Time (CS Low to Data Valid). Typically 80 ns

SCLK Falling Edge to Data Valid Delay. Typically 75 ns

CS High to Hi-Z Delay

t₁₂

t₁₃

t₁₄

t₁₅

160

150

250

200

160

150

250

200

7, 10

11

8

t₁₆

SCLK Falling Edge to Hi-Z Delay. T ypically 100 ns

NOT ES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

²See Figures 1 to 6.

³CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device can

draw higher current than specified and possibly become uncalibrated.

⁴T he AD7703 is production tested with f_CLKINat 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.

⁵Specified using 10% and 90% points on waveform of interest.

⁶In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.

⁷t₄and t₁₃are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

⁸t₉, t₁₀, t₁₅and t₁₆are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is

then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. T his means that the tune quoted in the T iming Characteristics is the

true bus relinquish time of the part and as such is independent of external bus loading capacitances.

⁹If CS is returned high before all 20 bits are output, the SDAT A and SCLK outputs will complete the current data bit and then go to high impedance.

¹⁰If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. T he propagation delay time may be as

great as 4 CLKIN cycles plus 160 ns. T o guarantee proper clocking of SDAT A when using asynchronous CS, the SCLK input should not be taken high sooner than

4 CLKIN cycles plus 160 ns after CS goes low.

¹¹SDAT A is clocked out on the falling edge of the SCLK input.

CAL

I

OL

1.6mA

t₂

SC1,SC2 VALID

t₁

TO

OUTPUT

SC1, SC2

+2.1V

C

L

100pF

Figure 2. Calibration Control Tim ing

I

OH

200µA

CLKIN

t₃

Figure 1. Load Circuit for Access Tim e and Bus Relinquish

Tim e

SLEEP

Figure 3. Sleep Mode Tim ing

–4–

REV. D

AD7703

CS

t₁₅

t₁₀

HI-Z

DATA

VALID

DATA

VALID

SDATA

Figure 4. SSC Mode Data Hold Tim e

Figure 5a. SEC Mode Data Hold Tim e

CLKIN

CS

DRDY

CS

t₇

t₁₂

t₈

t₁₁

HI-Z

SCLK

t₉

t₄

t₁₃

t₈

t₁₆

DB0

t₁₄

DB18

t₅

HI-Z

DB19

SDATA

DB1

HI-Z

DB19

SDATA

DB18

DB1

DB0

Figure 6. SSC Mode Tim ing Diagram

Figure 5b. SEC Mode Tim ing Diagram

P O SITIVE FULL-SCALE O VERRANGE

TERMINO LO GY

LINEARITY ERRO R

Positive full-scale overrange is the amount of overhead available

to handle input voltages greater than +V_REF(for example, noise

peaks or excess voltages due to system gain errors in system cali-

bration routines) without introducing errors due to overloading

the analog modulator or overflowing the digital filter.

T his is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. T he end-

points of the transfer function are zero-scale (not to be confused

with bipolar zero), a point 0.5 LSB below the first code transi-

tion (000 . . . 000 to 000 . . . 001) and full scale, a point 1.5 LSB

above the last code transition (111 . . . 110 to 111 . . . 111).

T he error is expressed as a percentage of full scale.

NEGATIVE FULL-SCALE O VERRANGE

T his is the amount of overhead available to handle voltages be-

low –V_REFwithout overloading the analog modulator or over-

flowing the digital filter. Note that the analog input will accept

negative voltage peaks even in the unipolar mode.

D IFFERENTIAL LINEARITY ERRO R

T his is the difference between any code’s actual width and the

ideal (1 LSB) width. Differential linearity error is expressed in

LSBs. A differential linearity specification of ±1 LSB or less

guarantees monotonicity.

O FFSET CALIBRATIO N RANGE

In the system calibration modes (SC2 Low) the AD7703 cali-

brates its offset with respect to the A_INpin. T he offset calibra-

tion range specification defines the range of voltages that the

AD7701 can accept and still calibrate offset accurately.

P O SITIVE FULL-SCALE ERRO R

Positive full-scale error is the deviation of the last code transition

(111 . . . 110 to 111 . . . 111) from the ideal (V_REF–3/2 LSBs).

It applies to both positive and negative analog input ranges.

FULL-SCALE CALIBRATIO N RANGE

T his is the range of voltages that the AD7703 can accept in the

system calibration mode and still calibrate full scale correctly.

UNIP O LAR O FFSET ERRO R

Unipolar offset error is the deviation of the first code transition

from the ideal (AGND + 0.5 LSB) when operating in the uni-

polar mode.

INP UT SP AN

In system calibration schemes, two voltages applied in sequence

to the AD7703’s analog input define the analog input range.

T he input span specification defines the minimum and maxi-

mum input voltages from zero to full scale that the AD7703 can

accept and still calibrate gain accurately.

BIP O LAR ZERO ERRO R

T his is the deviation of the midscale transition (0111 . . . 111 to

1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operat-

ing in the bipolar mode.

BIP O LAR NEGATIVE FULL-SCALE ERRO R

T his is the deviation of the first code transition from the ideal

(–V_REF+ 0.5 LSB), when operating in the bipolar mode.

REV. D

–5–

AD7703

P IN FUNCTIO N D ESCRIP TIO N

P in

Mnem onic D escription

1

MODE

Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)

mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB com-

ing first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.

SCLK is configured as an output, with a clock frequency for f_CLKIN/4 and 25% duty cycle.

2

CLKOUT

Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.

If an external clock is used, CLKOUT is not connected.

3

CLKIN

Clock Input for External Clock.

4, 17

SC1, SC2

System Calibration Pins. T he state of these pins, when CAL is taken high, determines the type of calibration

performed.

5

DGND

DV_SS

AV_SS

AGND

A_IN

Digital Ground. Ground reference for all digital signals.

Digital Negative Supply, –5 V nominal.

Analog Negative Supply, –5 V nominal.

Analog Ground. Ground reference for all analog signals.

Analog Input.

6

7

8

9

10

V_REF

Voltage Reference Input, +2.5 V nominal. T his determines the value of positive full-scale in the unipolar

mode and of both positive and negative full-scale in the Bipolar Mode.

11

12

13

SLEEP

BP/UP

CAL

Sleep mode pin. When this pin is taken low, the AD7703 goes into a low-power mode with typically 10 µW

power consumption.

Bipolar/Unipolar mode pin. When this pin is Low, the AD7703 is configured for a unipolar input range going

from AGND to V_REF. When Pin 12 is High, the AD7703 is configured for a bipolar input range, ±V_REF

.

Calibration mode pin. When CAL is taken High for more than 4 cycles, the AD7703 is reset and performs a

calibration cycle when CAL is brought Low again. T he CAL pin can also be used as a strobe to synchronize

the operation of several AD7703s.

14

15

16

AV_DD

DV_DD

CS

Analog Positive Supply, +5 V nominal.

Digital Positive Supply, +5 V nominal.

Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format deter-

mined by the state of the MODE pin.

18

DRDY

Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans-

mission of a word is completed. It also goes high for four clock cycles when a new data word is being loaded

into the output register, to indicate that valid data is not available, irrespective of whether data transmission is

complete or not.

19

20

SCLK

Serial Clock Input/Output. T he SCLK pin in configured as an input or output, dependent on the type of se-

rial data transmission that has been selected by the MODE pin. When configured as an output in the Syn-

chronous Self-Clocking mode, it has a frequency of f_CLKIN/4 and a duty cycle of 25%.

SDAT A

Serial Data Output. T he AD7703’s output data is available at this pin as a 20-bit serial word.

Table I. Bit Weight Table (2.5 V Reference Voltage)

P IN CO NFIGURATIO N

D IP , Cer dip, SO IC

UNIP O LAR MO D E

LSBs % FS ppm FS LSBs % FS

BIP O LAR MO D E

ppm FS

␮V

20

1

2

MODE

SDATA

19 SCLK

CLKOUT

0.596

1.192

2.384

4.768

9.537

0.25

0.5

1.00

2.00

4.00

0.0000238 0.24

0.13

0.26

0.5

1.00

2.00

0.0000119

0.0000238

0.0000477

0.0000954

0.0001907

0.12

0.24

0.48

0.95

1.91

3

18

17

16

15

DRDY

SC2

CLKIN

SC1

0.0000477 0.48

0.0000954 0.95

0.0001907 1.91

0.0003814 3.81

4

AD7703

TOP VIEW

5

CS

DGND

DV_SS

AV_SS

6

DV_DD

(Not to Scale)

14 AV_DD

7

13

8

CAL

AGND

A_IN

12

9

BP/UP

11

V_REF

10

SLEEP

–6–

REV. D

AD7703

GENERAL D ESCRIP TIO N

TH EO RY O F O P ERATIO N

T he AD7703 is a 20-bit A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low frequency signals such as those representing chemical,

physical or biological processes. It contains a charge-balancing

(sigma-delta) ADC, calibration microcontroller with on-chip

static RAM, a clock oscillator and a serial communications port.

T he general block diagram of a sigma-delta ADC is shown in

Figure 8. It contains the following elements:

1. A sample-hold amplifier

2. A differential amplifier or subtracter

3. An analog low-pass filter

4. A 1-bit A/D converter (comparator)

5. A 1-bit DAC

T he analog input signal to the AD7703 is continuously sampled

at a rate determined by the frequency of the master clock,

CLKIN. A charge-balancing A/D converter (sigma-delta modu-

lator) converts the sampled signal into a digital pulse train

whose duty cycle contains the digital information. A six-pole

Gaussian digital low-pass filter processes the output of the

sigma-delta modulator and updates the 20-bit output register at

a 4 kHz rate. T he output data can be read from the serial port

randomly or periodically at any rate up to 4 kHz.

6. A digital low-pass filter

S/H AMP

COMPARATOR

ANALOG

LOW-PASS

DIGITAL

FILTER

DIGITAL DATA

DAC

+5V

ANALOG

SUPPLY

AV

DV

DD

0.1µF

10µF

SLEEP

MODE

Figure 8. General Sigm a-Delta ADC

DATA

DRDY

CS

2.5V

READY

VOLTAGE

REFERENCE

V

REF

READ

(TRANSMIT)

In operation, the sampled analog signal is fed to the subtracter,

along with the output of the 1-bit DAC. T he filtered difference

signal is fed to the comparator, whose output samples the

difference signal at a frequency many times that of the analog

signal frequency (oversampling).

AD7703

SERIAL

CLOCK

SCLK

RANGE

SELECT

BP/UP

CAL

SERIAL

DATA

SDATA

CALIBRATE

CLKIN

ANALOG

INPUT

A

CLKOUT

IN

Oversampling is fundamental to the operation of sigma-delta

ADCs. Using the quantization noise formula for an ADC:

SC1

SC2

ANALOG

GROUND

AGND

DGND

0.1µF

SNR =(6.02 × number of bits +1.76) dB,

0.1µF

AV

SS

DV

SS

–5V

ANALOG

SUPPLY

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

10µF

T he AD7703 samples the input signal at 16 kHz, which spreads

the quantization noise from 0 kHz to 8 kHz. Since the specified

analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz,

the noise energy in this bandwidth would be only 1/800 of the

total quantization noise, assuming that the noise energy was

spread evenly throughout the spectrum. It is reduced still

further by analog filtering in the modulator loop, which shapes

the quantization noise spectrum to move most of the noise

energy to frequencies above 10 Hz. T he SNR performance in

the 0 Hz to 10 Hz range is conditioned to the 20-bit level in this

fashion.

Figure 7. Typical System Connection Diagram

T he AD7703 can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. A calibration cycle may be initiated at any time

using the CAL control input.

Other system components may also be included in the

calibration loop to remove offset and gain errors in the input

channel.

For battery operation, the AD7703 also offers a standby mode

that reduces idle power consumption to typically 10 µW.

T he output of the comparator provides the digital input for the

1-bit DAC, so the system functions as a negative feedback loop

which minimizes the difference signal. T he digital data that

represents the analog input voltage is in the duty cycle of the

pulse train appearing at the output of the comparator. It can be

retrieved as a parallel binary data word using a digital filter.

Sigma-delta ADCs are generally described by the order of the

analog low-pass filter. A simple example of a first order sigma-

delta ADC is shown in Figure 8. T his contains only a first-order

low-pass filter or integrator.

T he AD7703 uses a second-order sigma-delta modulator and a

digital filter that provides a rolling average of the sampled

output. After power-up or if there is a step change in the input

voltage, there is a settling time before valid data is obtained.

REV. D

–7–

AD7703

D IGITAL FILTERING

T he AD7703’s digital filter behaves like an analog filter, with a

few minor differences.

T he output settling of the AD7703 in response to a step input

change is shown in Figure 10. T he Gaussian response has fast

settling with no overshoot, and the worst-case settling time to

±0.0007% is 125 ms with a 4.096 MHz master clock frequency.

First, since digital filtering occurs after the A to D conversion

process, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator

and digital filter, even though the average value of the signal is

within limits. T o alleviate this problem, the AD7703 has over-

range headroom built into the sigma-delta modulator and digital

filter which allows overrange excursions of 100 mV. If noise sig-

nals are larger than this, consideration should be given to analog

input filtering, or to reducing the gain in the input channel so

that a full-scale input (2.5 V) gives only a half-scale input to the

AD7703 (1.25 V). T his will provide an overrange capability

greater than 100% at the expense of reducing the dynamic range

by 1 bit (50%).

100

80

60

40

20

0

40

80

120

160

TIME – ms

Figure 10. AD7703 Step Response

FILTER CH ARACTERISTICS

T he cutoff frequency of the digital filter is f_CLK/409600. At the

maximum clock frequency of 4.096 MHz, the cutoff frequency

of the filter is 10 Hz and the data update rate is 4 kHz.

USING TH E AD 7703

SYSTEM D ESIGN CO NSID ERATIO NS

T he AD7703 operates differently from successive approxima-

tion ADCs or integrating ADCs. Since it samples the signal con-

tinuously, like a tracking ADC, there is no need for a start convert

command. T he 20-bit output register is updated at a 4 kHz rate,

and the output can be read at any time, either synchronously or

asynchronously.

Figure 9 shows the filter frequency response. T his is a 6-pole

Gaussian response that provides 55 dB of 60 Hz rejection for a

10 Hz cutoff frequency. If the clock frequency is halved to give a

5 Hz cutoff, 60 Hz rejection is better than 90 dB.

20

CLO CKING

0

f

= 4MHz

CLK

T he AD7703 requires a master clock input, which may be an

external T T L/CMOS compatible clock signal applied to the

CLKIN pin (CLKOUT not used). Alternatively, a crystal of the

correct frequency can be connected between CLKIN and

CLKOUT , when the clock circuit will function as a crystal

controlled oscillator.

–20

–40

–60

f

= 2MHz

CLK

–80

–100

–120

Figure 11 shows a simple model of the on-chip gate oscillator

and T able II gives some typical capacitor values to be used with

various resonators.

f

= 1MHz

CLK

–140

–160

R1

5MΩ

1

100

10

FREQUENCY – Hz

2

Figure 9. Frequency Response of AD7703 Filter

C2*

10pF

X1

g_m= 1500µMHO

Since the AD7703 contains this low-pass filtering, there is a set-

tling time associated with step function inputs, and data will be

invalid after a step change until the settling time has elapsed.

T he AD7703 is, therefore, unsuitable for high speed multiplex-

ing, where channels are switched and converted sequentially at

high rates, as switching between channels can cause a step

change in the input. However, slow multiplexing of the AD7703

is possible, provided that the settling time is allowed to elapse

before data for the new channel is accessed.

3

C1*

10pF

AD7703

*SEE TABLE II

Figure 11. On-Chip Gate Oscillator

–8–

REV. D

AD7703

Table II. Resonator Loading Capacitors

low capacitance/voltage coefficient. T he device also achieves low

input drift through the use of chopper-stabilized techniques in

its input stage. T o ensure excellent performance over time and

temperature, the AD7703 uses digital calibration techniques

which minimize offset and gain error to typically ±4 LSBs.

Resonators

C1

C2

Ceramic

200 kHz

455 kHz

1.0 MHz

2.0 MHz

Crystals

330 pF

100 pF

50 pF

470 pF

100 pF

50 pF

AUTO CALIBRATIO N

T he AD7703 offers both self-calibration and system-calibration

facilities. For calibration to occur, the on-chip microcontroller

must record the modulator output for two different input condi-

tions. T hese are the “zero scale” and “full scale” points. In uni-

polar self-calibration mode, the zero scale point is V_AGNDand

the full-scale point is V_REF. With these readings the microcon-

troller can calculate the gain slope for the input to output trans-

fer function of the converter. In unipolar mode the slope factor

is determined by dividing the span between zero and full scale

by 2²⁰. In bipolar mode it is determined by dividing the span by

2¹⁹since the inputs applied represent only half the total codes.

In both unipolar and bipolar modes the slope factor is saved and

used to calculate the binary output code when an analog input is

applied to the device. T able IV gives the output code size after

calibration.

20 pF

2.000 MHz

3.579 MHz

4.096 MHz

30 pF

20 pF

None

30 pF

20 pF

None

T he input sampling frequency, output data rate, filter character-

istics and calibration time are all directly related to the master

clock frequency f_CLKINby the ratios given in the specification

table under Dynamic Performance. T herefore, the first step in

system design with the AD7703 is to select a master clock fre-

quency suitable for the bandwidth and output data rate required

by the application.

ANALO G INP UT RANGES

System calibration allows the AD7703 to compensate for system

gain and offset errors. A typical circuit where this might be used

is shown in Figure 12.

T he AD7703 performs conversion relative to an externally sup-

plied reference voltage, which allows easy interfacing to ratio-

metric systems. In addition, either unipolar or bipolar input

voltage ranges may be selected using the BP/UP input. With

BP/UP tied low, the input range is unipolar and the span is

(V_REF–V_AGND), where V_AGNDis the voltage at the device AGND

pin. With BP/UP tied high, the input range is bipolar and the

span is 2 V_REF. In the bipolar mode both positive and negative

full scale are directly determined by V_REF. T his offers superior

tracking of positive and negative full scale and better midscale

(bipolar zero) stability than bipolar schemes that simply scale

and offset the input range.

System calibration performs the same slope factor calculations

as self-calibration but uses voltage values presented by the

system to the A_INpin for the zero and full-scale points. T here

are two system calibration modes.

T he first mode offers system level calibration for system offset

and system gain. T his is a two step operation. T he zero-scale

point must be presented to the converter first. It must be

applied to the converter before the calibration step is initiated

and remain stable until the step is complete. T he DRDY output

from the device will signal when the step is complete by going

low. After the zero-scale point is calibrated the full-scale point is

applied and the second calibration step is initiated. Again the

voltage must remain stable throughout the calibration step.

T he digital output coding for the unipolar range is unipolar

binary and for the bipolar range it is offset binary. Bit weights

for the unipolar and bipolar modes are shown in T able I.

ACCURACY

T he two step calibration mode offers another feature. After the

sequence has been completed, additional offset calibrations can

be performed by themselves to adjust the zero reference point to

a new system zero reference value. T his second system

Sigma-delta ADCs, like VFCs and other integrating ADCs, do

not contain any source of nonmonotonicity and inherently offer

no missing codes performance.

calibration mode uses an input voltage for the zero-scale

calibration point but uses the V_REFvalue for the full-scale point.

T he AD7703 achieves excellent linearity by the use of high

quality, on-chip silicon dioxide capacitors, which have a very

SCLK

SYSTEM

REF HI

SDATA

SIGNAL

CONDITIONING

ANALOG

MUX

CAL

SC1

A

IN

MICRO

COMPUTER

SYSTEM

REF LO

SC2

A0

A1

AD7703

Figure 12. Typical Connections for System Calibration

REV. D

–9–

AD7703

Initiating Calibr ation

When self-calibration is completed, DRDY falls and the output

port is updated with a data word that represents the analog

input signal. When a system calibration step is completed,

DRDY will fall and the output port will be updated with the

appropriate data value (all 0s for the zero-scale point and all 1s

for the full-scale point). In the system calibration mode, the

digital filter must settle before the output code will represent the

value of the analog input signal. T ables IV and V indicate the

output code size and output coding of the AD7703 in its

various modes. In these tables, S_OFFis the measured system

offset in volts and S_GAINis the measured system gain at the

full-scale point in volts.

T able III illustrates the calibration modes available in the

AD7703. Not shown in the table is the function of the BP/UP

pin which determines whether the converter has been calibrated

to measure bipolar or unipolar signals. A calibration step is

initiated by bringing the CAL pin high for at least 4 CLKIN

cycles and then bringing it low again. T he states of SC1 and

SC2 along with the BP/UP pin will determine the type of

calibration to be performed. All three signals should be stable

before the CAL pin is taken positive. T he SC1 and SC2 inputs

are latched when CAL goes high. T he BP/UP input is not

latched and therefore must remain in a fixed state throughout

the calibration and measurement cycles. Any time the state of

the BP/UP is changed, a new calibration cycle must be

performed to enable the AD7703 to function properly in the

new mode.

Span and O ffset Lim its

Whenever a system calibration mode is used, there are limits on

the amount of offset and span which can be accommodated.

T he range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 V_REFand a maximum value of

2 (V_REF+ 0.1 V).

When a calibration step is initiated, the DRDY signal will go

high and remain high until the step is finished. T able III shows

the number of clock cycles each calibration requires. Once a

calibration step is initiated it must finish before a new calibra-

tion step can be executed. In the two step system calibration

mode, the offset calibration step must be initiated before initiat-

ing the gain calibration step.

T he amount of offset which can be accommodated depends on

whether the unipolar or bipolar mode is being used. In unipolar

mode, the system calibration modes can handle a maximum

offset of 0.2 V_REFand a minimum offset of –(V_REF+ 0.1 V).

T hus the AD7703 in the unipolar mode can be calibrated to

mimic bipolar operation.

Table III. Calibration Truth Table

ZERO -SCALE CAL FULL-SCALE CAL SEQUENCE

CAL

SC1

SC2

CAL TYP E

CALIBRATIO N TIME

0

1

0

1

0

1

0

Self-Cal

V_AGND

A_IN

_

V_REF

_

A_IN

V_REF

One Step

1st Step

2nd Step

One Step

3,145,655 Clock Cycles

1,052,599 Clock Cycles

1,068,813 Clock Cycles

2,117,389 Clock Cycles

System Offset

System Gain

System Offset

A_IN

NOT E

DRDY remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes

DRDY falls as the device begins to settle.

Table IV. O utput Code Size After Calibration

1 LSB

CAL MO D E

ZERO -SCALE

GAIN FACTO R

UNIP O LAR

BIP O LAR

(V_REF–V_AGND

)

2(V_REF–V_AGND)

Self-Cal

V_AGND

V_REF

1048576

(S_GAIN–S_OFF

)

2(S_GAIN–S_OFF)

System Cal

S_OFF

S_GAIN

1048576

–10–

REV. D

AD7703

Table V. AD 7703 O utput Coding

I

NP UT VO LTAGE, UNIP O LAR MO D E INP UT VO LTAGE, BIP O LAR MO D E

System Cal

Self Cal

O utput Codes

Self-Cal

System Cal

>(S_GAIN–1.5 LSB)

>(V_REF– 1.5 LSB)

FFFFF

>(V_REF–1.5 LSB)

>(S_GAIN– 1.5 LSB)

FFFFF

FFFFE

S_GAIN– 1.5 LSB

V_REF– 1.5 LSB

S_GAIN– 1.5 LSB

80000

(S_GAIN– S_OFF)/2 – 0.5 LSB

(V_REF– V_AGND)/2 – 0.5 LSB

V_AGND– 0.5 LSB

S_OFF– 0.5 LSB

7FFFF

00001

00000

S_OFF+ 0.5 LSB

V_AGND+ 0.5 LSB

–V_REF+ 0.5 LSB

–S_GAIN+ 2 S_OFF+ 0.5 LSB

<(–S_GAIN+2 S_OFF+ 0.5 LSB)

<(S_OFF+ 0.5 LSB)

<(V_AGND+ 0.5 LSB)

00000

<(–V_REF+ 0.5 LSB)

In the bipolar mode the system offset calibration range is

restricted to ±0.4 V_REF. It should be noted that the span

restrictions limit the amount of offset which can be calibrated.

T he span range of the converter in bipolar mode is equidistant

around the voltage used for the zero scale point. When the zero-

scale point is calibrated it must not cause either of the two

endpoints of the bipolar transfer function to exceed the positive

or the negative input overrange points (+V_REF+ 0.1) V or

updated at a rate determined by the master clock, therefore the

amount of offset drift which occurs will be proportional to the

elapsed time between samples. T hus, to minimize offset drift at

higher temperatures, higher CLKIN rates are recommended.

Gain drift within the converter depends mainly upon the tem-

perature tracking of the internal capacitors. It is not affected by

leakage currents so that it is significantly less than offset drift.

T he typical gain drift of the AD7703 is less than 40 LSBs over

the specified temperature range.

–V_REF+ 0.1) V. If the span range is set to a minimum (0.8 V_REF

)

the offset voltage can move +0.4 V_REFwithout causing the end

points of the transfer function to exceed the overrange points.

Alternatively, if the span range is set to 2 V_REF, the input offset

cannot move more than +0.1 V or –0.1 V before an endpoint of

the transfer function exceeds the input overrange limit.

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter. Using the sys-

tem calibration mode can also minimize offset and gain errors in

the signal conditioning circuitry. Integral and differential linear-

ity are not significantly affected by temperature changes.

P O WER-UP AND CALIBRATIO N

160

A calibration cycle must be carried out after power-up to

initialize the device to a consistent starting condition and correct

calibration. T he CAL pin must be held high for at least four

clock cycles, after which calibration is initiated on the falling

edge of CAL and takes a maximum of 3,145,655 clock cycles

(approximately 768 ms with a 4.096 MHz clock). See T able III.

CLKIN = 4.096MHz

80

0

–80

T he type of calibration cycle initiated by CAL is determined by

the SC1 and SC2 inputs, in accordance with T able III.

–160

–240

–320

D r ift Consider ations

T he AD7703 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. Figure 13 indicates the typi-

cal offset due to temperature changes after calibration at 25°C.

Drift is relatively flat up to 75°C. Above this temperature, leak-

age current becomes the main source of offset drift. Since leak-

age current doubles approximately every 10°C, the offset drifts

accordingly. T he value of the voltage on the sample capacitor is

–55

–35

–15

5

25

45

65

85

105

125

TEMPERATURE – °C

Figure 13. Typical Bipolar Offset vs. Tem perature after

Calibration at +25°C

REV. D

–11–

AD7703

INP UT SIGNAL CO ND ITIO NING

An RC filter may be added in front of the AD7703 to reduce

high frequency noise. With an external capacitor added from

A_INto AGND, the following equation will specify the maximum

allowable source resistance:

Reference voltages from +1 V to +3 V may be used with the

AD7703, with little degradation in performance. Input ranges

that cannot be accommodated by this range of reference voltages

may be achieved by input signal conditioning. T his may take the

form of gain to accommodate a smaller signal range, or passive

attenuation to reduce a larger input voltage range.

62

R_{S(MAX )}

=

C_IN

(C_IN+ C_EXT

V_E

100 mV •

Sour ce Resistance

)

f_CLKIN•(C_IN+ C_EXT) •ln

If passive attenuators are used in front of the AD7703, care

must be taken to ensure that the source impedance is suffi-

ciently low. T he dc input resistance for the AD7703 is over

1 GΩ. In parallel with this there as a small dynamic load which

varies with the clock frequency (see Figure 14). Each time the

T he practical limit to the maximum value of source resistance is

thermal (Johnson) noise. A practical resistor may be modeled as

an ideal (noiseless) resistor in series with a noise voltage source

or in parallel with a noise current source.

R1

A

AD7703

IN

V

IN

V_n= 4 kTRf Volts

1GΩ

R2

C

EXT

i_n= 4 kTf /R Amperes

C

10pF

IN

where k is Boltzmann’s constant (1.38 ϫ 10^–23J/K), and T is

temperature in degrees Kelvin (°C + 273).

V

≤ 100mV

OS

AGND

Active signal conditioning circuits such as op amps generally do

not suffer from problems of high source impedance. T heir open

loop output resistance is normally only tens of ohms and, in any

case, most modern general purpose op amps have sufficiently

fast closed loop settling time for this not to be a problem. Offset

voltage in op amps can be eliminated in a system calibration

routine.

Figure 14. Equivalent Input Circuit and Input Attenuator

analog input is sampled, a 10 pF capacitor draws a charge

packet of maximum 1 pC (10 pF ϫ 100 mV) from the analog

source with a frequency f_CLKIN/256. For a 4.096 MHz CLKIN,

this yields an average current draw of 16 nA. After each sample

the AD7703 allows 62 clock periods for the input voltage to

settle. T he equation which defines settling time is:

Antialias Consider ations

T he digital filter of the AD7703 does not provide any rejection

at integer multiples of the sampling frequency (nf_CLKIN/256,

where n = 1, 2, 3 . . . ).

V_O=V_IN[1– e^{–t / RC}

]

where V_O, is the final settled value, V_IN, is the value of the input

signal, R is the value of the input source resistance, C is the

With a 4.096 MHz master clock there are narrow (±10 Hz)

bands at 16 kHz, 32 kHz, 48 kHz, etc., where noise passes

unattenuated to the output.

10 pF sample capacitor. T he value of t is equal to 62/f_CLKIN

.

T he following equation can be developed which gives the max-

imum allowable source resistance, R_S(MAX)for an error of V_E.

However, due to the AD7703’s high oversampling ratio of 800

(16 kHz to 20 Hz) these bands occupy only a small fraction of

the spectrum, and most broadband noise is filtered.

62

R_{S(MAX )}

=

T he reduction in broadband noise is given by:

f_CLKIN•(10 pF )•ln (100 mV /V_E)

Provided the source resistance is less than this value, the analog

input will settle within the desired error band in the requisite 62

clock periods. Insufficient settling leads to offset errors. T hese

can be calibrated in system calibration schemes.

e_out= e 2 f_C/f _S= 0.035 e

in

where e_inand e_outare rms noise terms referred to the input and f_C

is the filter –3 dB corner frequency (f_CLKIN/409600) and f_Sis the

sampling frequency (f_CLKIN/256).

If a limit of 600 nV (0.25 LSB at 20 bits) is set for the maxi-

mum offset voltage, then the maximum allowable source resis-

tance is 125 kΩ from the above equation, assuming that there is

no external stray capacitance.

Since the ratio of f_Sto f_CLKINis fixed, the digital filter reduces

broadband white noise by 96.5% independent of the master

clock frequency.

–12–

REV. D

AD7703

T herefore, the two analog supplies should be individually

decoupled to AGND using 100 nF ceramic capacitors to

provide power supply noise rejection at these frequencies. T he

two digital supplies should similarly be decoupled to DGND.

VO LTAGE REFERENCE CO NNECTIO NS

T he voltage applied to the V_REFpin defines the analog input

range. T he specified reference voltage is 2.5 V, but the AD7703

will operate with reference voltages from 1 V to 3 V with little

degradation in performance.

T he positive digital supply (DV_DD) must never exceed the

positive analog supply (AV_DD) by more than 0.3 V. Power

supply sequencing is therefore important. If separate analog and

digital supplies are used, care must be taken to ensure that the

analog supply is powered up first.

T he reference input presents exactly the same dynamic load as

the analog input, but in the case of the reference input, source

resistance and long settling time introduce gain errors rather

than offset errors. Fortunately, most precision references have

sufficiently low output impedance and wide enough bandwidth

to settle to the required accuracy within 62 clock cycles.

It is also important that power is applied to the AD7703 before

signals at V_REF, A_INor the logic input pins in order to avoid any

possibility of latch-up. If separate supplies are used for the

AD7703 and the system digital circuitry, then the AD7703

should be powered up first.

T he digital filter of the AD7703 removes noise from the refer-

ence input, just as it does with noise at the analog input, and

the same limitations apply regarding lack of noise rejection at

integer multiples of the sampling frequency. Note that the refer-

ence should be chosen to minimize noise below 10 Hz. T he

AD7703 typically exhibits 1.6 LSB rms noise in its measure-

ments. T his specification assumes a clean reference. Many

monolithic bandgap references are available which can supply

the 2.5 V needed for the AD7703. However, some of these are

not specified for noise especially in the 0.1 Hz to 10 Hz band-

width. If the reference noise in this bandwidth is excessive, it

can degrade the performance of the AD7703. Recommended

references are the AD580 and the LT 1019. Both of these 2.5 V

references typically have less than 10 ␮V p-p noise in the 0.1 Hz

to 10 Hz band.

A typical scheme for powering the AD7703 from a single set of

±5 V rails is shown Figure 7. In this circuit AV_DDand DV_DDare

brought along separate tracks from the same +5 V supply.

T hus, there is no possibility of the digital supply coming up

before the analog supply.

SLEEP MO D E

T he low power standby mode is initiated by taking the SLEEP

input low, which shuts down all analog and digital circuits and

reduces power consumption to 10 µW. When coming out of

SLEEP mode it is sometimes possible (when using a crystal to

generate CLKIN, for example) to lose the calibration coeffi-

cients. T herefore, it is advisable as a safeguard to always do a

calibration cycle after coming out of SLEEP mode.

P O WER SUP P LIES AND GRO UND ING

AGND is the ground reference voltage for the AD7703, and is

completely independent of DGND. Any noise riding on the

AGND input with respect to the system analog ground will

cause conversion errors. AGND should therefore be used as the

system ground and also as the ground for the analog input and

the reference voltage.

D IGITAL INTERFACE

T he AD7703’s serial communications port allows easy

interfacing to industry standard microprocessors. T wo different

modes of operation are available, optimized for different types

of interface.

T he analog and digital power supplies to the AD7703 are

independent and separately pinned out, to minimize coupling

between analog and digital sections of the device. T he digital

filter will provide rejection of broadband noise on the power

supplies, except at integer multiples of the sampling frequency.

REV. D

–13–

AD7703

SYNCH RO NO US SELF-CLO CKING MO D E (SSC)

T he SSC mode (MODE pin high) allows easy interfacing to

serial-parallel conversion circuits in systems with parallel data

communication. T his mode allows interfacing to 74XX299

Universal Shift registers without any additional decoding. T he

SSC mode can also be used with microprocessors such as the

68HC11 and 68HC05, which allow an external device to clock

their serial port.

SCLK will become active and the data word currently in the

output register will be transmitted, MSB first. After the LSB has

been transmitted DRDY will go high until the new data word

becomes available. If CS, having been brought low, is taken

high again at any time during data transmission, SDAT A and

SCLK will go three-state after the current bit finishes. If CS is

subsequently brought low, transmission will resume with the

next bit during the subsequent digital computation period. If

transmission has not been initiated and completed by the time

the next data word is available, DRDY will go high for four

clock cycles then low again as the new word is loaded into the

output register.

Figure 15 shows the timing diagram for the SSC mode. Data is

clocked out by an internally generated serial clock. T he

AD7703 divides each sampling interval into sixteen distinct

periods. Eight periods of 64 clock pulses are for analog settling

and eight periods of 64 clock pulses are for digital computation.

T he status of CS is polled at the beginning of each digital

computation period. If it is low at any of these times, then

A more detailed diagram of the data transmission in the SSC

mode is shown in Figure 16. Data bits change on the falling

edge of SCLK and are valid on the rising edge of SCLK.

1024 CLKIN CYCLES

64 CLKIN

CYCLES

64 CLKIN

CYCLES

INTERNAL

STATUS

ANALOG TIME 0

DIGITAL TIME 0

DIGITAL TIME 7

72 CLKIN CYCLES

DRDY (O)

CS POLLED

CS (I)

HI-Z

SCLK (O)

MSB

LSB

HI-Z

SDATA (O)

Figure 15. Tim ing Diagram for SSC Data Transm ission Mode

CLKIN (I)

72

CLKIN

CYCLES

DRDY (O)

CS (I)

HI-Z

SDATA (O)

DB18

DB19 (MSB)

DB17

DB2

DB1

DB0 (LSB)

SCLK (O)

Figure 16. SSC Mode Showing Data Tim ing Relative to SCLK

–14–

REV. D

AD7703

SYNCH RO NO US EXTERNAL CLO CK MO D E (SEC)

T he SEC mode (MODE pin grounded) is designed for direct

interface to the synchronous serial ports of industry standard

microprocessors such as the 68HC11 and 68HC05. T he SEC

mode also allows customized interfaces, using I/O port pins, to

microprocessors that do not have a direct fit with the AD7703’s

other mode.

D IGITAL NO ISE AND O UTP UT LO AD ING

As mentioned earlier, the AD7703 divides its internal timing

into two distinct phases, analog sampling and settling and digital

computation. In the SSC mode, data is transmitted only during

the digital computation periods, to minimize the effects of

digital noise on analog performance. In the SEC mode data

transmission is externally controlled, so this automatic safeguard

does not exist. T o compensate, the AD7703 should be

synchronized to the digital system clock via CLKIN when used

in the SEC mode.

As shown in Figure 17, a falling edge on CS enables the serial

data output with the MSB initially valid. Subsequent data bits

change on the falling edge of an externally supplied SCLK.

After the LSB has been transmitted, DRDY and SDAT A go

three-state. If CS is low and the AD7703 is still transmitting

data when a new data word becomes available, the old data

word continues to be transmitted and the new data is lost.

Whatever mode of operation is used, resistive and capacitive

loads on digital outputs should be minimized in order to reduce

crosstalk between analog and digital portions of the circuit. For

this reason connection to low-power CMOS logic such as one of

the 4000 series or 74C families is recommended.

If CS is taken high at any time during data transmission,

SDAT A will go three-state immediately. If CS returns low, the

AD7703 will continue transmission with the same data bit. If

transmission has not been initiated and completed by the time

the next data word becomes available, and if CS is high, DRDY

will return high for four clock cycles, then fall as the new word is

loaded into the output register.

DRDY (O)

CS (I)

SCLK (O)

HI-Z

SDATA (O)

DB18

DB19 (MSB)

DB17

DB2

DB1

DB0 (LSB)

Figure 17. Tim ing Diagram for the SEC Mode

REV. D

–15–

AD7703

MECH ANICAL INFO RMATIO N

D imensions shown in inches and (mm)

20-P in P lastic D IP (Suffix N)

20-P in Cer dip (Suffix Q)

20-Lead SO IC (Suffix R)

–16–

REV. D


型号：	AD7703BRZ
厂家：	ADI
描述：	20-Bit A/D Converter 转换器
文件：	总16页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7703BRZ [ADI]

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