AD779TD [ADI]
14-Bit 128 kSPS Complete Sampling ADC; 14位128 kSPS的完整采样ADC
| 型号： | AD779TD |
| 厂家： | 
ADI |
| 描述： | 14-Bit 128 kSPS Complete Sampling ADC |
| 文件： | 总12页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit 128 kSPS
Complete Sampling ADC
a
AD779*
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
AC and DC Characterized and Specified (K, B, T
Grades)
128k Conversions per Second
1 MHz Full Pow er Bandw idth
500 kHz Full Linear Bandw idth
80 dB S/ N+D (K, B, T Grades)
Tw os Com plem ent Data Form at (Bipolar Mode)
Straight Binary Data Form at (Unipolar Mode)
10 M⍀ Input Im pedance
16-Bit Bus Interface (See AD679 for 8-Bit Interface)
Onboard Reference and Clock
10 V Unipolar or Bipolar Input Range
MIL-STD-883 Com pliant Versions Available
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD779 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-hold amplifier
(SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
l. COMPLET E INT EGRAT ION: T he AD779 minimizes
external component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock
and digital interface on a single chip. T his provides a fully
specified sampling A/D function unattainable with discrete
designs.
T he AD779 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, T HD and IMD which are important in signal
processing applications. In addition, the AD779K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
2. SPECIFICAT IONS: T he AD779K, B and T grades provide
fully specified and tested ac and dc parameters. T he AD779J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, T HD and IMD) are of value in signal process-
ing applications.
T he 14 data bits are accessed by a 16-bit bus in a single read
operation. Data format is straight binary for unipolar mode and
twos complement binary for bipolar mode. T he input has a full-
scale range of 10 V with a full power bandwidth of 1 MHz and a
full linear bandwidth of 500 kHz. High input impedance (10 MΩ)
allows direct connection to unbuffered sources without signal
degradation.
3. EASE OF USE: T he pinout is designed for easy board lay-
out, and the single cycle read output provides compatibility
with 16-bit buses. Factory trimming eliminates the need for
calibration modes or external trimming to achieve rated
performance.
T his product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. T he converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
4. RELIABILIT Y: T he AD779 utilizes Analog Devices’
monolithic BiMOS technology. T his ensures long term
reliability compared to multichip and hybrid designs.
T he AD779 operates from +5 V and ±12 V supplies and
dissipates 560 mW (typ). T wenty-eight-pin plastic DIP and
ceramic DIP packages are available.
5. T he AD779 is available in versions compliant with MIL-
ST D-883. Refer to the Analog Devices Military Products
Databook or current AD779/883B data sheet for detailed
specifications.
*P r otected by U.S. P atent Num ber s 4,804,960; 4,814,767; 4,833,345;
4,250,445; 4,808,908; RE 30,586.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD779–SPECIFICATIONS
(TMIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10%, fSAMPLE = 128 kSPS,
flN = 10.009 kHz unless otherwise noted)
MAX CC
EE
DD
1
AC SPECIFICATIONS
AD 779J/A/S
Typ
AD 779K/B/T
P aram eter
Min
Max
Min
Typ
Max
Units
SIGNAL-T O-NOISE AND DIST ORT ION (S/N+D) RAT IO
–0.5 dB Input (Referred to 0 dB Input)
–20 dB Input (Referred to –20 dB Input)
78
58
18
79
59
19
80
60
20
81
61
21
dB
dB
dB
–60 dB Input (Referred to –60 dB Input)
T OT AL HARMONIC DIST ORT ION (T HD)
@ +25°C
–90
0.003
–88
–84
0.006
–82
–90
0.003
–88
–84
0.006
–82
dB
%
dB
%
TMIN to TMAX
0.004
0.008
0.004
0.008
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
FULL POWER BANDWIDT H
–90
1
–84
–90
1
–84
dB
MHz
kHz
FULL LINEAR BANDWIDT H
500
500
INT ERMODULAT ION DIST ORT ION (IMD)2
2nd Order Products
3rd Order Products
–90
–90
–84
–84
–90
–90
–84
–84
dB
dB
(All device types TMIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10%)
DIGITAL SPECIFICATIONS
P aram eter
MAX CC
EE
DD
Test Conditions
Min
Max
Units
LOGIC INPUT S
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.0
0
–10
–10
VDD
0.8
+10
+10
10
V
V
µA
µA
pF
VIN = VDD
VIN = 0 V
LOGIC OUT PUT S
VOH
High Level Output Voltage
IOH = 0.1 mA
IOH = 0.5 mA
IOL = 1.6 mA
VIN = VDD
4.0
2.4
V
V
V
µA
pF
VOL
IOZ
COZ
Low Level Output Voltage
High Z Leakage Current
High Z Output Capacitance
0.4
+10
10
–10
NOT ES
1fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal
unless otherwise noted.
2fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE = 128 kSPS.
Specifications subject to change without notice.
–2–
REV. B
AD779
DC SPECIFICATIONS (T
MIN to T , V = +12 V ؎ 5%, V = –12 V ؎ 5%, V = +5 V ؎ 10% unless otherwise noted)
MAX CC
EE
DD
AD 779J/A/S
Typ
AD 779K/B/T
P aram eter
Min
Max
Min
Typ
Max
Units
T EMPERAT URE RANGE
J, K Grades
A, B Grades
0
–40
–55
+70
+85
+125
0
–40
–55
+70
+85
+125
°C
°C
°C
S, T Grades
ACCURACY
Resolution
14
14
14
14
Bits
LSB
Bits
% FSR*
% FSR
% FSR
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Unipolar Zero Error1 (@ +25°C)
Bipolar Zero Error1 (@ +25°C)
Gain Error1, 2 (@ +25°C)
T emperature Drift
Unipolar Zero3
J, K Grades
±2
±1
±2
0.08
0.08
0.12
0.05
0.05
0.09
0.07
0.07
0.11
0.04
0.05
0.09
0.04
0.05
0.09
0.05
0.07
0.10
% FSR
% FSR
% FSR
A, B Grades
S, T Grades
Bipolar Zero3
J, K Grades
A, B Grades
0.02
0.04
0.08
0.02
0.04
0.08
0 04
0.06
0.09
% FSR
% FSR
% FSR
S, T Grades
Gain3
J, K Grades
A, B Grades
0.09
0.10
0.20
0.09
0.10
0.20
0.11
0.16
0.25
% FSR
% FSR
% FSR
S, T Grades
Gain4
J, K Grades
A, B Grades
S, T Grades
0.04
0.05
0.09
0.04
0.05
0.09
0.05
0.07
0.10
% FSR
% FSR
% FSR
ANALOG INPUT
Input Ranges
Unipolar Mode
Bipolar Mode
0
–5
+10
+5
0
–5
+10
+5
V
V
Input Resistance
Input Capacitance
Input Settling T ime
Aperture Delay
Aperture Jitter
10
10
10
10
MΩ
pF
µs
ns
ps
1.5
1.5
10
150
10
150
INT ERNAL VOLT AGE REFERENCE
Output Voltage5
4.98
5.02
4.98
5.02
V
External Load
Unipolar Mode
Bipolar Mode
+1.5
+0.5
+1.5
+0.5
mA
mA
POWER SUPPLIES
Power Supply Rejection
VCC = +12 V ± 5%
VEE = –12 V ± 5%
VDD = +5 V ± 10%
Operating Current
ICC
±6
±6
±6
±6
±6
±6
LSB
LSB
LSB
18
25
8
20
34
12
745
18
25
8
20
34
12
745
mA
mA
mA
mW
IEE
IDD
Power Consumption
560
560
NOT ES
1Adjustable to zero. See Figures 5 and 6.
2Includes internal voltage reference error.
3Includes internal voltage reference drift.
4Excludes internal voltage reference drift.
5With maximum external load applied.
*% FSR = percent of full-scale range.
Specifications subject to change without notice.
REV. B
–3–
AD779
TIMING SPECIFICATIONS
(All device types TMIN to T , V = +12 V ؎ 5%, V = –12 V
MAX CC
EE
؎ 5%, V = +5 V ؎ 10%)
DD
P aram eter
Sym bol
Min
Max
Units
Conversion Rate1
Convert Pulse Width
Aperture Delay
Conversion T ime
Status Delay
tCR
tCP
tAD
tC
tSD
tBA
7.8
3.0
20
6.3
400
100
574
80
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
0.097
5
0
Access T ime2, 3
10
10
10
Float Delay5
Output Delay
OE Delay
Read Pulse Width
Conversion Delay
tFD
tOD
tOE
tRP
tCD
0
20
100
400
NOT ES
1Includes Acquisition T ime.
2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3COUT = 100 pF.
4COUT = 50 pF.
5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the
output voltage changes by 0.5 V. See Figure 4; C OUT = 10 pF.
Specifications subject to change without notice.
Figure 3. EOC Tim ing
Figure 1. Conversion Tim ing
Figure 4. Load Circuit for Bus Tim ing Specifications
Figure 2. Output Tim ing
–4–
REV. B
AD779
ABSO LUTE MAXIMUM RATINGS 1
With
Respect
Specification
To
Min
Max
Units
VCC
VBE
VCC
VDD
AGND
AGND
AGND
VEE
DGND
DGND
AGND
DGND
DGND
–0.3
–18
–0.3
0
+18
+0.3
+26.4
+7
+1
VCC
+7
V
V
V
V
V
V
V
V
2
–1
AIN, REFIN
VEE
–0.5
–0.5
Digital Inputs
Digital Outputs
Max Junction
T emperature
VDD +0.3
175
°C
Operating T emperature
J and K Grades
A and B Grades
S and T Grades
Storage T emperature
Lead T emperature
(10 sec max)
0
+70
+85
+125
+150
°C
°C
°C
°C
–40
–55
–65
+300
°C
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2T he AD779 is not designed to operate from ±15 V supplies.
ESD SENSITIVITY
T he AD779 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-ST D-883C, the AD779
has been classified as a Category 1 device.
WARNING!
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed. For
further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
ESD SENSITIVE DEVICE
O RD ERING GUID E 1
Model2
Tem perature Range
Tested and Specified
P ackage D escription
P ackage O ption3
AD779JN
AD779KN
AD779JD
AD779KD
AD779AD
AD779BD
AD779SD
AD779T D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
N-28
N-28
D-28
D-28
D-28
D-28
D-28
D-28
AC + DC
NOT ES
1For two cycle read (8+16 bits) interface to 8-bit buses, see AD679.
2For details on grade and package offerings screened in accordance with MIL-ST D-883, refer to the Analog Devices Military Products Databook or current
AD779/883B data sheet.
3D = Ceramic DIP; N = Plastic DIP.
REV. B
–5–
AD779
P IN D ESCRIP TIO N
Nam e and Function
28-P in D IP
P in No.
Sym bol
Type
AGND
AIN
7
P
Analog Ground. T his is the ground return for AIN only.
Analog Signal Input.
6
AI
AI
BIPOFF
10
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REFOUT for ±5 V input
bipolar mode and twos-complement binary output coding.
CS
12
DI
P
Chip Select. Active LOW.
Digital Ground.
DGND
DB13–DB0
14
28–15
DO
Data Bits. T hese pins provide all 14 bits in one 14 bit parallel output.
Active HIGH.
EOC
2
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion is finished. EOC is a three-state output. See
EOCEN pin for information on EOC gating.
EOCEN
OE
13
3
DI
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
Output Enable. A down-going transition on OE enables data bits.
Active LOW.
REFIN
REFOUT
SC
9
AI
AO
DI
P
Reference Input. +5 V input gives 10 V full scale range.
+5 V Reference Output. T ied to REFIN for normal operation.
Start Convert. Active LOW.
8
4
VCC
11
5
+12 V Analog Power.
VEE
P
–12 V Analog Power.
VDD
1
P
+5 V Digital Power.
T ype: AI = Analog Input.
AO = Analog Output.
DI = Digital Input.
DO = Digital Output. All DO pins are three-state drivers.
P = Power.
P IN CO NFIGURATIO N
D IP P ackage
–6–
REV. B
AD779
D EFINITIO N O F SP ECIFICATIO NS
NYQ UIST FREQ UENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
AP ERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INP UT SETTLING TIME
Settling time is a function of the SHA’s ability to track fast
slewing signals. T his is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
SIGNAL-TO -NO ISE AND D ISTO RTIO N (S/N+D ) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
D IFFERENTIAL NO NLINEARITY (D NL)
TO TAL H ARMO NIC D ISTO RTIO N (TH D )
T HD is the ratio of the rms sum of the first six harmonic
components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes
(NMC) are guaranteed.
INTEGRAL NO NLINEARITY (INL)
T he ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” T he point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code
transition. Integral nonlinearity error is the worst case deviation
of a code from the straight line. T he deviation of each code is
measured from the middle of that code.
P EAK SP URIO US O R P EAK H ARMO NIC CO MP O NENT
T he peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. T his
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMO D ULATIO N D ISTO RTIO N (IMD )
Note that the linearity error is not user adjustable.
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb) and the third order
terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). T he
IMD products are expressed as the decibel ratio of the rms sum
of the measured input signals to the rms sum of the distortion
terms. T he two signals applied to the converter are of equal
amplitude and the peak value of their sum is –0.5 dB from full
scale (9.44 V p-p). T he IMD products are normalized to a 0-dB
input signal.
P O WER SUP P LY REJECTIO N
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
TEMP ERATURE D RIFT
T his is the maximum change in the parameter from the initial
value (@+25°C) to the value at TMIN or T MAX
.
UNIP O LAR ZERO ERRO R
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the
deviation of the actual transition from that point. T his error
can be adjusted as discussed in the Input Connections and
Calibration section.
BAND WID TH
T he full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
T he full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency,
distortion of the sampled input signal increases significantly.
BIP O LAR ZERO ERRO R
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value
1/2 LSB below analog ground. Bipolar zero error is the deviation
of the actual transition from that point. T his error can be
adjusted as discussed in the Input Connections and Calibration
section.
T he AD779 has been designed to optimize input bandwidth,
allowing it to undersample input signals with frequencies
significantly above the converter’s Nyquist frequency.
GAIN ERRO R
T he last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9991 volts for a 0 V–10 V range,
4.9991 volts for a ±5 V range). T he gain error is the deviation of
the actual level at the last transition from the ideal level with the
zero error trimmed out. T his error can be adjusted as shown in
the Input Connections and Calibration section.
AP ERTURE D ELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion.
REV. B
–7–
AD779
CO NVERSIO N TRUTH TABLE
INP UTS
EOCEN CS
O UTP UTS
D B13 . . . D B0 Status
Mode
SC
OE
EO C
Start Conversion
1
f
0
X
X
X
X
X
X
X
X
X
No Conversion
Start Conversion
Continuous Conversion (Not Recommended)
Conversion Status
Data Access
X
X
X
0
0
1
X
X
X
X
X
X
0
1
Converting
Not Converting
Either
High Z
X
X
X
X
X
X
X
1
0
1
X
0
High Z
High Z
MSB . . . LSB
T hree-State
T hree-State
Data Out
NOT ES
1
0
= HIGH voltage level.
= LOW voltage level.
X = Don’t care.
f = HIGH to LOW transition. Must stay LOW for t = tCP
.
P O WER-UP
CO NVERSIO N CO NTRO L
T he AD779 typically requires 10 µs after power-up to reset
internal logic
Before a conversion is started, End-of-Convert (EOC) is HIGH
and the sample-hold is in track mode. A conversion is started by
bringing SC LOW, regardless of the state of CS.
14-BIT MO D E CO D ING FO RMAT (1 LSB = 0.61 m V)
After a conversion is started, the sample-hold goes into hold
mode and EOC goes LOW, signifying that a conversion is in
progress. During the conversion, the sample-hold will go back
into track mode and start acquiring the next sample.
Unipolar Coding
(Straight Binary)
Bipolar Coding
(Twos Com plem ent)
VIN
O utput Code
VIN
O utput Code
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 µs maximum. T he acquisition time does not affect the
throughput rate as the AD779 goes back into track mode more
than 2 µs before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
0.00000 V
5.00000 V
9.99939 V
000 . . . 0
100 . . . 0
111 . . . 1
–5.00000 V
–0.00061 V
0.00000 V
+2.50000 V
+4.99939 V
100 . . . 0
111 . . . 1
000 . . . 0
010 . . . 0
011 . . . 1
When EOC goes HIGH, the conversion is completed and the
output data may be read. Bringing OE LOW makes the output
register contents available on the output data bits (DB13–DB0).
A period of time tCD is required after OE is brought HIGH
before the next SC instruction is issued.
Application Information
INP UT CO NNECTIO NS AND CALIBRATIO N
T he high (10 MΩ) input impedance of the AD779 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 Ω. T he 10 V p-p
full-scale input range accepts the majority of signal voltages
without the need for voltage divider networks which could
deteriorate the accuracy of the ADC.
If SC is held LOW, conversion accuracy may deteriorate. For
this reason, SC should not be held low in any attempt to operate
in a continuously converting mode.
END -O F-CO NVERT
T he AD779 is factory trimmed to minimize offset, gain and
linearity errors. In unipolar mode, the only external component
that is required is a 50 Ω ± 1% resistor. T wo resistors are
required in bipolar mode. If offset and gain are not critical, even
these components can be eliminated.
End-of-Convert (EOC) is a three-state output which is enabled
by End-of-Convert Enable EOCEN.
O UTP UT ENABLE O P ERATIO N
T he data bits (DB13–DB0) are three-state outputs that are
enabled by Chip Select (CS) and Output Enable (OE). CS
should be LOW tOE before OE is brought LOW. T he output is
read in a single cycle as a 14-bit word.
In some applications, offset and gain errors need to be more
precisely trimmed. T he following sections describe the correct
procedure for these various situations.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REFOUT ),
output coding is twos complement binary.
–8–
REV. B
AD779
BIP O LAR RANGE INP UTS
T he first transition (from 00 0000 0000 0000 to 00 0000 0000
0001) should nominally occur for an input level of +1/2 LSB
(0.305 mV above ground for a 10 V range). T o trim unipolar
zero to this nominal value, apply a 0.305 mV signal to AIN and
adjust R1 until the first transition is located.
T he connections for the bipolar mode are shown in Figure 5. In
this mode, data output coding will be twos complement binary.
T his circuit will allow approximately ±25 mV of offset trim
range (±40 LSB) and ±0.5% of gain trim range (±80 LSB).
T he gain trim is done by adjusting R2. If the nominal value is
required, apply a signal 1 1/2 LSB below full scale (9.9997 V for
a 10 V range) and adjust R2 until the last transition is located
(11 1111 1111 1110 to 11 1111 1111 1111).
If offset adjustment is not required, BIPOFF should be con-
nected directly to AGND. If gain adjustment is not required, R2
should be replaced with a fixed 50 Ω ±1% metal film resistor. If
REFOUT is connected directly to REFIN, the additional gain
error will be approximately 1%.
REFERENCE D ECO UP LING
It is recommended that a 10 µF tantalum capacitor be
connected between REFIN (Pin 9) and ground. T his has the
effect of improving the S/N+D ratio through filtering possible
broadband noise contributions from the voltage reference.
Figure 5. Bipolar Input Connections with Gain and
Offset Trim s
BO ARD LAYO UT
Either or both of the trim pots can be replaced with 50 Ω ±1%
fixed resistors if the AD779 accuracy limits are sufficient for the
application. If the pins are shorted together, the additional offset
and gain errors will be approximately 80 LSB.
Designing with high resolution data converters requires careful
attention to board layout. T race impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 1 LSB at the 14-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and
capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals.
Finally, power supplies need to be decoupled in order to filter
out ac noise.
T o trim bipolar zero to its nominal value, apply a signal 1/2 LSB
below midrange (–0.305 mV for a ±5 V range) and adjust R1
until the major carry transition is located (11 1111 1111 1111 to
00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB
below full scale (+4.9991 V for a ±5 V range) and adjust R2 to
give the last positive transition (01 1111 1111 1110 to 01 1111
1111 1111). T hese trims are interactive so several iterations may
be necessary for convergence.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
A single pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
1/2 LSB above minus full scale (–4.9997 V for a ±5 V range)
and adjust R1 until the minus full-scale transition is located
(10 0000 0000 0000 to 10 000 000 0001). T hen perform the
gain error trim as outlined above.
T he AD779 incorporates several features to help the user’s layout.
Analog pins (VBE) AIN, AGND, REFOUT , REFIN, BIPOFF,
UNIP O LAR RANGE INP UTS
Offset and gain errors can be trimmed out by using the configu-
ration shown in Figure 6. T his circuit allows approximately
±25 mV of offset trim range (±40 LSB) and ±0.5% of gain trim
range (±80 LSB).
VCC) are adjacent to help isolate analog from digital signals. In
addition, the 10 MΩ input impedance of AIN minimizes input
trace impedance errors. Finally, ground currents have been
minimized by careful circuit design. Current through AGND is
200 µA, with no code dependent variation. T he current through
DGND is dominated by the return current for DB13–DB0 and
EOC.
SUP P LY D ECO UP LING
The AD779 power supplies should be well filtered, well regulated,
and free from high frequency noise. Switching power supplies
are not recommended due to their tendency to generate spikes
which can induce noise in the analog system.
Decoupling capacitors should be used as close as possible to all
power supply pins. A 10 µF tantalum capacitor in parallel with a
0.1 µF ceramic capacitor provides adequate decoupling.
Figure 6. Unipolar Input Connections with Gain and
Offset Trim s
REV. B
–9–
AD779
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. T he circuit layout should attempt to locate
the AD779, associated analog input circuitry and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD779 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit con-
struction is preferred.
from its value at 25°C over the 0°C to 70°C range. T his results
in a 0.06% FSR total gain drift for the AD779, which is a sub-
stantial improvement over the on-chip reference performance of
0.11% FSR. A noise-reduction network on Pins 4, 6 and 7 has
been shown. T he 1 µF capacitors form low pass filters with the
internal resistance of the AD588 Zener and amplifier cells and
external resistance. T his reduces the high frequency noise of
the AD588, providing optimum ac and dc performance of the
AD779.
GRO UND ING
If a single AD779 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. T hen connect AGND and DGND together at the
AD779. If multiple AD779s are used or the AD779 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. T his prevents large ground loops which inductively
couple noise and allow digital currents to flow through the
analog system.
USE O F EXTERNAL VO LTAGE REFERENCE
T he AD779 features an on-chip voltage reference. For improved
gain accuracy over temperature, a high performance external
voltage reference may be used in place of the on-chip reference.
Figure 8. Unipolar Input with Gain and Offset Trim s
T he AD586 and AD588 are popular references appropriate for
use with high resolution converters. T he AD586 is a low cost
reference which utilizes a buried Zener architecture to provide
low noise and drift. T he AD588 is a higher performance refer-
ence which uses a proprietary ion-implanted buried Zener diode
in conjunction with laser-trimmed thin-film resistors for low off-
set and low drift.
INTERFACING TH E AD 779 TO MICRO P RO CESSO RS
T he I/O capabilities of the AD779 allow direct interfacing to
general purpose and DSP microprocessor buses. T he asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
T he following examples illustrate typical AD779 interface
configurations.
Figure 7 shows the use of the AD586 with the AD779 in a bipo-
lar input mode. Over the 0°C to +70°C range, the AD586 L-grade
exhibits less than a 2.25 mV output change from its initial value
at 25°C. REFIN, (Pin 9) scales its input by a factor of two; thus,
this change becomes effectively 4.5 mV. When applied to the
AD779, this results in a total gain drift of 0.09% FSR which is
an improvement over the on-chip reference performance of
0.11% FSR. A noise-reduction capacitor, CN, has been shown.
T his capacitor reduces the broadband noise of the AD586 out-
put, thereby optimizing the overall ac and dc performance of the
AD779.
AD 779 TO TMS320C25
In Figure 9 the AD779 is mapped into the T MS320C25 I/O
space. AD779 conversions are initiated by issuing an OUT
instruction to Port 1. EOC status and the conversion result are
read in with an IN instruction to Port 1. A single wait state is
inserted by generating the processor READY input from IS,
Port 1 and MSC. T his configuration supports processor clock
speeds of 20 MHz and is capable of supporting processor clock
speeds of 40 MHz if a NOP instruction follows each AD779
read instruction.
Figure 7. Bipolar Input with Gain and Offset Trim s
Figure 8 shows the AD779 in unipolar input mode with the
AD588 reference. T he AD588 output is accurate to 0.65 mV
Figure 9. AD779 to TMS320C25 Interface
–10–
REV. B
AD779
AD 779 TO 80186
execution in one 80 ns cycle, the digital signal processor will
support the AD779 data memory interface with two wait states.
Figure 10 shows the AD779 interfaced to the 80186 micropro-
cessor. T his interface allows the 80186’s built-in DMA control-
ler to transfer the AD779 output into a RAM based FIFO buffer
of any length, with no microprocessor intervention.
T he converter runs asychronously using a sampling clock. T he
EOC output to the AD779 gets asserted at the end of each
conversion and causes an interrupt. Upon interrupt, the ADSP-
2100A starts a data memory read by providing an address on
the DMA bus. T he decoded address generates OE for the
converter. OE, together with logic and latch, is used to force the
ADSP-2100A into a one cycle wait state by generating
DMACK. T he read operation is thus started and completed
within two processor cycles (160 ns).
Figure 10. AD779 to 80186 DMA Interface
AD 779 TO Z80
T he AD779 can be interfaced to the Z80 processor in an I/O or
memory mapped configuration. Figure 11 illustrates an I/O con-
figuration, where the AD779 occupies several port addresses to
allow separate polling of the EOC status and reading of the data.
Figure 12. AD779 to ADSP-2100A Interface
Figure 13. Harm onic Distortion vs. Input Frequency
(0.5 dB Input)
Figure 11. AD779 to Z80 Interface
A useful feature of the Z80 is that a single wait state is automati-
cally inserted during I/O operations, allowing the AD779 to be
used with Z80 processors having clock speeds up to 8 MHz.
T he AD779 is asynchronous which allows conversions to be ini-
tiated by an external trigger source independent of the micro-
processor clock. After each conversion, the AD779 EOC signal
generates a DMA request to Channel 1 (DRQ1). T he subse-
quent DMA READ resets the interrupt latch. T he system de-
signer must assign a sufficient priority to the DMA channel to
ensure that the DMA request will be serviced before the com-
pletion of the next conversion. T his configuration can be used
with 6 MHz and 8 MHz 80186 processors.
Figure 14. Total Harm onic Distortion vs. Input Frequency
and Am plitude
AD 779 TO ANALO G D EVICES AD SP -2100A
Figure 12 demonstrates the AD779 interfaced to an ADSP-
2100A. With a clock frequency of 12.5 MHz, and instruction
REV. B
–11–
AD779
Figure 15. S/(N+D) vs. Input Frequency and Am plitude
Figure 16. 5-Plot Averaged 2048-Point FFT at 128 kSPS,
flN = 10.009 kHz
Figure 18. Power Supply Rejection (fIN = 10 kHz,
Figure 17. Nonaveraged IMD Plot for fIN = 9.08 kHz (fa),
9.58 kHz (fb) at 128 kSPS
f
SAMPLE = 128 kSPS, VRIPPLE = 0.1 V p-p)
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead P lastic D IP P ackage (N-28)
28-Lead Ceram ic D IP P ackage (D -28)
–12–
REV. B
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