AD7801 [ADI]

+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC; +2.7 V至+5.5 V ，并行输入，电压输出8位DAC


型号：	AD7801
厂家：	ADI
描述：	+2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC +2.7 V至+5.5 V ，并行输入，电压输出8位DAC
文件：	总16页 (文件大小：221K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

+2.7 V to +5.5 V, Parallel Input,

Voltage Output 8-Bit DAC

AD7801

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

Single 8-Bit DAC

20-Pin SOIC/ TSSOP Package

+2.7 V to +5.5 V Operation

Internal and External Reference Capability

DAC Pow er-Dow n Function

Parallel Interface

On-Chip Output Buffer Rail-to-Rail Operation

Low Pow er Operation 1.75 m A m ax @ 3.3 V

Pow er-Dow n to 1 ␮A m ax @ 25؇C

INPUT

DAC

I DAC

MUX

I/V

OUT

POWER-ON

RESET

CONTROL

LOGIC

÷2

AGND

AD7801

REFIN

DGND

CLR

LDAC

APPLICATIONS

Portable Battery Pow ered Instrum ents

Digital Gain and Offset Adjustm ent

Program m able Voltage and Current Sources

Program m able Attenuators

GENERAL D ESCRIP TIO N

P RO D UCT H IGH LIGH TS

1. Low Power, Single Supply operation. T his part operates

from a single +2.7 V to +5.5 V supply and consumes typically

5 mW at 3 V, making it ideal for battery powered applications.

T he AD7801 is a single, 8-bit, voltage out DAC that operates

from a single +2.7 V to +5.5 V supply. Its on-chip precision output

buffer allows the DAC output to swing rail to rail. T he AD7801

has a parallel microprocessor and DSP compatible interface with

high speed registers and double buffered interface logic. Data is

loaded to the input register on the rising edge of CS or WR.

2. T he on-chip output buffer amplifier allows the output of the

DAC to swing rail to rail with a settling time of typically 1.2 µs.

3. Internal or external reference capability.

4. High speed parallel interface.

Reference selection for the AD7801 can be either an internal

reference derived from the V_DDor an external reference applied

at the REFIN pin. T he output of the DAC can be cleared by

using the asynchronous CLR input.

5. Power-down capability. When powered down the DAC

consumes less than 1 µA at 25°C.

6. Packaged in 20-lead SOIC and T SSOP packages.

T he low power consumption of this part makes it ideally suited

to portable battery operated equipment. T he power consump-

tion is less than 5 mW at 3.3 V, reducing to less than 3 µW in

power-down mode.

T he AD7801 is available in a 20-lead SOIC and a 20-lead

T SSOP package.

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

(V = +2.7 V to +5.5 V, Internal Reference; C = 100 pF, R = 10 k⍀ to V and GND.

All specifications T_MINto T_MAXunless otherwise noted.)

AD7801–SPECIFICATIONS

P aram eter

B Versions¹

Units

Conditions/Com m ents

ST AT IC PERFORMANCE

Resolution

Bits

Relative Accuracy²

Differential Nonlinearity

Zero-Code Error @ +25°C

Full-Scale Error

±1

–0.75

100

±1

LSB max

LSB typ

µV/°C typ

% FSR typ

Guaranteed Monotonic

All Zeros Loaded to DAC Register

All Ones Loaded to DAC Register

Zero-Code Error Drift

Gain Error³

DAC REFERENCE INPUT

REFIN Input Range

REFIN Input Impedance

1 to V_DD/2

V min/V max

MΩ typ

OUT PUT CHARACT ERIST ICS

Output Voltage Range

Output Voltage Settling T ime

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

0 to V_DD

7.5

0.2

V min/V max

µs max

V/µs typ

nV-s typ

Ω typ

T ypically 1.2 µs

1 LSB Change Around Major Carry

DC Output Impedance

Short Circuit Current

0.0003

mA typ

%/% max

Power Supply Rejection Ratio⁴

∆V_DD= ±10%

LOGIC INPUT S

Input Current

±10

0.8

0.6

2.4

2.1

µA max

V max

V min

pF max

V_INL, Input Low Voltage

V_INH, Input High Voltage

Pin Capacitance

V_DD= +5 V

V_DD= +3 V

V_DD= +5 V

V_DD= +3 V

POWER REQUIREMENT S

V_DD

I_DD(Normal Mode)

V_DD= 3.3 V

@ 25°C

T _MINto T_MAX

V_DD= 5.5 V

@ 25°C

T _MINto T_MAX

I_DD(Power-Down)

@ 25°C

2.7/5.5

V min/V max

DAC Active and Excluding Load Current

V_IH= V_DDand V_IL= GND

See Figure 6

1.55

1.75

mA max

2.35

2.5

mA max

µA max

V_IH= V_DDand V_IL= GND

See Figure 18

T _MINto T_MAX

NOT ES

¹T emperature ranges are as follows: B Version: –40°C to +105°C

²Relative Accuracy is calculated using a reduced code range of 15 to 245.

³Gain Error is specified between Codes 15 and 245. T he actual error at Code 15 is typically 3 LSB.

⁴Guaranteed by characterization at product release, not production tested.

Specifications subject to change without notice.

t₁

t₂

t₃

t₄

t₅

D7-D0

t₆

t₇

LDAC

CLR

t₈

Figure 1. Tim ing Diagram for Parallel Data Write

–2–

REV. 0

AD7801

(V = +2.7 V to +5.5 V; GND = 0 V; Internal V /2 Reference. All specifications T to T

MAX

unless otherwise noted.)

MIN

1, 2

TIMING CHARACTERISTICS

Lim it at T_MIN, T_MAX

(B Version)

P aram eter

Units

Conditions/Com m ents

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

ns min

Chip Select to Write Setup T ime

Chip Select to Write Hold T ime

Write Pulse Width

Data Setup T ime

Data Hold T ime

Write to LDAC Setup T ime

LDAC Pulse Width

CLR Pulse Width

4.5

NOT ES

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of

(V_IL+ V_IH)/2. tr and tf should not exceed 1 µs on any digital input.

²See Figure 1.

ABSO LUTE MAXIMUM RATINGS*

O RD ERING GUID E

(T _A= +25°C unless otherwise noted)

Tem perature

Range

P ackage

O ption*

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Reference Input Voltage to AGND . . . . –0.3 V to V_DD+ 0.3 V

Digital Input Voltage to DGND . . . . . . –0.3 V to V_DD+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V_OUTto AGND . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range

Model

AD7801BR

AD7801BRU

–40°C to +105°C

R-20

RU-20

*R = Small Outline; RU = T hin Shrink Small Outline.

Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 700 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C/W

Lead T emperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 870 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W

Lead T emperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T his is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7801 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

AD7801

P IN CO NFIGURATIO N

(MSB) DB7

DB6

DGND

OUT

DB5

DB4

AGND

REFIN

DB3

AD7801

TOP VIEW

(Not to Scale)

DB2

DB1

CLR

(LSB) DB0

LDAC

WR 10

DGND

NC = NO CONNECT

P IN FUNCTIO N D ESCRIP TIO NS

P in

No.

Mnem onic

Function

1–8

D7–D0

Parallel Data Inputs. 8-bit data is loaded to the input register of the AD7801 under the control of CS and WR.

Chip Select. Active low logic input.

Write Input. WR is an active low logic input used in conjunction with CS to write data to the input register.

Digital Ground

DGND

Active low input used to put the part into low power mode reducing current consumption to less than 1 µA.

LDAC

Load DAC Logic Input. When this logic input is taken low the DAC output is updated with the contents of

its DAC register. If LDAC is permanently tied low the DAC is updated on the rising edge of WR.

CLR

Asynchronous Clear Input (Active Low). When this input is taken low the DAC register is loaded with all

zeroes and the DAC output is cleared to zero volts.

V_DD

Power Supply Input. T his part can be operated from +2.7 V to +5.5 V and should be decoupled to GND.

REFIN

External Reference Input. T his can be used as the reference for the DAC. T he range on this reference input is

1 V to V_DD/2. If REFIN is tied directly to V_DDthe internal V_DD/2 reference is selected.

AGND

Analog Ground reference point and return point for all analog current on the part.

No Connect Pin.

V_OUT

Analog Output Voltage from the DAC. T he output amplifier can swing rail to rail on its output.

Digital Ground reference point and return point for all digital current on the part.

DGND

REV. 0

–4–

Typical Performance Characteristics–

AD7801

4.92

4.84

4.76

4.68

4.6

800

720

640

560

480

400

320

240

160

3.5

3.25

3.0

= 5V AND 3V

INTERNAL REFERENCE

= +25 C

DAC LOADED WITH 00HEX

2.75

2.5

2.25

2.0

4.52

4.44

4.36

4.28

4.2

= 5V

= 3V

1.75

1.5

INTERNAL REFERENCE

DAC REGISTER LOADED

WITH FFHEX

INTERNAL REFERENCE

DAC REGISTER LOADED

WITH FFHex

= +25°C

1.25

1.0

= +25°C

SOURCE CURRENT – mA

SINK CURRENT – mA

SOURCE CURRENT – mA

Figure 2. Output Sink Current Capa-

bility with V_DD= 3 V and V_DD= 5 V

Figure 3. Output Source Current

Capability with V_DD= 5 V

Figure 4. Output Source Current

Capability with V_DD= 3 V

0.5

4.0

INTERNAL REFERENCE

DAC ACTIVE

INTERNAL REFERENCE

= 5V

= +25 C

0.45

0.4

LOGIC INPUTS = V OR GND

3.5

3.0

DAC ACTIVE

= +25°C

3.0

LOGIC INPUTS = V OR V

0.35

0.3

2.5

2.0

INL ERROR

0.25

0.2

= 5.5V

2.0

1.0

1.5

1.0

0.15

0.1

LOGIC INPUTS = V OR GND

= 3.3V

DNL ERROR

0.5

0.05

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

REFERENCE VOLTAGE – Volts

100

–50

–25

125

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE –

– Volts

Figure 5. Relative Accuracy vs.

External Reference

Figure 6. Typical Supply Current

vs. Tem perature

Figure 7. Typical Supply Current

vs. Supply Voltage

←

–5

←

–10

–15

–20

–25

OUT

←

OUT

= 3V

OUT

= 5V

←

INTERNAL VOLTAGE

REFERENCE

FULL SCALE CODE

CHANGE 00H-FFH

–30

–35

–40

EXTERNAL SINEWAVE REFERENCE

DAC REGISTER LOADED WITH FFHEX

AD7801 POWER-UP TIME

= 5V

= +25°C

INTERNAL REFERENCE

DAC IN POWER-DOWN INITIALLY

←

= +25°C

100

10k

FREQUENCY – Hz

CH1 = 2V/div, CH2 = 5V/Div,

TIME BASE = 2 µs/Div

CH1 5V, CH2 1V, CH3 20mV

TIME BASE = 200 ns/Div

Figure 10. Exiting Power-Down (Full

Power-Down)

Figure 9. Full-Scale Settling Tim e

Figure 8. Large Scale Signal

Frequency Response

REV. 0

–5–

AD7801–Typical Performance Characteristics

= 5V

←

INTERNAL VOLTAGE

REFERENCE

10 LSB STEP CHANGE

VDD = 2.7 TO 5.5V

DAC LOADED WITH ALL ZEROES

INTERNAL REFERENCE

= +25؇C

OUT

←

CH1 5.00V, CH2 50.0mV, M 250ns

M20.0ms

CH1

5.00V CH2 5.00V

CH1

–50 –25

100 125

TEMPERATURE –

Figure 11. Power-On—Reset

Figure 12. Zero Code Error vs.

Tem perature

Figure 13. Sm all-Scale Settling Tim e

0.5

0.4

0.3

0.5

0.4

0.3

0.2

= 5V

0.4

INTERNAL REFERENCE

5kΩ 100pF LOAD

LIMITED CODE RANGE (15–245)

0.3

0.2

0.1

= +25°C

0.2

0.1

= 5V

INTERNAL REFERENCE

= 5V

0.1

INTERNAL REFERENCE

–0.1

–0.2

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.3

–0.4

–0.5

64 96 128 160 192 224 256

INPUT CODE (15 to 245)

–60 –40 –20

20 40 60 80 100 120 140

–60 –40 –20

20 40 60 80 100 120 140

TEMPERATURE –

TEMPERATURE – C

Figure 14. Integral Linearity Plot

Figure 15. Typical INL vs. Tem perature

Figure 16. Typical DNL vs. Temperature

1000

1.0

= 5V

LOGIC INPUTS = V

900

= 5V

OR GND

800

700

600

500

0.8

0.6

0.4

400

300

200

0.2

100

–50

–25

100 150

–60 –40 –20

20 40 60 80 100 120 140

TEMPERATURE –

Figure 17. Typical Internal Reference

Error vs. Tem perature

Figure 18. Power-Down Current vs.

Tem perature

REV. 0

–6–

AD7801

TERMINO LO GY

Integr al Nonlinear ity

AD7801

REFERENCE

AMPLIFIER

11.7kΩ

For the DAC, Relative Accuracy or End-Point nonlinearity is a

measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

function. A graphical representation of the transfer curve is

shown in Figure 14.

30kΩ

CURRENT

DAC

REFIN

I/V

OUT

11.7kΩ

D iffer ential Nonlinear ity

Differential Nonlinearity is the difference between the mea-

sured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of ±1 LSB

maximum ensures monotonicity.

Figure 19. DAC Architecture

T he DAC output is internally buffered and has rail-to-rail

Zer o-Code Er r or

output characteristics. T he output amplifier is capable of driving

a load of 100 pF and 10 kΩ to both V_DDand ground. T he

reference selection for the DAC can be either internally gener-

ated from V_DDor externally applied through the REFIN pin. A

comparator on the REFIN pin detects whether the required

reference is the internally generated reference or the externally

applied voltage to the REFIN pin. If REFIN is connected to

Zero-Code Error is the measured output voltage from V_OUTof

the DAC when zero code (all zeros) is loaded to the DAC

latch. It is due to a combination of the offset errors in the DAC

and output amplifier. Zero-code error is expressed in LSBs.

Gain Er r or

T his is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from ideal

expressed as a percent of the full-scale value. It includes full-

scale errors but not offset errors.

V_DD, the reference selected is the internally generated V_DD/2

reference. When an externally applied voltage is more than one

volt below V_DD, the comparator selection switches to the externally

applied voltage on the REFIN pin. T he range on the external

reference input is from 1.0 V to V_DD/2 V. T he output voltage

from the DAC is given by:

D igital-to-Analog Glitch Im pulse

Digital-to-Analog Glitch Impulse is the impulse injected into

the analog output when the digital inputs change state with

the DAC selected and the LDAC used to update the DAC. It

is normally specified as the area of the glitch in nV-secs and

measured when the digital input code is changed by 1 LSB at

the major carry transition.

V_O= 2V_REF

256

where V_REFis the voltage applied to the external REFIN pin or

_DD/2 when the internal reference is selected. N is the decimal

D igital Feedthr ough

equivalent of the code loaded to the DAC register and ranges

from 0 to 255.

Digital Feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital inputs of the same

DAC, but is measured when the DAC is not updated. It is

specified in nV-secs and measured with a full-scale code change

on the data bus, i.e., from all 0s to all 1s and vice versa.

VTH

PMOS

P ower Supply Rejection Ratio (P SRR)

T his specification indicates how the output of the DAC is affected

by changes in the power supply voltage. Power supply rejection

ratio is quoted in terms of % change in output per % change in

V_DDfor full-scale output of the DAC. V_DDis varied ±10%.

COMPARATOR

INT REF

REF

EXT REF

MUX

INT

REF

GENERAL D ESCRIP TIO N

D /A Section

The AD7801 is an 8-bit voltage output digital-to-analog con-

verter. T he architecture consists of a reference amplifier and a

current source DAC followed by a current-to-voltage converter

capable of generating rail-to-rail voltages on the output of the

DAC. Figure 19 shows a block diagram of the basic DAC

architecture.

SELECTED REFERENCE

OUTPUT

Figure 20. Reference Selection Circuitry

REV. 0

–7–

AD7801

Autom atic Update Mode

Refer ence

In this mode of operation the LDAC signal is permanently tied

low. T he state of the LDAC is sampled on the rising edge of

WR. LDAC being low allows the DAC register to be automati-

cally updated on the rising edge of WR. T he output update

occurs on the rising edge of WR. Figure 23 shows the timing

associated with the automatic update mode of operation and

also the status of the various registers during this frame.

T he AD7801 has the ability to use either an external reference

applied through the REFIN pin or an internal reference generated

from V_DD. Figure 20 shows the reference input arrangement

where either the internal V_DD/2 or the externally applied reference

can be selected.

T he internal reference is selected by tying the REFIN pin to

V_DD. If an external reference is to be used, this can be directly

applied to the REFIN pin and if this is 1 V below V_DD, the

internal circuitry will select this externally applied reference as

the reference source for the DAC.

D igital Inter face

T he AD7801 contains a fast parallel interface allowing this

DAC to interface to industry standard microprocessors,

microcontrollers and DSP machines. T here are two modes in

which this parallel interface can be configured to update the

DAC output. T he synchronous update mode allows synchro-

nous updating of the DAC output; the automatic update mode

allows the DAC to be updated individually following a write

cycle. Figure 21 shows the internal logic associated with the

digital interface. T he PON ST RB signal is internally generated

from the power-on reset circuitry and is low during the power-

on reset phase of the power up procedure.

D7-D0

LDAC = 0

TRACK

HOLD

I/P REG (MLE)

HOLD

DAC REG (SLE)

TRACK

OUT

Figure 23. Tim ing and Register Arrangem ent for Auto-

m atic Update Mode

CLR

Synchr onous Update Mode

CLR

In this mode of operation the LDAC signal is used to update the

DAC output to synchronize with other updates in the system.

T he state of the LDAC is sampled on the rising edge of WR. If

LDAC is high, the automatic update mode is disabled and the

DAC latch is updated at any time after the write by taking

LDAC low. T he output update occurs on the falling edge of

LDAC. LDAC must be taken back high again before the next

data transfer takes place. Figure 24 shows the timing associated

with the synchronous update mode of operation and also the

status of the various registers during this frame.

PON STRB

MLE

SLE

CLEAR

SET SLE

LDAC

DAC CONTROL

LOGIC

ENABLE

Figure 21. Logic Interface

T he AD7801 has a double buffered interface, which allows for

synchronous updating of the DAC output. Figure 22 shows a

block diagram of the register arrangement within the AD7801.

D7-D0

DB7-DB0

UPPER

NIBBLE

LDAC

TRACK

HOLD

I/P REG (MLE)

HOLD

DAC REG (SLE)

TRACK

HOLD

LOWER

NIBBLE

OUT

MLE

SLE

Figure 24. Tim ing and Register Arrangem ent for Synchro-

nous Update Mode

LDAC

CLR

CONTROL LOGIC

Figure 22. Register Arrangem ent

REV. 0

–8–

AD7801

P O WER-O N RESET

256

V_O= 2 ×V_REF

T he AD7801 has a power-on reset circuit designed to allow

output stability during power up. T his circuit holds the DAC in

a reset state until a write takes place to the DAC. In the reset

state all zeros are latched into the input register of the DAC and

the DAC register is in transparent mode thus the output of the

DAC is held at ground potential until a write takes place to the

DAC. T he power-on reset circuitry generates a PON ST RB

signal which is a gating signal used within the logic to identify

a power-on condition.

where:

is the decimal equivalent of the binary input

code. N ranges from 0 to 255.

V_REFis the voltage applied to the external REFIN pin

when the external reference is selected and is V_DD/2

if the internal reference is used.

Table I. O utput Voltage for Selected Input Codes

P O WER-D O WN FEATURES

T he AD7801 has a power-down feature implemented by

exercising the external PD pin. An active low signal puts the

complete DAC into power-down mode. When in power-down,

the current consumption of the device is reduced to less than

1 µA max at +25°C or 2 µA max over temperature, making the

device suitable for use in portable battery powered equipment.

T he internal reference resistors, the reference bias servo loop,

the output amplifier and associated linear circuitry are all shut

down when the power-down is activated. T he output terminal

sees a load of ≈ 23 kΩ to GND when in power-down mode as

shown in Figure 25. T he contents of the data register are

unaffected when in power-down mode. T he device typically

comes out of power-down in 13 µs (see Figure 10).

D igital

MSB . . . LSB

Analog O utput

255

256

1111 1111

1111 1110

2 ×

×V_REF

254

256

129

256

1000 0001

1000 0000

V_REF

127

256

0111 1111

2 ×

×V_REF

11.7kΩ

V_REF

0000 0001

0000 0000

256

0 V

DAC

REF

11.7kΩ

REF

Figure 25. Output Stage During Power-Down

Analog O utputs

The AD7801 contains a voltage output DAC with 8-bit resolution

and rail-to-rail operation. T he output buffer provides a gain of

two at the output. Figures 2, 3 and 4 show the source and sink

capabilities of the output amplifier. T he slew rate of the output

amplifier is typically 7.5 V/µs and has a full-scale settling to

eight bits with a 100 pF capacitive load in typically 1.2 µs.

DAC INPUT CODE 00 01

7F 80 81

FE FF

T he input coding to the DAC is straight binary. T able I shows

the binary transfer function for the AD7801. Figure 26 shows

the DAC transfer function for binary coding. Any DAC output

voltage can be expressed as:

Figure 26. DAC Transfer Function

REV. 0

–9–

AD7801

MICRO P RO CESSO R INTERFACING

AD 7801–AD SP -2101/AD SP -2103 Inter face

Figure 29 shows an interface between the AD7801 and the ADSP-

2101/ADSP-2103. T he fast interface timing associated with the

AD7801 allows easy interface to the ADSP-2101/ADSP-2103.

Figure 27 shows a typical setup for the AD7801 when using its

internal reference. T he internal reference is selected by tying the

REFIN pin to V_DD. Internally in the reference section there is a

reference detect circuit that will select the internal V_DD/2 based

on the voltage connected to the REFIN pin. If REFIN is within

a threshold voltage of a PMOS device (approximately 1 V) of

V_DDthe internal reference is selected. When the REFIN voltage

is more than 1 V below V_DD, the externally applied voltage at

this pin is used as the reference for the DAC. T he internal

reference on the AD7801 is V_DD/2, the output current to

voltage converter within the AD7801 provides a gain of two.

T hus the output range of the DAC is from 0 V to V_DD, based on

T able I.

LDAC is permanently tied low in this circuit so the DAC

output is updated on the rising edge of the WR signal.

Data is loaded to the AD7801 input register using the following

ADSP-21xx instruction.

DM(DAC) = MR0

MR0 = ADSP-21xx MR0 Register.

DAC = Decoded DAC Address.

= 3V TO 5V

DMA14

ADDRESS BUS

0.1␮F

10␮F

DMA0

AD7801*

ADDR

DECODE

DMS

AGND DGND

REF IN

ADSP-2101*/

ADSP-2103*

OUT

LDAC

AD7801

OUT

CLR

CS WR LDAC

D7-D0

DB7

DB0

DATA BUS

CONTROL

INPUTS

DMD15

DMD0

DATA BUS

Figure 27. Typical Configuration Selecting the Internal

Reference

*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.

Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface

Figure 28 shows a typical setup for the AD7801 when using an

external reference. T he reference range for the AD7801 is from

1 V to V_DD/2 V. Higher values of reference can be incorporated

but will saturate the output at both the top and bottom end of

the transfer function. There is a gain of two from input to output

on the AD7801. Suitable references for 5 V operation are the

AD780 and REF192. For 3 V operation a suitable external

reference would be the AD589 a 1.23 V bandgap reference.

AD 7801–TMS320C20 Inter face

Figure 30 shows an interface between the AD7801 and the

T MS320C20. Data is loaded to the AD7801 using the following

instruction:

OUT DAC, D

DAC = Decoded DAC Address.

D = Data Memory Address.

= 3V TO 5V

A15

ADDRESS BUS

0.1␮F

10␮F

AD7801*

AGND DGND

EXT REF

GND

ADDR

DECODE

OUT

REF IN

OUT

TMS320C20

AD7801

OUT

CLR

LDAC

STRB

AD780/REF192 WITH V = 5V

LDAC

D7-D0

R/W

AD589 WITH V = 3V

DB7

DB0

DATA BUS

CONTROL

INPUTS

D15

DATA BUS

Figure 28. Typical Configuration Using An External

Reference

ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.

Figure 30. AD7801–TMS320C20 Interface

REV. 0

–10–

AD7801

In the circuit shown the LDAC is hardwired low thus the DAC

output is updated on the rising edge of WR. Some applications

may require synchronous updating of the DAC in the AD7801.

In this case the LDAC signal can be driven from an external

timer or can be controlled by the microprocessor. One option

for synchronous updating is to decode the LDAC from the ad-

dress bus so a write operation at this address will synchronously

update the DAC output. A simple OR gate with one input

driven from the decoded address and the second input from the

WR signal will implement this function.

= 3V TO 5V

20kΩ

0.1␮F

10␮F

10kΩ

+5V

AD820/

OP295

AGND DGND

EXT REF

GND

±5V

OUT

REF IN

OUT

0.1␮F

–5V

AD7801

CLR

10kΩ

AD780/REF192

WITH V = 5V

WR LDAC

D7-D0

20kΩ

AD589 WITH V = 3V

AD 7801–8051/8088 Inter face

Figure 31 shows a serial interface between the AD7801 and the

8051/8088 processors.

DATA

BUS

CONTROL

INPUTS

Figure 32. Bipolar Operation Using the AD7801

A15

D ecoding Multiple AD 7801s in a System

ADDRESS BUS

T he CS pin on the AD7801 can be used in applications to

decode a number of DACs. In this application, all DACs in the

system receive the same input data, but only the CS to one of

the DACs will be active at any one time allowing access to one

channel in the system. T he 74HC139 is used as a two-to-four

line decoder to address any of the DACs in the system. T o

prevent timing errors from occurring, the Enable input on the

74HC139 should be brought to its inactive state while the

Coded Address inputs are changing state. Figure 33 shows a

diagram of a typical setup for decoding multiple AD7801

devices in a system. T he built-in power-on reset circuit on the

AD7801 ensures that the outputs of all DACs in the system

power up with zero volts on their outputs.

AD7801*

ADDR

DECODE

PSEN OR DEN

8051/8088*

ALE

LDAC

OCTAL

LATCH

DB7

DB0

AD7

AD0

DATA BUS

ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.

Figure 31. AD7801–8051/8088 Interface

DATA BUS

AD7801

AP P LICATIO NS

OUT

Bipolar O per ation Using the AD 7801

T he AD7801 has been designed for unipolar operation but

bipolar operation is possible using the circuit in Figure 32. T he

circuit shown is configured for an output voltage range of –5 V

to +5 V. Rail-to-rail operation at the amplifier output is achievable

by using an AD820 or OP295 as the output amplifier.

LDAC

AD7801

1Y0

ENABLE

OUT

1Y1

1Y2

T he output voltage for any input code can be calculated as

follows:

CODED

ADDRESS

74HC139

LDAC

1Y3

DGND

2V_REF

V_O= R₂1+

/ R1+ R2 ×

−V_REF

(

)

256

AD7801

OUT

Where D is the decimal equivalent of the code loaded to the

DAC and V_REFis the reference voltage input.

LDAC

With V_REF= 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20 kΩ and

V_DD= 5 V.

AD7801

10D

256

V_O

–5

OUT

LDAC

Figure 33. Decoding Multiple AD7801s

REV. 0

–11–

AD7801

AD 7801 as a D igitally P r ogr am m able Indicator

= 5V

A digitally programmable upper limit detector using the DAC is

shown in Figure 34. T he upper limit for the test is loaded to the

DAC, which in turn sets the limit for the CMP04. If a signal at

the V_INinput is not below the programmed value, an LED will

indicate the Fail condition.

SOURCE

0.1µF

10µF

LOAD

+5V

EXT REF

GND

OUT

REF IN

OUT

0.1µF

2N3904/

BC107

AD820/

OP295

AD7801

+5V

AD780/ REF192

AGND DGND

0.1

WITH V = 5V

1kΩ

FAIL

PASS

4.7kΩ

REFIN

470Ω

AD7801

OUT

PASS/

Figure 35. Program m able Current Source

Coar se and Fine Adjustm ent using two AD 7801s

T he two DACs can be paired together to form a coarse and fine

adjustment function for a setpoint as shown in Figure 36. In this

circuit, the first DAC is used to provide the coarse adjustment

and the second DAC is used to provide the fine adjustment.

Varying the ratio of R1 and R2 will vary the relative effect of the

coarse and fine tune elements in the circuit. For the resistor

values shown, the second DAC has a resolution of 148 µV

giving a fine tune range of 38 mV (approximately 2 LSB) for

operation with a V_DDof 5 V and a reference of 2.5 V. T he

amplifier shown allows a rail-to-rail output voltage to be

achieved on the output. A typical application for the circuit

would be in a setpoint controller.

1/4

CMP-04

1/6

74HC05

DGND

AGND

Figure 34. Digitally Program m able Indicator

P r ogr am m able Cur r ent Sour ce

Figure 35 shows the AD7801 used as the control element of a

programmable current source. In this circuit the full-scale

current is set to 1 mA. T he output voltage from the DAC is

applied across the current setting resistor of 4.7 kΩ in series with

the full-scale setting resistor of 470 Ω. Suitable transistors to

place in the feedback loop of the amplifier include the BC107

and the 2N3904, which enable the current source to operate

from a minimum V_SOURCEof 6 V. T he operating range is

determined by the operating characteristics of the transistor.

Suitable amplifiers include the AD820 and the OP295, both of

which have rail-to-rail operation on their outputs. T he current

for any digital input code can be calculated as follows:

= 5V

390Ω

51.2kΩ

0.1µF

10µF

+5V

390Ω

AD820/

OP295

EXT REF

GND

OUT

REF IN

OUT

0.1µF

AD7801

AGND DGND

AD780/ REF192

WITH V = 5V

AD589 WITH V

= 3V

2 V

(

)

REF

I =

REF IN

256 (5 kΩ)

OUT

(

)

0.1µF

AD7801

51.2kΩ

AGND DGND

Figure 36. Coarse and Fine Adjustm ent

REV. 0

–12–

AD7801

P ower Supply Bypassing and Gr ounding

T he power supply lines of the AD7801 should use as large a

trace as possible to provide low impedance paths and reduce the

effects of glitches on the supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other parts of the board and should never be run near

reference inputs. Avoid crossover of digital and analog signals.

T races on opposite sides of the board should run at right angles

to each other. T his reduces the effect of feedthrough through

the board. A microstrip technique is by far the best, but not

always possible with a double-sided board. In this technique, the

component side of the board is dedicated to the ground plane

while signal traces are placed on the solder side.

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. T he printed circuit board on which the

AD7801 is mounted should be designed so that the analog and

digital sections are separated and confined to certain areas of the

board. If the AD7801 is in a system where multiple devices

require an AGND to DGND connection, the connection should

be made at one point only, a star ground point which should be

established as closely as possible to the AD7801. T he AD7801

should have ample supply bypassing of 10 µF in parallel with

0.1 µF located as close to the package as possible, ideally right

up against the device. T he 10 µF capacitors are the tantalum

bead type. T he 0.1 µF capacitors should have low Effective

Series Resistance (ESR) and Effective Series Inductance (ESI),

such as the common ceramic types, which provide a low

impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

REV. 0

–13–

AD7801

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

20-Lead Wide Body SO IC

(R-20)

0.5118 (13.00)

0.4961 (12.60)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

x 45°

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0138 (0.35)

20-Lead TSSO P

(RU-20)

0.260 (6.60)

0.252 (6.40)

0.006 (0.15)

0.002 (0.05)

PIN 1

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

8°

0°

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

REV. 0

–14–

–15–

–16–

AD7801 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E