AD783AQ [ADI]

Complete Very High Speed Sample-and-Hold Amplifier; 完整的超高速采样和保持放大器


型号：	AD783AQ
厂家：	ADI
描述：	Complete Very High Speed Sample-and-Hold Amplifier 完整的超高速采样和保持放大器放大器
文件：	总8页 (文件大小：134K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Complete Very High Speed

Sample-and-Hold Amplifier

AD783*

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

Acquisition Tim e to 0.01%: 250 ns Typical

Low Pow er Dissipation: 95 m W

Low Droop Rate: 0.02 ␮V/ ␮s

Fully Specified and Tested Hold Mode Distortion

Total Harm onic Distortion: –85 dB

Aperture J itter: 50 ps Maxim um

Internal Hold Capacitor

OUT

COMMON

S/H

Self-Correcting Architecture

8-Pin Mini Cerdip and SOIC Packages

AD783

NC = NO CONNECT

P RO D UCT D ESCRIP TIO N

P RO D UCT H IGH LIGH TS

T he AD783 is a high speed, monolithic sample-and-hold

amplifier (SHA). T he AD783 offers a typical acquisition time

of 250 ns to 0.01%. T he AD783 is specified and tested for hold

mode total harmonic distortion with input frequencies up to

100 kHz. T he AD783 is configured as a unity gain amplifier

and uses a patented self-correcting architecture that minimizes

hold mode errors and ensures accuracy over temperature. T he

AD783 is self-contained and requires no external components

or adjustments.

1. Fast acquisition time (250 ns), low aperture jitter (20 ps) and

fully specified hold mode distortion make the AD783 an

ideal SHA for sampling systems.

2. Low droop (0.02 µV/µs) and internally compensated hold

mode error result in superior system accuracy.

3. Low power (95 mW typical), complete functionality and

small size make the AD783 an ideal choice for a variety of

high performance applications.

4. T he AD783 requires no external components or adjustments.

T he AD783 retains the held value with a droop rate of 0.02 µV/

µs. Excellent linearity and hold mode dc and dynamic perfor-

mance make the AD783 ideal for high speed 12- and 14-bit

analog-to-digital converters.

5. T he AD783 is an excellent choice as a front-end SHA for

high speed analog-to-digital converters such as the AD671,

AD7586, AD674B, AD774B, AD7572 and AD7672.

T he AD783 is manufactured on Analog Devices’ ABCMOS

process which merges high performance, low noise bipolar

circuitry with low power CMOS to provide an accurate, high

speed, low power SHA.

6. Fully specified and tested hold mode distortion guarantees

the performance of the SHA in sampled data systems.

T he J grade device is specified for operation from 0°C to +70°C

and the A grade from –40°C to +85°C. T he J and A grades are

available in 8-pin cerdip and SOIC packages. T he military

temperature range version is specified for operation from –55°C

to +125°C and is available in an 8-pin cerdip package. For

details refer to the Analog Devices Military Products Databook or

AD783/883B data sheet.

*P r otected by U.S. P atent Num ber 4,962,325.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

AD783–SPECIFICATIONS

(T_MINto T_MAXwith V = +5 V ؎ 5%, V = –5 V ؎ 5%, C = pF, unless otherwise noted)

DC SPECIFICATIONS

AD 783J/A

Typ

P aram eter

Min

Max

Units

SAMPLING CHARACT ERIST ICS

Acquisition T ime

5 V Step to 0.01%

5 V Step to 0.1%

Small Signal Bandwidth

Full Power Bandwidth

250

200

375

350

MHz

HOLD CHARACT ERIST ICS

Effective Aperture Delay (+25°C)

Aperture Jitter (+25°C)

Hold Settling (to 1 mV, +25°C)

Droop Rate

–30

150

0.02

200

µV/µs

Feedthrough (+25°C)

(V_IN= ±2.5 V, 500 kHz)

–80

ACCURACY CHARACT ERIST ICS¹

Hold Mode Offset

Hold Mode Offset Drift

Sample Mode Offset

Nonlinearity

–5

±0.005

±0.03

µV/°C

% FS

200

±0.1

Gain Error

OUT PUT CHARACT ERIST ICS

Output Drive Current

Output Resistance, DC

T otal Output Noise (DC to 5 MHz)

Sampled DC Uncertainty

Hold Mode Noise (DC to 5 MHz)

Short Circuit Current

Source

0.6

Ω

µV rms

0.3

150

125

Sink

INPUT CHARACT ERIST ICS

Input Voltage Range

Bias Current

Input Impedance

Input Capacitance

–2.5

2.0

+2.5

250

100

MΩ

DIGIT AL CHARACT ERIST ICS

Input Voltage Low

Input Voltage High

0.8

µA

Input Current High (V_IN= 5 V)

POWER SUPPLY CHARACT ERIST ICS

Operating Voltage Range

Supply Current

+PSRR (+5 V ± 5%)

–PSRR (–5 V ± 5%)

±4.75

±5

9.5

±5.25

Power Consumption

175

T EMPERAT URE RANGE

Specified Performance (J)

Specified Performance (A)

–40

+70

+85

°C

NOT ES

¹Specified and tested over an input range of ±2.5 V.

Specifications subject to change without notice.

–2–

REV. A

AD783

HOLD MODE AC SPECIFICATIONS ^(Tto T_MAXwith V = +5 V ؎ 5%, V = –5 V ؎ 5%, C = 50 pF, unless otherwise noted)

MIN

AD 783J/A

Typ

P aram eter

Min

Max

Units

T OT AL HARMONIC DIST ORT ION

f_IN= 100 kHz

f_IN= 500 kHz

–85

–72

–80

SIGNAL-T O-NOISE AND DIST ORT ION

f_IN= 100 kHz

f_IN= 500 kHz

INT ERMODULAT ION DIST ORT ION

(F1 = 99 kHz, F2 = 100 kHz)

Second Order Products

–80

–85

T hird Order Products

NOT ES

¹f_INamplitude = 0 dB and f_SAMPLE= 300 kHz unless otherwise indicated.

Specifications subject to change without notice.

ABSO LUTE MAXIMUM RATINGS*

With

P IN CO NFIGURATIO N

Spec

Respect to

Min

Max Units

OUT

S/H

V_CC

V_EE

COM

–0.5

–6.5

–0.5

+6.5

+0.5

+6.5

AD783

TOP VIEW

Analog Input

Digital Input

Output Short Circuit to

Ground, V_CC, or V_EE

Maximum Junction

T emperature

Storage

COMMON

(Not to Scale)

Indefinite

–65

NC = NO CONNECT

+175 °C

+150 °C

Lead T emperature

(10 sec max)

+300 °C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD783 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

O RD ERING GUID E

Tem perature

P ackage

O ptions²

Model¹

Range

D escription

AD783JQ

AD783AQ

AD783JR

AD783AR

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

8-Pin Cerdip

8-Pin SOIC

Q-8

R-8

NOT ES

¹For details on grade and package offerings screened in accordance with MIL-ST D-883, refer to the

¹Analog Devices Military Products Databook or current AD783/883B data sheet.

²Q = Cerdip, R = SOIC.

REV. A

–3–

AD783–Typical Characteristics

10.0

1.0

V+

V–

0.1

0.01

0.001

100

125

150

100

10k

100k

TEMPERATURE –

FREQUENCY – Hz

Power Supply Rejection Ratio vs. Frequency

Droop Rate vs. Tem perature, V_IN= 0 V

200

150

300

100

250

–50

–100

–150

–200

200

–2.5

+2.5

INPUT STEP – V

INPUT VOLTAGE – V

Acquisition Tim e (to 0.01%) vs. Input Step Size

Bias Current vs. Input Voltage

–4–

REV. A

AD783

O utput D r ive Cur r ent—T he maximum current the SHA can

source (or sink) while maintaining a change in hold mode offset

of less than 2.5 mV.

D EFINITIO NS O F SP ECIFICATIO NS

Acquisition Tim e—T he length of time that the SHA must

remain in the sample mode in order to acquire a full-scale input

step to a given level of accuracy.

Signal-To-Noise and D istor tion (S/N+D ) Ratio—S/N+D is

the ratio of the rms value of the measured input signal to the

rms sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc. T he value for

S/N+D is expressed in decibels.

Sm all Signal Bandwidth—T he frequency at which the held

output amplitude is 3 dB below the input amplitude, under an

input condition of a 100 mV p-p sine wave.

Full P ower Bandwidth—T he frequency at which the held

output amplitude is 3 dB below the input amplitude, under an

input condition of a 5 V p-p sine wave.

Total H ar m onic D istor tion (TH D )—T HD is the ratio of the

rms sum of the first six harmonic components to the rms value

of the measured input signal and is expressed in decibels.

Effective Aper tur e D elay—T he difference between the switch

delay and the analog delay of the SHA channel. A negative

number indicates that the analog portion of the overall delay is

greater than the switch portion. T his effective delay represents

the point in time, relative to the hold command, that the input

signal will be sampled.

Inter m odulation D istor tion (IMD )—With inputs consisting

of sine waves at two frequencies, fa and fb, any device with

nonlinearities will create distortion products, of order (m+n), at

sum and difference frequency of mfa±nfb, where m, n = 0, 1, 2,

3. . . . Intermodulation terms are those for which m or n is not

equal to zero. For example, the second order terms are (fa+fb)

and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),

(fa+2fb) and (fa–2fb). T he IMD products are expressed as the

decibel ratio of the rms sum of the measured input signals to the

rms sum of the distortion terms. T he two signals are of equal

amplitude, and peak value of their sums is –0.5 dB from full

scale. T he IMD products are normalized to a 0 dB input signal.

Aper tur e Jitter—T he variations in aperture delay for

successive samples. Aperture jitter puts an upper limit on the

maximum frequency that can be accurately sampled.

H old Settling Tim e—T he time required for the output to

settle to within a specified level of accuracy of its final held value

after the hold command has been given.

D r oop Rate—T he drift in output voltage while in the hold

mode.

FUNCTIO NAL D ESCRIP TIO N

T he AD783 is a complete, high speed sample-and-hold

amplifier that provides high speed sampling to 12-bit accuracy

in 250 ns.

Feedthr ough—T he attenuated version of a changing input

signal that appears at the output when the SHA is in the hold

mode.

T he AD783 is completely self-contained, including an on-chip

hold capacitor, and requires no external components or adjust-

ments to perform the sampling function. Both input and output

are treated as a single-ended signal, referred to common.

H old Mode O ffset—T he difference between the input signal

and the held output. T his offset term applies only in the hold

mode and includes the error caused by charge injection and all

other internal offsets. It is specified for an input of 0 V.

T he AD783 utilizes a proprietary circuit design which includes a

self-correcting architecture. T his sample-and-hold circuit

corrects for internal errors after the hold command has been

given, by compensating for amplifier gain and offset errors, and

charge injection errors. Due to the nature of the design, the

SHA output in the sample mode is not intended to provide an

accurate representation of the input. However, in hold mode,

the internal circuitry is reconfigured to produce an accurately

held version of the input signal. Below is a block diagram of the

AD783.

Sam ple Mode O ffset—T he difference between the input and

output signals when the SHA is in the sample mode.

Nonlinear ity—T he deviation from a straight line on a plot of

input vs. (held) output as referenced to a straight line drawn

between endpoints, over an input range of –2.5 V and +2.5 V.

Gain Er r or—Deviation from a gain of +1 on the transfer

function of input vs. held output.

P ower Supply Rejection Ratio—A measure of change in the

held output voltage for a specified change in the positive or

negative supply.

OUT

Sam pled D C Uncer tainty—T he internal rms SHA noise that

is sampled onto the hold capacitor.

COMMON

S/H

H old Mode Noise—T he rms noise at the output of the SHA

while in the hold mode, specified over a given bandwidth.

Total O utput Noise—T he total rms noise that is seen at the

output of the SHA while in the hold mode. It is the rms

summation of the sampled dc uncertainty and the hold mode

noise.

AD783

NC = NO CONNECT

Functional Block Diagram

REV. A

–5–

AD783

D YNAMIC P ERFO RMANCE

HOLD – V ), mV

OUT

T he AD783 is compatible with 12-bit A-to-D converters in

terms of both accuracy and speed. T he fast acquisition time, fast

hold settling time and good output drive capability allow the

AD783 to be used with high speed, high resolution A-to-D

converters like the AD671 and AD7586. T he AD783’s fast

acquisition time provides high throughput rates for multichannel

data acquisition systems. T ypically, the AD783 can acquire a

5 V step in less than 250 ns. Figure 1 shows the settling

accuracy as a function of acquisition time.

, VOLTS

+2.5

–2.5

NONLINEARITY

0.08

HOLD MODE OFFSET

–1

GAIN ERROR

0.06

0.04

Figure 2. Hold Mode Offset, Gain Error and Nonlinearity

0.02

For applications where it is important to obtain zero offset, the

hold mode offset may be nulled externally at the input to the

A-to-D converter. Adjustment of the offset may be accom-

plished through the A-to-D itself or by an external amplifier

with offset nulling capability (e.g., AD711). T he offset will

change less than 0.5 mV over the specified temperature range.

250

500

ACQUISITION TIME – ns

Figure 1. V_OUTSettling vs. Acquisition Tim e

T he hold settling determines the required time, after the hold

command is given, for the output to settle to its final specified

accuracy. T he typical settling behavior of the AD783 is 150 ns.

T he settling time of the AD783 is sufficiently fast to allow the

SHA, in most cases, to directly drive an A-to-D converter

without the need for an added “start convert” delay.

SUP P LY D ECO UP LING AND GRO UND ING

CO NSID ERATIO NS

As with any high speed, high resolution data acquisition system,

the power supplies should be well regulated and free from

excessive high frequency noise (ripple). T he supply connection

to the AD783 should also be capable of delivering transient

currents to the device. T o achieve the specified accuracy and

dynamic performance, decoupling capacitors must be placed

directly at both the positive and negative supply pins to com-

mon. Ceramic type 0.1 µF capacitors should be connected from

V_CCand V_EEto common.

H O LD MO D E O FFSET

T he dc accuracy of the AD783 is determined primarily by the

hold mode offset. T he hold mode offset refers to the difference

between the final held output voltage and the input signal at the

time the hold command is given. T he hold mode offset arises

from a voltage error introduced onto the hold capacitor by

charge injection of the internal switches. T he nominal hold

mode offset is specified for a 0 V input condition. Over the in-

put range of –2.5 V to +2.5 V, the AD783 is also characterized

for an effective gain error and nonlinearity of the held value, as

shown in Figure 2. As indicated by the AD783 specifications,

the hold mode offset is very stable over temperature.

ANALOG

P.S.

DIGITAL

P.S.

+5V

–5V

+5V

0.1µF 0.1µF

1µF

INPUT

DIGITAL

DATA

OUTPUT

ANALOG-TO-DIGITAL

CONVERTER

AD783

SIGNAL GROUND

Figure 3. Basic Grounding and Decoupling Diagram

–6–

REV. A

AD783

T he AD783 does not provide separate analog and digital ground

leads as is the case with most A-to-D converters. T he common

pin is the single ground terminal for the device. It is the refer-

ence point for the sampled input voltage and the held output

voltage and also the digital ground return path. T he common

pin should be connected to the reference (analog) ground of the

A-to-D converter with a separate ground lead. Since the analog

and digital grounds in the AD783 are connected internally, the

common pin should also be connected to the digital ground,

which is usually tied to analog common at the A-to-D converter.

Figure 3 illustrates the recommended decoupling and grounding

practice.

T he accuracy in sampling high frequency signals is also

constrained by the distortion and noise created by the

sample-and-hold. T he level of distortion increases with

frequency and reduces the “effective number of bits” of the

conversion.

Measurements of Figures 6 and 7 were made using a 14-bit

A/D converter with V_IN= 5 V p-p and a sample frequency of

100 kSPS.

1/2 BIT @

8 BITS

NO ISE CH ARACTERISTICS

Designers of data conversion circuits must also consider the

effect of noise sources on the accuracy of the data acquisition

system. A sample-and-hold amplifier that precedes the A-to-D

converter introduces some noise and represents another source

of uncertainty in the conversion process. T he noise from the

AD783 is specified as the total output noise, which includes

both the sampled wideband noise of the SHA in addition to the

band limited output noise. T he total output noise is the rms

sum of the sampled dc uncertainty and the hold mode noise. A

plot of the total output noise vs. the equivalent input bandwidth

of the converter being used is given in Figure 4.

0.1%

1/2 BIT @

10 BITS

1/2 BIT @

12 BITS

APERTURE JITTER TYPICAL AT 20ps

0.01%

1/2 BIT @

14 BITS

10k

100k

FREQUENCY – Hz

300

200

100

Figure 5. Error Magnitude vs. Frequency

–65

–70

–75

–80

–85

–90

10k

100k

10M

FREQUENCY – Hz

–95

100

10k

100k

Figure 4. RMS Noise vs. Input Bandwidth of ADC

FREQUENCY – Hz

D RIVING TH E ANALO G INP UTS

Figure 6. Total Harm onic Distortion vs. Frequency

For best performance, it is important to drive the AD783 analog

input from a low impedance signal source. T his enhances the

sampling accuracy by minimizing the analog and digital cross-

talk. Signals which come from higher impedance sources (e.g.,

over 5 kΩ) will have a relatively higher level of crosstalk. For

applications where signals have high source impedance, an

operational amplifier buffer in front of the AD783 is required.

T he AD711 (precision BiFET op amp) is recommended for

these applications.

H IGH FREQ UENCY SAMP LING

Aperture jitter and distortion are the primary factors which limit

frequency domain performance of a sample-and-hold amplifier.

Aperture jitter modulates the phase of the hold command and

produces an effective noise on the sampled analog input. T he

magnitude of the jitter induced noise is directly related to the

frequency of the input signal.

10k

100k

FREQUENCY – Hz

A graph showing the magnitude of the jitter induced error vs.

frequency of the input signal is given in Figure 5.

Figure 7. Signal/(Noise and Distortion) vs. Frequency

REV. A

–7–

AD783

AD 783 TO AD 670 INTERFACE

T he low going one-shot output is connected to the clock input

of flip-flop2. T he D2 input of flip-flop2 is tied high. T he rising

edge of the low going pulse toggles the Q2 output of flip-flop2 to

a high state. T his output, which is tied to the ENCODE input of

the AD671, initiates a conversion of the buffered output signal

of the AD783. T he AD671 issues the signal DAV when the con-

version is complete. T he DAV signal is tied to the asynchronous

CLR1 and CLR2 inputs of both flip-flops. When DAV goes low,

the Q1 output goes high returning the AD783 to the sample or

acquisition mode. T he Q2 output (ENCODE) returns low until

it is again triggered by the rising edge of the one-shot output.

T he 15 MHz small signal bandwidth of the AD783 makes it a

good choice for undersampling applications. Figure 8 shows

the interface between the AD783 and the AD670 ADC, where

the AD783 samples the incoming IF signal. For this particular

application, the IF carrier was 10.7 MHz and the information

signal was a 5 kHz FSK-modulated tone. T he sample-and-hold

signal is applied to the 8-bit AD670 ADC and then digitally

processed for analysis.

T he CLKIN signal is connected directly to the S/H pin of the

AD783 and must comply with the acquisition and settling re-

quirements of the SHA. A delayed version of CLKIN is applied

to the R/W input of the AD670 in order to accommodate the

hold-mode settling requirements of the AD783. T he 10 µs con-

version speed of the AD670 combined with the 150 ns hold-

mode settling time of the AD783 result in a total system

throughput of 10.15 µs.

AD783

AIN

AD84X

AD671

CLOCK

CLR1

CLR2

By keeping the 10.7 MHz IF input to the AD783 at a low

amplitude, 255 mV p-p, the resultant distortion and jitter-

induced noise result in approximately 45 dB of dynamic range.

T he AD670 can be conveniently configured such that its full-

scale input range is 255 mV in order to retain the full 8-bit

dynamic range of the converter. T he maximum sample rate of

the AD670 is 10 µs; therefore, to comply with the Nyquist

criteria the maximum information bandwidth is 50 kHz.

+5V

DAV

ONE-

SHOT

ENCODE

Figure 9. AD783 to AD671 Interface

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

8-P in Cerdip (Q-8) P ackage

10k

ANALOG

INPUT

AD783

18 +V HI

10.7MHz

+V LOW

255mV p-p

0.310 (7.87)

0.220 (5.59)

–V HI

CLK IN

–V LOW

AD670

0.320 (8.13)

0.290 (7.37)

0.405 (10.29)

MAX

ONE -

SHOT

21 R/W

0.060 (1.52)

0.015 (0.38)

0.200

(5.08)

MAX

Figure 8. AD783 to AD670 Interface

0.150

(3.81)

MIN

0.015 (0.381)

0.008 (0.204)

AD 783 to AD 671 (12-Bit, 500 ns AD C) Inter face

T he AD783 to AD671 interface requires an op amp, a dual

flip-flop, and a monostable multivibrator or “one-shot.” T he

op amp amplifies the ±2.5 V output of the AD783 to the

full-scale input of the AD671. Appropriate op amps include the

AD841 and AD845 (see the AD671 data sheet for additional

information). T he flip-flops and one-shot are used to generate

the AD671 ENCODE pulse and the appropriately timed

AD783 S/H pulse.

0.023 (0.58)

0.014 (0.36)

0.100 (2.54)

BSC

0.070 (1.78)

0.030 (0.76)

8-P in SO IC (R-8) P ackage

0.198 (5.03)

0.188 (4.77)

A master sampling clock is tied to the clock input of flip-flop1

and the input of the one-shot. T he D1 input of flip-flop1

should be tied high and the one-shot should be configured to

generate a pulse on a rising edge of the sampling clock. T he ris-

ing edge of the sampling clock causes the Q1 output of the

flip-flop to go low placing the AD783 into hold mode. Simulta-

neously, a low going pulse is generated at the one-shot output.

T he length of this pulse would usually be made long enough to

allow the output of the AD783 to settle (hold-mode settling

time), but because of the error-correcting ability of the AD671,

the length of this pulse may be reduced to approximately 200 ns.

0.158 (4.01)

0.150 (3.81)

0.248 (6.29)

0.224 (5.69)

0.022 (0.56)

0.014 (0.36)

0.205 (5.21)

0.195 (4.95)

0.050 (1.27)

BSC

0.107 (2.72)

0.089 (2.26)

0.011 (0.275)

0.005 (0.125)

0.034 (0.86)

0.018 (0.46)

0.015 (0.38)

0.007 (0.18)

–8–

REV. A

AD783AQ [ADI]

相关型号：

AD783AR

AD783JN

AD783JQ

AD783JR

AD783JRZ

AD783SQ

AD783SQ/883B

AD7840

AD7840ACHIPS

AD7840AQ

AD7840ARS

AD7840ARSZ