AD7840KP [ADI]
LC2MOS Complete 14-Bit DAC; LC2MOS完整的14位DAC
| 型号： | AD7840KP |
| 厂家： | 
ADI |
| 描述： | LC2MOS Complete 14-Bit DAC |
| 文件： | 总16页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
Complete 14-Bit DAC
a
AD7840
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete 14-Bit Voltage Output DAC
Parallel and Serial Interface Capability
80 dB Signal-to-Noise Ratio
Interfaces to High Speed DSP Processors
e.g., ADSP-2100, TMS32010, TMS32020
45 ns m in WR Pulse Width
Low Pow er – 70 m W typ.
Operates from ؎5 V Supplies
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7840 is a fast, complete 14-bit voltage output D/A con-
verter. It consists of a 14-bit DAC, 3 V buried Zener reference,
DAC output amplifier and high speed control logic.
1. Complete 14-Bit D/A Function
T he AD7840 provides the complete function for creating ac
signals and dc voltages to 14-bit accuracy. T he part features
an on-chip reference, an output buffer amplifier and 14-bit
D/A converter.
T he part features double-buffered interface logic with a 14-bit
input latch and 14-bit DAC latch. Data is loaded to the input
latch in either of two modes, parallel or serial. T his data is then
transferred to the DAC latch under control of an asynchronous
signal. A fast data setup time of 21 ns allows direct
parallel interfacing to digital signal processors and high speed
16-bit microprocessors. In the serial mode, the maximum serial
data clock rate can be as high as 6 MHz.
2. Dynamic Specifications for DSP Users
In addition to traditional dc specifications, the AD7840 is
specified for ac parameters including signal-to-noise ratio and
harmonic distortion. T hese parameters along with important
timing parameters are tested on every device.
3. Fast, Versatile Microprocessor Interface
T he analog output from the AD7840 provides a bipolar output
range of ±3 V. T he AD7840 is fully specified for dynamic per-
formance parameters such as signal-to-noise ratio and harmonic
distortion as well as for traditional dc specifications. Full power
output signals up to 20 kHz can be created.
T he AD7840 is capable of 14-bit parallel and serial interfac-
ing. In the parallel mode, data setup times of 21 ns and write
pulse widths of 45 ns make the AD7840 compatible with
modern 16-bit microprocessors and digital signal processors.
In the serial mode, the part features a high data transfer rate
of 6 MHz.
T he AD7840 is fabricated in linear compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
T he part is available in a 24-pin plastic and hermetic
dual-in-line package (DIP) and is also packaged in a 28-termi-
nal plastic leaded chip carrier (PLCC).
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = O V, REF IN = +3 V, R = 2 k⍀,
DD
SS
L
AD7840–SPECIFICATIONS
C = 100 pF. All specifications TMIN to TMAX unless othewise noted.)
L
P aram eter
J, A1
K, B1 S1
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal to Noise Ratio3 (SNR)
76
78
76
dB min
dB max
dB max
VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically 82 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically –84 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz Sine Wave, fSAMPLE = 100 kHz
T ypically –84 dB at +25°C for 0 < VOUT < 20 kHz4
T otal Harmonic Distortion (T HD) –78
Peak Harmonic or Spurious Noise –78
–80
–80
–78
–78
DC ACCURACY
Resolution
14
14
14
Bits
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
±2
±1
±2
LSB max
LSB max
LSB max
LSB max
LSB max
±0.9
±10
±10
±10
±0.9
±10
±10
±10
±0.9
±10
±10
±10
Guaranteed Monotonic
Positive Full Scale Error5
Negative Full Scale Error5
REFERENCE OUT PUT6
REF OUT @ +25°C
2.99
3.01
±60
2.99
3.01
±60
2.99
3.01
±60
V min
V max
ppm/°C max
REF OUT T C
Reference Load Change
(∆REF OUT vs. ∆I)
–1
–1
–1
mV max
Reference Load Current Change (0–500 µA)
3 V ± 5%
REFERENCE INPUT
Reference Input Range
2.85
3.15
50
2.85
3.15
50
2.85
3.15
50
V min
V max
µA max
Input Current
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN =VSS to VDD
V max
µA max
µA max
pF max
Input Current (
Input Only)
7
Input Capacitance, CIN
ANALOG OUT PUT
Output Voltage Range
DC Output Impedance
Short-Circuit Current
±3
0.1
20
±3
0.1
20
±3
0.1
20
V nom
Ω typ
mA typ
AC CHARACT ERIST ICS7
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Settling T ime to within ±1/2 LSB of Final Value
T ypically 2 µs
T ypically 2.5 µs
4
4
10
2
4
4
10
2
4
4
10
2
µs max
µs max
nV secs typ
nV secs typ
POWER REQUIREMENT S
VDD
VSS
IDD
ISS
+5
–5
14
6
+5
–5
14
6
+5
–5
15
7
V nom
V nom
mA max
mA max
mW max
±5% for Specified Performance
±5% for Specified Performance
Output Unloaded, SCLK = +5 V. T ypically 10 mA
Output Unloaded, SCLK = +5 V. T ypically 4 mA
T ypically 70 mW
Power Dissipation
100
100
110
NOT ES
1T emperature ranges are as follows: J, K Versions, 0°C to +70°C; A, B Versions, –25°C to +85°C; S Version, –55°C to +125°C.
2VOUT (pk-pk) = ±3 V
3SNR calculation includes distortion and noise components.
4Using external sample-and-hold (see T esting the AD7840).
5Measured with respect to REF IN and includes bipolar offset error.
6For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
AD7840
1, 2
TIMING CHARACTERISTICS
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V.)
DD
SS
Lim it at TMIN, TMAX
(J, K, A, B Versions)
Lim it at TMIN, TMAX
(S Version)
P aram eter
Units
Conditions/Com m ents
t1
t2
t3
t4
t5
t6
0
0
0
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
to
to
Setup T ime
Hold T ime
45
21
10
40
50
150
30
75
75
50
28
15
40
50
200
40
100
100
Pulse Width
Data Valid to
Data Valid to
Pulse Width
to SCLK Falling Edge
SCLK Cycle T ime
Data Valid to SCLK Setup T ime
Data Valid to SCLK Hold T ime
to SCLK Hold T ime
Setup T ime
Hold T ime
t73
t8
t9
t10
t11
NOT ES
1T iming specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 6 and 8.
3SCLK mark/space ratio is 40/60 to 60/40.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
Integral
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD
REF IN to AGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . . –25°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
Tem perature
Range
SNR
(dB)
Nonlinearity P ackage
(LSB)
Model1
O ption2
AD7840JN
AD7840KN
AD7840JP
AD7840KP
AD7840AQ
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
78 min ±2 max
80 min ±1 max
78 min ±2 max
80 min ±1 max
78 min ±2 max
78 min ±2 max
80 min ±1 max
N-24
N-24
P-28A
P-28A
Q-24
RS-24
Q-24
Q-24
AD7840ARS –25°C to +85°C
AD7840BQ
AD7840SQ3
–25°C to +85°C
–55°C to +125°C 78 min ±2 max
NOT ES
1T o order MIL-ST D-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet and availability.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
3T his grade will be available to /883B processing only.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7840 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD7840
P IN FUNCTIO N D ESCRIP TIO N
D IP
P in
No.
P in
Mnem onic
Function
Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used
1
/SERIAL
in conjunction with
to load parallel data to the input latch. For applications where
is perma-
nently low, an R, C is required for correct power-up (see
fines the AD7840 for serial mode operation.
input). If this input is tied to VSS, it de-
2
3
Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with
parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se-
rial data expected after the falling edge of this signal.
to load
D13/SDAT A
D12/SCLK
Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode,
SDAT A is the serial data input which is used in conjunction with
to the AD7840 input latch.
and SCLK to transfer serial data
4
5
Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is
the serial clock input. Serial data bits are latched on the falling edge of SCLK when is low.
D11/FORMAT Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic
1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates
that the LSB is the first valid bit (see T able I).
6
D10/JUST IFY
Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode,
this input controls the serial data justification (see T able I).
7–11
12
D9–D5
DGND
Data Bit 9 to Data Bit 5. Parallel data inputs.
Digital Ground. Ground reference for digital circuitry.
Data Bit 4 to Data Bit 1. Parallel data inputs.
Data Bit 0 (LSB). Parallel data input.
13–16 D4–D1
17
18
19
20
D0
VDD
Positive Supply, +5 V ± 5%.
AGND
VOUT
Analog Ground. Ground reference for DAC, reference and output buffer amplifier.
Analog Output Voltage. T his is the buffer amplifier output voltage. Bipolar output range (±3 V with REF
IN = +3 V).
21
22
VSS
Negative Supply Voltage, –5 V ± 5%.
REF OUT
Voltage Reference Output. T he internal 3 V analog reference is provided at this pin. T o operate the
AD7840 with internal reference, REF OUT should be connected to REF IN. T he external load capability
of the reference is 500 µA.
23
24
REF IN
Voltage Reference Input. T he reference voltage for the DAC is applied to this pin. It is internally buffered
before being applied to the DAC. T he nominal reference voltage for correct operation of the AD7840 is
3 V.
Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling
edge of this signal (see Interface Logic Information section). T he AD7840 should be powered-up with
high. For applications where
(see Figure 19).
is permanently low, an R, C is required for correct power-up
Table I. Serial D ata Modes
–4–
REV. B
AD7840
P IN CO NFIGURATIO NS
D IP /SSO P
P LCC
D /A SECTIO N
for external use, it should he decoupled to AGND with a 200 Ω
resistor in series with a parallel combination of a 10 µF tantalum
capacitor and a 0.1 µF ceramic capacitor.
T he AD7840 contains a 14-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. T he simplified cir-
cuit diagram for the DAC section is shown in Figure 1. T he
three MSBs of the data word are decoded to drive the seven
switches A–G. T he 11 LSBs switch an 11-bit R-2R ladder struc-
ture. T he output voltage from this converter has the same polar-
ity as the reference voltage, REF IN.
T he REF IN voltage is internally buffered by a unity gain ampli-
fier before being applied to the D/A converter and the bipolar
bias circuitry. T he D/A converter is configured and sealed for a
3 V reference and the device is tested with 3 V applied to REF
IN. Operating the AD7840 at reference voltages outside the
±5% tolerance range may result in degraded performance from
the part.
Figure 2. Internal Reference
EXTERNAL REFERENCE
In some applications, the user may require a system reference or
some other external reference to drive the AD7840 reference in-
put. Figure 3 shows how the AD586 5 V reference can be con-
ditioned to provide the 3 V reference required by the AD7840
REF IN. An alternate source of reference voltage for the
AD7840 in systems which use both a DAC and an ADC is to
use the REF OUT voltage of ADCs such as the AD7870 and
AD7871. A circuit showing this arrangement is shown in
Figure 20.
Figure 1. DAC Ladder Structure
INTERNAL REFERENCE
T he AD7840 has an on-chip temperature compensated buried
Zener reference (see Figure 2) which is factory trimmed to 3 V
±10 mV. T he reference voltage is provided at the REF OUT
pin. T his reference can be used to provide both the reference
voltage for the D/A converter and the bipolar bias circuitry. T his
is achieved by connecting the REF OUT pin to the REF IN pin
of the device.
T he reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. T he maximum recommended capacitance on REF
OUT for normal operation is 50 pF. If the reference is required
Figure 3. AD586 Driving AD7840 REF IN
REV. B
–5–
AD7840
O P AMP SECTIO N
Table II. Ideal Input/O utput Code Table
T he output from the voltage mode DAC is buffered by a
noninverting amplifier. Internal scaling resistors on the AD7840
configure an output voltage range of ±3 V for an input reference
voltage of +3 V. T he arrangement of these resistors around the
output op amp is as shown in Figure 1. T he buffer amplifier is
capable of developing ±3 V across a 2 kΩ and 100 pF load to
ground and can produce 6 V peak-to-peak sine wave signals to a
frequency of 20 kHz. T he output is updated on the falling edge
D AC Latch Contents
MSB LSB
Analog O utput, VO UT
*
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0
+2.999634 V
+2.999268 V
+0.000366 V
0 V
–0.000366 V
–2.999634 V
–3 V
of the
input. T he amplifier settles to within 1/2 LSB of
its final value in typically less than 2.5 µs.
T he small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. T he output noise from the ampli-
*Assuming REF IN = +3 V.
T he output voltage can be expressed in terms of the input code,
N, using the following expression:
fier is low with a figure of 30 nV/√
at a frequency of 1 kHz.
T he broadband noise from the amplifier exhibits a typical peak-
to-peak figure of 150 µV for a 1 MHz output bandwidth. Figure
4 shows a typical plot of noise spectral density versus frequency
for the output buffer amplifier and for the on-chip reference.
2 × N × REFIN
VOUT
=
− 8192 ≤ N ≤ +8191
16384
INTERFACE LO GIC INFO RMATIO N
T he AD7840 contains two 14-bit latches, an input latch and a
DAC latch. Data can be loaded to the input latch in one of two
basic interface formats. T he first is a parallel 14-bit wide data
word; the second is a serial interface where 16 bits of data are
serially clocked into the input latch. In the parallel mode,
and
is selected, data is loaded using the SCLK,
serial inputs. Data is transferred from the input latch to the
DAC latch under control of the signal. Only the data in
control the loading of data. When the serial data format
and SDAT A
the DAC latch determines the analog output of the AD7840.
P ar allel D ata For m at
T able III shows the truth table for AD7840 parallel mode op-
eration. T he AD7840 normally operates with a parallel input
data format. In this case, all 14 bits of data (appearing on data
inputs D13 (MSB) through D0 (LSB)) are loaded to the
Figure 4. Noise Spectral Density vs. Frequency
AD7840 input latch at the same time.
and
control the
loading of this data. T hese control signals are level-triggered;
therefore, the input latch can be made transparent by holding
both signals at a logic low level. Input data is latched into the in-
TRANSFER FUNCTIO N
T he basic circuit configuration for the AD7840 is shown in Fig-
ure 5. T able II shows the ideal input code to output voltage re-
lationship for this configuration. Input coding to the DAC is 2s
complement with 1 LSB = FS/16,384 = 6 V/16,384 = 366 µV.
put latch on the rising edge of
T he DAC latch is also level triggered. T he DAC output is nor-
mally updated on the falling edge of the signal. However,
both latches cannot become transparent at the same time.
or
.
T herefore, if
lows; with
transparent. When
is hardwired low, the part operates as fol-
low and
and
and
go low (with
high, the DAC latch is
still low),
the input latch becomes transparent but the DAC latch is dis-
abled. When or return high, the input latch is locked
out and the DAC latch becomes transparent again and the DAC
output is updated. T he write cycle timing diagram for parallel
data is shown in Figure 6. Figure 7 shows the simplified parallel
input control logic for the AD7840.
Figure 5. AD7840 Basic Connection Diagram
–6–
REV. B
AD7840
Table III. P arallel Mode Truth Table
Ser ial D ata For m at
T he serial data format is selected for the AD7840 by connecting
the /SERIAL line to –5 V. In this case, the
CS
WR
LDAC
Function
/
,
D13/SDAT A, D12/SCLK, D11/FORMAT and D10/JUST IFY
pins all assume their serial functions. T he unused parallel inputs
should not be left unconnected to avoid noise pickup. Serial
data is loaded to the input latch under control of SCLK,
and SDAT A. T he AD7840 expects a 16-bit stream of serial data
on its SDAT A input. Serial data must be valid on the falling
H
X
L
H
H
X
f
X
H
L
H
X
H
f
H
H
H
L
L
L
L
Both Latches Latched
}
Input Latch T ransparent
Input Latch Latched
DAC Latch T ransparent
}
Analog Output Updated
Input Latch T ransparent
edge of SCLK. T he
input provides the frame synchroni-
zation signal which tells the AD7840 that valid serial data will
be available for the next 16 falling edges of SCLK. Figure 8
shows the timing diagram for serial data format.
DAC Latch Data T ransfer Inhibited
L
g
g
L
L
Input Latch Is Latched
}
DAC Latch Data T ransfer Occurs
X = Don’t Care
Figure 6. Parallel Mode Tim ing Diagram
Figure 8. Serial Mode Tim ing Diagram
Although 16 bits of data are clocked into the AD7840, only 14
bits go into the input latch. T herefore, two bits in the stream are
don’t cares since their value does not affect the input latch data.
T he order and position in which the AD7840 accepts the 14 bits
of input data depends upon the FORMAT and JUST IFY in-
puts. T here are four different input data modes which can be
chosen (see T able I in the Pin Function Description section).
Figure 7. AD7840 Sim plified Parallel Input Control Logic
T he first mode (M1) assumes that the first two bits of the input
data stream are don’t cares, the third bit is the LSB and the last
(or 16th bit) is the MSB. T his mode is chosen by tying both the
FORMAT and JUST IFY pins to a logic 0. T he second mode
(M2; FORMAT = 0, JUST IFY = 1) assumes that the first bit in
the data stream is the LSB, the fourteenth bit is the MSB and
the last two bits are don’t cares. T he third mode (M3;
FORMAT = 1, JUST IFY 0) assumes that the first two bits in
the stream are again don’t cares, the third bit is now the MSB
and the sixteenth bit is the LSB. T he final mode (M4; FOR-
MAT = 1, JUST IFY= 1) assumes that the first bit is the MSB,
the fourteenth bit is the LSB and the last two bits of the stream
are don’t cares.
REV. B
–7–
AD7840
As in the parallel mode, the
signal controls the loading
this graph is 81.8 dB. It should be noted that the harmonics are
taken into account when calculating the SNR.
of data to the DAC latch. Normally, data is loaded to the DAC
latch on the falling edge of . However, if is held
low, then serial data is loaded to the DAC latch on the sixteenth
falling edge of SCLK. If goes low during the transfer of
serial data to the input latch, no DAC latch update takes place
on the falling edge of . If stays low until the serial
transfer is completed, then the update takes place on the six-
teenth falling edge of SCLK. If returns high before the
serial data transfer is completed, no DAC latch update takes
place. Figure 9 shows the simplified serial input control logic for
the AD7840.
Figure 10. AD7840 FFT Plot
Effective Num ber of Bits
T he formula given in (1) relates the SNR to the number of bits.
Rewriting the formula, as in (2) it is possible to get a measure of
performance expressed in effective number of bits (N).
SNR −1. 76
N =
(2)
6.02
Figure 9. AD7840 Sim plified Serial Input Control Logic
T he effective number of bits for a device can be calculated
directly from its measured SNR.
AD 7840 D YNAMIC SP ECIFICATIO NS
T he AD7840 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as integral and differential nonlinearity. T hese ac specifications
are required for the signal processing applications such as
speech synthesis, servo control and high speed modems. T hese
applications require information on the DAC’s effect on the
spectral content of the signal it is creating. Hence, the param-
eters for which the AD7840 is specified include signal-to-noise
ratio, harmonic distortion and peak harmonics. T hese terms are
discussed in more detail in the following sections.
H ar m onic D istor tion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7840, total harmonic distortion
(T HD) is defined as
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. T he T HD is also derived from the 2048-point
FFT plot.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
DAC. T he signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fs/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. T he theoretical signal to noise ratio for a sine wave out-
put is given by
P eak H ar m onic or Spur ious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the DAC output
spectrum (up to fs/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor the peak
will be a noise peak.
SNR = (6.02N + 1.76) dB
(1)
Testing the AD 7840
where N is the number of bits. T hus for an ideal 14-bit con-
verter, SNR = 86 dB.
A simplified diagram of the method used to test the dynamic
performance specifications is outlined in Figure 11. Data is
loaded to the AD7840 under control of the microcontroller and
associated logic at a 100 kHz update rate. T he output of the
AD7840 is applied to a ninth order, 50 kHz, low-pass filter. T he
output of the filter is in turn applied to a 16-bit accurate digi-
tizer. T his digitizes the signal and the microcontroller generates
an FFT plot from which the dynamic performance of the
AD7840 can be evaluated.
Figure 10 shows a typical 2048 point Fast Fourier T ransform
(FFT ) plot of the AD7840KN with an output frequency of
1 kHz and an update rate of 100 kHz. T he SNR obtained from
–8–
REV. B
AD7840
P er for m ance ver sus Fr equency
T he typical performance plots of Figures 13 and 14 show the
AD7840’s performance over a wide range of input frequencies
at an update rate of 100 kHz. T he plot of Figure 13 is without a
sample-and-hold on the AD7840 output while the plot of Figure
14 is generated with the sample-and-hold circuit of Figure 12 on
the output.
Figure 11. AD7840 Dynam ic Perform ance Test Circuit
T he digitizer sampling is synchronized with the AD7840 update
rate to ease FFT calculations. T he digitizer samples the
AD7840 after the output has settled to its new value. T herefore,
if the digitizer was to sample the output directly it would effec-
tively be sampling a dc value each time. As a result, the dynamic
performance of the AD7840 would not be measured correctly.
Using the digitizer directly on the AD7840 output would give
better results than the actual performance of the AD7840. Us-
ing a filter between the DAC and the digitizer means that the
digitizer samples a continuously moving signal and the true dy-
namic performance of the AD7840 is measured.
Some applications will require improved performance versus fre-
quency from the AD7840. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 12 will
extend the very good performance of the AD7840 to 20 kHz.
Figure 13. Perform ance vs. Frequency
(No Sam ple-and-Hold)
Figure 12. Sam ple-and-Hold Circuit
Other applications will already have an inherent sample-and-
hold function following the AD7840. An example of this type of
application is driving a switched-capacitor filter where the up-
dating of the DAC is synchronized with the switched-capacitor
filter. T his inherent sample-and-hold function also extends the
frequency range performance of the AD7840.
Figure 14. Perform ance vs. Frequency
(with Sam ple-and-Hold)
REV. B
–9–
AD7840
MICRO P RO CESSO R INTERFACING
T he AD7840 logic architecture allows two interfacing options
for interfacing the part to microprocessor systems. It offers a
14-bit wide parallel format and a serial format. Fast pulse
widths and data setup times allow the AD7840 to interface
directly to most microprocessors including the DSP processors.
Suitable interfaces to various microprocessors are shown in
Figures 15 to 23.
P ar allel Inter facing
Figures 15 to 17 show interfaces to the DSP processors, the
ADSP-2100, the T MS32010 and T MS32020. An external
timer controls the updating of the AD7840. Data is loaded to
the AD7840 input latch using the following instructions:
ADSP-2100: DM(DAC) = MR0
T MS32010: OUT DAC,D
T MS32020: OUT DAC,D
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
DAC = AD7840 Address
Figure 17. AD7840–TMS32020 Parallel Interface
Some applications may require that the updating of the AD7840
DAC latch be controlled by the microprocessor rather than the
external timer. One option (for double-buffered interfacing) is
to decode the AD7840
from the address bus so that a
write operation to the DAC latch (at a separate address than the
input latch) updates the output. An example of this is shown in
the 8086 interface of Figure 18. Note that connecting the
input to the
input will not load the DAC latch cor-
rectly since both latches cannot he transparent at the same time.
AD7840–8086 Interface
Figure 18 shows an interface between the AD7840 and the 8086
microprocessor. For this interface, the
input is derived
from a decoded address. If the least significant address line, A0,
is decoded then the input latch and the DAC latch can reside at
consecutive addresses. A move instruction loads the input latch
while a second move instruction updates the DAC latch and the
AD7840 output. T he move instruction to load a data word
WXYZ to the input latch is as follows:
Figure 15. AD7840–ADSP-2100 Parallel Interface
MOV DAC,# YZWX
DAC = AD7840 Address
Figure 16. AD7840–TMS32010 Parallel Interface
Figure 18. AD7840–8086 Parallel Interface
–10–
REV. B
AD7840
AD7840–68000 Interface
low so the update of the DAC latch and analog output takes
An interface between the AD7840 and the 68000 microproces-
sor is shown in Figure 19. In this interface example, the
input is hardwired low. As a result the DAC latch and analog
place on the sixteenth falling edge of SCLK (with
T he FORMAT pin of the AD7840 must be tied to +5 V and
the JUST IFY pin tied to DGND for this interface to operate
correctly.
low).
output are updated on the rising edge of
. A single move
instruction, therefore, loads the input latch and updates the output.
MOVE.W D0,$DAC
D0 = 68000 D0 Register
DAC = AD7840 Address
Figure 20. Com plete DAC/ADC Serial Interface
Figure 19. AD7840–MC68000 Parallel Interface
AD7840–DSP56000 Serial Interface
Ser ial Inter facing
A serial interface between the AD7840 and the DSP56000 is
shown in Figure 21. T he DSP56000 is configured for normal
mode synchronous operation with gated clock. It is also set up
for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a 0. SCK is internally generated on the
DSP56000 and applied to the AD7840 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK. T he SC2
output provides the framing pulse for valid data. T his line must
Figures 20 to 23 show the AD7840 configured for serial inter-
facing with the
input hardwired to –5 V. T he parallel bus is
not activated during serial communication with the AD7840.
AD7840–ADSP-2101/ADSP-2102 Serial Interface
Figure 20 shows a serial interface between the AD7840 and the
ADSP-2101/ADSP-2102 DSP processor. Also included in the
interface is the AD7870, a 12-bit A/D converter. An interface
such as this is suitable for modem and other applications which
have a DAC and an ADC in serial communication with a
microprocessor.
be inverted before being applied to the
AD7840.
input of the
T he
input of the AD7840 is connected to DGND so the
T he interface uses just one of the two serial ports of the
ADSP-2101/ADSP-2102. Conversion is initiated on the
AD7870 at a fixed sample rate (e.g., 9.6 kHz) which is provided
by a timer or clock recovery circuitry. While communication
takes place between the ADC and the ADSP-2101/ ADSP-2102,
update of the DAC latch takes place on the sixteenth falling
edge of SCLK. As with the previous interface, the FORMAT
pin of the AD7840 must be tied to +5 V and the JUST IFY pin
tied to DGND.
the AD7870
line is low. T his
line is used to
provide a frame synchronization pulse for the AD7840
and ADSP-2101/ADSP-2102 T FS lines. T his means that com-
munication between the processor and the AD7840 can only
take place while the AD7870 is communicating with the processor.
T his arrangement is desirable in systems such as modems where
the DAC and ADC communication should be synchronous.
T he use of the AD7870 SCLK for the AD7840 SCLK and
ADSP-2101/ADSP-2102 SCLK means that only one serial port
of the processor is used. T he serial clock for the AD7870 must
be set for continuous clock for correct operation of this interface.
Data from the ADSP-2101/ADSP-2102 is valid on the falling
Figure 21. AD7840–DSP56000 Serial Interface
edge of SCLK. T he
input of the AD7840 is permanently
REV. B
–11–
AD7840
AD7840–TMS32020 Serial Interface
AP P LYING TH E AD 7840
Figure 22 shows a serial interface between the AD7840 and the
T MS32020 DSP processor. In this interface, the CLKX and
FSX pin of the T MS32020 are generated from the clock/timer
circuitry. T he same clock/timer circuitry generates the
signal of the AD7840 to synchronize the update of the output
with the serial transmission. T he FSX pin of the T MS32020
must be configured as an input.
Good printed circuit board layout is as important as the overall
circuit design itself in achieving high speed converter perfor-
mance. T he AD7840 works on an LSB size of 366 µV. T here-
fore, the designer must be conscious of minimizing noise in both
the converter itself and in the surrounding circuitry. Switching
mode power supplies are not recommended as the switching
spikes can feed through to the on-chip amplifier. Other causes
of concern are ground loops and digital feedthrough from mi-
croprocessors. T hese are factors which influence any high per-
formance converter, and a proper PCB layout which minimizes
these effects is essential for best performance.
Data from the T MS32020 is valid on the falling edge of CLKX.
Once again, the FORMAT pin of the AD7840 must be tied to
+5 V while the JUST IFY pin must be tied to DGND.
LAYO UT H INTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog lines separated as much as possible. T ake care
not to run any digital track alongside an analog signal track. Es-
tablish a single point analog ground (star ground) separate from
the logic system ground. Place this star ground as close as pos-
sible to the AD7840 as shown in Figure 24. Connect all analog
grounds to this star ground and also connect the AD7840
DGND pin to this ground. Do not connect any other digital
grounds to this analog ground point.
Figure 22. AD7840–TMS32020 Serial Interface
AD7840–NEC7720 Serial Interface
A serial interface between the AD7840 and the NEC7720 is
shown in Figure 23. T he serial clock must be inverted before
being applied to the AD7840 SCLK input because data from
the processor is valid on the rising edge of SCK.
T he NEC7720 is programmed for the LSB to be the first bit in
the serial data stream. T herefore, the AD7840 is set up with the
FORMAT pin tied to DGND and the JUSTIFY pin tied to +5 V.
Figure 24. Power Supply Grounding Practice
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of high performance
converters. T herefore, the foil width for these tracks should be
kept as wide as possible. T he use of ground planes minimizes
impedance paths and also guards the analog circuitry from digi-
tal noise. T he circuit layouts of Figures 27 and 28 have both
analog and digital ground planes which are kept separated and
only joined at the star ground close to the AD7840.
NO ISE
Keep the signal leads on the VOUT signal and the signal return
leads to AGND as short as possible to minimize noise coupling.
In applications where this is not possible, use a shielded cable
between the DAC output and its destination. Reduce the
ground circuit impedance as much as possible since any poten-
tial difference in grounds between the DAC and its destination
device appears as an error voltage in series with the DAC output.
Figure 23. AD7840–NEC7720 Serial Interface
–12–
REV. B
AD7840
D ATA ACQ UISITIO N BO ARD
P O WER SUP P LY CO NNECTIO NS
Figure 25 shows the AD7840 in a data acquisition circuit. T he
corresponding printed circuit board (PCB) layout and silkscreen
are shown in Figures 26 to 28. T he board layout has three inter-
face ports: one serial and two parallel. One of the parallel ports
is directly compatible with the ADSP-2100 evaluation board
expansion connector.
T he PCB requires two analog power supplies and one 5 V digi-
tal supply. Connections to the analog supplies are made directly
to the PCB as shown on the silkscreen in Figure 26. T he con-
nections are labelled V+ and V– and the range for both of these
supplies is 12 V to 15 V. Connection to the 5 V digital supply is
made through any of the connectors (SKT 4 to SKT 6). T he
–5 V analog supply required by the AD7840 is generated from
a voltage regulator on the V– power supply input (IC5 in
Figure 25).
Some systems will require the addition of a re-construction filter
on the output of the AD7840 to complete the data acquisition
system. T here is a component grid provided near the analog
output on the PCB which may be used for such a filter or any
other output conditioning circuitry. T o facilitate this option,
there is a shorting plug (labeled LK1 on the PCB) on the analog
output track. If this shorting plug is used, the analog output
connects to the output of the AD7840; otherwise this shorting
plug can be omitted and a wire link used to connect the analog
output to the PCB component grid.
SH O RTING P LUG O P TIO NS
T here are eight shorting plug options which must be set before
using the board. T hese are outlined below:
LK1
Connects the analog output to SKT 1. T he analog
output may also be connected to a component grid
for signal conditioning.
T he board also contains a simple sample-and-hold circuit which
can be used on the output of the AD7840 to extend the very
good performance of the AD7840 over a wider frequency range.
A second wire link (labelled LK2 on the PCB) connects VOUT
(SKT 1) to either the output of this sample-and-hold circuit or
directly to the output of the AD7840.
LK2
Selects either the AD7840 VOUT or the sample-and-
hold output.
LK3
LK4
Selects either the internal or external reference.
Selects the decoded R/ and
T MS32020 interfacing.
inputs for
LK5
LK6
LK7
LK8
Configures the D11/FORMAT input.
Configures the D10/JUST IFY input.
Selects either the inverted or noninverted
Selects either parallel or serial interfacing.
INTERFACE CO NNECTIO NS
T here are two parallel connectors, labeled SKT 4 and SKT 6,
and one serial connector, labeled SKT 5. A shorting plug option
(LK8 in Figure 25) on the AD7840
ures the DAC for the appropriate interface (see Pin Function
Description).
.
/SERIAL input config-
CO MP O NENT LIST
SKT 6 is a 96-contact (3-row) Eurocard connector which is di-
rectly compatible with the ADSP-2100 Evaluation Board Proto-
type Expansion Connector. T he expansion connector on the
ADSP-2100 has eight decoded chip enable outputs labeled
IC1
IC2
IC3
IC4
IC5
IC6
AD7840 Digital-to-Analog Converter
AD711 Op Amp
ADG201HS High Speed Switch
74HC221 Monostable
79L05 Voltage Regulator
74HC02
to
.
is used to drive the AD7840
input
on the data acquisition board. T o avoid selecting on-board
sockets at the same time, LK6 on the ADSP-2100 board must
be removed. T he AD7840 and ADSP-2100 data lines are
aligned for left justified data transfer.
C1, C3, C5, C7,
SKT 4 is a 26-way (2-row) IDC connector. T his connector con-
tains the same signal contacts as SKT 6 and in addition contains
C11, C13, C15, C17
10 µF Capacitors
C2, C4, C6, C8,
C12, C14, C16, C18
decoded R/ and
T MS32020 interfacing. T his decoded
inputs which are necessary for
can be selected via
0.1 µF Capacitors
330 pF Capacitor
68 pF Capacitor
2.2 kΩ Resistors
15 kΩ Resistor
C9
LK4. T he pinout for this connector is shown in Figure 29.
C10
SKT 5 is a nine-way D-type connector which is meant for serial
interfacing only. T he evaluation board has the facility to invert
line via LK7. T his is necessary for serial interfacing be-
tween the AD7840 and DSP processors such as the DSP56000.
T he SKT 5 pinout is shown in Figure 30.
R1, R2
R3
RP1, RP2
100 kΩ Resistor Packs
LK1, LK2, LK3,
LK4, LK5, LK6,
LK7, LK8
SKT 1, SKT 2 and SKT 3 are three BNC connectors which pro-
vide connections for the analog output, the
input and an
Shorting Plugs
external reference input. T he use of an external reference is op-
tional; the shorting plug (LK3) connects the REF IN pin to ei-
ther this external reference or to the AD7840’s own internal
reference.
SKT 1, SKT 2, SKT 3
BNC Sockets
SKT 4
SKT 5
SKT 6
26-Contact (2-Row) IDC Connector
9-Contact D-T ype Connector
Wire links LK5 and LK6 connect the D11 and D10 inputs to
the data lines for parallel operation. In the serial mode, these
links allow the user to select the required format and justifica-
tion for serial data (see T able I).
96-Contact (3-Row) Eurocard
Connector
REV. B
–13–
AD7840
Figure 25. Data Acquisition Circuit Using the AD7840
Figure 26. PCB Silkscreen for Figure 25
–14–
REV. B
AD7840
Figure 27. PCB Com ponent Side Layout for Figure 25
Figure 28. PCB Solder Side Layout for Figure 25
–15–
REV. B
AD7840
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP (N-24)
Cer am ic D IP (D -24A)
Figure 29. SKT4, IDC Connector Pinout
Cer dip (Q -24)
Figure 30. SKT5, D-Type Connector Pinout
P LCC (P -28A)
–16–
REV. B
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