AD7845TQ883B [ADI]
LC2MOS Complete 12-Bit Multiplying DAC; LC2MOS完整的12位乘法DAC
| 型号： | AD7845TQ883B |
| 厂家： | 
ADI |
| 描述： | LC2MOS Complete 12-Bit Multiplying DAC |
| 文件： | 总12页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
a
Complete 12-Bit Multiplying DAC
AD7845
FUNCTIONAL BLOCK DIAGRAM
FEATURES
12-Bit CMOS MDAC with Output Amplifier
4-Quadrant Multiplication
Guaranteed Monotonic (TMIN to TMAX
)
Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface
Mount Packages
Application Resistors On Chip for Gain Ranging, etc.
Low Power LC2MOS
APPLICATIONS
Automatic Test Equipment
Digital Attenuators
Programmable Power Supplies
Programmable Gain Amplifiers
Digital-to-4–20 mA Converters
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7845 is the industry’s first 4-quadrant multiplying D/A
converter with an on-chip amplifier. It is fabricated on the
LC2MOS process, which allows precision linear components
and digital circuitry to be implemented on the same chip.
1. Voltage Output Multiplying DAC
The AD7845 is the first DAC which has a full 4-quadrant
multiplying capability and an output amplifier on chip. All
specifications include amplifier performance.
The 12 data inputs drive latches which are controlled by stan-
dard CS and WR signals, making microprocessor interfacing
simple. For stand-alone operation, the CS and WR inputs can
be tied to ground, making all latches transparent. All digital
inputs are TTL and 5 V CMOS compatible.
2. Matched Application Resistors
Three application resistors provide an easy facility for gain
ranging, voltage offsetting, etc.
3. Space Saving
The AD7845 saves space in two ways. The integration of the
output amplifier on chip means that chip count is reduced.
The part is housed in skinny 24-lead 0.3" DIP, 28-terminal
LCC and PLCC and 24-terminal SOIC packages.
The output amplifier can supply ±10 V into a 2 kΩ load. It is
internally compensated, and its input offset voltage is low due to
laser trimming at wafer level. For normal operation, RFB is tied
to VOUT, but the user may alternatively choose RA, RB or RC to
scale the output voltage range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD7845–SPECIFICATIONS1
(VDD = +15 V, ؎ 5%, VSS = –15 V, ؎ 5%, VREF = +10 V, AGND = DGND = O V,
VOUT connected to RFB. VOUT load = 2 k⍀, 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
J Version
K Version
A Version
B Version
S Version
T Version
Units
Test Conditions/Comments
ACCURACY
Resolution
Relative Accuracy
at +25°C
TMIN to TMAX
Differential Nonlinearity
Zero Code Offset Error
at +25°C
VREF
212
12
12
12
12
12
12
Bits
1 LSB =
= 2.4 mV
±1
±1
±1
±1/2
±3/4
±1
±1
±1
±1
±1/2
±3/4
±1
±1
±1
±1
±1/2
±3/4
±1
LSB max
LSB max
LSB max
All Grades Are Guaranteed
Monotonic over Temperature
DAC Register Loaded with
All 0s.
±2
±3
±1
±2
±2
±3
±1
±2
±2
±4
±1
±3
mV max
mV max
TMIN to TMAX
Offset Temperature Coefficient;
(∆Offset/∆Temperature)2
Gain Error
±5
±3
±6
±6
±7
±5
±2
±6
±6
±7
±5
±3
±6
±6
±7
±5
±2
±6
±6
±7
±5
±3
±6
±6
±7
±5
±2
±6
±6
±7
µV/°C typ
LSB max
LSB max
LSB max
LSB max
RFB, VOUT Connected
RC, VOUT Connected, VREF = +5 V
RB, VOUT Connected, VREF = +5 V
RA, VOUT Connected, VREF = +2.5 V
Gain Temperature Coefficient;
(∆Gain/∆Temperature)2
±2
±2
±2
±2
±2
±2
ppm of FSR/°C RFB, VOUT Connected
typ
REFERENCE INPUT
Input Resistance, Pin 17
8
16
8
16
8
16
8
16
8
16
8
16
kΩ min
kΩ max
Typical Input Resistance = 12 kΩ
APPLICATION RESISTOR
RATIO MATCHING
0.5
0.5
0.5
0.5
0.5
0 5
% max
Matching Between RA, RB, RC
Digital Inputs at 0 V and VDD
DIGITAL INPUTS
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN (Input Current)
2.4
0.8
±1
7
2.4
0.8
±1
7
2.4
0.8
±1
7
2.4
0.8
±1
7
2.4
0.8
±1
7
2.4
0.8
±1
7
V min
V max
µA max
pF max
CIN (Input Capacitance)2
POWER SUPPLY4
VDD Range
VSS Range
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
14.25/15.75
V min/V max
–14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/V max
Power Supply Rejection
∆Gain/∆VDD
∆Gain/∆VSS
IDD
±0.01
±0.01
6
±0.01
±0.01
6
±0.01
±0.01
6
±0.01
±0.01
6
±0.01
±0.01
6
±0.01
±0.01
6
% per % max
% per % max
mA max
VDD = +15 V ± 5%, VREF = –10 V
VSS = –15 V ± 5%.
VOUT Unloaded
ISS
4
4
4
4
4
4
mA max
VOUT Unloaded
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance and are not subject to test.
DYNAMIC PERFORMANCE
Output Voltage Settling Time
5
5
5
5
5
5
µs max
To 0.01% of Full-Scale Range
VOUT Load = 2 kΩ, 100 pF.
DAC Register Alternately Loaded
with All 0s and All 1s. Typically
2.5 µs at 25°C.
Slew Rate
Digital-to-Analog
Glitch Impulse
11
55
11
55
11
55
11
55
11
55
11
55
V/µs typ
nV–s typ
VOUT Load = 2 kΩ, 100 pF.
Measured with VREF = 0 V.
DAC Register Alternately Loaded
with All 0s and All 1s.
Multiplying Feedthrough
Error3
Unity Gain Small Signal
Bandwidth
5
5
5
5
5
5
mV p-p typ
kHz typ
VREF = ±10 V, 10 kHz Sine Wave
DAC Register Loaded with All 0s.
600
175
–90
600
175
600
175
600
175
600
175
600
175
VOUT, RFB Connected. DAC Loaded
with All 1s VREF = 100 mV p-p
Sine Wave.
VOUT, RFB Connected. DAC Loaded
with All 1s. VREF = 20 V p-p
Sine Wave. RL = 2 kΩ.
Full Power Bandwidth
kHz typ
Total Harmonic Distortion
OUTPUT CHARACTERISTICS5
Open Loop Gain
–90
85
–90
85
–90
85
–90
85
–90
85
dB typ
VREF = 6 V rms, 1 kHz Sine Wave.
85
dB min
VOUT, RFB Not Connected
VOUT = ±10 V, RL = 2 kΩ
RL = 2 kΩ, CL = 100 pF
RFB, VOUT Connected,
VOUT Shorted to AGND
Includes Noise Due to Output
Amplifier and Johnson Noise
of RFB
Output Voltage Swing
Output Resistance
Short Circuit Current @ +25°C
Output Noise Voltage
(0.1 Hz to 10 Hz) @ +25°C
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
±10
0.2
11
±10
0.2
11
±10
0.2
11
±10
0.2
11
±10
0.2
11
±10
0.2
11
V min
Ω typ
mA typ
2
2
2
2
2
2
µV rms typ
nV/√Hz typ
nV/√Hz typ
nV/√Hz typ
nV/√Hz typ
nV/√Hz typ
250
100
50
50
50
250
100
50
50
50
250
100
50
50
50
250
100
50
50
50
250
100
50
50
50
250
100
50
50
50
NOTES
1Temperature ranges are as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C.
2Guaranteed by design and characterization, not production tested.
3The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND).
4The device is functional with a power supply of ± 12 V.
5Minimum specified load resistance is 2 kΩ.
Specifications subject to change without notice.
–2–
REV. B
AD7845
TIMING CHARACTERISTICS1
(VDD = +15 V, ؎ 5%. VSS = –15 V, ؎ 5%. VREF = +10 V. AGND = DGND = O V.)
Limit at TMIN to TMAX
(All Versions)
Parameter
Units
Test Conditions/Comments
tCS
30
0
30
80
0
ns min
ns min
ns min
ns min
ns min
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Data Setup Time
Data Hold Time
tCH
tWR
tDS
tDH
NOTES
1Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature Range
(TA = +25°C unless otherwise stated)
Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
VREF to AGND . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRFB to AGND . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRA to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRB to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VRC to AGND . . . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . .VDD + 0.3 V, VSS – 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Power Dissipation (Any Package)
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect device
reliability. Only one Absolute Maximum Rating may be applied at any one time.
2VOUT may be shorted to AGND provided that the power dissipation of the
package is not exceeded.
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE1
t
t
CS
CH
5V
0V
Relative
Accuracy Package
@ +25؇C
CS
Temperature
Range
Model2
Option3
t
WR
AD7845JN
AD7845KN
AD7845JP
AD7845KP
AD7845JR
AD7845KR
AD7845AQ
AD7845BQ
AD7845AR
AD7845BR
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
N-24
N-24
P-28A
P-28A
R-24
R-24
Q-24
Q-24
R-24
R-24
Q-24
Q-24
E-28A
5V
0V
WR
t
t
DH
DS
5V
0V
DATA
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF +5V. t = t = 20ns.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
R
F
V
+ V
2
IH
IL
AD7845SQ/883B –55°C to +125°C ±1 LSB
AD7845TQ/883B –55°C to +125°C ±1/2 LSB
AD7845SE/883B
Figure 1. AD7845 Timing Diagram
–55°C to +125°C ±1 LSB
NOTES
1Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip
(Q-24) hermetic packages.
2To order MIL-STD-883, Class B processed parts, add /883B to part number.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
REV. B
–3–
AD7845
PIN CONFIGURATIONS
LCC
DIP, SOIC
PLCC
TERMINOLOGY
LEAST SIGNIFICANT BIT
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the analog weighting of 1 bit of the digital word in a
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in either pA-secs or
nV-secs depending upon whether the glitch is measured as a
VREF
DAC. For the AD7845, 1 LSB =
.
12
2
current or voltage. The measurement takes place with VREF
AGND.
=
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain error are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
DIGITAL FEEDTHROUGH
When the DAC is not selected (i.e., CS is high) high frequency
logic activity on the device digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
DIFFERENTIAL NONLINEARITY
MULTIPLYING FEEDTHROUGH ERROR
This is ac error due to capacitive feedthrough from the VREF
terminal to VOUT when the DAC is loaded with all 0s.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of +1 LSB max over
the operating temperature range ensures monotonicity.
OPEN-LOOP GAIN
Open-loop gain is defined as the ratio of a change of output
voltage to the voltage applied at the VREF pin with all 1s loaded
in the DAC. It is specified at dc.
GAIN ERROR
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer. See Figure 13.
UNITY GAIN SMALL SIGNAL BANDWIDTH
This is the frequency at which the magnitude of the small signal
voltage gain of the output amplifier is 3 dB below unity. The
device is operated as a closed-loop unity gain inverter (i.e.,
DAC is loaded with all 1s).
ZERO CODE OFFSET ERROR
This is the error present at the device output with all 0s loaded
in the DAC. It is due to the op amp input offset voltage and
bias current and the DAC leakage current.
OUTPUT RESISTANCE
This is the effective output source resistance.
TOTAL HARMONIC DISTORTION
This is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.
FULL POWER BANDWIDTH
Full power bandwidth is specified as the maximum frequency, at
unity closed-loop gain, for which a sinusoidal input signal will
produce full output at rated load without exceeding a distortion
level of 3%.
OUTPUT NOISE
This is the noise due to the white noise of the DAC and the
input noise of the amplifier.
–4–
REV. B
Typical Performance Characteristics–AD7845
Figure 2. Frequency Response, G = –1
Figure 3. Output Voltage Swing vs.
Resistive Load
Figure 4. Noise Spectral Density
Figure 6. Typical AD7845 Linearity
vs. Power Supply
Figure 7. Multiplying Feedthrough
Error vs. Frequency
Figure 5. THD vs. Frequency
80
70
60
50
40
30
20
10
0
–10
–20
0
2
4
6
8
10 12 14 16 18 20
TIME – s
Figure 8. Unity Gain Inverter Pulse
Response (Large Signal)
Figure 9. Unity Gain Inverter Pulse
Response (Small Signal)
Figure 10. Digital-to-Analog Glitch
Impulse (All 1s to All 0s Transition)
REV. B
–5–
AD7845
PIN FUNCTION DESCRIPTION (DIP)
Description
Pin
Mnemonic
1
2-11
12
13-14
15
VOUT
DB11–DB2
DGND
DB1–DB0
WR
Voltage Output Terminal
Data Bit 11 (MSB) to Data Bit 2
Digital Ground. The metal lid on the ceramic package is connected to this pin
Data Bit 1 to Data Bit 0 (LSB)
Write Input. Active low
16
17
18
19
20
21
CS
VREF
AGND
VSS
VDD
Chip Select Input. Active low
Reference Input Voltage which can be an ac or dc signal
Analog Ground. This is the reference point for external analog circuitry
Negative power supply for the output amplifier (nominal –12 V to +15 V)
Positive power supply (nominal +12 V to +15 V)
Application resistor. RA = 4 RFB
RA
22
23
RB
RC
Application resistor. RB = 2 RFB
Application resistor. RC = 2 RFB
24
RFB
Feedback resistor in the DAC. For normal operation this is connected to VOUT
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
CIRCUIT INFORMATION
Digital Section
Figure 11 is a simplified circuit diagram of the AD7845 input
control logic. When CS and WR are both low, the DAC latch is
loaded with the data on the data inputs. All the digital inputs
are TTL, HCMOS and +5 V CMOS compatible, facilitating
easy microprocessor interfacing. All digital inputs incorporate
standard protection circuitry.
An output amplifier and feedback resistor perform the current-
to-voltage conversion giving
V
OUT = – D × VREF
where D is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The amplifier can maintain ±10 V across a 2 kΩ load. It is inter-
nally compensated and settles to 0.01% FSR (1/2 LSB) in less
than 5 µs. The input offset voltage is laser trimmed at wafer
level. The amplifier slew rate is typically 11 V/µs, and the unity
gain small signal bandwidth is 600 kHz. There are three extra
on-chip resistors (RA, RB, RC) connected to the amplifier invert-
ing terminal. These are useful in a number of applications in-
cluding offset adjustment and gain ranging.
V
REF
R
R
R
Figure 11. AD7845 Input Control Logic
2R
S8
2R
2R
B
2R
A
2R
S9
2R
S0
2R
C
D/A Section
Figure 12 shows a simplified circuit diagram for the AD7845
D/A section and output amplifier.
I
OUT
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
AGND
SHOWN FOR ALL 1s ON DAC
Figure 12. Simplified Circuit Diagram for the AD7845 D/A
Section
–6–
REV. B
AD7845
UNIPOLAR BINARY OPERATION
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit for bipolar operation is shown in
Figure 14. Offset binary coding is used.
Figure 13 shows the AD7845 connected for unipolar binary
operation. When VIN is an ac signal, the circuit performs
2-quadrant multiplication. The code table for Figure 13 is given
in Table I.
The offset specification of this circuit is determined by the
matching of internal resistors RB and RC and by the zero code
offset error of the device. Gain error may be adjusted by varying
the ratio of R1 and R2.
To use this circuit without trimming and keep within the gain
error specifications, resistors R1 and R2 should be ratio
matched to 0.01%.
The code table for Figure 14 is given in Table II.
Figure 13. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7845
Binary Number In
DAC Register
Analog Output, VOUT
MSB
1111
LSB
1111
4095
1111
–VIN
4096
2048
1000
0000
0000
–VIN
= –1/2 VIN
4096
Figure 14. Bipolar Offset Binary Operation
1
Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 14
0000
0000
0000
0000
0001
0000
–VIN
0 V
4096
Binary Number In
DAC Register
Analog Output, VOUT
OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13
MSB
1111
LSB
1111
2047
Zero Offset Adjustment
1. Load DAC with all 0s.
2. Trim R3 until VOUT = 0 V.
1111
+VIN
2048
1
Gain Adjustment
1. Load DAC with all 1s.
1000
1000
0111
0000
0000
1111
0001
0000
1111
+VIN
2048
4095
0 V
.
2. Trim R1 so that VOUT = –VIN
4096
1
–VIN
In fixed reference applications, full scale can also be adjusted by
omitting R1 and R2 and trimming the reference voltage magni-
tude. For high temperature applications, resistors and potenti-
ometers should have a low temperature coefficient.
2048
2048
2048
0000
0000
0000
–VIN
= –VIN
REV. B
–7–
AD7845
APPLICATIONS CIRCUITS
PROGRAMMABLE CURRENT SOURCES
The AD7845 is ideal for designing programmable current
sources using a minimum of external components. Figures 16
and 17 are examples. The circuit of Figure 16 drives a program-
mable current IL into a load referenced to a negative supply.
Figure 17 shows the circuit for sinking a programmable current,
IL. The same set of circuit equations apply for both diagrams.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The AD7845 performs a PGA function when connected as in
Figure 15. In this configuration, the R-2R ladder is connected
in the amplifier feedback loop. RFB is the amplifier input resis-
tor. As the code decreases, the R-2R ladder resistance increases
and so the gain increases.
1
4095
4096
IL = I3 = I2 + I1
RDAC
D
D = 0 to
,
VOUT = –VIN
×
×
RFB
D ×|VIN
|
4095
4096
D = 0 to
,
I1 =
I2 =
IL =
=
1
RDAC
D
–VIN
RDAC
= –VIN
×
×
=
, since RFB = RDAC
RDAC
D
D ×|VIN
|
1
D ×|VIN
|
RFB
=
, since RFB = RDAC
R1
RDAC
R1
D ×|VIN
|
D ×|VIN
R1
|
+
RDAC
R1
1 +
D ×|VIN
R1
|
×
RDAC
Note that by making R1 much smaller than RDAC, the circuit
becomes insensitive to both the absolute value of RDAC and its
temperature variations. Now, the only resistor determining load
current IL is the sense resistor R1.
If R1 = 100 Ω, then the programming range is 0 mA to 100 mA,
and the resolution is 0.024 mA.
Figure 15. AD7845 Connected as PGA
As the programmed gain increases, the error and noise also
increase. For this reason, the maximum gain should be limited
to 256. Table III shows gain versus code.
Note that instead of using RFB as the input resistor, it is also
possible to use combinations of the other application resistors,
RA, RB and RC. For instance, if RB is used instead of RFB, the
gain range for the same codes of Table II now goes from l/2
to 128.
Table III. Gain and Error vs. Input Code for Figure 15
Digital Inputs
Gain
Error (%)
1111
1000
0100
0010
0001
0000
0000
0000
0000
1111
0000
0000
0000
0000
1000
0100
0010
0001
1111
0000
0000
0000
0000
0000
0000
0000
0000
4096/4095 ≈ 1
2
4
8
16
32
64
128
256
0.04
0.07
0.13
0.26
0.51
1.02
2.0
Figure 16. Programmable Current Source
4.0
8.0
–8–
REV. B
AD7845
Figure 18. 4–20 mA Current Loop
APPLICATION HINTS
Figure 17. Programmable Current Sink
4–20 mA CURRENT LOOP
General Ground Management: AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7845. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel be-
tween the AD7845 AGND and DGND pins (IN914 or
equivalent).
The AD7845 provides an excellent way of making a 4-20 mA
current loop circuit. This is basically a variation of the circuits
in Figures 16 and 17 and is shown in Figure 18. The application
resistor RA (Value 4R) produces the effective 4 mA offset.
IL = I3 = I2 + I1
Since I2 > I1,
2.5
2.5
VX
1
× RFB
+
× D × RFB
IL = –
=
×
4R
RDAC
156
156
Digital Glitches: When a new digital word is written into the
DAC, it results in a change of voltage applied to some of the
DAC switch gates. This voltage change is coupled across the
switch stray capacitance and appears as an impulse on the cur-
rent output bus of the DAC. In the AD7845, impulses on this
bus are converted to a voltage by RFB and the output amplifier.
The output voltage glitch energy is specified as the area of the
resulting spike in nV-seconds. It is measured with VREF con-
nected to analog ground and for a zero to full-scale input code
transition. Since microprocessor based systems generally have
noisy grounds which couple into the power supplies, the
AD7845 VDD and VSS terminals should be decoupled to signal
ground.
and since RDAC=RFB=R
2.5
4
1000
+ D × 2.5 ×
mA
IL =
156
= [4 + (16 × D)]mA, where D goes from 0 to 1 with
Digital Code
When D = 0 (Code of all 0s):
IL = 4 mA
When D = 1 (Code of all 1s):
IL = 20 mA
Temperature Coefficients: The gain temperature coefficient
of the AD7845 has a maximum value of 5 ppm/°C. This corre-
sponds to worst case gain shift of 2 LSBs over a 100°C tem-
perature range. When trim resistors R1 and R2 in Figure 13
are used to adjust full-scale range, the temperature coefficient
of R1 and R2 must be taken into account. The offset tempera-
ture coefficient is 5 ppm of FSR/°C maximum. This corre-
sponds to a worst case offset shift of 2 LSBs over a 100°C
temperature range.
The above circuit succeeds in significantly reducing the circuit
component count. Both the on-chip output amplifier and the
application resistor RA contribute to this.
The reader is referred to Analog Devices Application Note
“Gain Error and Gain Temperature Coefficient of CMOS Mul-
tiplying DACs,” Publication Number E630C-5-3/86.
REV. B
–9–
AD7845
MICROPROCESSOR INTERFACING
8-BIT MICROPROCESSOR SYSTEMS
16-BIT MICROPROCESSOR SYSTEMS
Figure 22 shows an interface circuit for the AD7845 to the
8085A 8-bit microprocessor. The software routine to load data
to the device is given in Table IV. Note that the transfer of the
12 bits of data requires two write operations. The first of these
loads the 4 MSBs into the 7475 latch. The second write opera-
tion loads the 8 LSBs plus the 4 MSBs (which are held by the
latch) into the DAC.
Figures 19, 20 and 21 show how the AD7845 interfaces to
three popular 16-bit microprocessor systems. These are the
MC68000, 8086 and the TM32010. The AD7845 is treated as
a memory-mapped peripheral to the processors. In each case, a
write instruction loads the AD7845 with the appropriate data.
The particular instructions used are as follows:
MC68000: MOVE
8086:
MOV
TMS32010: OUT
Figure 22. 8085A Interface
Table IV. Subroutine Listing for Figure 22
Figure 19. AD7845 to MC68000 Interface
2000 LOAD DAC: LXI
H,#3000 The H,L register pair
are loaded with latch
address 3000.
MVI
A,#“MS” Load the 4 MSBs of
data into accumulator.
MOV M,A
Transfer data from
accumulator to latch.
INR
MVI
L
Increment H,L pair to
AD7845 address.
A,#“LS” Load the 8 LSBs of
data into accumulator.
MOV M,A
Transfer data from
accumulator to DAC.
Figure 20. AD7845 to 8086 Interface
RET
End of routine.
Figure 21. TMS32010
–10–
REV. B
AD7845
Figure 23 and 24 are the interface circuits for the Z80 and
MC6809 microprocessors. Again, these use the same basic
format as the 8085A interface.
DIGITAL FEEDTHROUGH
In the preceding interface configurations, most digital inputs to
the AD7845 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be con-
stantly changing. The high frequency logic activity on the bus
can feed through the DAC package capacitance to show up as
noise on the analog output. To minimize this digital feedthrough
isolate the DAC from the noise source. Figure 25 shows an
interface circuit which uses this technique. All data inputs are
latched from the busy by the CS signal. One may also use other
means, such as peripheral interface devices, to reduce the digital
feedthrough.
Figure 23. AD7845 to Z80 Interface
Figure 25. AD7845 Interface Circuit Using Latches to
Minimize Digital Feedthrough
Figure 24. MC6809 Interface
REV. B
–11–
AD7845
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP
(N-24)
28-Terminal Leadless Ceramic Chip Carrier
(E-28A)
24-Lead Cerdip
(Q-24)
28-Terminal Plastic Leaded Chip Carrier
(P-28A)
24-Lead Ceramic DIP
(D-24A)
24-Lead SOIC
(R-24)
0.6141 (15.60)
0.5985 (15.20)
24
1
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
12
PIN 1
0.1043 (2.65)
0.0291 (0.74)
؋
45؇ 0.0926 (2.35)
0.0098 (0.25)
8؇
0؇
0.0500
(1.27)
BSC
SEATING
PLANE
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
–12–
REV. B
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