AD7846APZ [ADI]
LC2MOS 16-Bit Voltage Output DAC; LC2MOS 16位电压输出DAC
| 型号： | AD7846APZ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 16-Bit Voltage Output DAC |
| 文件： | 总24页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
16-Bit Voltage Output DAC
AD7846
FUNCTIONAꢀ BꢀOCK DIAGRAM
FEATURES
V
V
CC
DD
16-bit monotonicity over temperature
2 ꢀSBs integral linearity error
Microprocessor compatible with readback capability
Unipolar or bipolar output
Multiplying capability
ꢀow power (100 mW typical)
21
4
V
REF+
7
AD7846
R
R
R
R
R
6
5
R
IN
A2
A1
16
SEGMENT
SWITCH
MATRIX
V
A3
OUT
12-BIT DAC
12
23
CS
V
REF–
8
DAC LATCH
12
22
25
24
4
R/W
CONTROL
LOGIC
LDAC
CLR
I/O LATCH
9
10
3
20
V
DB15 DB0
DGND
SS
Figure 1.
GENERAꢀ DESCRIPTION
The AD7846 is a 16-bit DAC constructed with the Analog Devices,
Inc., LC2MOS process. It has VREF+ and VREF− reference inputs
and an on-chip output amplifier. These can be configured to
give a unipolar output range (0 V to +5 V, 0 V to +10 V) or
bipolar output ranges ( 5 V, 10 V).
W
to 00…000 or 10…000 depending on the state of R/ . This
means that the DAC output can be reset to 0 V in both the
unipolar and bipolar configurations.
The AD7846 is available in 28-lead plastic, ceramic, and PLCC
packages.
The DAC uses a segmented architecture. The four MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral
linearity results from tight matching between the input offset
voltages of the two buffer amplifiers.
PRODUCT HIGHꢀIGHTS
1. 16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature
makes the AD7846 ideal for closed-loop applications.
2. Readback
The ability to read back the DAC register contents
minimizes software routines when the AD7846 is used in
ATE systems.
In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor interface. There are
3. Power Dissipation
CS W LDAC
CLR
16 data I/O pins, plus control lines ( , R/
,
and
allow writing to and reading from the I/O latch.
This is the readback function, which is useful in ATE applications.
).
Power dissipation of 100 mW makes the AD7846 the
lowest power, high accuracy DAC on the market.
W
CS
R/ and
LDAC
allows simultaneous updating of DACs in a multi-DAC
CLR
system and the
line will reset the contents of the DAC latch
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved.
AD7846
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Stage................................................................................ 12
Unipolar Binary Operation........................................................... 13
Bipolar Operation........................................................................... 14
Multiplying Operation............................................................... 14
Position Measurement Application.............................................. 15
Microprocessor Interfacing........................................................... 16
AD7846-to-8086 Interface........................................................ 16
AD7846-to-MC68000 Interface ............................................... 16
Digital Feedthrough....................................................................... 17
Application Hints ........................................................................... 18
Noise ............................................................................................ 18
Grounding................................................................................... 18
Printed Circuit Board Layout ................................................... 18
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 22
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 10
Circuit Description......................................................................... 11
Digital Section............................................................................. 11
Digital-to-Analog Conversion.................................................. 11
REVISION HISTORY
4/10—Rev. F to Rev. G
Change to Figure 1 ........................................................................... 1
12/09—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 6
Deleted Other Output Voltage Ranges Section ............................ 9
Deleted Figure 20 and Table 5; Renumbered Sequentially ......... 9
Deleted Test Application Section and Figure 21 ........................ 10
Deleted Figure 29 to Figure 31...................................................... 14
Changes to Printed Circuit Board Layout Section..................... 18
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide .......................................................... 22
Rev. G | Page 2 of 24
AD7846
SPECIFICATIONS
VDD = +14.25 V to +15.75 V; VSS = −14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V. VOUT loaded with 2 kΩ, 1000 pF to 0 V; VREF+ = +5 V;
IN connected to 0 V. All specifications TMIN to TMAX, unless otherwise noted.
R
Table 1.
Parameter1
J, A Versions
K, B Versions
Unit
Test Conditions/Comments
RESOLUTION
16
16
Bits
UNIPOLAR OUTPUT
Relative Accuracy at +25°C
TMIN to TMAX
Differential Nonlinearity Error
Gain Error at +25°C
TMIN to TMAX
Offset Error at +25°C
TMIN to TMAX
Gain TC2
Offset TC2
VREF− = 0 V, VOUT = 0 V to +10 V
1 LSB = 153 μV
±12
±16
±1
±12
±16
±12
±16
±1
±4
±±
±0.5
±6
±16
±6
±16
±1
±1
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/°C typ
ppm FSR/°C typ
All grades guaranteed monotonic
VOUT load = 10 MΩ
±1
BIPOLAR OUTPUT
Relative Accuracy at +25°C
TMIN to TMAX
VREF− = –5 V, VOUT = −10 V to +10 V
1 LSB = 305 μV
±6
±±
±2
±4
LSB typ
LSB max
Differential Nonlinearity Error
Gain Error at +25°C
TMIN to TMAX
Offset Error at +25°C
TMIN to TMAX
Bipolar Zero Error at +25°C
TMIN to TMAX
Gain TC2
Offset TC2
Bipolar Zero TC2
±1
±6
±16
±6
±16
±6
±12
±1
±1
±0.5
±4
±16
±4
±12
±4
±±
±1
±1
±1
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/°Ctyp
ppm FSR/°Ctyp
ppm FSR/°Ctyp
All grades guaranteed monotonic
VOUT load = 10 MΩ
VOUT load = 10 MΩ
±1
REFERENCE INPUT
Input Resistance
20
40
VSS + 6 to
VDD − 6
VSS + 6 to
VDD − 6
20
40
VSS + 6 to
VDD − 6
VSS + 6 to
VDD − 6
kΩ min
kΩ max
V min to
V max
V min to
V max
Resistance from VREF+ to VREF−
Typically 30 kΩ
VREF+ Range
VREF− Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
V max
V
V
2
1000
0.3
SS + 4 to
DD − 3
VSS + 4 to
VDD − 3
2
1000
0.3
Resistive Load
Capacitive Load
Output Resistance
Short Circuit Current
DIGITAL INPUTS
kΩ min
pF max
Ω typ
To 0 V
To 0 V
±25
±25
mA typ
To 0 V or any power supply
VIH (Input High Voltage)
VIL (Input Low Voltage)
IIN (Input Current)
2.4
0.±
±10
10
2.4
0.±
±10
10
V min
V max
μA max
pF max
CIN (Input Capacitance)2
Rev. G | Page 3 of 24
AD7846
Parameter1
J, A Versions
K, B Versions
Unit
Test Conditions/Comments
DIGITAL OUTPUTS
VOL (Output Low Voltage)
VOH (Output High Voltage)
Floating State Leakage Current
Floating State Output Capacitance2
0.4
4.0
±10
10
0.4
4.0
±10
10
V max
V min
μA max
pF max
ISINK = 1.6 mA
ISOURCE = 400 μA
DB0 to DB15 = 0 to VCC
POWER REQUIREMENTS3
VDD
VSS
VCC
IDD
+11.4/+15.75
−11.4/−15.75
+4.75/+5.25
5
+11.4/+15.75
−11.4/−15.75
+4.75/+5.25
5
V min/V max
V min/V max
V min/V max
mA max
VOUT unloaded
VOUT unloaded
ISS
5
5
mA max
ICC
1
1.5
100
1
1.5
100
mA max
LSB/V max
mW typ
Power Supply Sensitivity4
Power Dissipation
VOUT unloaded
1 Temperature ranges as follows: J, K versions: 0°C to +70°C; A, B versions: −40°C to +±5°C.
2 Guaranteed by design and characterization, not production tested.
3 The AD7±46 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section.
4 Sensitivity of gain error, offset error, and bipolar zero error to VDD, VSS variations.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not subject to test. VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = −14.25 V
to −15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V, unless otherwise noted.
Table 2.
Parameter
ꢀimit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
Output Settling Time1
6
9
7
μs max
μs max
V/μs typ
To 0.006% FSR, VOUT loaded, VREF− = 0 V, typically 3.5 μs
To 0.003% FSR, VOUT loaded, VREF− = –5 V, typically 6.5 μs
Slew Rate
Digital-to-Analog Glitch
Impulse
70
nV-sec typ
DAC alternately loaded with 10…0000 and 01…1111,
V
OUT unloaded
AC Feedthrough
0.5
mV p-p typ VREF− = 0 V, VREF+ = 1 V rms, 10 kHz sine wave, DAC loaded
with all 0s
Digital Feedthrough
10
50
nV-sec typ
nV/√Hz typ Measured at VOUT, DAC loaded with 0111011…11,
REF+ = VREF− = 0 V
DAC alternately loaded with all 1s and all 0s. CS high
Output Noise Voltage
Density, 1 kHz to 100 kHz
V
1 LDAC
= 0. Settling time does not include deglitching time of 2.5 μs (typ).
Rev. G | Page 4 of 24
AD7846
TIMING CHARACTERISTICS
VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter1
ꢀimit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
R/W to CS setup time
CS pulse width (write cycle)
R/W to CS hold time
Data setup time
Data hold time
Data access time
0
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
t1
t2
t3
t4
t5
60
0
60
0
120
10
60
0
2
t6
t7
3
Bus relinquish time
CLR setup time
t±
70
0
CLR pulse width
t9
CLR hold time
t10
t11
t12
70
130
LDAC pulse width
CS pulse width (read cycle)
1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.± V or 2.4 V.
3 t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
t1
t3
t1
t3
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
R/W
CS
t12
t2
t5
t7
t6
t4
DB0
TO
DB15
DATA VALID
DATA VALID
t9
t10
t8
t9
t10
t8
CLR
t11
LDAC
Figure 2. Timing Diagram
DBn
DBn
100pF
10pF
3kΩ
DGND
3kΩ
DGND
Figure 3. Load Circuit for Access Time (t6)—High Z to VOH
Figure 5. Load Circuit for Access Time (t7)—High Z to VOH
5V
5V
3kΩ
3kΩ
DBn
DBn
10pF
100pF
DGND
DGND
Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL
Figure 4. Load Circuits for Bus Relinquish Time (t6)—High Z to VOL
Rev. G | Page 5 of 24
AD7846
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
VDD to DGND
VCC to DGND
Rating
−0.4 V to +17 V
−0.4 V, VDD + 0.4 V, or +7 V
(whichever is lower)
+0.4 V to −17 V
VSS to DGND
VREF+ to DGND
VREF− to DGND
VOUT to DGND1
VDD + 0.4 V, VSS − 0.4 V
VDD + 0.4 V, VSS − 0.4 V
VDD + 0.4 V, VSS − 0.4 V, or ±10 V
(whichever is lower)
VDD + 0.4 V, VSS − 0.4 V
−0.4 V to VCC + 0.4 V
ESD CAUTION
RIN to DGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND −0.4 V to VCC + 0.4 V
Power Dissipation (Any Package)
To +75°C
1000 mW
10 mW/°C
Derates above +75°C
Operating Temperature Range
J, K Versions
A, B Versions
Storage Temperature Range
Lead Temperature (Soldering)
0°C to +70°C
−40°C to +±5°C
−65°C to +150°C
+300°C
1 VOUT can be shorted to DGND, VDD, VSS, or VCC provided that the power
dissipation of the package is not exceeded.
Rev. G | Page 6 of 24
AD7846
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB2
DB1
DB0
DB3
DB4
DB5
1
28
27
26
25
24
23
22
21
4
3
2
1
28 27 26
2
PIN 1
IDENTIFIER
3
V
5
6
7
8
9
25
24
23
22
21
LDAC
CLR
CS
OUT
R
V
4
IN
LDAC
CLR
CS
DD
V
V
5
REF+
REF–
V
OUT
AD7846
TOP VIEW
(Not to Scale)
R/W
6
R
IN
AD7846
TOP VIEW
(Not to Scale)
V
V
SS
CC
7
V
V
R/W
REF+
DB15 10
DB14 11
20 DGND
19 DB6
8
V
REF–
CC
9
V
20 DGND
SS
10
11
12
13
14
19
DB15
DB14
DB13
DB12
DB11
DB6
12 13 14 15 16 17 18
18
DB7
17
DB8
16
DB9
15
DB10
Figure 7. PDIP Pin Configuration
Figure 8. CERDIP Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
DB2 to DB0
VDD
VOUT
RIN
Description
1 to 3
Data I/Os. DB0 is LSB.
Positive Supply for Analog Circuitry. This is +15 V nominal.
DAC Output Voltage.
Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6.
VREF+ Input. The DAC is specified for VREF+ = +5 V.
VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is
specified for both conditions.
4
5
6
7
±
VREF+
VREF−
9
VSS
Negative Supply for the Analog Circuitry. This is −15 V nominal.
10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB.
20
21
22
23
24
25
DGND
VCC
R/W
CS
Ground for Digital Circuitry.
Positive Supply for Digital Circuitry. This is +5 V nominal.
R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents.
Chip Select Input. This pin selects the device.
Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7.
Asynchronous Load Input to DAC.
CLR
LDAC
26 to 2± DB5 to DB3
Data I/Os.
Table 6. Output Voltage Ranges
Output Range
0 V to +5 V
0 V to +10 V
+5 V to −5 V
VREF+
+5 V
+5 V
+5 V
+5 V
+5 V
VREF−
0 V
0 V
−5 V
0 V
−5 V
RIN
VOUT
0 V
VOUT
+5 V
0 V
+5 V to −5 V
+10 V to −10 V
Rev. G | Page 7 of 24
AD7846
TYPICAL PERFORMANCE CHARACTERISTICS
500
450
400
350
300
250
200
150
100
50
A1 –0.40V
V
= V = 0V
REF–
REF+
GAIN = +1
DAC LOADED WITH ALL 1s
1V 2mV
20µs
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 12. Noise Spectral Density
Figure 9. AC Feedthrough, VREF+ = 1 V rms, 10 kHz Sine Wave
8
V
V
V
V
= +15V
= –15V
DD
7
6
5
4
3
2
1
0
SS
+
–
= +1V rms
= 0V
REF
REF
50mV/DIV
V
OUT
5V/DIV
DATA
0.5µs/DIV
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 10. AC Feedthrough to VOUT vs. Frequency
Figure 13. Digital-to-Analog Glitch Impulse Without Internal Deglitcher
(10…000 to 011…111 Transition)
30
25
20
15
10
5
V
V
V
V
= +15V
= –15V
DD
SS
= ±5V SINE WAVE
= 0V
REF+
REF–
50mV/DIV
V
OUT
GAIN = +2
5V/DIV
5V/DIV
LDAC
DATA
0
10
1µs/DIV
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 14. Digital-to-Analog Glitch Impulse with Internal Deglitcher
(10…000 to 011…111 Transition)
Figure 11. Large Signal Frequency Response
Rev. G | Page ± of 24
AD7846
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
A1
0V
T
V
V
= +25°C
A
= +5V
= 0V
REF+
REF–
V
+, ±5V
REF
GAIN = +1
V
+, ±10V
2µs
OUT
10V
5V
11
12
13
14
, V (V)
15
16
V
DD SS
Figure 18. Typical Integral Nonlinearity vs. VDD/VSS
Figure 15. Pulse Response (Large Signal)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
A1 0.025V
T = +25°C
A
V
V
= +5V
= 0V
REF+
REF–
V
+, ±50mV
REF
GAIN = +1
V
+, ±100mV
OUT
100mV 50mV
1µs
11
12
13
14
, V (V)
15
16
V
DD SS
Figure 19. Typical Differential Nonlinearity vs. VDD/VSS
Figure 16. Pulse Response (Small Signal)
REF 2.24V
10dB/DIV
MARKER 442.0Hz
RANGE 3.98V
1.70V
START 100.0Hz
RBW 3Hz
STOP 2000.0Hz
ST 422 SEC
VBW 10Hz
Figure 17. Spectral Response of Digitally Constructed Sine Wave
Rev. G | Page 9 of 24
AD7846
TERMINOLOGY
Offset Error
Least Significant Bit
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
This is the analog weighting of 1 bit of the digital word in a
DAC. For the AD7846, 1 LSB = (VREF+ − VREF−)/216.
Relative Accuracy
Bipolar Zero Error
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (that is, offset and gain errors are
adjusted out) and is normally expressed in least significant bits
or as a percentage of full-scale range.
When the AD7846 is connected for bipolar output and 10…000
is loaded to the DAC, the deviation of the analog output from
the ideal midscale of 0 V is called the bipolar zero error.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec
depending upon whether the glitch is measured as a current or
a voltage.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of 1 LSB over the operating
temperature range ensures monotonicity.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
Digital Feedthrough
CS
When the DAC is not selected (that is,
is held high), high
frequency logic activity on the digital inputs is capacitively
coupled through the device to show up as noise on the VOUT pin.
This noise is digital feedthrough.
Rev. G | Page 10 of 24
AD7846
CIRCUIT DESCRIPTION
DIGITAꢀ SECTION
Table 7. Control Logic Truth Table
CS R/W ꢀDAC CꢀR
Function
Figure 20 shows the digital control logic and on-chip data latches
in the AD7846. Table 7 is the associated truth table. The digital-
to-analog converter (DAC) has two latches that are controlled
1
0
X
0
X
X
X
X
3-state DAC I/O latch in high-Z state
DAC I/O latch loaded with DB15
to DB0
CS W LDAC
CLR
by four signals: , R/
,
, and
. The input latch is
0
1
X
0
X
1
Contents of DAC I/O latch available
on DB15 to DB0
Contents of DAC I/O latch transferred
to DAC latch
connected to the data bus (DB15 to DB0). A word is written to
CS
W
the input latch by bringing
of the input latch can be read back by bringing
low and R/ low. The contents
CS
X
X
W
low and R/
high. This feature is called readback and is used in system
diagnostic and calibration routines.
X
X
0
1
X
X
0
0
DAC latch loaded with 000…000
DAC latch loaded with 100…000
Data is transferred from the input latch to the DAC latch with
LDAC
DIGITAꢀ-TO-ANAꢀOG CONVERSION
the
contents appears at the DAC output. The
DAC latch contents to 000…000 or 100…000, depending on the
CLR CLR
strobe. The equivalent analog value of the DAC latch
Figure 21 shows the digital-to-analog section of the AD7846.
There are three DACs, each of which has its own buffer
amplifiers. DAC1 and DAC2 are 4-bit DACs. They share a
16-resistor string but have their own analog multiplexers. The
voltage reference is applied to the resistor string. DAC3 is a
12-bit voltage mode DAC with its own output stage.
CLR
pin resets the
W
state of R/ . Writing a
loads 100…000. To reset a DAC to 0 V in a unipolar system, the
CLR
loads 000…000 and reading a
W
while R/ is low; to reset to 0 V in a
user should assert
CLR
W
bipolar system, assert the
while R/ is high.
The four MSBs of the 16-bit digital code drive DAC1 and DAC2,
and the 12 LSBs control DAC3. Using DAC1 and DAC2, the
MSBs select a pair of adjacent nodes on the resistor string and
present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.
R/W
CLR
DAC
16
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 leap along the resistor string. For
example, when switching from Segment 1 to Segment 2, DAC1
switches from the bottom of Segment 1 to the top of Segment 2
while DAC2 stays connected to the top of Segment 1. The code
driving DAC3 is automatically complemented to compensate
for the inversion of its inputs. This means that any linearity
effects due to amplifier offset voltages remain unchanged when
switching from one segment to the next and 16-bit monotonicity is
ensured if DAC3 is monotonic. Thus, 12-bit resistor matching
in DAC3 guarantees overall 16-bit monotonicity. This is much
more achievable than 16-bit matching, which a conventional
R-2R structure needs.
DB15 RST
DB15 SET
LDAC
DB15 TO DB0
LATCHES
DB14 TO DB0
RST
16
3-STATE I/O
LATCH
CS
16
DB15
DB0
Figure 20. Input Control Logic
Rev. G | Page 11 of 24
AD7846
V
REF+
SEGMENT 16
R
R
DAC1
DAC2
R
V
IN
S1
S3
S2
S4
DAC3
A1
A2
A3
OUT
12-BIT DAC
S15
S17
S14
S16
DB11 TO DB0
DB15 TO DB12
DB15 TO DB12
SEGMENT 1
V
REF–
Figure 21. Digital-to-Analog Conversion
operation. Figure 13 and Figure 14 show the outputs of the
AD7846 without and with the deglitcher.
OUTPUT STAGE
The output stage of the AD7846 is shown in Figure 22. It is capable
of driving a 2 kΩ/1000 pF load. It also has a resistor feedback
network that allows the user to configure it for gains of 1 or 2.
Table 6 shows the different output ranges that are possible.
R
IN
10kΩ
10kΩ
C1
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 μs
V
OUT
DAC3
LDAC
after the leading edge of
. This short state keeps the DAC
ONE
SHOT
output at its previous voltage while the AD7846 is internally
changing to its new value. Thus, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
LDAC
is tied permanently low, the deglitching is not in
Figure 22. Output Stage
Rev. G | Page 12 of 24
AD7846
UNIPOLAR BINARY OPERATION
Figure 23 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586 +5 V reference.
Because RIN is tied to 0 V, the output amplifier has a gain of 2
and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, RIN should be tied to VOUT, configuring the output
stage for a gain of 1. Table 8 gives the code table for the circuit
of Figure 23.
Table 8. Code Table for Figure 23
Binary Number in DAC ꢀatch
MSB
ꢀSB1
Analog Output (VOUT
)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+10 (65,535/65,536) V
+10 (32,76±/65,536) V
+10 (1/65,536) V
0 V
+15V
+5V
1 LSB = 10 V/216 = 10 V/65,536 = 152 ꢀV.
4
21
Offset and gain can be adjusted in Figure 23 as follows:
2
V
V
DD
CC
•
To adjust offset, disconnect the VREF− input from 0 V, load
the DAC with all 0s, and adjust the VREF− voltage until VOUT
= 0 V.
For gain adjustment, the AD7846 should be loaded with all
1s and R1 adjusted until VOUT = 10 (65,535)/(65,536) =
9.999847 V. If a simple resistor divider is used to vary the
V
OUT
(0V TO +10V)
5
V
6
5
7
8
V
OUT
REF+
AD586
8
R1
10kΩ
AD7846*
C1
R
6
IN
1µF
4
•
V
REF–
20
DGND
V
SS
SIGNAL
GROUND
VREF− voltage, it is important that the temperature
coefficients of these resistors match that of the DAC input
resistance (−300 ppm/°C). Otherwise, extra offset errors are
introduced over temperature. Many circuits do not require
these offset and gain adjustments. In these circuits, R1 can
be omitted. Pin 5 of the AD586 can be left open circuit and
Pin 8 (VREF−) of the AD7846 tied to 0 V.
*ADDITIONAL PINS
OMITTED FOR CLARITY
–15V
Figure 23. Unipolar Binary Operation
Rev. G | Page 13 of 24
AD7846
BIPOLAR OPERATION
Figure 24 shows the AD7846 set up for 10 V bipolar operation.
The AD588 provides precision 5 V tracking outputs that are
fed to the VREF+ and VREF− inputs of the AD7846. The code table
for Figure 24 is shown in Table 9.
Full-scale and bipolar zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and −5 V outputs together
with respect to ground.
+15V
+15V
+5V
For bipolar zero adjustment on the AD7846, load the DAC with
100…000 and adjust R3 until VOUT = 0 V. Full scale is adjusted
R1
39kΩ
4
21
4
6
by loading the DAC with all 1s and adjusting R2 until VOUT
=
V
V
CC
DD
+15V
2
3
1
7
9
9.999694 V.
C1
V
V
V
V
5
7
8
OUT
REF+
OUT
1µF
(–10V TO +10V)
When bipolar zero and full-scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be connected
to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V
output range, there are two choices. By tying Pin 6 (RIN) of the
AD7846 to VOUT (Pin 5), the output stage gain is reduced to
unity and the output range is 5 V. If only a positive 5 V reference
is available, bipolar 5 V operation is still possible. Tie VREF− to
0 V and connect RIN to VREF+. This also gives a 5 V output
range. However, the linearity, gain, and offset error specifications
are the same as the unipolar 0 V to 5 V range.
AD588
AD7846*
R2
10kΩ
5
R
6
IN
14
15
16
10
11
REF–
20
DGND
–15V
SIGNAL
GROUND
V
SS
12
8
13
9
R3
100kΩ
–15V
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Bipolar 10 V Operation
Table 9. Offset Binary Code Table for Figure 24
Binary Number in DAC ꢀatch
MUꢀTIPꢀYING OPERATION
The AD7846 is a full multiplying DAC. To obtain four-quadrant
multiplication, tie VREF− to 0 V, apply the ac input to VREF+, and
tie RIN to VREF+. Figure 11 shows the large signal frequency
response when the DAC is used in this fashion.
ꢀSB1
Analog Output (VOUT
)
MSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+10 (32,767/32,76±) V
+10 (1/32,76±) V
0 V
−10 (1/32,76±) V
−10 (32,76±/32,76±) V
1 LSB = 10 V/215 = 10 V/32,76± = 305 μV.
Rev. G | Page 14 of 24
AD7846
POSITION MEASUREMENT APPLICATION
Figure 25 shows the AD7846 in a position measurement applica-
tion using an linear variable displacement transducer (LVDT),
an AD630 synchronous demodulator and a comparator to make
a 16-bit LVDT-to-digital converter. The LVDT is excited with a
fixed frequency and fixed amplitude sine wave (usually 2.5 kHz,
2 V p-p). The outputs of the secondary coil are in antiphase and
their relative amplitudes depend on the position of the core in the
LVDT. The AD7846 output interpolates between these two inputs
in response to the DAC input code. The AD630 is set up so that
it rectifies the DAC output signal. Thus, if the output of the DAC is
in phase with the VREF+ input, the inverting input to the compara-
tor is positive, and if it is in phase with VREF−, the output is nega-
tive. By turning on each bit of the DAC in succession starting
with the MSB and deciding to leave it on or turn it off based on
the comparator output, a 16-bit measurement of the core position
is obtained.
ASIN ω t
LVDT
x ASIN ω t
V
5
6
OUT
V
7
REF+
R
IN
AD7846*
8
V
REF–
DGND
20
–(1–x) ASIN ω t
DB15 DB0
10
SIGNAL
GROUND
3
PROCESSOR DATA BUS
9
16
R1
100kΩ
10
13
AD630*
TO
C1
1µF
PROCESSOR PORT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD7846 in Position Measurement Application
Rev. G | Page 15 of 24
AD7846
MICROPROCESSOR INTERFACING
AD7846-TO-8086 INTERFACE
AD7846-TO-MC68000 INTERFACE
Figure 26 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used in
Interfacing between the AD7846 and MC68000 is accomplished
using the circuit of Figure 28. The following routine writes data
to the DAC latches and then outputs the data via the DAC latch.
LDAC
this circuit because
is permanently tied to 0 V. AD0 to
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0 to DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is 0xD000.
1000 MOVE.W
#W,
D0
The desired DAC data,
W, is loaded into
Data Register 0. W
may be any value
ADDRESS BUS
between 0 and 65535
(decimal) or 0 and
FFFF (hexadecimal).
ADDRESS
CS
DECODE
16-BIT
LATCH
LDAC
ALE
8086
MOVE.W
D0,
The data, W, is
$E000 transferred between
D0 and the DAC
+5V
CLR
DEN
RD
AD7846*
register.
R/W
WR
MOVE.W
TRAP
#228, Control is returned
DATA BUS
AD0 TO AD15
DB0 TO DB15
D7
to the System Monitor
using these two
instructions.
#14
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 26. AD7846-to-8086 Interface Circuit
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure 27,
a 16-bit word is loaded to the input latches of each of the DACs
in sequence. Then, with one instruction to the appropriate
A1 TO A23
ADDRESS BUS
MC68000
DS
ADDRESS
DECODE
CS
+5V
CLR
DTACK
LDAC
CS4
LDAC
address,
(that is,
) is brought low, updating all the
AD7846*
R/W
DACs simultaneously.
R/W
ADDRESS BUS
DATA BUS
D0 TO D15
DB0 TO DB15
ADDRESS
CS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
DECODE
16-BIT
LATCH
ALE
Figure 28. AD7846-to-MC68000 Interface
8086
LDAC
DEN
RD
AD7846*
R/W
WR
CLR
+5V
AD0 TO AD15
DATA BUS
DB0 TO DB15
CS
AD7846*
LDAC
R/W
CLR
+5V
DB0 TO DB15
CS
AD7846*
LDAC
R/W
CLR
+5V
DB0 TO DB15
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 27. AD7846-to-8086 Interface: Multiple DAC System
Rev. G | Page 16 of 24
AD7846
DIGITAL FEEDTHROUGH
In the preceding interface configurations, most digital inputs to
the AD7846 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs are constantly
changing. The high frequency logic activity on the bus can feed
through the DAC package capacitance to show up as noise on
the analog output. To minimize this digital feedthrough, isolate
the DAC from the noise source. Figure 29 shows an interface
circuit that isolates the DAC from the bus.
Note that to make use of the AD7846 readback feature using
the isolation technique of Figure 29, the latch needs to be
bidirectional.
A1 TO A15
ADDRESS BUS
ADDRESS
DECODE
CS
MICRO-
PROCESSOR
+5V
CLR
LDAC
R/W
R/W
DIR
G
AD7846*
DATA BUS
B BUS A BUS
D0 TO D15
DB0 TO DB15
2×
74LS245
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 29. AD7846 Interface Circuit Using Latches to Minimize Digital Feedthrough
Rev. G | Page 17 of 24
AD7846
APPLICATION HINTS
R1 to R5 represent lead and track resistances on the printed
circuit board. R1 is the resistance between the analog power
supply ground and the signal ground. Because current flowing
in R1 is very low (bias current of AD588 sense amplifier), the
effect of R1 is negligible. R2 and R3 represent track resistance
between the AD588 outputs and the AD7846 reference inputs.
Because of the force and sense outputs on the AD588, these
resistances will also have a negligible effect on accuracy.
NOISE
In high resolution systems, noise is often the limiting factor.
With a 10 V span, a 16-bit LSB is 152 ꢀV (–96 dB). Thus, the
noise floor must stay below −96 dB in the frequency range of
interest. Figure 12 shows the noise spectral density for the
AD7846.
GROUNDING
As well as noise, the other prime consideration in high resolution
DAC systems is grounding. With an LSB size of 152 ꢀV and a
load current of 5 mA, 1 LSB of error can be introduced by series
resistance of only 0.03 ꢁ.
R4 is the resistance between the DAC output and the load. If RL
is constant, then R4 introduces a gain error only that can be
trimmed out in the calibration cycle. R5 is the resistance
between the load and the analog common. If the output voltage
is sensed across the load, R5 introduces a further gain error,
which can be trimmed out. If, on the other hand, the output
voltage is sensed at the analog supply common, R5 appears as
part of the load and therefore introduces no errors.
Figure 30 shows recommended grounding for the AD7846 in a
typical application.
ANALOG SUPPLY
+15V 0V –15V
DIGITAL SUPPLY
+5V DGND
PRINTED CIRCUIT BOARD ꢀAYOUT
Figure 31 shows the AD7846 in a typical application with the
AD588 reference, producing an output analog voltage in the
10 V range. Full-scale and bipolar zero adjustment are
provided by Potentiometer R2 and Potentiometer R3. Latches
(2 × 74LS245) isolate the DAC digital inputs from the active
microprocessor bus and minimize digital feedthrough.
R1
SIGNAL
GROUND
2
9
16
4
9
21
20
R2
R3
1
3
7
8
6
5
AD588*
AD7846*
R4
V
OUT
(+5V TO –5V)
15
14
R
L
R5
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. AD7846 Grounding
Rev. G | Page 1± of 24
AD7846
+15V
4
J1
C5
10µF
C6
0.1µF
+5V
C1
10µF
21
C31/A31
C7
0.1µF
R1
DB15 10
DB14 11
39kΩ
20
C2
0.1µF
2
3
4
18
17
16
C4/A4
C5/A5
C6/A6
DB13
12
4
6
2
5
6
7
8
9
15
14
13
12
11
C12
1µF
74LS245
DB12 13
DB11 14
C7/A7
C8/A8
C9/A9
7
5
7
3
1
V
REF+
C10/A10
C11/A11
15
DB10
DB9 16
17
AD7846
1
19
20
10
AD588
14
15
DB8
DB7 18
19
R2
100kΩ
+5V
8
9
V
V
REF–
SS
10
11
2
3
4
18
17
16
–15V
C12/A12
C13/A13
C14/A14
DB6
DB5 26
16
C4
0.1µF
C3
10µF
5
6
7
8
9
15
14
13
12
11
27
28
1
74LS245
DB4
DB3
DB2
DB1
DB0
C15/A15
C16/A16
12
C17/A17
C18/A18
C19/A19
C20/A20
8
13
9
2
10
20
6
DGND
1
19
R3
100kΩ
C21/A21
C22/A22
C23/A23
C32/A32
3
R
IN
22
23
R/W
CS
V
OUT
(+10V TO –10V)
V
CLR 24
25
5
OUT
LDAC
Figure 31. Schematic for AD7846 Board
Rev. G | Page 19 of 24
AD7846
OUTLINE DIMENSIONS
0.100 (2.54)
MAX
0.005 (0.13)
MIN
28
15
14
0.610 (15.49)
0.500 (12.70)
1
PIN 1
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.018 (0.46)
0.008 (0.20)
15°
0°
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.026 (0.66)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28-2)
Dimensions shown in inches and (millimeters)
1.565 (39.75)
1.380 (35.05)
28
1
15
0.580 (14.73)
0.485 (12.31)
14
0.625 (15.88)
0.600 (15.24)
0.100 (2.54)
BSC
0.195 (4.95)
0.125 (3.17)
0.250 (6.35)
MAX
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.700 (17.78)
MAX
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
COMPLIANT TO JEDEC STANDARDS MS-011
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
Figure 33. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
Rev. G | Page 20 of 24
AD7846
0.300 (7.62)
REF
0.100 (2.54)
0.064 (1.63)
0.075
(1.91)
REF
0.020 (0.51)
MIN
19
25
0.028 (0.71)
0.022 (0.56)
18
26
28
0.05 (1.27)
0.458
BOTTON
VIEW
0.458 (11.63)
0.442 (11.23)
(11.63)
MAX
SQ
1
SQ
0.15 (3.81)
REF
0.075 (1.91)
REF
12
4
11
5
0.095 (2.41)
0.075 (1.90)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 34. 28-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-28-1)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.020 (0.51)
MIN
0.042 (1.07)
4
26
25
0.048 (1.22)
0.042 (1.07)
5
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
19
18
12
0.045 (1.14)
0.025 (0.64)
R
0.456 (11.582)
0.450 (11.430)
SQ
0.120 (3.04)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
Rev. G | Page 21 of 24
AD7846
ORDERING GUIDE
Model1
Temperature Range
Relative Accuracy
±16 LSB
±16 LSB
±16 LSB
±16 LSB
±± LSB
Package Description
Package Option
5962-±9697013A
5962-±969701XA
AD7±46JN
AD7±46JNZ
AD7±46KN
AD7±46KNZ
AD7±46JP
AD7±46JP-REEL
AD7±46JPZ
AD7±46JPZ-REEL
AD7±46KP
AD7±46KP-REEL
AD7±46KPZ
AD7±46KPZ-REEL
AD7±46AP
AD7±46APZ
AD7±46AQ
AD7±46BP
−55°C to +125°C
−55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
−40°C to +±5°C
2±-Terminal Ceramic Leadless Chip Carrier [LCC] E-2±-1
2±-Lead Ceramic Dual In-Line Package [CERDIP] Q-2±-2
2±-Lead Plastic Dual In-Line Package [PDIP]
2±-Lead Plastic Dual In-Line Package [PDIP]
2±-Lead Plastic Dual In-Line Package [PDIP]
2±-Lead Plastic Dual In-Line Package [PDIP]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
N-2±-2
N-2±-2
N-2±-2
N-2±-2
P-2±
P-2±
P-2±
P-2±
P-2±
P-2±
P-2±
P-2±
P-2±
±± LSB
±16 LSB
±16 LSB
±16 LSB
±16 LSB
±± LSB
±± LSB
±± LSB
±± LSB
±16 LSB
±16 LSB
±16 LSB
±± LSB
±± LSB
±16 LSB
P-2±
2±-Lead Ceramic Dual In-Line Package [CERDIP] Q-2±-2
2±-Lead Plastic Leaded Chip Carrier [PLCC]
2±-Lead Plastic Leaded Chip Carrier [PLCC]
P-2±
P-2±
DIE
AD7±46BPZ
AD7±46ACHIPS
1 Z = RoHS Compliant Part.
Rev. G | Page 22 of 24
AD7846
NOTES
Rev. G | Page 23 of 24
AD7846
NOTES
©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08490-0-4/10(G)
Rev. G | Page 24 of 24
相关型号：
AD7846BD
IC PARALLEL, WORD INPUT LOADING, 16-BIT DAC, CDIP28, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-28, Digital to Analog Converter
ADI
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