AD7851KRZ_技术文档

14-Bit 333 kSPS

Serial A/D Converter

a

AD7851

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

AV

Single 5 V Supply

AGND

DD

333 kSPS Throughput Rate/ ؎2 LSB DNL—A Grade

285 kSPS Throughput Rate/ ؎1 LSB DNL—K Grade

A & K Grades Guaranteed to 125؇C/ 238 kSPS

Throughput Rate

Pseudo-Differential Input w ith Tw o Input Ranges

System and Self-Calibration w ith Autocalibration on

Pow er-Up

AIN (+)

AIN (–)

DV

DD

T/H

AD7851

DGND

4.096 V

REFERENCE

REF

/

IN

BUF

COMP

REF

OUT

Read/ Write Capability of Calibration Data

Low Pow er: 60 m W typ

AMODE

Pow er-Dow n Mode: 5 ␮W typ Pow er Consum ption

Flexible Serial Interface:

8051/ SPI/ QSPI/ ␮P Com patible

24-Pin DIP, SOIC and SSOP Packages

CLKIN

C

CHARGE

REDISTRIBUTION

DAC

REF1

CONVST

SAR + ADC

CONTROL

BUSY

REF2

SLEEP

APPLICATIONS

CALIBRATION

MEMORY

AND CONTROLLER

CAL

Digital Signal Processing

Speech Recognition and Synthesis

Spectrum Analysis

DSP Servo Control

SERIAL INTERFACE / CONTROL REGISTER

Instrum entation and Control System s

High Speed Modem s

SM1

SM2

DIN DOUT SCLK

POLARITY

SYNC

Autom otive

GENERAL D ESCRIP TIO N

P RO D UCT H IGH LIGH TS

T he AD7851 is a high speed, 14-bit ADC that operates from a

single 5 V power supply. T he ADC powers-up with a set of

default conditions at which time it can be operated as a read-

only ADC. T he ADC contains self-calibration and system-

calibration options to ensure accurate operation over time and

temperature and has a number of power-down options for low

power applications.

1. Single 5 V supply.

2. Operates with reference voltages from 4 V to V_DD

3. Analog input ranges from 0 V to V_DD

.

4. System and self-calibration including power-down mode.

5. Versatile serial I/O port.

T he AD7851 is capable of 333 kHz throughput rate. T he input

track-and-hold acquires a signal in 0.33 µs and features a

pseudo-differential sampling scheme. T he AD7851 has the

added advantage of two input voltage ranges (0 V to V_REF,and

–V_REF/2 to +V_REF/2 centered about V_REF/2). Input signal range

is to V_DDand the part is capable of converting full-power signals

to 20 MHz.

CMOS construction ensures low power dissipation (60 mW typ)

with power-down mode (5 µW typ). T he part is available in 24-

pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small

outline (SOIC) and 24-lead small shrink outline (SSOP) packages.

*P atent pending.

See P age 35 for data sheet index.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

A Grade: f_CLKIN= 7 MHz (–40؇C to +85؇C), f_SAMPLE= 333 kHz; K Grade: f_CLKIN= 6 MHz

1, 2

(0؇C to +85؇C), f_SAMPLE= 285 kHz; A and K Grade: f_CLKIN= 5 MHz (to +125؇C), f_SAMPLE

238 kHz; (AV = DV = +5.0 V ؎ 5%, REF_IN/REF_OUT = 4.096 V External Reference; SLEEP = Logic High; T = T_MINto T , unless otherwise noted)

=

AD7851–SPECIFICATIONS

DD

A

MAX

P aram eter

A¹

K¹

Units

Test Conditions/Com m ents

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio³(SNR) 77

78

dB min

dB max

T ypically SNR is 79.5 dB

V_IN= 10 kHz, Sine Wave, f_SAMPLE= 333 kHz

T otal Harmonic Distortion (T HD)

–86

–87

V_IN= 10 kHz, Sine Wave, f_SAMPLE= 333 kHz,

T ypically –96 dB

V_IN= 10 kHz, f_SAMPLE= 333 kHz

Peak Harmonic or Spurious Noise

Intermodulation Distortion (IMD)

Second Order T erms

T hird Order T erms

Full Power Bandwidth

–87

–86

20

–90

20

dB typ

MHz typ

fa = 9.983 kHz, fb = 10.05 kHz, f_SAMPLE= 333 kHz

@ 3 dB

DC ACCURACY

Resolution

14

Bits

Integral Nonlinearity

Differential Nonlinearity

Unipolar Offset Error

Positive Full-Scale Error

Negative Full-Scale Error

Bipolar Zero Error

±2

±10

±1

±10

±1

LSB max

LSB typ

Guaranteed No Missed Codes to 14 Bits

Review: “Adjusting the Offset Calibration

Register” in the “Calibration Registers” section

of the data sheet.

ANALOG INPUT

Input Voltage Ranges

0 V to V_REF0 V to V_REF

Volts

i.e., AIN(+) – AIN(–) = 0 V to V_REF, AIN(–) can be

biased up but AIN(+) cannot go below AIN(–).

i.e., AIN(+) – AIN(–) = –V_REF/2 to +V_REF/2, AIN(–)

should be biased up and AIN(+) can go below

AIN(–) but cannot go below 0 V.

±V_REF/2

Leakage Current

±1

µA max

Input Capacitance

20

pF typ

REFERENCE INPUT /OUT PUT

REF_INInput Voltage Range

Input Impedance

4/V_DD

150

4/V_DD

150

V min/max Functional from 1.2 V

kΩ typ

Resistor Connected to Internal Reference Node

REF_OUTOutput Voltage

REF_OUTT empco

3.696/4.496 3.696/4.496

V min/max

ppm/°C typ

50

LOGIC INPUT S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

V_DD– 1.0

0.4

±10

V_DD– 1.0

0.4

±10

V min

V max

µA max

pF max

V_IN= 0 V or V_DD

5

Input Capacitance, C_IN

10

LOGIC OUT PUT S

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁵

Output Coding

V_DD– 0.4

0.4

±10

V_DD– 0.4

0.4

±10

V min

I_SOURCE= 200 µA

I_SINK= 0.8 mA

V max

µA max

pF max

10

Straight (Natural) Binary

2s Complement

Unipolar Input Range

Bipolar Input Range

CONVERSION RAT E

Conversion T ime

Conversion + T /H Acquisition T ime

2.78

3.0

3.25

3.5

µs max

19.5 CLKIN Cycles

21 CLKIN Cycles T hroughput Rate

–2–

REV. A

AD7851

P aram eter

A¹

K¹

Units

Test Conditions/Com m ents

POWER PERFORMANCE

AV_DD,DV_DD

+4.75/+5.25

17

+4.75/+5.25

17

V min/max

mA max

I_DD

Normal Mode⁵

AV_DD= DV_DD= 4.75 V to 5.25 V. T ypically

12 mA.

Sleep Mode⁶

With External Clock On

20

µA typ

µA max

Full Power-Down. Power management bits

in control register set as PMGT 1 = 1, PMGT 0 = 0.

Partial Power-Down. Power management bits in

control register set as PMGT 1 = 1, PMGT 0 = 1.

T ypically 1 µA. Full Power-Down. Power

management bits in control register set as

PMGT 1 = 1, PMGT 0 = 0.

600

10

600

10

With External Clock Off

300

µA typ

Partial Power-Down. Power management bits in

control register set as PMGT 1 = 1, PMGT 0 = 1.

Normal Mode Power Dissipation

Sleep Mode Power Dissipation

With External Clock On

89.25

mW max

V_DD= 5.25 V: T ypically 63 mW; SLEEP = V_DD

.

105

µW typ

V_DD= 5.25 V; SLEEP = 0 V

With External Clock Off

52.5

µW max

V_DD= 5.25 V; T ypically 5.25 µW; SLEEP = 0 V

SYST EM CALIBRAT ION

Offset Calibration Span⁷

Gain Calibration Span⁷

+0.05 × V_REF/–0.05 × V_REF

+1.025 × V_REF/–0.975 × V_REFV max/min Allowable Full-Scale Voltage Span for Calibratio

V max/min Allowable Offset Voltage Span for Calibration

n

NOT ES

¹T emperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to +125°C.

²Specifications apply after calibration.

³SNR calculation includes distortion and noise components.

⁴Sample tested @ +25°C to ensure compliance.

⁵All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital outputs. Analog inputs @ AGND.

⁶CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV_DD. No load on the digital outputs.

Analog inputs @ AGND.

⁷T he offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are

not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V_REF, and the

allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V_REF± 0.025 × V_REF). T his is

explained in more detail in the calibration section of the data sheet.

Specifications subject to change without notice.

REV. A

–3–

AD7851

1

(AV = DV = +5.0 V ؎ 5%; f_CLKIN= 6 MHz, T = T_MINto T , unless otherwise noted)

TIMING SPECIFICATIONS

DD

A

MAX

Lim it at T_MIN, T_MAX

A, K

P aram eter

Units

D escription

Master Clock Frequency

2

f_CLKIN

500

kHz min

MHz max

ns min

7

10

3

f_SCLK

Interface Modes 1, 2, 3 (External Serial Clock)

Interface Modes 4, 5 (Internal Serial Clock)

CONVST Pulse Width

f_{CLK IN}

100

4

t₁

t₂

50

3.25

–0.4 t_SCLK

±0.4 t_SCLK

0.6 t_SCLK

30

45

30

ns max

µs max

ns min

ns min/max

ns min

ns max

ns min

CONVST↓ to BUSY↑ Propagation Delay

Conversion T ime = 20 t_CLKIN

t_CONVERT

t₃

SYNC↓ to SCLK↓ Setup T ime (Noncontinuous SCLK Input)

SYNC↓ to SCLK↓ Setup T ime (Continuous SCLK Input)

SYNC↓ to SCLK↓ Setup T ime. Interface Mode 4 Only

Delay from SYNC↓ until DOUT 3-State Disabled

Delay from SYNC↓ until DIN 3-State Disabled

Data Access T ime After SCLK↓

t₄

t₅

5

t_5A₅

t₆

t₇

Data Setup T ime Prior to SCLK↑

t₈₆

20

ns min

ns min/max

ns max

ms typ

Data Valid to SCLK Hold T ime

t₉

0.4 t_SCLK

30

30/0.4 t_SCLK

50

90

50

SCLK High Pulse Width (Interface Modes 4 and 5)

SCLK Low Pulse Width (Interface Modes 4 and 5)

SCLK↑ to SYNC↑ Hold T ime (Noncontinuous SCLK)

(Continuous SCLK) Does Not Apply to Interface Mode 3

SCLK↑ to SYNC↑ Hold T ime

Delay from SYNC↑ until DOUT 3-State Enabled

Delay from SCLK↑ to DIN Being Configured as Output

Delay from SCLK↑ to DIN Being Configured as Input

CAL↑ to BUSY↑ Delay

6

t₁₀

t₁₁

t_11A

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t_CAL

7

8

2.5 t_CLKIN

41.7

CONVST↓ to BUSY↑ Delay in Calibration Sequence

Full Self-Calibration T ime, Master Clock Dependent (250026

9

t_CLKIN

Internal DAC Plus System Full-Scale Cal T ime, Master Clock

Dependent (222228 t_CLKIN

System Offset Calibration T ime, Master Clock Dependent

(27798 t_CLKIN

Delay from CLK to SCLK

)

9

t_CAL1

37.04

4.63

65

ms typ

ns max

)

9

t_CAL2

)

t_DELAY

NOT ES

Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARIT Y pin HIGH. For the POLARIT Y pin LOW then the opposite edge of

SCLK will apply.

¹Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V. See

T able X and timing diagrams for different interface modes and calibration.

²Mark/Space ratio for the master clock input is 40/60 to 60/40.

³For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f _CLKIN

.

⁴T he CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-

Down section).

⁵Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

⁶For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t _SCLK= 0.5 t_CLKIN

.

⁷t₁₂is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t ₁₂, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

⁸t₁₄is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time quoted in the timing characteristics is the true delay of the part in

turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will

not occur.

⁹T he typical time specified for the calibration times is for a master clock of 6 MHz.

Specifications subject to change without notice.

REV. A

–4–

AD7851

TYP ICAL TIMING D IAGRAMS

I

1.6mA

OL

Figures 2 and 3 show typical read and write timing diagrams.

Figure 2 shows the reading and writing after conversion in In-

terface Modes 2 and 3. T o attain the maximum sample rate of

285 kHz in Interface Modes 2 and 3, reading and writing must

be performed during conversion. Figure 3 shows the timing dia-

gram for Interface Modes 4 and 5 with sample rate of 285 kHz.

At least 330 ns acquisition time must be allowed (the time from

the falling edge of BUSY to the next rising edge of CONVST)

before the next conversion begins to ensure that the part is

settled to the 14-bit level. If the user does not want to provide

the CONVST signal, the conversion can be initiated in software

by writing to the control register.

TO

OUTPUT

+2.1V

C

L

50pF

I

200µA

OH

Figure 1. Load Circuit for Digital Output Tim ing

Specifications

t_CONVERT= 3.25µs MAX, t₁= 100ns MIN,

t₅= 30ns MAX, t₇= 30ns MIN

POLARITY PIN LOGIC HIGH

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (I/P)

t₃

t₁₁

t₉

1

5

6

16

SCLK (I/P)

DOUT (O/P)

DIN (I/P)

t₁₀

t₅

3-STATE

t₆

DB11

t₁₂

t₆

DB15

3-STATE

DB0

t₇

t₈

DB15

DB0

DB11

Figure 2. AD7851 Tim ing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

t_CONVERT= 3.25µs MAX, t₁= 100ns MIN,

t₅= 30ns MAX, t₇= 30ns MIN

POLARITY PIN LOGIC HIGH

t₁

CONVST (I/P)

t_CONVERT

t₂

BUSY (O/P)

SYNC (O/P)

t₄

t₁₁

t₉

1

5

6

16

SCLK (O/P)

DOUT (O/P)

DIN (I/P)

t₁₀

t₅

3-STATE

t₁₂

3-STATE

t₆

DB11

DB15

DB0

t₇

t₈

DB15

DB0

DB11

Figure 3. AD7851 Tim ing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

REV. A

–5–

AD7851

ABSO LUTE MAXIMUM RATINGS ¹

P INO UT FO R D IP , SO IC AND SSO P

(T _A= +25°C unless otherwise noted)

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

REF_IN/REF_OUTto AGND . . . . . . . . . –0.3 V to AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies². . . . . . . . ±10 mA

Operating T emperature Range

Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C

Storage T emperature Range . . . . . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

θ_JCT hermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

Lead T emperature, (Soldering, 10 secs) . . . . . . . . . . +260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

24

1

2

SYNC

SCLK

CLKIN

DIN

CONVST

BUSY

23

22

21

20

19

18

17

3

SLEEP

4

REF /REF

IN

OUT

AV

5

DOUT

DGND

DD

AD7851

TOP VIEW

(Not to Scale)

AGND

6

C

7

DV

DD

1

2

REF

C

8

CAL

REF

AIN(+)

AIN(–)

NC

16 SM2

9

10

11

15

14

SM1

POLARITY

AGND 12

13 AMODE

θ

_JAThermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

θ_JCThermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

Lead T emperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV

NOT ES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²T ransient currents of up to 100 mA will not cause SCR latch-up.

O RD ERING GUID E ¹

Linearity

Error

Tem p

Range

Throughput Throughput P ackage

Model

(LSB)²

Rate

@ +125؇C

O ptions³

AD7851AN

AD7851KN

AD7851AR

AD7851KR

–40°C to +85°C

0°C to +85°C

–40°C to +85°C

0°C to +85°C

±2

±1

±2

±1

±2

333 kSPS

285 kSPS

333 kSPS

285 kSPS

333 kSPS

238 kSPS

N-24

R-24

RS-24

AD7851ARS

–40°C to +85°C

EVAL-AD7851CB⁴

EVAL-CONT ROL BOARD⁵

NOT ES

¹Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).^.

²Linearity error refers to the integral linearity error.

³N = Plastic DIP; R = SOIC; RS = SSOP.

⁴T his can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONT ROL BOARD for evaluation/demonstration

purposes.

⁵T his board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the

CB designators.

REV. A

–6–

AD7851

TERMINO LO GY

Total H ar m onic D istor tion

Integr al Nonlinear ity

T otal harmonic distortion (T HD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7851, it is defined as:

T his is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. T he end-

points of the transfer function are zero scale, a point 1/2 LSB

below the first code transition, and full scale, a point 1/2 LSB

above the last code transition.

2

V₂+V₃+V₄+V₅+V₆

THD(dB) = 20log

V₁

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

D iffer ential Nonlinear ity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

P eak H ar m onic or Spur ious Noise

Total Unadjusted Er r or

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

T his is the deviation of the actual code from the ideal code tak-

ing all errors into account (Gain, Offset, Integral Nonlinearity,

and other errors) at any point along the transfer function.

Unipolar O ffset Er r or

T his is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)

when operating in the unipolar mode.

Inter m odulation D istor tion

P ositive Full-Scale Er r or

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are

those for which neither m nor n are equal to zero. For example,

the second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and

(fa – 2fb).

T his applies to the unipolar and bipolar modes and is the devia-

tion of the last code transition from the ideal AIN(+) voltage

(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been

adjusted out.

Negative Full-Scale Er r or

T his applies to the bipolar mode only and is the deviation of the

first code transition (00 . . . 000 to 00 . . . 001) from the ideal

AIN(+) voltage (AIN(–) – V_REF/2 + 0.5 LSB).

T esting is performed using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used. In

this case, the second order terms are usually distanced in fre-

quency from the original sine waves while the third order terms

are usually at a frequency close to the input frequencies. As a

result, the second and third order terms are specified separately.

T he calculation of the intermodulation distortion is as per the

T HD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in dBs.

Bipolar Zer o Er r or

T his is the deviation of the midscale transition (all 0s to all 1s)

from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).

Tr ack/H old Acquisition Tim e

T he track/hold amplifier returns into track mode and the end of

conversion. T rack/Hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion.

Signal to (Noise + D istor tion) Ratio

P ower Supply Rejection Ratio

T his is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. T he signal is the rms amplitude of

the fundamental. Noise is the sum of all nonfundamental sig-

nals up to half the sampling frequency (f_S/2), excluding dc. T he

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantiza-

tion noise. T he theoretical signal to (noise + distortion) ratio for

an ideal N-bit converter with a sine wave input is given by:

Power Supply Rejection Ratio (PSRR) is defined as the ratio of

the power in ADC output at frequency f to the power of the full-

scale sine wave applied to the supply voltage (V_DD). T he units

are in LSB, %of FS per % of supply voltage, or expressed loga-

rithmically, in dB (PSRR (dB) = 10 log(Pf/Pfs)).

Full P ower Bandwidth

T he Full Power Bandwidth (FPBW) is that frequency at which

the amplitude of the reconstructed (using FFT s) fundamental

(neglecting harmonics and SNR) is reduced by 3 dB for a full-

scale input.

Signal to (Noise + Distortion) = (6.02 N +1.76) dB

T hus for a 14-bit converter, this is 86 dB.

REV. A

–7–

AD7851

P IN FUNCTIO N D ESCRIP TIO N

P in Mnem onic

D escription

1

CONVST

Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and

starts conversion. When this input is not used, it should be tied to DV_DD

.

2

BUSY

Busy Output. T he busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed

its on-chip calibration sequence.

3

4

SLEEP

Sleep Input/Low Power Mode. A logic 0 initiates a sleep and all circuitry is powered down including the in-

ternal voltage reference provided there is no conversion or calibration being performed. Calibration data is

retained. A logic 1 results in normal operation. See Power-Down section for more details.

REF_IN

/

Reference Input/Output. T his pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. T he nominal reference voltage is 4.096 V and this ap-

REF_OUT

pears at the pin. T his pin can be overdriven by an external reference or can be taken as high as AV_DD

.

When this pin is tied to AV_DD, then the C_REF1pin should also be tied to AV_DD

.

5

AV_DD

Analog Positive Supply Voltage, +5.0 V ± 5%.

6, 12 AGND

Analog Ground. Ground reference for track/hold, reference and DAC.

7

C_REF1

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). T his external capacitor is

used as a charge source for the internal DAC. T he capacitor should be tied between the pin and AGND.

8

C_REF2

Reference Capacitor (0.01 µF ceramic disc in parallel with a 470 nF NPO type). T his external capacitor is

used in conjunction with the on-chip reference. T he capacitor should be tied between the pin and AGND.

9

AIN(+)

AIN(–)

Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time, and cannot go below AIN(–) when the unipolar input range is selected.

10

Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

AV_DDat any time.

11

13

NC

No Connect Pin.

AMODE

Analog Mode Pin. T his pin allows two different analog input ranges to be selected. A logic 0 selects range 0

to V_REF(i.e., AIN(+) – AIN(–) = 0 to V_REF). In this case AIN(+) cannot go below AIN(–) and

AIN(–) cannot go below AGND. A logic 1 selects range –V_REF/2 to +V_REF/2 (i.e., AIN(+) – AIN(–) =

–V_REF/2 to +V_REF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to

+V_REF/2 to allow AIN(+) to go from 0 V to +V_REFV.

14

POLARIT Y

Serial Clock Polarity. T his pin determines the active edge of the serial clock (SCLK). T oggling this pin will

reverse the active edge of the serial clock (SCLK). A logic 1 means that the serial clock (SCLK) idles high

and a logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and

T able X for the SCLK active edges.

15

16

17

SM1

SM2

CAL

Serial Mode Select Pin. T his pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in T able XI.

Serial Mode Select Pin. T his pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in T able XI.

Calibration Input. T his pin has an internal pull-up current source of 0.15 µA. A logic 0 on this pin resets all

logic and initiates a calibration on its rising edge. T here is the option of connecting a 10 nF capacitor from

this pin to AGND to allow for an automatic self calibration on power-up. T his input overrides all other

internal operations.

18

19

20

21

DV_DD

DGND

DOUT

DIN

Digital Supply Voltage, +5.0 V ± 5%.

Digital Ground. Ground reference point for digital circuitry.

Serial Data Output. T he data output is supplied to this pin as a 16-bit serial word.

Serial Data Input. T he data to be written is applied to this pin in serial form (16-bit word). T his pin can act

as an input pin or as a I/O pin depending on the serial interface mode the part is in (see T able XI).

22

23

CLKIN

SCLK

Master Clock Signal for the device (6 MHz or 7 MHz). Sets the conversion and calibration times.

Serial Port Clock. Logic input/output. T he SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. T he SCLK idles high or low depending on the state of the POLARIT Y pin.

24

SYNC

T his pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see T able XI).

REV. A

–8–

AD7851

AD 7851 O N-CH IP REGISTERS

T he AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7851 will

operate as a Read-Only ADC. T he AD7851 still retains the flexibility for performing a full power-down, and a full self-calibration.

Note that the DIN pin should be tied to DGND for operating the AD7851 as a Read-Only ADC.

Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-

bration, and software conversion start can be selected by writing to the part.

T he AD7851 contains a Contr ol r egister, AD C output data r egister, Status r egister, Test r egister and 10 Calibr ation r egis-

ter s. T he control register is write-only, the ADC output data register and the status register are read-only, and the test and calibra-

tion registers are both read/write registers. T he test register is used for testing the part and should not be written to.

Addr essing the O n-Chip Register s

Wr iting

A write operation to the AD7851 consists of 16 bits. T he two MSBs, ADDR0 and ADDR1, are decoded to determine which register

is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that the

data is latched into the addressed register. T able I shows the decoding of the address bits, while Figure 4 shows the overall write reg-

ister hierarchy.

Table I. Write Register Addressing

AD D R1

AD D R0

Com m ent

0

1

0

1

0

T his combination does not address any register so the subsequent 14 data bits are ignored.

This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.

T his combination addresses the CALIBRATIO N REGISTERS. T he subsequent 14 data bits are written

to the selected calibration register.

1

T his combination addresses the CO NTRO L REGISTER. T he subsequent 14 data bits are written to the

control register.

Rea ding

T o read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT 0 and RDSLT 1. T hese

bits are decoded to determine which register is addressed during a read operation. T able II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. T he power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RD SLT1 RD SLT0 Com m ent

0

All successive read operations will be from AD C O UTP UT D ATA REGISTER. T his is the power-up de-

fault setting. T here will always be four leading zeros when reading from the ADC output data register.

0

1

0

1

All successive read operations will be from TEST REGISTER.

All successive read operations will be from CALIBRATIO N REGISTERS.

All successive read operations will be from STATUS REGISTER.

RDSLT1, RDSLT0

ADDR1, ADDR0

DECODE

00

01

TEST

10

11

01

TEST

10

11

ADC OUTPUT

DATA REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

CALIBRATION

REGISTERS

CONTROL

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

10

GAIN (1)

11

OFFSET (1)

10

GAIN (1)

11

00

01

00

01

CALSLT1, CALSLT0

DECODE

CALSLT1, CALSLT0

DECODE

Figure 5. Read Register Hierarchy/Address Decoding

Figure 4. Write Register Hierarchy/Address Decoding

REV. A

–9–

AD7851

CO NTRO L REGISTER

T he arrangement of the control register is shown below. T he control register is a write only register and contains 14 bits of data. T he

control register is selected by putting two 1s in ADDR1 and ADDR0. T he function of the bits in the control register are described

below. T he power-up status of all bits is 0.

M S B

ZERO

PMGT 1

CALST 1

PMGT 0

PMGT 1

RDSLT 0 2/3 MODE CON VST

C ALM D

CALSLT 0

ST CAL

LSB

Control Register Bit Function D escription

Bit

Mnem onic

Com m ent

T hese four bits must be set to 0 when writing to the control register.

13

12

11

10

ZERO

9

8

PMGT 1

PMGT 0

Power Management Bits. T hese two bits are used with the SLEEP pin for putting the part into various

power-down modes (see Power-Down section for more details).

7

6

RDSLT 1

RDSLT 0

T heses two bits determine which register is addressed for the read operations. See T able II.

5

2/3 MODE

Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. T his bit is set to 0 by

default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every

write cycle.

4

3

CONVST

CALMD

Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. T his bit may also used in conjunction with system calibration

(see Calibration section on page 21).

Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2

1

0

CALSLT 1

CALSLT 0

ST CAL

Calibration Selection Bits and Start Calibration Bit. T hese bits have two functions.

With the ST CAL bit set to 1, the CALSLT 1 and CALSLT 0 bits determine the type of calibration per-

formed by the part (see T able III). T he ST CAL bit is automatically reset to 0 at the end of calibration.

With the ST CAL bit set to 0, the CALSLT 1 and CALSLT 0 bits are decoded to address the calibration

register for read/write of calibration coefficients (see section on the calibration registers for more details).

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

0

A full inter nal calibr ation is initiated where the internal DAC is calibrated followed by the

internal gain error and finally the internal offset error is calibrated out. This is the default setting.

0

1

Here the internal gain error is calibrated out followed by the internal offset error calibrated

out.

0

1

0

1

0

T his calibrates out the inter nal offset er r or only.

T his calibrates out the inter nal gain er r or only.

A full system calibr ation is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out.

1

0

1

0

1

Here the system gain er r or is calibrated out followed by the system offset er r or.

T his calibrates out the system offset er r or only.

T his calibrates out the system gain er r or only.

REV. A

–10–

AD7851

STATUS REGISTER

T he arrangement of the status register is shown below. T he status register is a read-only register and contains 16 bits of data. T he

status register is selected by first writing to the control register and putting two 1s in RDSLT 1 and RDSLT 0. T he function of the

bits in the status register are described below. T he power-up status of all bits is 0.

START

WRITE TO CONTROL REGISTER

SETTING RDSLT0 = RDSLT1 = 1

READ STATUS REGISTER

Figure 6. Flowchart for Reading the Status Register

M S B

ZERO

BUSY

ZERO

X

ZERO

PMGT 1

PMGT 0

RDSLT 1

RDSLT 0 2/3 MODE

C ALM D

CALSLT 1 CALSLT 0

ST CAL

LSB

Status Register Bit Function D escription

Bit Mnem onic

Com m ent

T his bit is always 0.

15

ZERO

BUSY

14

Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration

in progress. When this bit is 0, there is no conversion or calibration in progress.

13

12

11

10

ZERO

T hese four bits are always 0.

9

8

PMGT 1

PMGT 0

Power Management Bits. T hese bits along with the SLEEP pin will indicate if the part is in a power-down

mode or not. See T able VI in Power-Down Section for description.

7

6

ONE

Both these bits are always 1 indicating it is the status register that is being read. See T able II.

5

2/3 MODE

Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in

Interface Mode 1. T his bit is reset to 0 after every read cycle.

4

3

X

Don’t care bit.

CALMD

Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a

system calibration is selected (see T able III).

2

1

0

CALSLT 1

CALSLT 0

ST CAL

Calibration Selection Bits and Start Calibration Bit. T he ST CAL bit is read as a 1 if a calibration is in

progress and as a 0 if there is no calibration in progress. T he CALSLT 1 and CALSLT 0 bits indicate

which of the calibration registers are addressed for reading and writing (see section on the Calibration

Registers for more details).

REV. A

–11–

AD7851

CALIBRATIO N REGISTERS

T he AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to or read from all

10 calibration registers. In self and system calibration the part automatically modifies the calibration registers; only if the user needs

to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addr essing the Calibr ation Register s

T he calibration selection bits in the control register CALSLT 1 and CALSLT 0 determine which of the calibration registers are ad-

dressed (see T able IV). T he addressing applies to both the read and write operations for the calibration registers. T he user should

not attempt to read from and write to the calibration registers at the same time.

Table IV. Calibration Register Addressing

CALSLT1 CALSLT0

Com m ent

0

1

0

1

0

1

T his combination addresses the Gain (1), O ffset (1) and D AC Register s (8). T en registers in total.

T his combination addresses the Gain (1) and O ffset (1) Registers. T wo registers in total.

T his combination addresses the O ffset Register. One register in total.

T his combination addresses the Gain Register. One register in total.

When reading from the calibration registers there will always be

two leading zeros for each of the registers. When operating in

serial Interface Mode 1, the read operations to the calibration

registers cannot be aborted. T he full number of read operations

must be completed (see section on serial Interface Mode 1 tim-

ing for more detail).

Wr iting to/Reading fr om the Calibr ation Register s

For writing to the calibration registers a write to the control reg-

ister is required to set the CALSLT 0 and CALSLT 1 bits. For

reading from the calibration registers a write to the control reg-

ister is required to set the CALSLT 0 and CALSLT 1 bits, but

also to set the RDSLT 1 and RDSLT 0 bits to 10 (this addresses

the calibration registers for reading). T he calibration register

pointer is reset on writing to the control register setting the

CALSLT 1 and CALSLT 0 bits, or upon completion of all the

calibration register write/read operations. When reset it points

to the first calibration register in the selected write/read

sequence. T he calibration register pointer will point to the gain

calibration register upon reset in all but one case, this case be-

ing where the offset calibration register is selected on its own

(CALSLT 1 = 1, CALSLT 0 = 0). Where more than one cali-

bration register is being accessed, the calibration register

pointer will be automatically incremented after each calibration

register write/read operation. T he order in which the 10 calibra-

tion registers are arranged is shown in Figure 7. T he user may

abort at any time before all the calibration register write/read

operations are completed, and the next control register write

operation will reset the calibration register pointer. T he flow-

chart in Figure 8 shows the sequence for writing to the calibra-

tion registers and Figure 9 for reading.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

REGISTER

CALIBRATION REGISTERS

CAL REGISTER

ADDRESS POINTER

NO

WRITE

OPERATION

OR

ABORT

?

(1)

(2)

GAIN REGISTER

OFFSET REGISTER

(3)

DAC 1st MSB REGISTER

YES

FINISHED

(10)

DAC 8th MSB REGISTER

CALIBRATION REGISTER ADDRESS POINTER POSITION IS

DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS

ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.

Figure 8. Flowchart for Writing to the Calibration Registers

Figure 7. Calibration Register Arrangem ent

REV. A

–12–

AD7851

T his gives a resolution of ±0.0006% of V_REFapproximately.

More accurately the resolution is ±(0.05 × V_REF)/2¹³volts =

±0.015 mV, with a 2.5 V reference. T he maximum offset that

can be compensated for is ±5% of the reference voltage, which

equates to ±125 mV with a 2.5 V reference and ±250 mV with a

5 V reference.

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,

RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

Q. If a +20 mV offset is present in the analog input signal and the

reference voltage is 2.5 V, what code needs to be written to the

offset register to compensate for the offset?

READ CAL REGISTER

A. 2.5 V reference implies that the resolution in the offset reg-

ister is 5% × 2.5 V/2¹³= 0.015 mV. +20 mV/0.015 mV =

1310.72; rounding to the nearest number gives 1311. In

binary terms this is 0101 0001 1111, therefore decrease the

offset register by 0101 0001 1111.

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

T his method of compensating for offset in the analog input sig-

nal allows for fine tuning the offset compensation. If the offset

on the analog input signal is known, there will be no need to

apply the offset voltage to the analog input pins and do a system

calibration. T he offset compensation can take place in software.

LAST

REGISTER

NO

WRITE

OPERATION

OR

ABORT

?

Adjusting the Gain Calibr ation Register

YES

T he gain calibration register contains 16 bits, two leading 0s

and 14 data bits. T he data bits are binary weighted as in the off-

set calibration register. T he gain register value is effectively mul-

tiplied by the analog input to scale the conversion result over the

full range. Increasing the gain register compensates for a

smaller analog input range and decreasing the gain register com-

pensates for a larger input range. T he maximum analog input

range that the gain register can compensate for is 1.025 times

the reference voltage, and the minimum input range is 0.975

times the reference voltage.

FINISHED

Figure 9. Flowchart for Reading from the Calibration

Registers

Adjusting the O ffset Calibr ation Register

T he offset calibration register contains 16 bits, two leading zeros

and 14 data bits. By changing the contents of the offset register,

different amounts of offset on the analog input signal can be

compensated for. Increasing the number in the offset calibration

register compensates for negative offset on the analog input sig-

nal, and decreasing the number in the offset calibration register

compensates for positive offset on the analog input signal. T he

default value of the offset calibration register is 0010 0000 0000

0000 approximately. T his is not an exact value, but the value in

the offset register should be close to this value. Each of the 14

data bits in the offset register is binary weighted; the MSB has a

weighting of 5% of the reference voltage, the MSB-1 has a

weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so

on down to the LSB which has a weighting of 0.0006%.

REV. A

–13–

AD7851

CIRCUIT INFO RMATIO N

not met, the conversion will take 19.5 CLKIN periods. T he

maximum specified conversion time is 3.25 µs (6 MHz ) and

2.8 µs (7 MHz) for the A and K Grades respectively for the

AD7851 (19.5 t_CLKIN,CLKIN = 6/7 MHz). When a conversion

is completed, the BUSY output goes low, and then the result of

the conversion can be read by accessing the data through the se-

rial interface. T o obtain optimum performance from the part,

the read operation should not occur during the conversion or

500 ns prior to the next CONVST rising edge. However, the

maximum throughput rates are achieved by reading/writing dur-

ing conversion, and reading/writing during conversion is likely

to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The

AD7851 can operate at throughput rates up to 333 kHz. For the

AD7851 a conversion takes 19.5 CLKIN periods, 2 CLKIN

periods are needed for the acquisition time giving a full cycle

time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz) for the K grade

and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for the A grade.

T he AD7851 is a fast, 14-bit single supply A/D converter. T he

part requires an external 6/7 MHz master clock (CLKIN), two

C_REFcapacitors, a CONVST signal to start conversion and

power supply decoupling capacitors. T he part provides the user

with track/hold, on-chip reference, calibration features, A/D

converter and serial interface logic functions on a single chip.

T he A/D converter section of the AD7851 consists of a conven-

tional successive-approximation converter based around a ca-

pacitor DAC. T he AD7851 accepts an analog input range of

0 V to +V_DDwhere the reference can be tied to V_DD. T he refer-

ence input to the part is buffered onchip.

A major advantage of the AD7851 is that a conversion can be

initiated in software as well as applying a signal to the CONVST

pin. Another innovative feature of the AD7851 is self-calibration

on power-up, which is initiated having a 0.01 µF capacitor from

the CAL pin to AGND, to give superior dc accuracy. T he part

should be allowed 150 ms after power-up to perform this auto-

matic calibration before any reading or writing takes place. T he

part is available in a 24-pin SSOP package and this offers the user

considerable space saving advantages over alternative solutions.

TYP ICAL CO NNECTIO N D IAGRAM

Figure 10 shows a typical connection diagram for the AD7851.

T he DIN line is tied to DGND so that no data is written to the

part. T he AGND and the DGND pins are connected together

at the device for good noise suppression. T he CAL pin has a

0.01 µF capacitor to enable an automatic self-calibration on

power-up. T he SCLK and SYNC are configured as outputs by

having SM1 and SM2 at DV_DD. T he conversion result is output

in a 16-bit word with 2 leading zeros followed by the MSB of

the 14-bit result. Note that after the AV_DDand DV_DDpower-up,

the part will require 150 ms for the internal reference to settle

and for the automatic calibration on power-up to be completed.

CO NVERTER D ETAILS

T he master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7851 by pulsing the

CONVST input or by writing to the control register and setting

the CONVST bit to 1. On the rising edge of CONVST (or at

the end of the control register write operation), the on-chip

track/hold goes from track to hold mode. T he falling edge of the

CLKIN signal which follows the rising edge of the edge of

CONVST signal initiates the conversion, provided the rising

edge of CONVST occurs at least 10 ns typically before this

CLKIN edge. T he conversion cycle will take 18.5 CLKIN peri-

ods from this CLKIN falling edge. If the 10 ns setup time is

For applications where power consumption is a major concern,

the SLEEP pin can be connected to DGND. See Power-Down

section for more detail on low power applications.

7MHz/6MHz

OSCILLATOR

333kHz/285kHz PULSE

GENERATOR

ANALOG (5V)

SUPPLY

0.01µF

0.1µF

10µF

CONVERSION

START INPUT

0V TO V

MASTER

CLOCK

INPUT

REF

AV

DD

DV

DD

AIN(+)

INPUT

AIN(–)

UNIPOLAR RANGE

OSCILLOSCOPE

CLKIN

SCLK

AMODE

CH1

CH2

C

SERIAL CLOCK OUTPUT

REF1

0.01µF

47nF

470nF

CONVST

SYNC

DOUT

DIN

AD7851

C

REF2

CH3

CH4

0.01µF

FRAME SYNC OUTPUT

SERIAL DATA OUTPUT

SLEEP

DV

DD

POLARITY

CAL

0.01µF

SM1

SM2

AGND

DIN AT DGND

=> NO WRITING

TO DEVICE

2 LEADING ZEROS

FOR ADC DATA

DV

DD

DGND

REF /REF

IN

OUT

SERIAL MODE

SELECTION BITS

AUTO CAL ON

POWER-UP

INTERNAL

0.01µF

REFERENCE

OPTIONAL

EXTERNAL

REFERENCE

AD1584/REF198

ANALOG (5V)

SUPPLY

0.1µF

10µF

Figure 10. Typical Circuit

–14–

REV. A

AD7851

ANALO G INP UT

When no amplifier is used to drive the analog input the source

impedance should be limited to low values. T he maximum

source impedance will depend on the amount of total harmonic

distortion (T HD) that can be tolerated. T he T HD will increase

as the source impedance increases and performance will degrade.

Figure 12 shows a graph of the total harmonic distortion vs.

analog input signal frequency for different source impedances.

With the setup as in Figure 13, the T HD is at the –90 dB level.

With a source impedance of 1 kΩ and no capacitor on the

AIN(+) pin, the T HD increases with frequency.

T he equivalent circuit of the analog input section is shown in

Figure 11. During the acquisition interval the switches are

both in the track position and the AIN(+) charges the 20 pF

capacitor through the 125 Ω resistance. On the rising edge of

CONVST switches SW1 and SW2 go into the hold position

retaining charge on the 20 pF capacitor as a sample of the signal

on AIN(+). T he AIN(–) is connected to the 20 pF capacitor,

and this unbalances the voltage at node A at the input of the

comparator. T he capacitor DAC adjusts during the remainder of

the conversion cycle to restore the voltage at node A to the cor-

rect value. T his action transfers a charge, representing the analog

input signal, to the capacitor DAC which in turn forms a digital

representation of the analog input signal. T he voltage on the

AIN(–) pin directly influences the charge transferred to the

capacitor DAC at the hold instant. If this voltage changes during

the conversion period, the DAC representation of the analog

input voltage will be altered. T herefore it is most important that

the voltage on the AIN(–) pin remains constant during the con-

version period. Furthermore, it is recommended that the AIN(–)

pin is always connected to AGND or to a fixed dc voltage.

–50

THD VS. FREQUENCY FOR DIFFERENT

SOURCE IMPEDANCES

–60

–70

R

= 560Ω

IN

–80

–90

R

= 10Ω, 10nF

IN

AS IN FIGURE 13

–100

–110

125Ω

TRACK

AIN(+)

AIN(–)

CAPACITOR

DAC

1

10

20

50

100

120

140

166

80

SW1

NODE A

SW2

TRACK

20pF

INPUT FREQUENCY – kHz

HOLD

Figure 12. THD vs. Analog Input Frequency

COMPARATOR

HOLD

In a single supply application (5 V), the V+ and V– of the op

amp can be taken directly from the supplies to the AD7851

which eliminates the need for extra external power supplies.

When operating with rail-to-rail inputs and outputs at frequen-

cies greater than 10 kHz, care must be taken in selecting the

particular op amp for the application. In particular, for single

supply applications the input amplifiers should be connected in

a gain of –1 arrangement to get the optimum performance. Fig-

ure 13 shows the arrangement for a single supply application

with a 10 Ω and 10 nF low-pass filter (cutoff frequency 320

kHz) on the AIN(+) pin. Note that the 10 nF is a capacitor with

good linearity to ensure good ac performance. Recommended

single supply op amp is the AD820.

C

REF2

Figure 11. Analog Input Equivalent Circuit

Acquisition Tim e

T he track and hold amplifier enters its tracking mode on the fall-

ing edge of the BUSY signal. T he time required for the track and

hold amplifier to acquire an input signal will depend on how

quickly the 20 pF input capacitance is charged. T he acquisition

time is calculated using the formula:

t_ACQ= 9 × (R_IN+ 125 Ω) × 20 pF

where R_INis the source impedance of the input signal, and

125 Ω, 20 pF is the input R, C.

+5V

D C/AC Applications

0.1µF

10µF

10kΩ

For dc applications high source impedances are acceptable, pro-

vided there is enough acquisition time between conversions to

charge the 20 pF capacitor. T he acquisition time can be calcu-

lated from the above formula for different source impedances.

For example with R_IN= 5 kΩ, the required acquisition time will

be 922 ns.

10kΩ

V

V+

IC1

IN

/2

10Ω

AD820

–V

REF

/2 TO +V

V

REF

TO AIN(+) OF

AD7851

10kΩ

/2

10nF

REF

V–

(NPO)

For ac applications, removing high frequency components from

the analog input signal is recommended by use of an RC low-

pass filter on the AIN(+) pin, as shown in Figure 13. In applica-

tions where harmonic distortion and signal to noise ratio are

critical, the analog input should be driven from a low impedance

source. Large source impedances will significantly affect the ac

performance of the ADC. T his may necessitate the use of an in-

put buffer amplifier. T he choice of the op amp will be a function

of the particular application.

Figure 13. Analog Input Buffering

REV. A

–15–

AD7851

Input Ranges

4.096 V/16384 = 0.25 mV when V_REF= 4.096 V. T he ideal in-

put/output transfer characteristic for the unipolar range is shown

in Figure 16.

T he analog input range for the AD7851 is 0 V to V_REFin both

the unipolar and bipolar ranges.

T he only difference between the unipolar range and the bipolar

range is that in the bipolar range the AIN(–) has to be biased up

to +V_REF/2 and the output coding is 2s complement (See T able

V and Figures 14 and 15). T he unipolar or bipolar mode is se-

lected by the AMODE pin (0 for the unipolar range and 1 for

the bipolar range).

OUTPUT

CODE

111...111

111...110

111...101

111...100

Table V. Analog Input Connections

Analog Input Input Connections Connection

FS

000...011

1LSB =

Range

AIN(+)

AIN(–)

D iagram

AMO D E

16384

000...010

1

0 V to V_REF

V_IN

AGND

V_REF/2

Figure 8

Figure 9

DGND

DV_DD

000...001

000...000

±V_REF/2²

0V 1LSB

+FS –1LSB

NOT ES

V

= (AIN(+) – AIN(–)), INPUT VOLTAGE

IN

¹Output code format is straight binary.

²Range is ±V_REF/2 biased about V_REF/2. Output code format is 2s complement.

Figure 16. AD7851 Unipolar Transfer Characteristic

Note that the AIN(–) pin on the AD7851 can be biased up

above AGND in the unipolar mode also, if required. T he ad-

vantage of biasing the lower end of the analog input range away

from AGND is that the user does not have to have the analog

input swing all the way down to AGND. T his has the advantage

in true single supply applications that the input amplifier does

not have to swing all the way down to AGND. T he upper end of

the analog input range is shifted up by the same amount. Care

must be taken so that the bias applied does not shift the upper

end of the analog input above the AV_DDsupply. In the case

where the reference is the supply, AV_DD, the AIN(–) must be

tied to AGND in unipolar mode.

Figure 15 shows the AD7851’s ±V_REF/2 bipolar analog input

configuration (where AIN(+) cannot go below 0 V so for the full

bipolar range then the AIN(–) pin should be biased to +V_REF/2).

Once again the designed code transitions occur midway between

successive integer LSB values. T he output coding is 2s comple-

ment with 1 LSB = 16384 = 4.096 V/16384 = 0.25 mV. T he

ideal input/output transfer characteristic is shown in

Figure 17.

OUTPUT

CODE

011...111

011...110

TRACK AND HOLD

AIN(+)

AIN(–)

AMPLIFIER

V

= 0 TO V

REF

STRAIGHT

BINARY

IN

DOUT

(V

/2) –1 LSB

REF

FORMAT

000...001

000...000

0V

AD7851

+ FS – 1 LSB

/2) +1 LSB

UNIPOLAR

ANALOG

INPUT RANGE

SELECTED

111...111

AMODE

(V

REF

FS = V

V

100...010

REF

FS

16384

1LSB =

100...001

100...000

Figure 14. 0 V to V_REFUnipolar Input Configuration

Tr ansfer Functions

For the unipolar range the designed code transitions occur mid-

way between successive integer LSB values (i.e., 1/2 LSB,

3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). T he output coding is

straight binary for the unipolar range with 1 LSB = FS/16384 =

V

/2

REF

= (AIN(+) – AIN(–)), INPUT VOLTAGE

V

IN

Figure 17. AD7851 Bipolar Transfer Characteristic

TRACK AND HOLD

AIN(+)

AIN(–)

AMPLIFIER

V

= 0 TO V

V

2S

IN

REF

/2

DOUT

COMPLEMENT

FORMAT

REF

DV

DD

AD7851

UNIPOLAR

ANALOG

AMODE

INPUT RANGE

SELECTED

Figure 15. ±V_REF/2 about V_REF/2 Bipolar Input Configuration

REV. A

–16–

AD7851

REFERENCE SECTIO N

AD 7851 P ERFO RMANCE CURVES

For specified performance, it is recommended that when using

an external reference this reference should be between 4 V and

the analog supply AV_DD. T he connections for the relevant refer-

ence pins are shown in the typical connection diagrams. If the

internal reference is being used, the REF_IN/REF_OUTpin should

have a 100 nF capacitor connected to AGND very close to the

REF_IN/REF_OUTpin. T hese connections are shown in Figure 18.

Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz

sample rate and 10 kHz input frequency.

0

AV = DV = 5V

DD

–20

–40

F

= 333 kHz

SAMPLE

= 10kHz

IN

SNR = 79.5dB

THD = –95.2

If the internal reference is required for use external to the ADC,

it should be buffered at the REF_IN/REF_OUTpin and a 100 nF

connected from this pin to AGND. The typical noise performance

for the internal reference, with 5 V supplies is 150 nV/√Hz @

1 kHz and dc noise is 100 µV p-p.

–60

–80

10Ω

ANALOG

SUPPLY

–100

–120

0.01µF

10µF

0.1µF

+5V

0

20

40

60

80

100

AV

DV

DD

FREQUENCY – kHz

C

REF1

0.01µF

470nF

47nF

Figure 20. FFT Plot

AD7851

Figure 21 shows the SNR versus Frequency for 5 V supply and

a 4.096 external references (5 V reference is typically 1 dB bet-

ter performance).

C

REF2

REF /REF

IN

OUT

0.1µF

79

78

77

76

75

Figure 18. Relevant Connections When Using Internal

Reference

T he other option is that the REF_IN/REF_OUTpin be overdriven

by connecting it to an external reference. T his is possible due to

the series resistance from the REF_IN/REF_OUTpin to the internal

reference. T his external reference can have a range that includes

AV_DD. When using AV_DDas the reference source, the 100 nF

capacitor from the REF_IN/REF_OUTpin to AGND should be as

close as possible to the REF_IN/REF_OUTpin, and also the C_REF1

pin should be connected to AV_DDto keep this pin at the same

level as the reference. T he connections for this arrangement are

shown in Figure 19. When using AV_DDit may be necessary to

add a resistor in series with the AV_DDsupply. T his will have the

effect of filtering the noise associated with the AV_DDsupply.

0

10

20

50

80

100

120

140

166

INPUT FREQUENCY – kHz

Figure 21. SNR vs. Frequency

Figure 22 shows the Power Supply Rejection Ratio versus

Frequency for the part. T he Power Supply Rejection Ratio is

defined as the ratio of the power in ADC output at frequency f

to the power of a full-scale sine wave.

10Ω

ANALOG

SUPPLY

0.1µF

+5V

0.01µF

10µF

PSRR (dB) = 10 log (Pf/Pfs)

AV

DV

DD

Pf = Power at frequency f in ADC output, Pfs = power of a full-

scale sine wave. Here a 100 mV peak-to-peak sine wave is

coupled onto the AV_DDsupply while the digital supply is left

unaltered.

C

REF1

0.01µF

470nF

47nF

AD7851

10Ω

C

REF2

0.01µF

REF /REF

IN

OUT

0.1µF

Figure 19. Relevant Connections When Using AV_DDas the

Reference

REV. A

–17–

AD7851

–72

–74

–76

–78

–80

–82

–84

–86

–88

a long power-down period when using the on-chip reference

(See Power-Up Times—Using On-Chip Reference).

AV = DV = 5.0V

DD

100mV pk-pk SINEWAVE ON AV

DD

When using the SLEEP pin, the power management bits

PMGT 1 and PMGT 0 should be set to zero (default status on

power-up). Bringing the SLEEP pin logic high ensures normal

operation, and the part does not power down at any stage. T his

may be necessary if the part is being used at high throughput

rates when it is not possible to power down between conver-

sions. If the user wishes to power down between conversions at

lower throughput rates (i.e., <100 kSPS for the AD7851) to

achieve better power performances, then the SLEEP pin should

be tied logic low.

REF = 4.098 EXT REFERENCE

IN

–90

If the power-down options are to be selected in software only,

then the SLEEP pin should be tied logic high. By setting the

power management bits PMGT 1 and PMGT 0 as shown in

T able VI, a Full Power-Down, Full Power-Up, Full Power-

Down Between Conversions, and a Partial Power-Down

Between Conversions can be selected.

0.91

13.4

25.7

38.3

50.3

63.5

74.8

87.4

100

INPUT FREQUENCY – kHz

Figure 22. PSRR vs. Frequency

P O WER-D O WN O P TIO NS

T he AD7851 provides flexible power management to allow the

user to achieve the best power performance for a given through-

put rate. T he power management options are selected by pro-

gramming the power management bits, PMGT 1 and PMGT 0,

in the control register and by use of the SLEEP pin. T able VI

summarizes the power-down options that are available and how

they can be selected by using either software, hardware or a

combination of both. T he AD7851 can be fully or partially pow-

ered down. When fully powered down, all the on-chip circuitry

is powered down and I_DDis 1 µA typ. If a partial power-down is

selected, then all the on-chip circuitry except the reference is

powered down and I_DDis 400 µA typ. T he choice of full or par-

tial power-down does not give any significant improvement in

throughput with a power-down between conversions. T his is dis-

cussed in the next section—Power-Up Times. But a partial

power-down does allow the on-chip reference to be used exter-

nally even though the rest of the AD7851 circuitry is powered

down. It also allows the AD7851 to be powered up faster after

A combination of hardware and software selection can also be

used to achieve the desired effect.

Table VI. P ower Managem ent O ptions

P MGT1 P MGT0 SLEEP

Bit

P in

Com m ent

0

Full Power-Down Between

Conversions (HW/SW)

0

1

X

Full Power-Up (HW/SW)

Full Power-Down Between

Conversions (SW)

1

0

1

X

Full Power-Down (SW)

Partial Power-Down Between

Conversions (SW)

NOT E

SW = Software selection, HW = Hardware selection.

CURRENT, I = 12mA TYP

ANALOG

6/7MHz

OSCILLATOR

285/333kHz PULSE

GENERATOR

(+5V)

SUPPLY

0.01µF

0.1µF

10µF

0V TO V

MASTER

CLOCK

INPUT

REF

AV

DD

DV

DD

AIN(+)

INPUT

AIN(–)

UNIPOLAR RANGE

CLKIN

SCLK

AMODE

SERIAL CLOCK OUTPUT

C

REF1

0.01µF

47nF

470nF

CONVST

SYNC

CONVERSION

START INPUT

LOW POWER

µC/µP

C

AD7851

REF2

0.01µF

DOUT

DIN

SLEEP

SERIAL DATA OUTPUT

AUTO POWER-

DOWN AFTER

CONVERSION

DIN AT DGND

=> NO WRITING

TO DEVICE

DV

POLARITY

CAL

DD

0.01µF

AGND

SM1

SM2

SERIAL MODE

SELECTION BITS

REF /REF

IN

DGND

OUT

AUTO CAL ON

POWER-UP

3-WIRE MODE

SELECTED

INTERNAL

REFERENCE

OPTIONAL

EXTERNAL

0.01µF

REF198

REFERENCE

Figure 23. Typical Low Power Circuit

–18–

REV. A

AD7851

P O WER-UP TIMES

Using An Exter nal Refer ence

When using the on-chip reference and powering up when AV_DD

and DV_DDare first connected, it is recommended that the

power-up calibration mode be disabled as explained above.

When using the on-chip reference, the power-up time is effec-

tively the time it takes to charge up the external capacitor on the

REF_IN/REF_OUTpin. T his time is given by the equation:

When the AD7851 are powered up, the parts are powered up

from one of two conditions. First, when the power supplies are

initially powered up and, secondly, when the parts are powered

up from either a hardware or software power-down (see last

section).

t_UP= 9 × R × C

When AV_DDand DV_DDare powered up, the AD7851 enters a

mode whereby the CONVST signal initiates a timeout followed

by a self-calibration. T he total time taken for this time-out and

calibration is approximately 35 ms—see Calibration on Power-Up

in the calibration section of this data sheet. During power-up

the functionality of the SLEEP pin is disabled, i.e., the part will

not power down until the end of the calibration if SLEEP is tied

logic low. T he power-up calibration mode can be disabled if the

user writes to the control register before a CONVST signal is

applied. If the time out and self-calibration are disabled, then

the user must take into account the time required by the

AD7851 to power up before a self-calibration is carried out.

T his power-up time is the time taken for the AD7851 to power

up when power is first applied (300 µs typ) or the time it takes

the external reference to settle to the 14-bit level—whichever is

the longer.

where R ≈ 150K and C = external capacitor.

T he recommended value of the external capacitor is 100 nF;

this gives a power-up time of approximately 135 ms before a

calibration is initiated and normal operation should commence.

When C_REFis fully charged, the power-up time from a hardware

or software power-down reduces to 5 µs. T his is because an

internal switch opens to provide a high impedance discharge

path for the reference capacitor during power-down—see Figure

25. An added advantage of the low charge leakage from the

reference capacitor during power-down is that even though the

reference is being powered down between conversions, the refer-

ence capacitor holds the reference voltage to within 0.5 LSBs

with throughput rates of 100 samples/second and over with a

full power-down between conversions. A high input impedance

op amp like the AD707 should be used to buffer this reference

capacitor if it is being used externally. Note, if the AD7851 is

left in its powered-down state for more than 100 ms, the charge

on C_REFwill start to leak away and the power-up time will

increase. If this long power-up time is a problem, the user can

use a partial power-down for the last conversion so the reference

remains powered up.

T he AD7851 powers up from a full hardware or software

power-down in 5 µs typ. T his limits the throughput which the

part is capable of to 120 kSPS for the K Grade and 126 kSPS

for the A Grade when powering down between conversions. Fig-

ure 24 shows how power-down between conversions is imple-

mented using the CONVST pin. T he user first selects the

power-down between conversions option by using the SLEEP

pin and the power management bits, PMGT 1 and PMGT 0, in

the control register. See last section. In this mode the AD7851

automatically enters a full power-down at the end of a conver-

sion, i.e., when BUSY goes low. T he falling edge of the next

CONVST pulse causes the part to power up. Assuming the ex-

ternal reference is left powered up, the AD7851 should be ready

for normal operation 5 µs after this falling edge. T he rising edge

of CONVST initiates a conversion so the CONVST pulse

should be at least 5 µs wide. T he part automatically powers

down on completion of the conversion. Where the software con-

vert start is used, the part may be powered up in software before

a conversion is initiated.

SWITCH OPENS

AD7851

DURING POWER-DOWN

REF /REF

IN

OUT

ON-CHIP

REFERENCE

EXTERNAL

CAPACITOR

TO OTHER

CIRCUITRY

BUF

Figure 25. On-Chip Reference During Power-Down

P O WER VS. TH RO UGH P UT RATE

T he main advantage of a full power-down after a conversion is

that it significantly reduces the power consumption of the part

at lower throughput rates. When using this mode of operation,

the AD7851 is only powered up for the duration of the conver-

sion. If the power-up time of the AD7851 is taken to be 5 µs

and it is assumed that the current during power up is 12 mA

typ, then power consumption as a function of throughput can

easily be calculated. T he AD7851 has a conversion time of

3.25 µs with a 6 MHz external clock. T his means the AD7851

consumes 12 mA typ for 8.25 µs in every conversion cycle if the

parts are powered down at the end of a conversion. T he graph,

Figure 26, shows the power consumption of the AD7851 as a

function of throughput. T able VII lists the power consump-

tion for various throughput rates.

START CONVERSION ON RISING EDGE

POWER-UP ON FALLING EDGE

5µs

3.25µs

CONVST

t

CONVERT

BUSY

POWER-UP

TIME

NORMAL

OPERATION POWER-DOWN

FULL

POWER-UP

TIME

Figure 24. Using the CONVST Pin to Power Up the AD7851

for a Conversion

Using The Inter nal (O n-Chip) Refer ence

As in the case of an external reference, the AD7851 can power

up from one of two conditions, power-up after the supplies are

connected or power-up from hardware/software power-down.

REV. A

–19–

AD7851

Table VIII. Calibration Tim es (AD 7851 with 6 MH z CLKIN)

Table VII. P ower Consum ption vs. Throughput

Type of Self- or System Calibration

Tim e

P ower

Throughput Rate

AD 7851

Full

Gain + Offset

Offset

41.7 ms

9.26 ms

4.63 ms

1 kSPS

2 kSPS

9 mW

18 mW

Gain

100

Autom atic Calibr ation on P ower -O n

T he CAL pin has a 0.15 µA pull-up current source connected to

it internally to allow for an automatic full self-calibration on

power-on. A full self-calibration will be initiated on power-on if

a 10 nF capacitor is connected from the CAL pin to AGND.

T he internal current source connected to the CAL pin charges

up the external capacitor and the time required to charge the ex-

ternal capacitor will be 100 ms approximately. T his time is large

enough to ensure that the internal reference is settled before the

calibration is performed. However, if an external reference is be-

ing used, this reference must have stabilized before the auto-

matic calibration is initiated (if larger time than 100 ms is

required then a larger capacitor on the CAL pin should be

used). After this 100 ms has elapsed, the calibration will be per-

formed which will take 42 ms/36 ms (6 MHz /7 MHz CLKIN).

T herefore 142 ms/136 ms should be allowed before operating

the part. After calibration, the part is accurate to the 14-bit level

and the specifications quoted on the data sheet apply. T here will

be no need to perform another calibration unless the operating

conditions change or unless a system calibration is required.

10

1

0.1

0.01

0

200 400 600 800 1000 1200 1400 1600 1800 2000

THROUGHPUT RATE – Hz

Figure 26. Power vs. Throughput AD7851

NOT E

When setting the power-down mode by writing to the part, it is

recommended to be operating in an interface mode other than

Interface Modes 4, and 5. T his way the user has more control to

initiate power-down, and power-up commands.

Self-Calibr ation D escr iption

T here are a four different calibration options within the self-

calibration mode. T here is a full self-calibration where the

DAC, internal offset, and internal gain errors are calibrated out.

T hen, there is the (Gain + Offset) self-calibration which cali-

brates out the internal gain error and then the internal offset er-

rors. T he internal DAC is not calibrated here. Finally, there are

the self-offset and self-gain calibrations which calibrate out the

internal offset errors and the internal gain errors respectively.

CALIBRATIO N SECTIO N

Calibr ation O ver view

T he automatic calibration that is performed on power-up en-

sures that the calibration options covered in this section will not

be required in a significant amount of applications. T he user

will not have to initiate a calibration unless the operating condi-

tions change (CLKIN frequency, analog input mode, reference

voltage, temperature, and supply voltages). T he AD7851 have a

number of calibration features that may be required in some ap-

plications and there are a number of advantages in performing

these different types of calibration. First, the internal errors in

the ADC can be reduced significantly to give superior dc perfor-

mance; and second, system offset and gain errors can be removed.

T his allows the user to remove reference errors (whether it be

internal or external reference) and to make use of the full dy-

namic range of the AD7851 by adjusting the analog input range

of the part for a specific system.

T he internal capacitor DAC is calibrated by trimming each of

the capacitors in the DAC. It is the ratio of these capacitors to

each other that is critical, and so the calibration algorithm en-

sures that this ratio is at a specific value by the end of the cali-

bration routine. For the offset and gain there are two separate

capacitors, one of which is trimmed when an offset or gain cali-

bration is performed. Again it is the ratio of these capacitors to

the capacitors in the DAC that is critical and the calibration al-

gorithm ensures that this ratio is at a specified value for both the

offset and gain calibrations.

T here are two main calibration modes on the AD7851, self-cali-

bration and system calibration. T here are various options in

both self-calibration and system calibration as outlined previ-

ously in T able III. All the calibration functions can be initiated

by pulsing the CAL pin or by writing to the control register and

setting the ST CAL bit to 1. T he timing diagrams that follow in-

volve using the CAL pin.

In bipolar mode the midscale error is adjusted for an offset

calibration and the positive full-scale error is adjusted for the

gain calibration; in unipolar mode the zero-scale error is ad-

justed for an offset calibration and the positive full-scale error is

adjusted for a gain calibration.

T he duration of each of the different types of calibrations is

given in T able VIII for the AD7851 with a 6 MHz/7 MHz mas-

ter clock. T hese calibration times are master clock dependent.

REV. A

–20–

AD7851

Self-Calibr ation Tim ing

MAX SYSTEM FULL SCALE

T he diagram of Figure 27 shows the timing for a full self-

calibration. Here the BUSY line stays high for the full length of

the self-calibration. A self-calibration is initiated by bringing the

CAL pin low (which initiates an internal reset) and then high

again or by writing to the control register and setting the

ST CAL bit to 1 (note that if the part is in a power-down mode, the

CAL pulse width must take account of the power-up time). T he

BUSY line is triggered high from the rising edge of CAL (or the

end of the write to the control register if calibration is initiated

in software), and BUSY will go low when the full self-calibration

is complete after a time t_CALas shown in Figure 27.

IS ±2.5% FROM V

REF

V

+ SYS OFFSET

REF

V

– 1LSB

V

– 1LSB

REF

SYSTEM OFFSET

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

CALIBRATION

SYS OFFSET

AGND

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

MAX SYSTEM OFFSET

IS ±5% OF V

REF

Figure 28. System Offset Calibration

t₁= 100ns MIN,

t₁₅= 2.5 t_CLKINMAX,

t_CAL= 250026 t_CLKIN

t₁

Figure 29 shows a system gain calibration (assuming a system

full scale greater than the reference voltage) where the analog

input range has been increased after the system gain calibration

is completed. A system full-scale voltage less than the reference

voltage may also be accounted for a by a system gain calibration.

CAL (I/P)

t₁₅

BUSY (O/P)

MAX SYSTEM FULL SCALE

t_CAL

IS ±2.5% FROM V

REF

SYS FULL S.

Figure 27. Tim ing Diagram for Full Self-Calibration

V

– 1LSB

V

– 1LSB

REF

SYSTEM GAIN

CALIBRATION

For the self-(gain + offset), self-offset and self-gain calibrations,

the BUSY line will be triggered high by the rising edge of the

CAL signal (or the end of the write to the control register if cali-

bration is initiated in software) and will stay high for the full du-

ration of the self-calibration. T he length of time that the BUSY

is high for will depend on the type of self-calibration that is initi-

ated. T ypical figures are given in T able IX. T he timing dia-

grams for the other self-calibration options will be similar to that

outlined in Figure 27.

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

AGND

Figure 29. System Gain Calibration

Finally in Figure 30 both the system offset and gain are accounted

for by the system offset followed by a system gain calibration.

First the analog input range is shifted upwards by the positive

system offset and then the analog input range is adjusted at the

top end to account for the system full scale.

System Calibr ation D escr iption

System calibration allows the user to take out system errors

external to the AD7851 as well as calibrate the errors of the

AD7851 itself. T he maximum calibration range for the system

offset errors is ±5% of V_REFand for the system gain errors is

±2.5% of V_REF. T his means that the maximum allowable system

offset voltage applied between the AIN(+) and AIN(–) pins for

the calibration to adjust out this error is ±0.05 × V_REF(i.e., the

AIN(+) can be 0.05 × V_REFabove AIN(–) or 0.05 × V_REFbelow

AIN(–)). For the system gain error the maximum allowable

system full-scale voltage, in unipolar mode, that can be applied

between AIN(+) and AIN(–) for the calibration to adjust out

MAX SYSTEM FULL SCALE

IS ±2.5% FROM V

REF

V

+ SYS OFFSET

REF

SYS F.S.

– 1LSB

SYS F.S.

– 1LSB

V

REF

SYSTEM OFFSET

CALIBRATION

FOLLOWED BY

ANALOG

INPUT

RANGE

ANALOG

INPUT

RANGE

SYSTEM GAIN

CALIBRATION

SYS OFFSET

AGND

this error is V_REF± 0.025 × V_REF(i.e., the AIN(+) can be V_REF

0.025 × V_REFabove AIN(–) or V_REF– 0.025 × V_REFabove

AIN(–)). If the system offset or system gain errors are outside

the ranges mentioned, the system calibration algorithm will

reduce the errors as much as the trim range allows.

+

SYS OFFSET

AGND

MAX SYSTEM OFFSET

IS ±5% OF V

REF

MAX SYSTEM OFFSET

IS ±5% OF V

REF

Figure 30. System (Gain + Offset) Calibration

Figures 28 through 30 illustrate why a specific type of system

calibration might be used. Figure 29 shows a system offset cali-

bration (assuming a positive offset) where the analog input

range has been shifted upwards by the system offset after the

system offset calibration is completed. A negative offset may

also be accounted for by a system offset calibration.

REV. A

–21–

AD7851

System Gain and O ffset Inter action

Next the system offset voltage is applied to the AIN pin for a

minimum setup time (t_{SET UP}) of 100 ns before the rising edge of

the CONVST and remain until the BUSY signal goes low. T he

rising edge of the CONVST starts the system offset calibration

section of the full system calibration and also causes the BUSY

signal to go high. T he BUSY signal will go low after a time t_CAL2

when the calibration sequence is complete.

T he inherent architecture of the AD7851 leads to an interaction

between the system offset and gain errors when a system calibra-

tion is performed. T herefore it is recommended to perform the

cycle of a system offset calibration followed by a system gain

calibration twice. Separate system offset and system gain cali-

brations reduce the offset and gain errors to at least the 14-bit

level. By performing a system offset calibration first and a sys-

tem gain calibration second, priority is given to reducing the

gain error to zero before reducing the offset error to zero. If the

system errors are small, a system offset calibration would be per-

formed, followed by a system gain calibration. If the systems er-

rors are large (close to the specified limits of the calibration

range), this cycle would be repeated twice to ensure that the off-

set and gain errors were reduced to at least the 14-bit level. T he

advantage of doing separate system offset and system gain cali-

brations is that the user has more control over when the analog

inputs need to be at the required levels, and the CONVST sig-

nal does not have to be used.

T he timing for a system (gain + offset) calibration is very similar

to that of Figure 31, the only difference being that the time

t_CAL1will be replaced by a shorter time of the order of t_CAL2as

the internal DAC will not be calibrated. T he BUSY signal will

signify when the gain calibration is finished and when the part is

ready for the offset calibration.

t₁= 100ns MIN, t₁₄= 50 MAX,

t₁₅= 4 t_CLKINMAX, t_CAL1= 222228 t_CLKINMAX,

t_CAL2= 27798 t_CLKIN

t₁

CAL (I/P)

t₁₅

Alternatively, a system (gain + offset) calibration can be per-

formed. It is recommended to perform three system (gain + off-

set) calibrations to reduce the offset and gain errors to the 14-bit

level. For the system (gain + offset) calibration priority is given

to reducing the offset error to zero before reducing the gain er-

ror to zero. T hus if the system errors are small then two system

(gain + offset) calibrations will be sufficient. If the system errors

are large (close to the specified limits of the calibration range),

three system (gain + offset) calibrations may be required to re-

duced the offset and gain errors to at least the 14-bit level.

T here will never be any need to perform more than three system

(offset + gain) calibrations.

BUSY (O/P)

t_CAL2

t_CAL1

t₁₆

CONVST (I/P)

t_SETUP

AIN (I/P)

V

OFFSET

V

SYSTEM FULL SCALE

Figure 31. Tim ing Diagram for Full System Calibration

T he timing diagram for a system offset or system gain calibra-

tion is shown in Figure 32. Here again the CAL is pulsed and

the rising edge of the CAL initiates the calibration sequence (or

the calibration can be initiated in software by writing to the con-

trol register). T he rising edge of the CAL causes the BUSY line

to go high and it will stay high until the calibration sequence is

finished. T he analog input should be set at the correct level for

a minimum setup time (t_{SET UP}) of 100 ns before the rising edge

of CAL and stay at the correct level until the BUSY signal goes

low.

In Bipolar Mode the midscale error is adjusted for an offset cali-

bration and the positive full-scale error is adjusted for the gain

calibration; in Unipolar Mode the zero-scale error is adjusted

for an offset calibration and the positive full-scale error is ad-

justed for a gain calibration.

System Calibr ation Tim ing

T he calibration timing diagram in Figure 31 is for a full system

calibration where the falling edge of CAL initiates an internal

reset before starting a calibration (note that if the part is in power-

down mode the CAL pulse width must take account of the power-up

time). If a full system calibration is to be performed in software,

it is easier to perform separate gain and offset calibrations so

that the CONVST bit in the control register does not have to be

programmed in the middle of the system calibration sequence.

T he rising edge of CAL starts calibration of the internal DAC

and causes the BUSY line to go high. If the control register is

set for a full system calibration, the CONVST must be used

also. T he full-scale system voltage should be applied to the ana-

log input pins from the start of calibration. T he BUSY line will

go low once the DAC and system gain calibration are complete.

t₁

CAL (I/P)

t₁₅

BUSY (O/P)

t_CAL2

t_SETUP

V

OR V

SYSTEM OFFSET

AIN (I/P)

SYSTEM FULL SCALE

Figure 32. Tim ing Diagram for System Gain or System

Offset Calibration

REV. A

–22–

AD7851

SERIAL INTERFACE SUMMARY

and SM2. Interface Mode 1 may only be set by programming

the control register (see section on control register). External

SCLK and SYNC signals (SYNC may be hardwired low) are

required for Interfaces Modes 1, 2, and 3. In Interface Modes 4

and 5 the AD7851 generates the SCLK and SYNC.

T able IX details the five interface modes and the serial clock

edges from which the data is clocked out by the AD7851

(DOUT Edge) and that the data is latched in on (DIN Edge).

T he logic level of the POLARIT Y pin is shown and it is clear

that this reverses the edges.

Some of the more popular µProcessors, µControllers, and the

DSP machines that the AD7851 will interface to directly are

mentioned here. T his does not cover all µCs, µPs and DSPs.

T he interface mode of the AD7851 that is mentioned here for a

specific µC, µP, or DSP is only a guide and in most cases an-

other interface mode may work just as well.

In Interface Modes 4 and 5 the SYNC always clocks out the

first data bit and SCLK will clock out the subsequent bits.

In Interface Modes 1, 2, and 3 the SYNC is gated with the

SCLK and the POLARIT Y pin. T hus the SYNC may clock out

the MSB of data. Subsequent bits will be clocked out by the se-

rial clock, SCLK. T he conditions for the SYNC clocking out

the MSB of data is as follows:

A more detailed timing description on each of the interface

modes follows.

With the POLARITY pin high the falling edge of SYNC will clock

out the MSB if the serial clock is low when the SYNC goes low.

Table X. Interface Mode D escription

With the POLARITY pin low the falling edge of SYNC will clock

out the MSB if the serial clock is high when the SYNC goes low.

SM1 SM2

␮P rocessor/

␮Controller

Interface

Mode

P in

0

8XC51

8XL51

PIC17C42

1 (2-Wire)

(DIN is an Input/

Output pin)

Table IX. SCLK Active Edge for D ifferent Interface Modes

Interface

Mode

P O LARITY

P in

D O UT

Edge

D IN

Edge

0

1

68HC11

68L11

2 (3-Wire, SPI/QSPI)

(Default Mode)

1, 2, 3

0

1

SCLK ↑

SCLK ↓

SCLK ↑

68HC16

3 (QSPI)

PIC16C64

ADSP-21xx

DSP56000

DSP56001

DSP56002

DSP56L002

T MS320C30

(External Serial

Clock, SCLK, and

External Frame Sync,

SYNC, are required)

4, 5

0

1

SCLK ↓

SCLK ↑

SCLK ↓

Resetting the Ser ial Inter face

When writing to the part via the DIN line there is the possibility

of writing data into the incorrect registers, such as the test regis-

ter for instance, or writing the incorrect data and corrupting the

serial interface. T he SYNC pin acts as a reset. Bringing the

SYNC pin high resets the internal shift register. T he first data

bit after the next SYNC falling edge will now be the first bit of a

new 16-bit transfer. It is also possible that the test register con-

tents were altered when the interface was lost. T herefore, once

the serial interface is reset, it may be necessary to write the 16-

bit word 0100 0000 0000 0010 to restore the test register to its

default value. Now the part and serial interface are completely

reset. It is always useful to retain the ability to program the

SYNC line from a port of the µController/DSP to have the abil-

ity to reset the serial interface.

1

0

1

68HC16

4 (DSP is Slave)

(AD7851

generates a

noncontinuous

(16 clocks) Serial

Clock, SCLK, and the

Frame Sync, SYNC)

ADSP-21xx

DSP56000

DSP56001

5 (DSP is Slave)

(AD7851

generates a

DSP56002

continuous Serial

Clock, SCLK, and the

Frame Sync, SYNC)

T able X summarizes the interface modes provided by the

AD7851. It also outlines the various µP/µC to which the par-

ticular interface is suited.

DSP56L002

T MS320C20

T MS320C25

T MS320C30

T MS320C5X

T MS320LC5X

T he interface mode is determined by the serial mode selection

pins SM1 and SM2. Interface mode 2 is the default mode. Note

that Interface Mode 1 and 2 have the same combination of SM1

REV. A

–23–

AD7851

D ETAILED TIMING SECTIO N

MO D E 1 (2-Wir e 8051 Inter face)

continuous SCLK shown by the dotted waveform in Figure 33

can be used provided that the SYNC is low for only 16 clock

pulses in each of the read and write cycles. T he POLARIT Y pin

may be used to change the SCLK edge which the data is

sampled on and clocked out on.

T he read and writing takes place on the DIN line and the con-

version is initiated by pulsing the CONVST pin (note that in

every write cycle the 2/3 MODE bit must be set to 1). T he con-

version may be started by setting the CONVST bit in the con-

trol register to 1 instead of using the CONVST line.

In Figure 34 the SYNC line is tied low permanently and this re-

sults in a different timing arrangement. With SYNC tied low

permanently the DIN pin will never be 3-stated. T he 16th rising

edge of SCLK configures the DIN pin as an input or an output

as shown in the diagram. Here no more than 16 SCLK pulses

must occur for each of the read and write operations.

Below in Figure 33 and in Figure 34 are the timing diagrams for

Interface Mode 1 in T able XI where we are in the 2-wire inter-

face mode. Here the DIN pin is used for both input and output

as shown. T he SYNC input is level triggered active low and can

be pulsed (Figure 33) or can be constantly low (Figure 34).

If reading from and writing to the calibration registers in this in-

terface mode, all the selected calibration registers must be read

from or written to. T he read and write operations cannot be

aborted. When reading from the calibration registers, the DIN

pin will remain as an output for the full duration of all the cali-

bration register read operations. When writing to the calibration

registers, the DIN pin will remain as an input for the full dura-

tion of all the calibration register write operations.

In Figure 33 the part samples the input data on the rising edge

of SCLK. After the 16th rising edge of SCLK the DIN is con-

figured as an output. When the SYNC is taken high the DIN is

3-stated. T aking SYNC low disables the 3-state on the DIN pin

and the first SCLK falling edge clocks out the first data bit.

Once the 16 clocks have been provided the DIN pin will auto-

matically revert back to an input after a time t₁₄. Note that a

t₃= –0.4 t_SCLKMIN (NONCONTINUOUS SCLK) –/+0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

t₃

t₁₁

t₃

t₁₁

1

16

1

16

SCLK (I/P)

t_5A

t₇

t₁₄

t₁₂

t₆

t₈

DIN (I/O)

DB15

DB0

DB15

DB0

3-STATE

DATA READ

DATA WRITE

DIN BECOMES AN OUTPUT

DIN BECOMES AN INPUT

Figure 33. Tim ing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Interface Mode 1, SM1 = SM2 = 0)

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN,

t₁₃= 90 MAX, t₁₄= 50ns MAX

POLARITY PIN

LOGIC HIGH

6

1

16

1

16

SCLK (I/P)

DIN (I/O)

t₇

t₁₄

t₁₃

t₆

t₈

DB15

DB0

DB15

DB0

DATA READ

DATA WRITE

DIN BECOMES AN INPUT

Figure 34. Tim ing Diagram for Read/Write Operation with DIN as an Input/Output and SYNC Input Tied Low

(i.e., Interface Mode 1, SM1 = SM2 = 0)

REV. A

–24–

AD7851

MO D E 2 (3-Wir e SP I/Q SP I Inter face Mode)

MO D E 3 (Q SP I Inter face Mode)

This is the D EFAULT INTERFACE MO D E.

Figure 36 shows the timing diagram for Interface Mode 3. In

this mode the DSP is the master and the part is the slave. Here

the SYNC input is edge triggered from high to low, and the 16

clock pulses are counted from this edge. Since the clock pulses

are counted internally then the SYNC signal does not have to go

high after the 16th SCLK rising edge as shown by the dotted

SYNC line in Figure 36. T hus a frame sync that gives a high

pulse, of one SCLK cycle minimum duration, at the beginning

of the read/write operation may be used. T he rising edge of

SYNC enables the 3-state on the DOUT pin. T he falling edge

of SYNC disables the 3-state on the DOUT pin, and data is

clocked out on the falling edge of SCLK. Once SYNC goes

high, the 3-state on the DOUT pin is enabled. T he data input is

sampled on the rising edge of SCLK and thus has to be valid a

time t₇before this rising edge. T he POLARIT Y pin may be

used to change the SCLK edge which the data is sampled on

and clocked out on. If resetting the interface is required, the

SYNC must be taken high and then low.

In Figure 35 below we have the timing diagram for Interface

Mode 2 which is the SPI/QSPI interface mode. Here the SYNC

input is active low and may be pulsed or tied permanently low.

If SYNC is permanently low 16 clock pulses must be applied to

the SCLK pin for the part to operate correctly, and with a

pulsed SYNC input a continuous SCLK may be applied pro-

vided SYNC is low for only 16 SCLK cycles. In Figure 35 the

SYNC going low disables the three-state on the DOUT pin.

T he first falling edge of the SCLK after the SYNC going low

clocks out the first leading zero on the DOUT pin. T he DOUT

pin is 3-stated again a time t₁₂after the SYNC goes high. With

the DIN pin the data input has to be set up a time t₇before the

SCLK rising edge as the part samples the input data on the

SCLK rising edge in this case. T he POLARIT Y pin may be

used to change the SCLK edge which the data is sampled on

and clocked out on. If resetting the interface is required, the

SYNC must be taken high and then low.

t₃= –0.4 t_CLKINMIN (NONCONTINUOUS SCLK) –/+0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN, t₁₁= 30 MIN (NONCONTINUOUS SCLK) ,

30/0.4 t_SCLK= ns MIN/MAX (CONTINUOUS SCLK)

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

t₉

t₁₁

t₃

1

2

3

4

5

6

16

SCLK (I/P)

t₅

t₁₀

t₆

t₁₂

t₆

3-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB12

DB11

DB10

t₈

DB0

t₇

t₈

DB15

DB14

DB13

DB12

DB11

DB10

DB0

Figure 35. SPI/QSPI Mode 2 Tim ing Diagram for Read/Write Operation with DIN Input, DOUT Output and SYNC Input

(SM1 = SM2 = 0)

t₃= –0.4 t_CLKINMIN (NONCONTINUOUS SCLK) –/+0.4 t_SCLKMIN/MAX (CONTINUOUS SCLK),

t₆= 45 MAX, t₇= 30ns MIN, t₈= 20 MIN, t₁₁= 30 MIN

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

t₉

t₁₁

t₃

1

2

3

4

5

6

16

SCLK (I/P)

t₅

t₁₀

t₆

t₁₂

t₆

3-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB12

DB11

DB10

t₈

DB0

t₇

t₈

DB15

DB14

DB13

DB12

DB11

DB10

DB0

Figure 36. QSPI Mode 3 Tim ing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)

REV. A

–25–

AD7851

MO D E 4 and 5 (Self-Clocking Modes)

the rising edge of CONVST assuming a 6 MHz CLKIN). At this

time the conversion will be complete, the SYNC will go high,

and the BUSY will go low. T he next falling edge of the

CONVST must occur at least 330 ns after the falling edge of

BUSY to allow the track/hold amplifier adequate acquisition

time as shown in Figure 38. T his gives a throughput time of

3.68 µs. T he maximum throughput rate in this case is 272 kHz.

T he timing diagrams in Figure 38 and Figure 39 are for Inter-

face Modes 4 and 5. Interface Mode 4 has a noncontinuous

SCLK output and Interface Mode 5 has a continuous SCLK

output (SCLK is switched off internally during calibration for

both Modes 4 and 5). T hese modes of operation are especially

different to all the other modes since the SCLK and SYNC are

outputs. T he SYNC is generated by the part as is the SCLK.

T he master clock at the CLKIN pin is routed directly to the

SCLK pin for Interface Mode 5 (Continuous SCLK) and the

CLKIN signal is gated with the SYNC to give the SCLK

(noncontinuous) for Interface Mode 4.

OUTPUT SERIAL SHIFT

REGISTER IS RESET

t₁

CONVST

(I/P)

BUSY

(O/P)

T he most important point about these two modes of operation

mode is that the result of the current conversion is clocked out during

the same conversion and a write to the part during this conversion

is for the next conversion. T he arrangement is shown in Figure

37. Figure 38 and Figure 39 show more detailed timing for the

arrangement of Figure 37.

SYNC

(O/P)

SCLK

(O/P)

t_CONVERT= 3.25µs

400ns MIN

CONVERSION IS INITIATED

AND TRACK/HOLD GOES

INTO HOLD

SERIAL READ

AND WRITE

OPERATIONS

READ OPERATION

SHOULD END 500ns

PRIOR TO NEXT RISING

EDGE OF CONVST

THE CONVERSION RESULT DUE TO

WRITE N+1 IS READ HERE

WRITE N+1

WRITE N+2

WRITE N+3

READ N+2

t₁= 100ns MIN

CONVERSION ENDS

3.25µs LATER

READ N+1

READ N

Figure 38. Mode 4, 5 Tim ing Diagram (SM1 = 1, SM2 = 1

and 0)

CONVERSION N

3.25µs

CONVERSION N+1

3.25µs

CONVERSION N+2

3.25µs

In these interface modes the part is now the master and the

DSP is the slave. Figure 39 is an expansion of Figure 38. T he

AD7851 will ensure SYNC goes low after the rising edge C of

the continuous SCLK (Interface Mode 5) in Figure 39. Only in

the case of a noncontinuous SCLK (Interface Mode 4) will

the time t₄apply. T he first data bit is clocked out from the

falling edge of SYNC. T he SCLK rising edge clocks out all

subsequent bits on the DOUT pin. T he input data present on

the DIN pin is clocked in on the rising edge of the SCLK. T he

POLARIT Y pin may be used to change the SCLK edge which

the data is sampled on and clocked out on. T he SYNC will go

high after the 16th SCLK rising edge and before the rising edge

D of the continuous SCLK in Figure 39. T his ensures the part

will not clock in an extra bit from the DIN pin or clock out an

Figure 37.

In Figure 38 the first point to note is that the BUSY, SYNC,

and SCLK are all outputs from the AD7851 with the CONVST

being the only input signal. Conversion is initiated with the

CONVST signal going low. T his CONVST falling edge also

triggers the BUSY to go high. T he CONVST signal rising edge

triggers the SYNC to go low after a short delay (2.5 t_CLKINto

3.5 t_CLKINtypically) after which the SCLK will clock out the

data on the DOUT pin during conversion. T he data on the DIN

pin is also clocked in to the AD7851 by the same SCLK for the

next conversion. T he read/write operations must be complete

after sixteen clock cycles (which takes 3.25 µs approximately from

t₄= 0.6 t_SCLK(NONCONTINUOUS SCLK), t₆= 45ns MAX,

t₇= 30ns MIN, t₈= 20ns MIN , t_11A= 50ns MAX

POLARITY PIN

LOGIC HIGH

SYNC (O/P)

t_11A

t₄

C

t₉

D

1

2

3

4

5

6

16

SCLK (O/P)

t₁₀

t₅

t₁₂

DB0

t₆

DB11

3-STATE

DOUT (O/P)

DIN (I/P)

DB15

DB14

DB13

DB12

DB10

t₈

t₇

DB15

t₈

DB14

DB13

DB12

DB11

DB10

DB0

Figure 39. Tim ing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and Noncontinuous)

(i.e., Operating Mode Num bers 4 and 5, SM1 = 1, SM2 = 1 and 0)

REV. A

–26–

AD7851

extra bit on the DOUT pin.

CO NFIGURING TH E AD 7851

AD 7851 as a Read-O nly AD C

If the user has control of the CONVST pin but does not want to

exercise it for every conversion, the control register may be used

to start a conversion. Setting the CONVST bit in the control

register to 1 starts a conversion. If the user does not have con-

trol of the CONVST pin, a conversion should not initiated by

writing to the control register. T he reason for this is that the

user may get “locked out” and not be able to perform any fur-

ther write/read operations. When a conversion is started by writ-

ing to the control register, the SYNC goes low and read/write

operations take place while the conversion is in progress. How-

ever, once the conversion is complete, there is no way of writing

to the part unless the CONVST pin is exercised. T he CONVST

signal triggers the SYNC signal low which allows read/write op-

erations to take place. SYNC must be low to perform read/write

operations. T he SYNC is triggered low by the CONVST signal

rising edge or setting the CONVST bit in the control register to

1. T herefore if there is not full control of the CONVST pin the

user may end up getting “locked out.”

T he AD7851 contains fourteen on-chip registers which can be

accessed via the serial interface. In the majority of applications it

will not be necessary to access all of these registers. Figure 40

outlines a flowchart of the sequence which is used to configure

the AD7851 as a Read-Only ADC. In this case there is no writ-

ing to the on-chip registers and only the conversion result data is

read from the part. Interface Mode 1 cannot be used in this case

as it is necessary to write to the control register to set Interface

Mode 1. Here the CLKIN signal is applied directly after power-

on, the CLKIN signal must be present to allow the part to per-

form a calibration. T his automatic calibration will be completed

approximately 150 ms after power-on.

START

DIN CONNECTED TO DGND

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

SERIAL

4, 5

INTERFACE

MODE

?

2, 3

PULSE CONVST PIN

READ

DATA

YES

DURING

CONVERSION

?

SYNC AUTOMATICALLY GOES LOW

AFTER CONVST RISING EDGE

NO

WAIT APPROXIMATELY 200ns

AFTER CONVST RISING EDGE

WAIT FOR BUSY SIGNAL

TO GO LOW

SCLK AUTOMATICALLY ACTIVE, READ

CONVERSION RESULT ON DOUT PIN

APPLY SYNC (IF REQUIRED), SCLK AND READ

CONVERSION RESULT ON DOUT PIN

Figure 40. Flowchart for Setting Up and Reading from the AD7851

REV. A

–27–

AD7851

Wr iting to the AD 7851

logic 0, to indicate the end of conversion, the user in this case

would poll the BUSY bit in the status register.

For accessing the on-chip registers it is necessary to write to the

part. T o enable Serial Interface Mode 1, the user must also write

to the part. Figure 41 through 43 outline flowcharts of how to

configure the AD7851 for each of the different serial interface

modes. T he continuous loops on all diagrams indicate the se-

quence for more than one conversion. T he options of using a

hardware (pulsing the CONVST pin) or software (setting the

CONVST bit to 1) conversion start, and reading/writing during

or after conversion are shown in Figures 41 and 42. If the

CONVST pin is never used then it should be tied to DV_DDper-

manently. Where reference is made to the BUSY bit equal to a

Inter face Modes 2 and 3 Configur ation

Figure 41 shows the flowchart for configuring the part in Inter-

face Modes 2 and 3. For these interface modes, the read and

write operations take place simultaneously via the serial port.

Writing all 0s ensures that no valid data is written to any of the

registers. When using the software conversion start and transfer-

ring data during conversion, Note must be obeyed.

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

NOTE:

SERIAL

INTERFACE

MODE

WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING

DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL

REGISTER WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF

BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND

ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE

NEXT CONVERSION.

?

2, 3

INITIATE

CONVERSION

YES

IN

SOFTWARE

?

NO

TRANSFER

YES

DATA DURING

CONVERSION

PULSE CONVST PIN

NO

TRANSFER

DATA

YES

DURING

CONVERSION

?

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS

CONVERSION RESULT ON DOUT PIN (SEE NOTE)

WAIT APPROXIMATELY 200ns

AFTER CONVST RISING EDGE

NO

APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL

REGISTER SETTING CONVST BIT TO 1, READ CURRENT

CONVERSION RESULT ON DOUT PIN

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

WAIT FOR BUSY SIGNAL TO GO LOW

OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DOUT PIN,

AND WRITE ALL 0s ON DIN PIN

Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3

REV. A

–28–

AD7851

Inter face Mode 1 Configur ation

Inter face Modes 4 and 5 Configur ation

Figure 42 shows the flowchart for configuring the part in Inter-

face Mode 1. T his mode of operation can only be enabled by

writing to the control register and setting the 2/3 MODE bit.

Reading and writing cannot take place simultaneously in this

mode as the DIN pin is used for both reading and writing.

Figure 43 shows the flowchart for configuring the AD7851 in

Interface Modes 4 and 5, the self-clocking modes. In this case it

is not recommended to use the software conversion start option.

T he read and write operations always occur simultaneously and

during conversion.

START

POWER-ON, APPLY CLKIN SIGNAL,

WAIT 150ms FOR AUTOMATIC CALIBRATION

SERIAL

INTERFACE

MODE

SERIAL

INTERFACE

MODE

?

4, 5

1

PULSE CONVST PIN

INITIATE

CONVERSION

YES

IN

SOFTWARE

?

SYNC AUTOMATICALLY GOES

LOW AFTER CONVST RISING EDGE

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE TWO-WIRE MODE

AND CONVST BIT TO 1

NO

SCLK AUTOMATICALLY ACTIVE, READ CURRENT

CONVERSION RESULT ON DOUT PIN, WRITE

TO CONTROL REGISTER ON DIN PIN

APPLY SYNC (IF REQUIRED),

SCLK, WRITE TO CONTROL REGISTER

SETTING THE TWO-WIRE MODE

Figure 43. Flowchart for Setting Up, Reading, and Writing

in Interface Modes 4 and 5

PULSE CONVST PIN

READ

DATA

DURING

YES

CONVERSION

?

WAIT APPROXIMATLY 200ns

AFTER CONVST RISING EDGE

OR AFTER END OF CONTROL

REGISTER WRITE

NO

WAIT FOR BUSY SIGNAL TO GO

LOW OR WAIT FOR BUSY BIT = 0

APPLY SYNC (IF REQUIRED),

SCLK, READ PREVIOUS CONVERSION

RESULT ON DIN PIN

APPLY SYNC (IF REQUIRED), SCLK, READ

CURRENT CONVERSION RESULT ON DIN PIN

Figure 42. Flowchart for Setting Up, Reading, and Writing

in Interface Mode 1

REV. A

–29–

AD7851

MICRO P RO CESSO R INTERFACING

OPTIONAL

AD7851

In many applications, the user may not require the facility of

writing to the on-chip registers. T he user may just want to

hardwire the relevant pins to the appropriate levels and read the

conversion result. In this case the DIN pin can be tied low so

that the on-chip registers are never used. Now the part will op-

erate as a nonprogrammable analog to digital converter where

the CONVST is applied, a conversion is performed and the re-

sult may be read using the SCLK to clock out the data from the

output register on to the DOUT pin. Note that the DIN pin

cannot be tied low when using the two-wire interface mode of

operation.

7MHz/6MHz

CONVST

(8XC51/L51)

/PIC17C42

CLKIN

SCLK

DIN

P3.1/CK

P3.0/DT

MASTER

(INT0/P3.2)/INT

OPTIONAL

BUSY

SYNC

SM1

SLAVE

SM2

DV FOR 8XC51/L51

DD

DGND FOR PIC17C42

POLARITY

T he SCLK can also be connected to the CLKIN pin if the user

does not want to have to provide separate serial and master

clocks in Interface Modes 1, 2, and 3. With this arrangement

the SYNC signal must be low for 16 SCLK cycles in Interface

Modes 1 and 2 for the read and write operations. For Interface

Mode 3 the SYNC can be low for more than 16 SCLK cycles

for the read and write operations. Note that in Interface Modes

4 and 5 the CLKIN and SCLK cannot be tied together as the

SCLK is an output and the CLKIN is an input.

Figure 45. 8XC51/PIC16C42 Interface

AD 7851 to 68H C11/16/L11 / P IC16C42 Inter face

Figure 46 shows the AD7851 SPI/QSPI interface to the

68HC11/16/L11/PIC16C42. T he SYNC line is not used and is

tied to DGND. T he µController is configured as the master, by

setting the MST R bit in the SPCR to 1, and thus provides the

serial clock on the SCK pin. For all the µControllers, the CPOL

bit is set to 1 and for the 68HC11/16/L11, the CPHA bit is set

to 1. T he CLKIN and CONVST signals can be supplied from

the µController or from separate sources. T he BUSY signal can

be used as an interrupt to tell the µController when the conver-

sion is finished, then the reading and writing can take place. If

required the reading and writing can take place during conver-

sion and there will be no need for the BUSY signal in this case.

For no writing to the part then the DIN pin can be tied perma-

nently low. For the 68HC16 and the QSPI interface the SM2

pin should be tied high and the SS line tied to the SYNC pin.

T he microsequencer on the 68HC16 QSPI port can be used for

performing a number of read and write operations independent

of the CPU and storing the conversion results in memory with-

out taxing the CPU. T he typical sequence of events would be

writing to the control register via the DIN line setting a conver-

sion start and at the same time reading data from the previous

conversion on the DOUT line, wait for the conversion to be

finished (3.25 µs with 6 MH z CLKIN), and then repeat the

sequence. T he maximum serial frequency will be determined by

the data access and hold times of the µControllers and the

AD7851.

CONVERSION

START

CONVST

7 MHz/6MHz

MASTER CLOCK

CLKIN

SCLK

AD7851

SYNC SIGNAL

TO GATE

THE SCLK

SYNC

DIN

SERIAL DATA

OUTPUT

DOUT

Figure 44. Sim plified Interface Diagram with DIN

Grounded and SCLK Tied to CLKIN

AD 7851 to 8XC51/P IC17C42 Inter face

Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42.

T he 8XC51/PIC17C42 only run at 5 V. T he 8XC51 is in Mode

0 operation. T his is a two-wire interface consisting of the SCLK

and the DIN which acts as a bidirectional line. T he SYNC is

tied low. T he BUSY line can be used to give an interrupt driven

system but this would not normally be the case with the 8XC51/

PIC17C42. For the 8XC51 12 MHz version, the serial clock

will run at a maximum of 1 MHz so that the serial interface to

the AD7851 will only be running at 1 MHz. T he CLKIN signal

must be provided separately to the AD7851 from a port line on

the 8XC51 or from a source other than the 8XC51. Here the

SCLK cannot be tied to the CLKIN as the 8XC51 only pro-

vides a noncontinuous serial clock. T he CONVST signal can be

provided from an external timer or conversion can be started in

software if required. T he sequence of events would typically be

writing to the control register via the DIN line setting a conver-

sion start and the 2-wire interface mode (this would be per-

formed in two 8-bit writes), wait for the conversion to be

finished (3.25 µs with 6 MHz CLKIN), read the conversion re-

sult data on the DIN line (this would be performed in two 8-bit

reads), and then repeat the sequence. T he maximum serial fre-

quency will be determined by the data access and hold times of

the 8XC51/PIC16C42 and the AD7851.

OPTIONAL

AD7851

7MHz/6MHz

CONVST

DV

DD

68HC11/L11/16

SS

CLKIN

SPI

HC16, QSPI

SYNC

SCLK

DOUT

BUSY

SCK

MISO

IRQ

MASTER

OPTIONAL

DIN

MOSI

SLAVE

SM1

DIN AT DGND FOR

NO WRITING TO PART

DV FOR HC11, SPI

DD

DGND FOR HC16, QSPI

SM2

POLARITY

DV

DD

Figure 46. 68HC11 and 68HC16 Interface

REV. A

–30–

AD7851

AD 7851 to AD SP -21xx Inter face

OPTIONAL

7MHz/6MHz

AD7851

Figure 47 shows the AD7851 interface to the ADSP-21xx. T he

ADSP-21xx is the slave and the AD7851 is the master. T he

AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in

the serial port control register should be set up as T FSR =

RFSR = 1 (need a frame sync for every transfer), SLEN = 15

(16-bit word length), T FSW = RFSW = 1 (alternate framing

mode for transmit and receive operations), INVRFS = INVT FS

= 1 (active low RFS and T FS), IRFS = IT FS = 0 (External

RFS and T FS), and ISCLK = 0 (external serial clock). T he

CLKIN and CONVST signals could be supplied from the

ADSP-21xx or from an external source. T he AD7851 supplies

the SCLK and the SYNC signals to the ADSP-21xx and the

reading and writing takes place during conversion. T he BUSY

signal only indicates when the conversion is finished and may

not be required. T he data access and hold times of the ADSP-

21xx and the AD7851 allows for a CLKIN of 7 MHz/6 MHz

with a 5 V supply.

CONVST

DSP

56000/1/2/L002

CLKIN

SCLK

DOUT

SYNC

SCK

SRD

SC2

OPTIONAL

BUSY

DIN

IRQ

MASTER

STD

SLAVE

DIN AT DGND FOR

NO WRITING TO PART

SM1

SM2

DV

DD

POLARITY

Figure 48. DSP56000/1/2 Interface

AD 7851 to TMS320C20/25/5x/LC5x Inter face

Figure 49 shows the AD7851 to the T MS320Cxx interface. T he

AD7851 is the master and operates in Interface Mode 5. For

the T MS320Cxx the CLKX, CLKR, FSX, and FSR pins

should all be configured as inputs. T he CLKX and the CLKR

should be connected together as should the FSX and FSR. Since

the AD7851 is the master and the reading and writing occurs

during the conversion, the BUSY only indicates when the con-

version is finished and thus may not be required. Again the data

access and hold times of the T MS320Cxx and the AD7851 al-

lows for a CLKIN of 7 MHz/6 MHz.

OPTIONAL

AD7851

7MHz/6MHz

CONVST

CLKIN

ADSP-21xx

SCK

SCLK

DOUT

DR

RFS

TFS

IRQ

DT

SYNC

SLAVE

OPTIONAL

BUSY

DIN

OPTIONAL

MASTER

AD7851

TMS320C20/

25/5x/LC5x

7MHz/6MHz

CONVST

SM1

DIN AT DGND FOR

NO WRITING TO PART

CLKIN

CLKX

SM2

SCLK

DOUT

SYNC

CLKR

DR

POLARITY

DV

DD

FSR

FSX

SLAVE

MASTER

OPTIONAL

Figure 47. ADSP-21xx Interface

AD 7851 to D SP 56000/1/2/L002 Inter face

INT0

DT

BUSY

DIN

OPTIONAL

Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface.

Here the DSP5600x is the master and the AD7851 is the slave.

T he AD7851 is in Interface Mode 3. T he setting of the bits in

the registers of the DSP5600x would be for synchronous opera-

tion (SYN = 1), internal frame sync (SCD2 = 1), Internal clock

(SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames

sync only active at beginning of the transfer (FSL1 = 0, FSL0 =

1). A gated clock can be used (GCK = 1) or if the SCLK is to

be tied to the CLKIN of the AD7851, then there must be a con-

tinuous clock (GCK = 0). Again the data access and hold times

of the DSP5600x and the AD7851 should allow for an SCLK of

7 MHz/6 MHz.

SM1

SM2

DIN AT DGND FOR

NO WRITING TO PART

POLARITY

DV

DD

Figure 49. TMS320C20/25/5x Interface

REV. A

–31–

AD7851

AP P LICATIO N H INTS

Evaluating the AD 7851 P er for m ance

Gr ounding and Layout

T he recommended layout for the AD7851 is outlined in the

evaluation board for the AD7851. T he evaluation board pack-

age includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from the

PC via the EVAL-CONT ROL BOARD. T he EVAL-CON-

T ROL BOARD can be used in conjunction with the AD7851

Evaluation board, as well as many other Analog Devices evalua-

tion boards ending in the CB designator, to demonstrate/evalu-

ate the ac and dc performance of the AD7851.

T he analog and digital supplies to the AD7851 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. T he part has very good

immunity to noise on the power supplies as can be seen by the

PSRR versus Frequency graph. However, care should still be

taken with regard to grounding and layout.

T he printed circuit board that houses the AD7851 should be de-

signed such that the analog and digital sections are separated

and confined to certain areas of the board. T his facilitates the

use of ground planes that can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7851 is the only device requiring

an AGND to DGND connection, then the ground planes should

be connected at the AGND and DGND pins of the AD7851. If

the AD7851 is in a system where multiple devices require

AGND to DGND connections, the connection should still be

made at one point only, a star ground point which should be

established as close as possible to the AD7851.

T he software allows the user to perform ac (fast Fourier trans-

form) and dc (histogram of codes) tests on the AD7851. It also

gives full access to all the AD7851 on-chip registers allowing for

various calibration and power-down options to be programmed.

AD 785x Fam ily

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD 7853 – Single Channel Ser ial

AD 7854 – Single Channel P ar allel

AD 7858 – Eight Channel Ser ial

AD 7859 – Eight Channel P ar allel

Avoid running digital lines under the device as these will couple

noise onto the die. T he analog ground plane should be allowed

to run under the AD7851 to avoid noise coupling. T he power

supply lines to the AD7851 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. T races on opposite sides of the board should

run at right angles to each other. T his will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum in parallel with 0.1 µF ca-

pacitors to AGND. All digital supplies should have a 0.1 µF

disc ceramic capacitor to AGND. T o achieve the best from these

decoupling components, they must be placed as close as possible

to the device, ideally right up against the device. In systems

where a common supply voltage is used to drive both the AV_DD

and DV_DDof the AD7851, it is recommended that the system’s

AV_DDsupply is used. In this case there should be a 10 Ω resistor

between the AV_DDpin and DV_DDpin. T his supply should have

the recommended analog supply decoupling capacitors between

the AV_DDpin of the AD7851 and AGND and the recommended

digital supply decoupling capacitor between the DV_DDpin of the

AD7851 and DGND.

REV. A

–32–

AD7851

P AGE IND EX

Topic

Self-Calibration T iming . . . . . . . . . . . . . . . . . . . . . . . . . . 21

System Calibration Description . . . . . . . . . . . . . . . . . . . . 21

System Gain and Offset Interaction . . . . . . . . . . . . . . . . . 22

System Calibration T iming . . . . . . . . . . . . . . . . . . . . . . . 22

SERIAL INT ERFACE SUMMARY . . . . . . . . . . . . . . . . . . 23

Resetting the Serial Interface . . . . . . . . . . . . . . . . . . . . . . 23

DET AILED T IMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Mode 1 (2-Wire 8051 Interface) . . . . . . . . . . . . . . . . . . . 24

Mode 2 (3-Wire SPI/QSPI Interface Mode) . . . . . . . . . . . 25

Mode 3 (QSPI Interface Mode) . . . . . . . . . . . . . . . . . . . . 25

Mode 4 and 5 (Self-Clocking Modes) . . . . . . . . . . . . . . . 26

CONFIGURING T HE AD7851 . . . . . . . . . . . . . . . . . . . . . 27

AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 27

Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28

Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29

Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29

MICROPROCESSOR INT ERFACING . . . . . . . . . . . . . . . 30

AD7851 – 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . . 30

AD7851 – 68HC11/16/L11/PIC16C42 Interface . . . . . . . . 30

AD7851 – ADSP-21xx Interface . . . . . . . . . . . . . . . . . . . . . 31

AD7851 – DSP56000/1/2/L002 Interface . . . . . . . . . . . . . . 31

AD7851 – T MS320C20/25/5x/LC5x Interface . . . . . . . . . . 31

APPLICAT IONS HINT S . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Evaluating the AD7851 Performance . . . . . . . . . . . . . . . . 32

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

P age

FEAT URES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHT S . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

T IMING SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . 4

T YPICAL T IMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . 5

ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PINOUT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

T ERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCT ION DESCRIPT ION . . . . . . . . . . . . . . . . . . . 8

AD7851 ON-CHIP REGIST ERS . . . . . . . . . . . . . . . . . . . . . 9

Addressing the On-Chip Registers . . . . . . . . . . . . . . . . . . . 9

Writing/Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CONT ROL REGIST ER . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ST AT US REGIST ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CALIBRAT ION REGIST ERS . . . . . . . . . . . . . . . . . . . . . . 12

Addressing the Calibration Registers . . . . . . . . . . . . . . . . 12

Writing to/Reading from the Calibration Registers . . . . . . 12

Adjusting the Offset Calibration Register . . . . . . . . . . . . . 13

Adjusting the Gain Calibration Registers . . . . . . . . . . . . . 13

CIRCUIT INFORMAT ION . . . . . . . . . . . . . . . . . . . . . . . . 14

CONVERT ER DET AILS . . . . . . . . . . . . . . . . . . . . . . . . . . 14

T YPICAL CONNECT ION DIAGRAM . . . . . . . . . . . . . . . 14

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Acquisition T ime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC/AC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

T ransfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REFERENCE SECT ION . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AD7851 PERFORMANCE CURVES . . . . . . . . . . . . . . . . 17

POWER-DOWN OPT IONS . . . . . . . . . . . . . . . . . . . . . . . . 18

POWER-UP T IMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Using an External Reference . . . . . . . . . . . . . . . . . . . . . . 19

Using the Internal (On-Chip) Reference . . . . . . . . . . . . . 19

POWER VS. T HROUGHPUT RAT E . . . . . . . . . . . . . . . . 19

CALIBRAT ION SECT ION . . . . . . . . . . . . . . . . . . . . . . . . 20

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Automatic Calibration on Power-On . . . . . . . . . . . . . . . . 20

Self-Calibration Description . . . . . . . . . . . . . . . . . . . . . . . 20

TABLE IND EX

#

T itle

P a ge

I

Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9

Read Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 9

II

III Calibration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 10

IV Calibrating Register Addressing . . . . . . . . . . . . . . . . . . 12

V

Analog Input Connections . . . . . . . . . . . . . . . . . . . . . . 16

VI Power Management Options . . . . . . . . . . . . . . . . . . . . 18

VII Power Consumption vs. T hroughput . . . . . . . . . . . . . . 20

VIII Calibration T imes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IX SCLK Active Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

X

Interface Mode Description . . . . . . . . . . . . . . . . . . . . . 23

REV. A

–33–

AD7851

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

24-P in P lastic D IP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

1

13

0.280 (7.11)

0.240 (6.10)

12

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.210

(5.33)

MAX

0.150

(3.81)

MIN

0.200 (5.05)

0.125 (3.18)

0.015 (0.381)

0.008 (0.204)

0.100 (2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77) SEATING

PLANE

0.045 (1.15)

24-P in Sm all O utline P ackage

(R-24)

0.6141 (15.60)

0.5985 (15.20)

24

13

12

1

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

x 45°

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0125 (0.32)

0.0091 (0.23)

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

24-P in Shr ink Sm all O utline P ackage

(RS-24)

0.328 (8.33)

0.318 (8.08)

24

13

1

12

0.07 (1.78)

0.078 (1.98)

0.068 (1.73)

PIN 1

0.066 (1.67)

0.037 (0.94)

8°

0°

0.015 (0.38)

0.010 (0.25)

0.0256

(0.65)

BSC

0.022 (0.559)

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

REV. A

–34–

–35–

–36–


型号：	AD7851KRZ
厂家：	ADI
描述：	14-Bit, 333 kSPS, Serial Sampling A/D Converter 转换器
文件：	总36页 (文件大小：437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7851KRZ [ADI]

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