AD7872KR [ADI]
LC2MOS Complete 14-Bit, Sampling ADCs; LC2MOS完整的14位，采样ADC
| 型号： | AD7872KR |
| 厂家： | 
ADI |
| 描述： | LC2MOS Complete 14-Bit, Sampling ADCs |
| 文件： | 总16页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Complete 14-Bit, Sampling ADCs
AD7871/AD7872
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
Com plete Monolithic 14-Bit ADC
2s Com plem ent Coding
Parallel, Byte and Serial Digital Interface
80 dB SNR at 10 kHz Input Frequency
57 ns Data Access Tim e
Low Pow er—50 m W typ
83 kSPS Throughput Rate
16-Lead SOIC (AD7872)
APPLICATIONS
Digital Signal Processing
High Speed Modem s
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL D ESCRIP TIO N
T he AD7871 and AD7872 are fast, complete, 14-bit analog-to-
digital converters. T hey consist of a track/hold amplifier,
successive-approximation ADC, 3 V buried Zener reference and
versatile interface logic. The ADC features a self-contained, laser
trimmed internal clock, so no external clock timing components
are required. The on-chip clock may be overridden to synchronize
ADC operation to the digital system for minimum noise.
T he AD7871 offers a choice of three data output formats: a sin-
gle, parallel, 14-bit word; two 8-bit bytes or a 14-bit serial data
stream. T he AD7872 is a serial output device only. T he two
parts are capable of interfacing to all modern microprocessors
and digital signal processors.
T he AD7871 and AD7872 operate from ±5 V power supplies,
accept bipolar input signals of ±3 V and can convert full power
signals up to 41.5 kHz.
In addition to the traditional dc accuracy specifications, the
AD7871 and AD7872 are also fully specified for dynamic perfor-
mance parameters including distortion and signal-to-noise ratio.
Both devices are fabricated in Analog Devices’ LC2MOS mixed
technology process. The AD7871 is available in 28-pin plastic DIP
and PLCC packages. The AD7872 is available in a 16-pin plastic
DIP, hermetic DIP and 16-lead SOIC packages.
P RO D UCT H IGH LIGH TS
1. Complete 14-Bit ADC on a Chip.
2. Dynamic Specifications for DSP Users.
3. Low Power.
REV. D
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND =
DD
SS
O V, fCLK = 2 MHz external, fSAMPLE = 83 kHz unless otherwise
noted.) All Specifications TMIN to TMAX unless otherwise noted.
AD7871/AD7872–SPECIFICATIONS
J, A
K
T, B
P aram eter
Versions1 Version1 Versions1 Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR) @ +25°C
T MIN to T MAX
80
80
–86
80
80
–88
79
79
dB min
dB min
dB max
dB typ
dB max
dB typ
VIN = 10 kHz Sine Wave
SNR is T ypically 82 dB for <VIN<41.5 kHz;
VIN = 10 kHz Sine Wave
T otal Harmonic Distortion (T HD)
–85
–85
Peak Harmonic or Spurious Noise
–86
–88
VIN = 10 kHz.
Intermodulation Distortion (IMD)
Second Order T erms
–86
–86
2
–88
–88
2
dB max
dB typ
dB max
dB typ
µs max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
–85
T hird Order T erms
–85
2
T rack/Hold Acquisition T ime
DC ACCURACY
Resolution
14
14
14
14
Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity @ +25°C
Integral Nonlinearity
Bipolar Zero Error
14
±1/2
±1
±12
±12
±12
14
±1/2
±1
±12
±12
±12
Bits
LSB typ
LSB max
LSB max
LSB max
LSB max
±12
±12
±12
Positive Gain Error4
Negative Gain Error4
ANALOG INPUT
Input Voltage Range
Input Current
±3
±500
±3
±500
±3
±500
Volts
µA max
REFERENCE OUT PUT
REF OUT @ +25°C
T MIN to T MAX
2.99/3.01 2.99/3.01 2.99/3.01 V min/V max
2.98/3.02 2.98/3.02 2.98/3.02 V min/V max
REF OUT T empco
Reference Load Sensitivity
(∆REF OUT /∆I)
±40
±40
ppm/°C max
T ypically 35 ppm
±1.2
±1.2
±1.2
mV max
Reference Load Current Change (0 µA–300 µA);
Reference Load Should Not Be Changed During
Conversion
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to VDD
V max
µA max
µA max
pF max
Input Current (14/8/CLK Input Only)
5
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB13 – DB0
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
10
15
10
15
10
15
µA max
pF max
Floating-State Output Capacitance5
CONVERSION T IME
External Clock
Internal Clock
10
10.5
10
10.5
10
11
µs max
µs max
T he Internal Clock Has a Nominal Value of 2 MHz
POWER REQUIREMENT S
VDD
VSS
IDD
ISS
+5
–5
13
6
+5
–5
13
6
+5
–5
13
6
V nom
V nom
mA max
mA max
mW max
±5% for Specified Performance
±5% for Specified Performance
T ypically 6 mA
T ypically 4 mA
T ypically 50 mW
Power Dissipation
95
95
95
NOT ES
1T emperature ranges are as follows: J, K versions, 0°C to +70°C; A, B versions, –40°C to +85°C; T version; –55°C to +125°C.
2VIN = ±3 V.
3SNR calculation includes distortion and noise components.
4Measured with respect to internal reference.
5Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. D
AD7871/AD7872
1, 2
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = O V. See Figures 9, 10, 11 and 12.)
TIMING CHARACTERISTICS
DD
SS
Lim it at TMIN, TMAX
Lim it at TMIN, TMAX
P aram eter
(J, K, A, B Versions) (T Version)
Units
Conditions/Com m ents
t1
t2
t3
50
0
60
50
0
75
ns min CONVST Pulse Width
ns min CS to RD Setup T ime (Mode 1)
ns min RD Pulse Width
t4
0
0
ns min CS to RD Hold T ime (Mode 1)
ns min RD to INT Delay
ns max Data Access T ime after RD
ns min Bus Relinquish T ime after RD
ns max
ns min HBEN to RD Setup T ime
ns min HBEN to RD Hold T ime
ns min SSTRB to SCLK Falling Edge Setup T ime
ns min SCLK Cycle T ime
ns max SCLK to Valid Data Delay. CL = 35 pF
ns max SCLK Rising Edge to SSTRB
ns min
t53
t64
t7
70
57
5
50
0
70
70
5
50
0
t8
t9
t10
t11
0
0
100
440
155
140
20
4
100
60
120
200
0
100
440
155
150
20
4
100
60
120
200
0
5
6
t12
t13
t14
ns min Bus Relinquish T ime after SCLK
ns max
t15
t16
t17
t18
t19
t20
ns min CS to RD Setup T ime (Mode 2)
ns max CS to BUSY Propagation Delay
ns min Data Setup T ime Prior to BUSY
ns min CS to RD Hold T ime (Mode 2)
ns min HBEN to CS Setup T ime
ns min HBEN to CS Hold T ime
3
0
0
0
0
NOT ES
1T iming Specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on SDAT A and SSTRB and a 2 kΩ pull-up resistor on SCLK. T he capacitance on all three outputs is 35 pF.
3t6 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. T he measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t 7, quoted in the T iming Characteristics is the true bus relinquish
time of the part and is independent of bus loading.
5SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6SDAT A will drive higher capacitive loads, but this will add to t 12 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
REF OUT , CREF to AGND . . . . . . . . . . . . . . . . . . 0 V to VDD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
Figure 1. Load Circuit for Access Tim e
Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 2. Load Circuit for Output Float Delay
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7871/AD7872 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD7871/AD7872
AD 7871 P IN FUNCTIO N D ESCRIP TIO N
D IP
No.
Mnem onic
Function
1
CONVST
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. T his
input is asynchronous to the CLK. CS and RD must be held high for the duration of this pulse.
2
CS
Chip Select. Active low logic input. T he device is selected when this input is active. With CONVST
tied low, a new conversion is initiated when CS goes low.
3
4
5
RD
Read. Active low logic input. T his input is used in conjunction with CS low to enable the data outputs.
BUSY/INT
CLK
Busy/Interrupt. Logic low output indicating converter status. See timing diagrams.
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying
this pin to VSS enables the internal laser-trimmed oscillator.
6
DB13/HBEN
Data Bit 13 (MSB)/High Byte Enable. T he function of this pin is dependent on the state of the
14/8/CLK input (see Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When
either byte or serial data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit
bus interfacing. When HBEN is low, DB7 to DB0 is the lower byte of data. With HBEN high, DB7
to DB0 is the upper byte of data (see T able I).
Table I. Byte O utput Form at
HBEN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HIGH LOW LOW DB13 DB12 DB11 DB10 DB9 DB8
LOW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
7
8
DB12/SSTRB
Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output.
Otherwise it is an active low three-state output that provides a framing pulse for serial data.
DB11/SCLK
Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output.
Otherwise SCLK is the gated serial clock output that is derived from the internal or external ADC
clock. If the 14/8/CLK input is held at –5 V, then the SCLK runs continuously. With 14/8/CLK at
0 V, it is gated off (three-state) after serial transmission is complete.
9
DB10/SDAT A
Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data
output. Otherwise it is the three-state serial data output used in conjunction with SCLK and SSTRB
in serial data transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low.
10–13 DB9–DB6
T hree-State Data Outputs controlled by CS and RD. T heir function depends on the state of the
14/8/CLK and the HBEN inputs. With 14/8/CLK high, they are always DB9–DB6; with 14/8/CLK
low, their function depends on HBEN (see T able I).
14
DGND
Digital Ground. Ground return for digital circuitry.
15–20 DB5/DB13–
DB0/DB8
T hree-State Data Outputs controlled by CS and RD. T heir function depends on the 14/8/CLK
and HBEN inputs. With 14/8/CLK high, they are always DB5–DB0; with 14/8/CLK low or –5 V,
their function is controlled by HBEN (see T able I).
21
22
23
24
25
VDD
Positive Supply, +5 V ± 5%.
AGND
CREF
Analog Ground. Ground reference for analog circuitry.
Decoupling point for on-chip reference. Connect 10 nF between this pin and AGND.
No Connect.
NC
REF OUT
Voltage Reference Output. T he internal 3 V reference is provided at this pin. T he external load
capability is 500 µA.
26
27
28
VIN
Analog Input. T he input range is ±3 V.
Negative Supply, –5 V ± 5%.
VSS
14/8/CLK
T hree-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the
output data is 14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and
the SCLK is noncontinuous. With this pin at –5 V, both byte and serial data are available and the
SCLK is continuous.
REV. D
–4–
AD7871/AD7872
AD 7872 P IN FUNCTIO N D ESCRIP TIO N
D IP
No.
Mnem onic
Function
1
CONT ROL
Control Input. With this pin at 0 V, the SCLK is noncontinuous; with this pin at –5 V, the SCLK
is continuous.
2
3
4
5
CONVST
CLK
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. T his
input is asynchronous to the CLK.
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying
this pin to VSS, enables the internal laser-trimmed oscillator.
SSTRB
SCLK
T his is an active low three-state output that provides a framing pulse for serial data. An external
4.7 kΩ pull-up resistor is required on SSTRB.
Serial Clock. SCLK is the gated serial clock output derived from the internal or external ADC
clock. If the 14/8/CLK input is at –5 V, then the SCLK runs continuously. With CONT ROL
at 0 V, it is gated off (three-state) after serial transmission is complete. SCLK is an open-drain
output and requires an external 2 kΩ pull-up resistor.
6
SDAT A
Serial Data. T his is the three-state serial data output used in conjunction with SCLK and SSTRB in
serial data transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low. An
external 4.7 kΩ pull-up resistor is required on SDAT A.
7
NC
No Connect.
8
DGND
VDD
Digital Ground. Ground return for digital circuitry.
Positive Supply for analog circuitry, +5 V ± 5%.
No Connect.
9
10
11
12
13
NC
CREF
Decoupling point for on-chip reference. Connect 10 nF capacitor between this pin and AGND.
Analog Ground. Ground reference for analog circuitry.
AGND
REF OUT
Voltage Reference Output. T he internal 3 V reference is provided at this pin. T he external load
capability is 500 µA.
14
15
16
VIN
VSS
VDD
Analog Input. T he input range is ±3 V.
Negative Supply, –5 V ± 5%.
Positive Supply for analog circuitry, +5 V ± 5%. Pin 16 and Pin 9 should be connected together.
P IN CO NFIGURATIO NS
D IP
D IP , SO IC
P LCC
REV. D
–5–
AD7871/AD7872
CO NVERTER D ETAILS
T he operation of the track/hold amplifier is essentially transpar-
ent to the user. T he track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion. If the
CONVST input is used to start conversion, then the track to
hold transition occurs on the rising edge of CONVST. If CS on
the AD7871 starts conversion, this transition occurs on the fall-
ing edge of CS.
T he AD7871/AD7872 is a complete 14-bit A/D converter, re-
quiring no external components apart from power supply
decoupling capacitors. It is comprised of a 14-bit successive ap-
proximation ADC based on a fast settling voltage-output DAC,
a high speed comparator and CMOS SAR, a track/hold ampli-
fier, a 3 V buried Zener reference, a clock oscillator and control
logic.
ANALO G INP UT
INTERNAL REFERENCE
Figure 4 shows the AD7871/AD7872 analog input. T he analog
input range is ±3 V into an input resistance of typically 15 kΩ.
T he designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS
–3/2 LSBs). T he output code is twos-complement binary with
1 LSB = FS/16384 = 6 V/16384 = 366 µV. T he ideal input/out-
put transfer function is shown in Figure 5.
T he AD7871/AD7872 has an on-chip temperature compensated
buried Zener reference that is factory trimmed to 3 V ± 10 mV.
Internally it provides both the DAC reference and the dc bias
required for bipolar operation. Reference noise is minimized by
connecting a capacitor between CREF and AGND. For specified
operation this capacitor should be 10 nF. T he reference output
is available (REF OUT ) and capable of providing up to 500 µA to
an external load.
T he maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the AD7871/AD7872, it should be decoupled with a
200 Ω resistor in series with a parallel combination of a 10 µF
tantalum capacitor and a 0.1 µF ceramic capacitor. T hese
decoupling components are required to remove voltage spikes
caused by the AD7871/AD7872’s internal operation.
Figure 5. Bipolar Input/Output Transfer Function
BIP O LAR O FFSET AND FULL-SCALE AD JUSTMENT
When the AD7871/AD7872’s offset and full-scale errors need to
be adjusted, offset error must be adjusted first. T his is achieved
by trimming the offset of the op amp driving the analog input of
the AD7871/AD7872 while the input voltage is 1/2 LSB below
AGND. T he trim procedure is as follows: apply a voltage of
–0.183 mV (–1/2 LSB) at V1 in Figure 6 and adjust the op amp
offset voltage until the ADC output code flickers between 11
1111 1111 1111 and 00 0000 0000 0000.
Figure 3. Reference Circuit
TRACK-AND -H O LD AMP LIFIER
T he track-and-hold amplifier on the analog input of the
AD7871/AD7872 allows the ADC to accurately convert an in-
put sine wave of 6 V peak-peak amplitude to 14-bit accuracy.
T he input bandwidth of the track/hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate. T he 0.1 dB cutoff fre-
quency occurs typically at 500 kHz. T he track/hold amplifier
acquires an input signal to 14-bit accuracy in less than 2 µs. T he
overall throughput rate is determined by the conversion time
plus the track/hold amplifier acquisition time. For a 2 MHz
input clock the throughput time is 12 µs maximum.
Figure 6. Bipolar Adjust Circuit
REV. D
Figure 4. Analog Input
–6–
AD7871/AD7872
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). T he trim procedures for both cases are as follows
(see Figure 6).
UNIP O LAR O FFSET AND FULL-SCALE AD JUSTMENT
When absolute accuracy is required, offset and full-scale error
can be adjusted to zero. Offset must be adjusted before full-
scale. T his is achieved by applying an input voltage of 1/2 LSB
to V1 and adjust R6 until the ADC output code flickers between
10 0000 0000 0000 and 10 0000 0000 0001. For full-scale
adjustment apply an input voltage of (FS –3/2 LSBs) to V1 and
adjust R5 until the output code flickers between 01 1111 1111
1110 and 01 1111 1111 1111.
P ositive Full-Scale Adjust
Apply a voltage of 2.9995 V (FS/2 –3/2 LSBs) at V1 and adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 and 01 1111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –2.9998 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 10 0000
0000 0000 and 10 0000 0000 0001.
TIMING AND CO NTRO L
T he conversion time for both external and internal clocks can
vary from 19 to 20 rising clock edges depending on the conver-
sion start to ADC clock synchronization. If a conversion is initi-
ated within 30 ns prior to a rising edge of the ADC clock, the
conversion time will consist of 20 rising clock edges.
UNIP O LAR O P ERATIO N
A typical unipolar circuit is shown in Figure 7. T he AD7871/
AD7872 REF OUT is used to offset the analog input by 3 V.
T he analog input range is determined by the ratio of R3 to R4.
T he minimum range with which the circuit will work is 0 to
+3 V. T he resistor values are given in Figure 7 for input ranges
of 0 to +5 V and 0 to +10 V. R5 and R6 are included for offset
and full scale adjust only and should be omitted if adjustment is
not required.
T here are two basic operating modes for the AD7871. In the
first mode (Mode 1) the CONVST line is used to start conver-
sion and drive the track/hold into its hold mode. At the end of
conversion, the track/hold returns to its tracking mode. It is
principally intended for digital signal processing and other
applications where precise sampling in time is required. In these
applications, it is important that the signal sampling occurs at
exactly equal intervals to minimize errors due to sampling un-
certainty or jitter. For these cases, the CONVST line is driven
by a timer or some precise clock source.
T he second mode is achieved by hard-wiring the CONVST line
low. T his mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS and RD start conver-
sion, and the microprocessor will normally be driven into a
WAIT state for the duration of conversion by BUSY/INT.
T he AD7872 has one operating mode only. T his is Mode 1, de-
scribed above, which uses CONVST to start conversion.
D ATA O UTP UT FO RMATS
T he AD7871 offers a choice of three data output formats, one
serial and two parallel. T he parallel data formats include a single
14-bit parallel word for 16-bit data buses and a two-byte format
for 8-bit data buses. T he data format is controlled by the
14/8/CLK input. A logic high on this pin selects the 14-bit par-
allel output format only. A logic low or –5 V applied to this pin
allows the user access to either serial or byte formatted data.
T hree of the pins previously assigned to the four MSBs in paral-
lel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
T he three possible data output formats can be selected in either
of the modes of operation.
Figure 7. Unipolar Circuit
T he ideal input/output transfer function is shown in Figure 8.
T he output can be converted to straight binary by inverting the
MSB.
T he AD7872 is a serial output device only. T he serial data for-
mat is exactly the same as the AD7871.
P ar allel O utput For m at
T he two parallel formats available on the AD7871 are a 14-bit
wide data word and a 2-byte data word. In the first, all 14 bits
of data are available at the same time on DB13 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB13/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the AD7871. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read opera-
tion; with HBEN high, the upper six bits of the 14-bit word are
Figure 8. Unipolar Transfer Function
REV. D
–7–
AD7871/AD7872
placed on the data bus. T hese six bits are right justified and
thereby occupy the lower six bits of the byte while the upper two
bits are zeros.
Figure 9 shows the Mode 1 timing diagram for a 14-bit parallel
data output format (14/8/CLK = +5 V). A read to the AD7871
at the end of conversion accesses all 14 bits of data at the same
time. Serial data is not available for this data output format.
Ser ial O utput For m at
Serial data is available on the AD7871 when the 14/8/CLK
input is at 0 V or –5 V and in this case the DB12/SSTRB,
DB11/SCLK and DB10/SDAT A pins assume their serial func-
tions. T he AD7872 is a serial output device only. T he serial
function on both devices is identical. Serial data is available dur-
ing conversion with a word length of 16 bits; two leading zeros,
followed by the 14-bit conversion result starting with the MSB.
T he data is synchronized to the serial clock output (SCLK) and
is framed by the serial strobe (SSTRB). Data is clocked out on a
low to high transition of the serial clock and is valid on the fall-
ing edge of this clock while the SSTRB output is low. SSTRB
goes low at the start of conversion and the first serial data bit
(which is the first leading zero) is valid on the first falling edge
of SCLK. All the serial lines are open-drain outputs and require
external pull-up resistors.
Figure 9. Mode 1 Tim ing Diagram , 14-Bit Parallel Read
T he serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, SCLK is
required during the serial transmission only. In these cases it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., T MS32020) require a
serial clock that runs continuously. Both options are available
on the AD7871 and AD7872. With the 14/8/CLK input on the
AD7871 at –5 V, the serial clock (SCLK) runs continuously;
when 14/8/CLK is at 0 V, SCLK goes into three-state at the end
of transmission. T he CONT ROL pin on the AD7872 performs
the same function. When this is at 0 V, SCLK is noncontinuous
and when it is at –5 V, SCLK is continuous.
T he Mode 1 function timing diagram for byte and serial data is
shown in Figure 10. INT goes low at the end of conversion and
is reset high by the first falling edge of CS and RD. T his first
read at the end of conversion can either access the low byte or
high byte of data depending on the status of HBEN (Figure 10
shows low byte for example only). T he diagram shows both the
SCLK output going into three-state at the end of transmission
and a continuously running clock (dashed line).
MO D E 2 INTERFACE
T he second interface mode is achieved by hard-wiring CONVST
low and conversion is initiated by taking CS low while HBEN is
low. T he track/hold amplifier goes into the hold mode on the
falling edge of CS. In this mode the BUSY/INT pin assumes its
BUSY function. BUSY goes low at the start of conversion, stays
low during the conversion and returns high when the conversion
is complete. It is normally used in parallel interfaces to drive the
microprocessor into a WAIT state for the duration of conversion.
T he SCLK, SDAT A and SSTRB lines are open-drain outputs.
If these are required to drive capacitive loads in excess of 35 pF,
buffering is recommended.
MO D E 1 INTERFACE
Conversion is initiated by a low going pulse on the CONVST
input. T he rising edge of this CONVST pulse starts conversion
and drives the track/hold amplifier into its hold mode. T he
BUSY/INT status output assumes its INT function in this
mode. INT is normally high and goes low at the end of conver-
sion. T his INT line can be used to interrupt the microprocessor.
A read operation to the AD7871 accesses the data and the INT
line is reset high on the falling edge of CS and RD. The CONVST
input must be high when CS and RD are brought low for the
AD7871 to operate correctly in this mode. It is important, espe-
cially in systems where the conversion start (CONVST) pulse is
asynchronous to the microprocessor, to ensure that a parallel or
byte data read is not attempted during a conversion. T rying to
read data during a conversion can cause errors to the conversion
in progress. Avoid pulsing the CONVST line a second time be-
fore conversion end since it can cause errors in the conversion
result. In applications where precise sampling is not critical, the
CONVST pulse can be generated from microprocessor WR line
OR-gated with the AD7871 CS input. In some applications, de-
pending on power supply turn-on time, the AD7871/AD7872
may perform a conversion on power-up. In this case, the INT
line on the AD7871 will power up low, and a dummy read to
the device will be required to reset the INT line before starting
conversion.
Figure 11 shows the Mode 2 timing diagram for the 14-bit paral-
lel data output format (14/8/CLK = +5 V). In this case the ADC
behaves like slow memory. T he major advantage of this interface
is that it allows the microprocessor to start conversion, WAIT
and then read data with a single READ instruction. T he user
does not have to worry about servicing interrupts or ensuring
that software delays are long enough to avoid the reading during
conversion.
T he Mode 2 timing diagram for byte and serial data is shown in
Figure 12. For 2-byte data read, the lower byte (DB0–DB7) has
to be accessed first since HBEN must be low to start con-ver-
sion. T he ADC behaves like slow memory for this first read, but
the second read to access the upper byte of data is a normal read.
Operation to the serial functions is identical between Mode 1
and Mode 2. Once again, the timing diagram of Figure 12 shows
SCLK going into three-state or running continuously (dashed
line).
REV. D
–8–
AD7871/AD7872
Figure 10. Mode 1 Tim ing Diagram , Byte or Serial Read
Figure 11. Mode 2 Tim ing Diagram , 14-Bit Parallel Read
Figure 12. Mode 2 Tim ing Diagram , Byte or Serial Read
–9–
REV. D
AD7871/AD7872
D YNAMIC SP ECIFICATIO NS
Effective Num ber of Bits
T he AD7871/AD7872 is specified and tested for dynamic per-
formance specifications as well as traditional dc specifications
such as Integral and Differential Nonlinearity. T hese ac specifi-
cations are required for signal processing applications such as
Speech Recognition, Spectrum Analysis and H igh Speed
Modems. T hese applications require information on the effects
on the spectral content of the input signal. Hence, the param-
eters for which the AD7871/AD7872 is specified include SNR,
Harmonic Distortion, Intermodulation Distortion and Peak
Harmonics. T hese terms are discussed in more detail in the fol-
lowing sections.
T he formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
SNR –1.76
N =
(2)
6.02
T he effective number of bits for a device can be calculated di-
rectly from its measured SNR. Figure 14 shows a typical plot of
effective number of bits versus frequency for the AD7871/
AD7872 with a sampling frequency of 60 kHz.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. T he signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fs/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. T he theoretical signal to noise ratio for a sine wave input
is given by:
SNR(dB) = (6.02N + 1.76)
(1)
where N is the number of bits in the ADC. T hus for an ideal
14-bit converter, SNR = 86 dB.
T he output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input, which is
sampled at an 83 kHz sampling rate. A Fast Fourier T ransform
(FFT ) plot is generated from which the SNR data can be ob-
tained. Figure 13 shows a typical 2048 point FFT plot of the
AD7871/AD7872, with an input signal of 10 kHz and a sam-
pling frequency of 83 kHz. T he SNR obtained from this graph
is
Figure 14. Effective Num ber of Bits vs. Frequency
H ar m onic D istor tion
Harmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7871/AD7872, T otal Harmonic
Distortion (T HD) is defined as
2
2
2
2
2
√
V2 +V3 +V4 +V5 +V6
THD(dB) = 20 log
V1
80 dB. It should be noted that the harmonics are included when
calculating the SNR.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic. T he T HD is also derived from the FFT plot of
the ADC output spectrum. Figure 15 shows how the T HD var-
ies with input frequency.
Figure 15. Total Harm onic Distortion vs. Frequency
Inter m odulation D istor tion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second or-
der terms include (fa+fb) and (fa–fb), while the third order
terms include (2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb).
Figure 13. Fast Fourier Transform Plot
REV. D
–10–
AD7871/AD7872
microprocessor and the conversion result is read from the ADC
with the following instruction:
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second and third or-
der terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs. In this case, the
input consists of two, equal amplitude, low distortion sine waves.
Figure 16 shows a typical IMD plot for the AD7871/AD7872.
ADSP-2100 MR0 = DM(ADC)
T MS32020/C25: IN D,ADC
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
ADC = AD7871 Address
Figure 17. AD7871 to ADSP-2100 Parallel Interface
Figure 16. IMD Plot
P eak H ar m onic or Spur ious Noise
Peak Harmonic or Spurious Noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fs/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, peak
will be a noise peak.
MICRO P RO CESSO R INTERFACE
T he AD7871 and AD7872 have a wide variety of interfacing op-
tions. T he AD7871 offers two operating modes and three
data-output formats, while the AD7872 is a dedicated serial
output device. T he fast data access times on the parallel modes
of the AD7871 allow interfacing to the very fast DSPs. T he se-
rial mode on both the AD7871 and AD7872 is compatible with
the serial port structures on all the popular DSPs.
Figure 18. AD7871 to TMS32020/C25 Interface
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the AD7871 CONVST from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note, a read opera-
tion must not be attempted during conversion.
P ar allel Read Inter facing
Figures 17 and 18 show interfaces to the ADSP-2100 and the
T MS32020/C25 DSP processors. T he AD7871 is operating in
Mode 1, parallel read for both interfaces. An external timer con-
trols conversion start asynchronously to the microprocessor. At
the end of each conversion the ADC BUSY/INT interrupts the
REV. D
–11–
AD7871/AD7872
Ser ial Inter facing
Both the AD7871 and the AD7872 have an identical serial in-
terface. T he diagrams that follow show the AD7872 interfaces
only, but the AD7871 could just as easily be used in these cir-
cuits. Figures 19, 20 and 21 show the AD7872 connected to
three popular DSPs. In all three interfaces, CONVST is used to
start conversion since this does not activate the parallel bus.
T hus, the microprocessor can continue to use its parallel bus re-
gardless of the state of the AD7872. T he interfaces show a timer
driving the CONVST input but this could be generated from a
decoded address if required.
AD7872–DSP56000 Serial Interface
Figure 19 shows a serial interface between the AD7872 and the
DSP56000. T he interface arrangement is two-wire with the
AD7872 configured for noncontinuous clock operation CON-
T ROL = 0 V). T he DSP56000 is configured for Normal Mode
Asynchronous Operation with Gated Clock. It is set up for a
16-bit word with SCK as an input and the FSL control bit set to
a 0. In this configuration, the DSP56000 assumes valid data on
the first falling edge of SCK. Since the AD7872 provides valid
data on this first edge, there is no need for a strobe or framing
pulse for the data. SCLK and SDAT A are three-stated when the
AD7872 is not performing a conversion. During conversion,
data is valid on the SDAT A output of the AD7872 and is
clocked into the Receive Data Shift Register of the DSP56000.
When this register has received 16 bits of data, it generates an
internal interrupt on the DSP56000 to read the data from the
register.
Figure 20. AD7872 to TMS32020/C25 Interface
AD7872–ADSP-2101/ADSP-2102 Serial Interface
Figure 21 shows a serial interface between the AD7872 and the
ADSP-2101/ADSP-2102 DSP Microcomputer. T he AD7872 is
configured for continuous clock operation. Data is clocked into
the serial port register of the microcomputer during conversion.
As with the previous interfaces, when a 16-bit data word is re-
ceived by the ADSP-2101/ADSP-2102 an internal microproces-
sor interrupt is generated and the data is read from the serial
port register.
Figure 21. AD7872 to ADSP-2101/ADSP-2102 Serial Interface
STAND -ALO NE O P ERATIO N
Figure 19. AD7872 to DSP56000 Interface
T he AD7871 can be used in its Mode 2, parallel mode for
stand-alone operation. In this case, conversion is initiated with a
pulse to the CS input. T his pulse must be longer than the con-
version time of the ADC. T he BUSY output is used to drive the
RD input. Data is latched from the AD7871 DB0–DB11 out-
puts to an external latch on the rising edge of BUSY.
T he DSP56000 and AD7872 can also be configured for con-
tinuous clock operation. In this case a strobe pulse is required
by the DSP56000 to indicate when data is valid. T he SSTRB
output of the AD7872 is inverted and applied to the SC1 input
of the DSP56000 to provide this strobe pulse. All other condi-
tions and connections are the same as for the gated clock
operation.
AP P LICATIO N H INTS
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
T he AD7871/AD7872 is required to make bit decisions on an
LSB size of 366 µV. T hus, the designer has to be conscious of
noise both in the ADC itself and in the preceding analog cir-
cuitry. Switching mode power supplies are not recommended as
the switching spikes will feed through to the comparator causing
noisy code transitions. Other causes of concern are ground loops
and digital feedthrough from microprocessors. T hese are factors
that influence any ADC; a proper PCB layout that minimizes
these effects is essential for best performance.
AD7872–TMS32020/C25 Serial Interface
Figure 20 shows a serial interface between the AD7872 and the
T MS32020/C25. T he AD7872 is configured for continuous
clock operation. Note, the ADC will not interface correctly to
the T MS32020/C25 if it is configured for a noncontinuous
clock. Data is clocked into the Data Receive Register (DRR) of
the T MS32020/C25 during conversion. As with the previous in-
terfaces, when a 16-bit word is received by the DSP it generates
an internal interrupt to read the data from the DRR.
REV. D
–12–
AD7871/AD7872
LAYO UT H INTS
terrupts labelled EIRQ0 to EIRQ3. T he AD7871 BUSY/INT
output connects to EIRQ0. T here is a single wait state generator
connected to EDMACK to allow the AD7871 to interface to the
faster versions of the ADSP-2100.
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. T ake
care not to run a digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
SKT 4 is a 26-way (2-row) IDC connector. T his contains the
same signal contacts as SKT 6 except for EDMACK, which is
connected to SKT 6 only. It also contains decoded R/W and
STRB inputs necessary for T MS32020 interfacing.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7871/AD7872 AGND
pin or as close as possible to the AD7871/AD7872. Connect all
other grounds and the AD7871/AD7872 DGND to this single
analog ground point. Do not connect any other digital grounds
to this analog ground point.
SKT 5 is a 5-way D-type connector meant for serial interfacing
only. An inverted DB11/SCLK output is also provided on this
connector for systems that accept data on a rising clock edge.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. T he use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise. T he circuit layout of Figures
26 and 27 have both analog and digital ground planes that are
kept separated and joined together only at the AD7871/AD7872
AGND pin.
SKT 1, SKT 2 and SKT 3 are three BNC connectors providing
connections for the analog input, the CONVST input and an
external clock.
NO ISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
D ATA ACQ UISITIO N BO ARD
Figure 24 shows the AD7871/AD7872 in a data acquisition cir-
cuit. T he corresponding printed circuit board (PCB) layout has
three interface ports: one serial and two parallel. Note that the
AD7871/AD7872 serial lines are buffered by a 74HC244. T his
allows long lines with large capacitive loads to be driven. One of
the parallel ports is directly compatible with the ADSP-2100
evaluation board expansion connector.
Figure 22. SKT4 Pinout
Figure 23. SKT5 Pinout
P O WER SUP P LY CO NNECTIO NS
T he PCB requires two analog power supplies and one 5 V logic
supply. T he analog supplies are labelled V+ and V–, and the
range for both supplies is 12 V to 15 V. Connection to the 5 V
digital supply is made through any of the connectors SKT 4 to
SKT 6. T he ±5 V supply required by the AD7871 and AD7872
is generated from voltage regulators on the V+ and V– power
supplies input (IC6 and IC7 in Figure 24).
T he only additional component required for a full data acquisi-
tion system is an anti-aliasing filter. T here is a component grid
provided near the analog input on the PCB, which may be used
for such a filter or any other input conditioning circuitry. T o fa-
cilitate this option, there is a shorting plug (labelled LK1 on the
PCB) on the analog input track. If this shorting plug is used, the
analog input connects to the buffer amplifier driving the AD7871/
AD7872; if this shorting plug is omitted, a wire link can be used to
connect the analog input to the PCB component grid.
SH O RTING P LUG O P TIO NS
T here are seven shorting plug options which must be set before
using the board. T hese are outlined below:
LK1 Connects the analog input to a buffer amplifier. T he
analog input may also be connected to a component
grid for signal conditioning.
LK2 Selects either the AD7871/AD7872 internal clock or
an external clock source.
INTERFACE CO NNECTIO NS
T here are two parallel connectors labeled SKT 4 and SKT 6,
and one serial connector labeled SKT 5. A shorting plug option
(LK3 in Figure 24) configures the ADC for the appropriate
interface.
LK3 Configures the AD7871 14/8/CLK input for the
appropriate serial or parallel interface.
SKT 6 is a 96-contact (3-row) Eurocard connector that is directly
compatible with the ADSP-2100 Evaluation Board Prototype
Expansion Connector. T he expansion connector on the
ADSP-2100 has eight decoded chip enable outputs labeled
ECE1 to ECE8. ECE6 is used to drive the AD7871 CS input
on the board. T o avoid selecting the onboard RAM sockets at
the same time, LK6 on the ADSP-2100 board must be removed.
In addition, the ADSP-2100 expansion connector has four in-
LK4 Connects the AD7871 RD input directly to the two par-
allel connectors or to a decoded STRB and R/W input.
LK5 Connects the pull-up resistor R3 to SSTRB.
LK6 Connects the pull-up resistor R4 to SCLK.
LK7 Connects the pull-up resistor R5 to SDAT A.
Note that LK5 to LK7 should be removed for parallel interfacing.
REV. D
–13–
AD7871/AD7872
Figure 24. Data Acquisition Circuit Using the AD7871/AD7872
Figure 25. PCB Silkscreen for Figure 24
–14–
REV. D
AD7871/AD7872
Figure 26. PCB Com ponent Side Layout for Figure 24
Figure 27. PCB Solder Side Layout for Figure 24
–15–
REV. D
AD7871/AD7872
AD 7871 O RD ERING GUID E
AD 7872 O RD ERING GUID E
Tem perature
Range
Relative P ackage
Accuracy O ption3
Tem perature
Range
Relative P ackage
Model1, 2
SNR
Model1
SNR
Accuracy O ption2
AD7871JN
AD7871KN
AD7871JP
AD7871KP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
80 dBs min
80 dBs min ±1 max
80 dBs min
N-28A
AD7872AN –40°C to +85°C 80 dBs min
AD7872JN 0°C to +70°C 80 dBs min
AD7872KN 0°C to +70°C 80 dBs min ±1 max
AD7872BR –40°C to +85°C 79 dBs min ±1 max
N-16
N-16
N-28A
P-28A
P-28A
Q-28
N-16
R-16
R-16
R-16
Q-16
80 dBs min ±1 max
AD7871T Q4 –55°C to +125°C 79 dBs min ±1 max
AD7872JR
0°C to +70°C
80 dBs min
AD7872KR 0°C to +70°C
80 dBs min ±1 max
NOT ES
AD7872T Q3 –55°C to +125°C 79 dBs min ±1 max
1T o order MIL-ST D-883, Class B, processed parts, add /883B to part number.
Contact local sales office for military data sheet.
NOT ES
2Contact local sales office for LCCC availability.
1T o order MIL-ST D-883, Class B, processed parts, add /883B to part number.
Contact local sales office for military data sheet.
3N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC);Q = Cerdip.
4Available to /883B processing only.
2N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
3Available to /883B processing only.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-P in P lastic D IP (N-16)
0.755 (19.18)
28-P in P lastic D IP (N-28A)
1.450 (36.83)
0.745 (18.93)
1.440 (36.576)
16
1
9
28
15
0.26 (6.61)
0.24 (6.1)
0.306 (7.78)
0.294 (7.47)
PIN 1
0.550 (13.97)
0.530 (13.462)
8
PIN 1
1
14
0.606 (15.39)
0.594 (15.09)
0.14 (3.56)
0.12 (3.05)
0.17 (4.32)
MAX
0.200
(5.080)
MAX
0.160 (4.06)
0.140 (3.56)
0.175 (4.45)
0.120 (3.05)
0.175 (4.45)
0.12 (3.05)
SEATING
PLANE
0.012 (0.305)
0.008 (0.203)
0.065 (1.66) 0.02 (0.508)
0.045 (1.15) 0.015 (0.381)
0.105 (2.67)
0.095 (2.42)
SEATING
PLANE
15°
0
15°
0°
0.012 (0.305)
0.008 (0.203)
0.105 (2.67)
0.095 (2.41)
0.065 (1.65) 0.020 (0.508)
0.045 (1.14) 0.015 (0.381)
LEAD NO. 1 IDENTIFIED BY NOT OR NOTCH.
LEADS ARE SOLDER OF TIN-PLATED KOVAR OR ALLOY 42.
LEAD NO. 1 IDENTIFIED BY NOT OR NOTCH.
LEADS ARE SOLDER DIPPED OF TIN-PLATED ALLOY 42 OR COPPER.
16-P in Cer dip (Q -16)
0.785 (19.94)
28-P in Cer dip (Q -28)
1.490 (37.84) MAX
0.75 (19.05)
16
9
8
28
15
0.30 (7.62)
0.24 (6.1)
0.32 (8.128)
0.29 (7.366)
PIN 1
0.525 (13.33)
0.515 (13.08)
1
PIN 1
0.155
(3.937)
MIN
0.18 (4.572)
1
14
0.14 (3.56)
0.20 (5.08)
0.62 (15.74)
0.59 (14.93)
GLASS SEALANT
SEATING
PLANE
0.125 (3.175)
0.22
(5.59)
MAX
0.18 (4.57)
MAX
0.015 (0.381)
0.008 (0.203)
0.023 (0.584)
0.015 (0.381)
0.07 (1.778)
0.03 (0.762)
0.11 (2.794)
0.09 (2.28)
15°
0°
0.125 (3.175)
MIN
0.012 (0.305)
0.008 (0.203)
SEATING
PLANE
LEAD NO. 1 IDENTIFIED BY NOT OR NOTCH.
LEADS ARE SOLDER OF TIN-PLATED KOVAR OR ALLOY 42.
0.11 (2.79)
0.02 (0.5)
0.016 (0.406)
15°
0°
0.099 (2.28)
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
LEADS ARE SOLDER OF TIN-PLATED KOVAR OR ALLOY 42.
16-P in SO IC (R-16)
0.413 (10.49)
0.398 (10.11)
28-P in P LCC (P -28A)
16
9
8
0.180 (4.51)
0.165 (4.20)
0.456 (11.582)
0.450 (11.430)
SQ
26
0.419 (10.64)
0.394 (10.01)
0.300 (7.62)
0.292 (7.42)
4
5
25
PIN 1
IDENTIFIER
0.021 (0.533)
0.013 (0.331)
1
0.02 (0.508) x
45؇C
CHAMP
0.430 (10.5)
0.390 (9.9)
PIN 1
TOP VIEW
(PINS DOWN)
0.050 ±0.005
(1.27 ±0.13)
0.350 (8.89)
0.032 (0.812)
0.026 (0.661)
0.104 (2.64)
0.093 (2.36)
11
12
19
18
0.011 (0.279)
0.004 (0.102)
STANDOFF
0.050 (1.27)
0.019 (0.483)
0.050
(1.27)
BSC
0.495 (12.57)
0.01 (0.254)
SEATING
PLANE
SQ
0.014 (0.356)
0.120 (3.04)
0.090 (2.29)
0.485 (12.32)
REV. D
–16–
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