AD7873ARQZ-REEL7_技术文档

Touch Screen Digitizer

Data Sheet

AD7873

FEATURES

4-wire touch screen interface

FUNCTIONAL BLOCK DIAGRAM

+V

PENIRQ

CC

On-chip temperature sensor: −40°C to +85°C

On-chip 2.5 V reference

Direct battery measurement (0 V to 6 V)

Touch pressure measurement

PEN

INTERRUPT

TEMP

SENSOR

X+

X–

Specified throughput rate of 125 kSPS

Single supply, V_CCof 2.2 V to 5.25 V

Ratiometric conversion

High speed serial interface

Programmable 8-bit or 12-bit resolution

One auxiliary analog input

AD7873

Y+

Y–

T/H

6-TO-1

I/P

MUX

AUX

COMP

BATTERY

MONITOR

Shutdown mode: 1 µA maximum

16-lead QSOP, TSSOP, and LFCSP packages

V

BAT

APPLICATIONS

V

REF

GND

Personal digital assistants

Smart hand-held devices

Touch screen monitors

Point-of-sale terminals

Pagers

CHARGE

REDISTRIBUTION

DAC

+V

CC

2.5V

REF

BUF

SAR + ADC

CONTROL LOGIC

GENERAL DESCRIPTION

The AD7873 is a 12-bit successive approximation ADC with a

synchronous serial interface and low on resistance switches for

driving touch screens. The AD7873 operates from a single 2.2 V

to 5.25 V supply, with a throughput rate of 125 kSPS.

SPORT

The AD7873 features direct battery measurement, temperature

measurement, and touch pressure measurement. The AD7873

also has an on-board reference of 2.5 V that can be used for the

auxiliary input, battery monitor, and temperature measurement

modes. When not in use, the internal reference can be shut

down to conserve power. An external reference can also be

applied and varied from 1 V to V_CCwith an analog input range

from 0 V to V_REF. The device includes a shutdown mode that

reduces the current consumption to less than 1 µA.

DIN

DOUT

DCLK

BUSY

CS

Figure 1.

PRODUCT HIGHLIGHTS

1. Ratiometric conversion mode available, eliminating errors

due to on-board switch resistances.

2. On-board temperature sensor: −40°C to +85°C.

3. Battery monitor input.

4. Touch pressure measurement capability.

The AD7873 features on-board switches. This, coupled with low

power and high speed operation, makes the device ideal for

battery-powered systems with resistive touch screens. The part

is available in a 16-lead, 0.15 inch quarter size outline package

(QSOP), a 16-lead, thin shrink small outline package (TSSOP),

and a 16-lead, lead frame chip scale package (LFCSP).

5. Low power consumption of 1.37 mW maximum with the

reference off, or 2.41 mW typical with the reference on, at

125 kSPS and V_CCat 3.6 V.

6. Package options include 4 mm × 4 mm LFCSP.

7. Analog input range from 0 V to V_REF

8. Versatile serial I/O ports.

.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

IMPORTANT LINKS for the AD7873*

Last content update 08/31/2013 11:50 pm

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DOCUMENTATION

DESIGN SUPPORT

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Linear and Data Converters

Embedded Processing and DSP

AN-577: Layout and Grounding Recommendations for Touch Screen

Digitizers

UG-062: Evaluation Board for AD7843/AD7873 Resistive Touch Screen

Controllers

The PDA Challenge—Met by the AD7873 Resistive-Touch-Screen

Controller ADC

Telephone our Customer Interaction Centers toll free:

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Europe:

China:

1-800-262-5643

00800-266-822-82

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Products for Wireless Handset Applications

Product Solutions for Handset Applications

India:

Russia:

1800-419-0108

8-800-555-45-90

Quality and Reliability

Lead(Pb)-Free Data

EVALUATION KITS & SYMBOLS & FOOTPRINTS

Symbols and Footprints

SAMPLE & BUY

AD7873

View Price & Packaging

Request Evaluation Board

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AD7873

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Circuit Information........................................................................ 13

ADC Transfer Function............................................................. 13

Typical Connection Diagram ................................................... 13

Analog Input ............................................................................... 14

Measurements............................................................................. 16

Pen Interrupt Request................................................................ 18

Control Register ......................................................................... 19

Power vs. Throughput Rate....................................................... 20

Serial Interface............................................................................ 21

Grounding and Layout .................................................................. 23

PCB Design Guidelines for Chip Scale Package .................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 25

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

REVISION HISTORY

2/13—Rev. E to Rev. F

4/03—Rev. B to Rev. C

Changes to General Description Section ...................................... 1

Added EPAD Note to Figure 3 and Table 5................................... 7

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide .......................................................... 26

Changes to Formatting ......................................................Universal

Updated Outline Dimensions....................................................... 19

1/02—Rev. A to Rev. B

Addition of 16-Lead Lead Frame Chip Scale Package ..Universal

Edits to Features.................................................................................1

Edits to General Description ...........................................................1

Addition of LFCSP Pin Configuration ...........................................4

Edit to Absolute Maximum Ratings................................................4

Addition to Ordering Guide ............................................................4

Addition of CP-16 Outline Dimensions .................................... 19

9/06—Rev. D to Rev. E

Changes to Figure 13 Caption ...................................................... 10

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide .......................................................... 25

6/04—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings....................................... 6

Additions to PD0 and PD1 Description...................................... 21

PBC Guidelines for Chip Scale Package Added ......................... 23

Additions to Ordering Guide........................................................ 25

2/01—Rev. 0 to Rev A

Edits to Notes in the Ordering Guide

Rev. F | Page 2 of 28

Data Sheet

AD7873

SPECIFICATIONS

V_CC= 2.7 V to 3.6 V, V_REF= 2.5 V internal or external, f_DCLK= 2 MHz; T_A= −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

AD7873A¹

AD7873B¹

Unit

Test Conditions/Comments

DC ACCURACY

Resolution

12

11

±2

12

± 1

–0.9/+1.5

±±

±ꢀ

70

Bits

No Missing Codes

Integral Nonlinearity²

Differential Nonlinearity²

Offset Error²

Gain Error²

Noise

Power Supply Rejection

SWITCH DRIVERS

On Resistance²

Bits min

LSB max

µV rms typ

dB typ

±±

±ꢀ

70

+V_CC= 2.7 V

External reference

Y+, X+

Y–, X–

5

±

5

±

Ω typ

ANALOG INPUT

Input Voltage Ranges

DC Leakage Current

Input Capacitance

REFERENCE INPUT/OUTPUT

Internal Reference Voltage

Internal Reference Tempco

V_REFInput Voltage Range

DC Leakage Current

V_REFInput Impedance

0 to V_REF

±0.1

37

0 to V_REF

±0.1

37

V

µA typ

pF typ

2.ꢀ5/2.55

±15

1/V_CC

±1

2.ꢀ5/2.55

±15

1/V_CC

± 1

V min/max

ppm/°C typ

V min/max

µA max

1

GΩ typ

CS = GND or +V_CC; typically 2±0 Ω when the

on-board reference is enabled

TEMPERATURE MEASUREMENT

Temperature Range

Resolution

–ꢀ0/+85

°C min/max

Differential Method³

Single Conversion Method^ꢀ

Accuracy

1.±

0.3

1.±

0.3

°C typ

Differential Method³

Single Conversion Method^ꢀ

BATTERY MONITOR

Input Voltage Range

Input Impedance

±2

°C typ

0/±

10

±2.5

±3

0/±

10

±2

±3

V min/max

kΩ typ

% max

Sampling; 1 GΩ when battery monitor is off

External reference

Internal reference

Accuracy

% max

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.ꢀ

0.ꢀ

±1

10

2.ꢀ

0.ꢀ

±1

10

V min

V max

µA max

pF max

Typically 10 nA, V_IN= 0 V or +V_CC

5

Input Capacitance, C_IN

Rev. F | Page 3 of 28

AD7873

Data Sheet

Parameter

AD7873A¹

AD7873B¹

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

PENIRQ Output Low Voltage, V_OL

Floating-State Leakage Current

Floating-State Output Capacitance⁵

Output Coding

V_CC– 0.2

0.ꢀ

V_CC– 0.2

0.ꢀ

V min

I_SOURCE= 250 µA; V_CC= 2.2 V to 5.25 V

I_SINK= 250 µA

100 kΩ pull-up; I_SINK= 250 µA

V max

µA max

pF max

±10

10

±10

10

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

Throughput Rate

12

3

125

12

3

125

DCLK cycles max

DCLK cycles min

kSPS max

POWER REQUIREMENTS

+V_CC(Specified Performance)

I_CC

2.7/3.±

V min/max

Functional from 2.2 V to 5.25 V

Digital I/Ps = 0 V or V_CC

±

Normal Mode (f_SAMPLE= 125 kSPS)

380

±70

380

±70

170

150

580

1

µA max

µA typ

µA max

Internal reference off, V_CC= 3.± V, 2ꢀ0 µA typ

Internal reference on, V_CC= 3.± V

Internal reference off, V_CC= 2.7 V, f_DCLK= 200 kHz

Internal reference off, V_CC= 3.± V

Internal reference on, V_CC= 3.± V

200 nA typ

Normal Mode (f_SAMPLE= 12.5 kSPS) 170

Normal Mode (Static)

150

580

1

Shutdown Mode (Static)

Power Dissipation^±

Normal Mode (f_SAMPLE= 125 kSPS)

1.3±8

2.ꢀ12

3.±

1.3±8

2.ꢀ12

3.±

mW max

mW typ

µW max

Internal reference off, V_CC= 3.± V

Internal reference on, V_CC= 3.± V

V_CC= 3.± V

Shutdown

¹Temperature range as follows: A, B Versions: –ꢀ0°C to +85°C.

²See the Terminology section.

³Difference between TEMP0 and TEMP1 measurement. No calibration necessary.

^ꢀTemperature drift is –2.1 mV/°C.

⁵Sample tested @ 25°C to ensure compliance.

^±See the Power vs. Throughput Rate section.

Rev. F | Page ꢀ of 28

Data Sheet

AD7873

TIMING SPECIFICATIONS

T_A= T_MINto T_MAX, unless otherwise noted; V_CC= 2.7 V to 5.25 V, V_REF= 2.5 V.

Table 2. Timing Specifications¹

Parameter

Limit at T_MIN, T_MAX

Unit

Description

2

f_DCLK

10

2

1.5

10

kHz min

MHz max

µs min

ns min

ns max

ns min

ns max

ns min

ns max

ns min

ns max

t_ACQ

t₁

Acquisition time

CS falling edge to first DCLK rising edge

CS falling edge to busy three-state disabled

CS falling edge to DOUT three-state disabled

DCLK high pulse width

t₂

±0

3

t₃

±0

t_ꢀ

t₅

t_±

t₇

t₈

200

±0

10

DCLK low pulse width

DCLK falling edge to BUSY rising edge

Data setup time prior to DCLK rising edge

Data valid to DCLK hold time

Data access time after DCLK falling edge

CS rising edge to DCLK ignored

3

t₉

200

0

t₁₀

t₁₁

CS rising edge to BUSY high impedance

CS rising edge to DOUT high impedance

100

ꢀ

t₁₂

¹Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V_CC) and timed from a voltage level of 1.± V.

²Mark/space ratio for the DCLK input is ꢀ0/±0 to ±0/ꢀ0.

³Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.ꢀ V or 2.0 V.

^ꢀt₁₂is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t₁₂, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

200µA

I

OL

TO OUTPUT

1.6V

C

L

50pF

200µA

I

OH

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. F | Page 5 of 28

AD7873

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

+V_CCto GND

–0.3 V to +7 V

Analog Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

V_REFto GND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

Commercial (A, B Versions)

Storage Temperature Range

Junction Temperature

Power Dissipation

–0.3 V to V_CC+ 0.3 V

±10 mA

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

–ꢀ0°C to +85°C

–±5°C to +150°C

150°C

Table 4. Thermal Resistance

Package Type

1±-Lead QSOP

1±-Lead TSSOP

1±-Lead LFCSP

θ_JA

θ_JC

Unit

°C/W

1ꢀ9.97

150.ꢀ

135.7

38.8

27.±

ꢀ50 mW

IR Reflow Soldering

Peak Temperature

Time-to-Peak Temperature

Ramp-Down Rate

220°C (±5°C)

10 sec to 30 sec

±°C/sec max

ESD CAUTION

Pb-free Parts Only

Peak Temperature

250°C

Time-to-Peak Temperature

Ramp-Up Rate

Ramp-Down Rate

20 sec to ꢀ0 sec

3°C/sec max

±°C/sec max

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. F | Page ± of 28

Data Sheet

AD7873

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AUX

1

2

3

4

12

Y+

V

11 X+

REF

AD7873

TOP VIEW

+V

10

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

+V

DCLK

CS

CC

9

PENIRQ

DCLK

X+

Y+

X–

Y–

DIN

BUSY

DOUT

PENIRQ

AD7873

TOP VIEW

(Not to Scale)

GND

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.

FOR INCREASED RELIABILITY OF THE SOLDER JOINTS

AND MAXIMUM THERMAL CAPABILITY, IT IS

RECOMMENDED THAT THE PAD BE SOLDERED

TO GROUND PLANE.

V

+V

CC

BAT

AUX

V

REF

Figure 3. LFCSP Pin Configuration

Figure 4. QSOP/TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

QSOP/

TSSOP

Mnemonic

Description

LFCSP

3, 10

1, 10

+V_CC

Power Supply Input. The +V_CCrange for the AD7873 is from 2.2 V to 5.25 V. Both +V_CCpins should be

connected directly together.

11

12

13

1ꢀ

15

2

3

ꢀ

5

±

X+

Y+

X–

Y–

GND

X+ Position Input. ADC Input Channel 1.

Y+ Position Input. ADC Input Channel 2.

X– Position Input.

Y– Position Input. ADC Input Channel 3.

Analog Ground. Ground reference point for all circuitry on the AD7873. All analog input signals

and any external reference signals should be referred to this GND voltage.

1±

1

2

7

8

9

V_BAT

AUX

V_REF

Battery Monitor Input. ADC Input Channel ꢀ.

Auxiliary Input. ADC Input Channel 5.

Reference Output for the AD7873. Alternatively, an external reference can be applied to this input.

The voltage range for the external reference is 1.0 V to +V_CC. For specified performance, it is 2.5 V on

the AD7873. The internal 2.5 V reference is available on this pin for use external to the device. The

reference output must be buffered before it is applied elsewhere in a system. A 0.1 µF capacitor is

recommended between this pin and GND to reduce system noise effects.

ꢀ

5

11

12

PENIRQ

DOUT

Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally).

Data Out. Logic output. The conversion result from the AD7873 is provided on this output as a

serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is

high impedance when CS is high.

±

7

13

1ꢀ

BUSY

DIN

BUSY Output. Logic output. This output is high impedance when CS is high.

Data In. Logic Input. Data to be written to the AD7873 control register is provided on this input and

is clocked into the register on the rising edge of DCLK (see the Control Register section).

8

9

15

CS

Chip Select Input. Active low logic input. This input provides the dual function of initiating

conversions on the AD7873 and enabling the serial input/output register.

External Clock Input. Logic input. DCLK provides the serial clock for accessing data from the part.

This clock input is also used as the clock source for the AD7873 conversion process.

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder

joints and maximum thermal capability, it is recommended that the pad be soldered to the ground

plane.

1±

DCLK

EPAD

N/A¹

¹N/A = not applicable.

Rev. F | Page 7 of 28

AD7873

Data Sheet

TERMINOLOGY

Integral Nonlinearity

Gain Error

Integral nonlinearity is the maximum deviation from a straight

line passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point 1 LSB

below the first code transition, and full scale, a point 1 LSB

above the last code transition.

Gain error is the deviation of the last code transition (111…110)

to (111…111) from the ideal (that is, V_REF– 1 LSB) after the

offset error is adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier enters the acquisition phase on

the fifth falling edge of DCLK after the start bit has been

detected. Three DCLK cycles are allowed for the track-and-hold

acquisition time. The input signal is fully acquired to the 12-bit

level within this time even with the maximum specified DCLK

frequency. See the Analog Input section for more details.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

and the ideal 1 LSB change between any two adjacent codes in

the ADC.

Offset Error

Offset error is the deviation of the first code transition (00…000)

On Resistance

to (00…001) from the ideal, that is, AGND + 1 LSB.

On resistance is a measure of the ohmic resistance between the

drain and source of the switch drivers.

Rev. F | Page 8 of 28

Data Sheet

AD7873

TYPICAL PERFORMANCE CHARACTERISTICS

141

140

139

138

137

136

135

134

207

206

205

204

203

202

201

200

199

198

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

4.6

80

100

TEMPERATURE (°C)

Figure 5. Supply Current vs. Temperature

Figure 8. Power-Down Supply Current vs. Temperature

230

1000

f_SAMPLE= 12.5kHz

220

210

200

190

180

170

160

150

V

= +V

REF

CC

V

= +V

CC

REF

100

2.2

2.6

3.0

3.4

3.8

4.2

5.0

2.2

2.7

3.2

3.7

4.2

4.7

5.2

+V (V)

CC

+V (V)

CC

Figure 6. Supply Current vs. +V_CC

Figure 9. Maximum Sample Rate vs. +V_CC

0.20

0.15

0.10

0.05

0

0.6

0.4

0.2

0

–0.05

–0.10

–0.15

–0.20

–0.2

–0.4

–0.6

–40

–20

0

20

40

60

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 7. Change in Gain vs. Temperature

Figure 10. Change in Offset vs. Temperature

Rev. F | Page 9 of 28

AD7873

Data Sheet

7.5

6.5

5.5

4.5

3.5

2.5

1.5

14

13

12

11

10

9

8

7

6

5

4

3

0.5

10

2

–40

25

40

55

70

85

100

115

130

–20

0

20

40

60

80

SAMPLE RATE (kHz)

TEMPERATURE (°C)

Figure 11. Reference Current vs. Sample Rate

Figure 14. Reference Current vs. Temperature

10

9

8

7

6

5

4

3

Y+

X+

Y+

X+

8

X–

7

Y–

X–

6

Y–

5

4

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

–40

–20

0

20

40

60

80

100

+V (V)

CC

TEMPERATURE (°C)

Figure 12. Switch On Resistance vs. +V_CC

(X+, Y+: +V_CCto Pin; X−, Y−: Pin to GND)

Figure 15. Switch On Resistance vs. Temperature

(X+, Y+: +VCC to Pin; X−, Y−: Pin to GND)

2.5006

2.5004

2.5002

2.5000

2.4998

2.4996

2.4994

2.4992

2.4990

2.4988

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INL: R = 2kΩ

INL: R = 500Ω

DNL: R = 2kΩ

DNL: R = 500Ω

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

15

35

55

75

95

115

135

155

175

195

SAMPLING RATE (kSPS)

Figure 13. Linearity Error vs. Sampling Rate for Various R_IN

Figure 16. Internal V_REFvs. Temperature

Rev. F | Page 10 of 28

Data Sheet

AD7873

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

2.488

2.486

2.484

5

4

3

2

1

0

NO CAP (7µs)

SETTLING TIME

1µF CAP (1800µs)

SETTLING TIME

2.5

2.7

2.9

3.1

+V (V)

3.3

3.5

3.7

0

200

400

600

800 1000 1200 1400 1600 1800

TURN-ON TIME (µs)

CC

Figure 17. Internal V_REFvs. +V_CC

Figure 20. Internal V_REFvs. Turn-on Time

610

609

608

607

606

605

604

603

602

601

600

850

800

750

700

650

600

550

500

450

TEMP1

95.95mV

TEMP0

142.15mV

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

2.7

2.8

2.9

3.0

3.1

3.2

(V)

3.3

3.4

3.5

3.6

V

SUPPLY

Figure 18. Temp Diode Voltage vs. Temperature (2.7 V Supply)

Figure 21. TEMP0 Diode Voltage vs. V_SUPPLY(25°C)

730

729

728

727

726

725

724

723

722

721

720

0

f_SAMPLE= 125kHz

f_IN= 15kHz

SNR = 68.34dB

20

40

60

80

100

120

0

7.5

15.0

22.5

30.0

37.5

45.0

52.5

60.0

2.7

3.0

3.3

3.6

FREQUENCY (kHz)

V

(V)

SUPPLY

Figure 19. TEMP1 Diode Voltage vs. V_SUPPLY(25°C)

Figure 22. Auxiliary Channel Dynamic Performance

(f_SAMPLE=125 kHz, f_INPUT= 15 kHz)

Rev. F | Page 11 of 28

AD7873

Data Sheet

0

Figure 23 shows the power supply rejection ratio vs. V_DDsupply

frequency for the AD7873. The power supply rejection ratio is

defined as the ratio of the power in the ADC output at full-scale

frequency, f, to the power of a 100 mV sine wave applied to the

ADC V_CCsupply of frequency f_S

V

= 3V

CC

100mV p-p SINE WAVE ON +V

CC

–20

–40

V

= 2.5V EXT REFERENCE

REF

f_SAMPLE= 125kHz, f_IN= 20kHz

PSSR (dB) = 10log(Pf/Pf_s)

–60

where:

–80

Pf is power at frequency, f, in ADC output.

Pf_sis power at frequency, f_s, coupled onto the ADC V_CCsupply.

–100

–120

Here a 100 mV p-p sine wave is coupled onto the V_CCsupply.

Decoupling capacitors of 10 µF and 0.1 µF were used on the supply.

0

10

20

30

CC

40

50

60

70

80

90

100

V

RIPPLE FREQUENCY (kHz)

Figure 23. AC PSRR vs. Supply Ripple Frequency

Rev. F | Page 12 of 28

Data Sheet

AD7873

CIRCUIT INFORMATION

The AD7873 is a fast, low power, 12-bit, single-supply analog-

to-digital converter (ADC). The AD7873 can be operated from

a 2.2 V to 5.25 V supply. When operated from either a 5 V

supply or a 3 V supply, the AD7873 is capable of throughput

rates of 125 kSPS when provided with a 2 MHz clock.

111...111

111...110

111...000

011...111

1LSB = V

/4096

REF

The AD7873 provides the user with on-chip track-and-hold,

multiplexer, ADC, reference, temperature sensor, and serial

interface, housed in a tiny 16-lead QSOP, TSSOP, or LFCSP

package, offering the user considerable space-saving advantages

over alternative solutions. The serial clock input (DCLK)

accesses data from the part and also provides the clock source

for the successive approximation ADC. The analog input range

is 0 V to V_REF(where the externally applied V_REFcan be between

1 V and +V_CC). The AD7873 has a 2.5 V reference on-board

with this reference voltage available for use externally if buffered.

000...010

000...001

000...000

+V

– 1LSB

1LSB

REF

0V

ANALOG INPUT

Figure 24. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 25 shows a typical connection diagram for the AD7873

in a touch screen control application. The AD7873 features an

internal reference, but this can be overdriven with an external

low impedance source between 1 V and +V_CC. The value of the

reference voltage sets the input range of the converter. The

conversion result is output MSB first, followed by the remaining

11 bits and three trailing zeros, depending on the number of

clocks used per conversion (see the Serial Interface section). For

applications where power consumption is a concern, the power

management option should be used to improve power perform-

ance. See Table 8 for available power management options.

The analog input to the ADC is provided via an on-chip

multiplexer. This analog input can be any one of the X, Y, and Z

panel coordinates, the battery voltage, or the chip temperature.

The multiplexer is configured with low resistance switches that

allow an unselected ADC input channel to provide power and

an accompanying pin to provide ground for an external device.

For some measurements, the on resistance of the switches could

present a source of error. However, with a differential input to

the converter and a differential reference architecture, this error

can be negated.

ADC TRANSFER FUNCTION

The output coding of the AD7873 is straight binary. The

designed code transitions occur at successive integer LSB values

(that is, 1 LSB, 2 LSBs, and so on). The LSB size is V_REF/4096.

The ideal transfer characteristic for the AD7873 is shown in

Figure 24.

2.2V TO 5V

+

1µF TO 10µF

(OPTIONAL)

0.1µF

+V

DCLK

1

2

3

4

5

6

7

8

16

15

14

SERIAL/CONVERSION CLOCK

CHIP SELECT

CC

X+

Y+

X–

CS

AD7873

SERIAL DATA IN

DIN

CONVERTER STATUS

SERIAL DATA OUT

BUSY 13

TOUCH

SCREEN

12

Y–

DOUT

TO BATTERY

11

GND

PEN INTERRUPT

PENIRQ

+V

V

10

9

CC

BAT

AUXILIARY

INPUT

50kΩ

AUX

REF

+

0.1µF

VOLTAGE

REGULATOR

Figure 25. Typical Application Circuit

Rev. F | Page 13 of 28

AD7873

Data Sheet

ANALOG INPUT

Figure 26 shows an equivalent circuit of the analog input

structure of the AD7873 that contains a block diagram of the

input multiplexer, the differential input of the ADC, and the

differential reference.

V

CC

X+

X–

Table 6 shows the multiplexer address corresponding to each

Y+

Y–

REF

INT/

analog input, both for the SER/

bit in the control register

DFR

X+ Y+ EXT

set high and low. The control bits are provided serially to the

device via the DIN pin. For more information on the control

register, see the Control Register section.

3-TO-1

MUX

ON-CHIP SWITCHES

When the converter enters hold mode, the voltage difference

between the +IN and –IN inputs (see Figure 26) is captured on

the internal capacitor array. The input current on the analog

inputs depends on the conversion rate of the device. During the

sample period, the source must charge the internal sampling

capacitor (typically 37 pF). Once the capacitor is fully charged,

there is no further input current. The rate of charge transfer

from the analog source to the converter is a function of

conversion rate.

X+

Y+

Y–

REF+

ADC CORE

IN+

DATA OUT

IN+

6-TO-1

MUX

IN– REF–

V

BAT

AUX

3-TO-1

MUX

TEMP

X– Y– GND

Figure 26. Equivalent Analog Input Circuit

Table 6. Analog Input, Reference, and Touch Screen Control

A2

0

A1

0

1

A0

0

1

0

1

Analog Input

TEMP0

X+

VBAT

X+ (Z1)

X Switches

Off

Y Switches

+REF¹

V_REF

–REF¹

GND

SER/ DFR

1

Off

On

Off

Y+ On

Y– Off

Y+ On

Y– Off

Off

X+ Off

X– On

X+ Off

X– On

On

V_REF

1

0

1

Y– (Z2)

V_REF

GND

1

0

1

0

1

0

1

0

1

0

Y+

V_REF

GND

AUX

TEMP1

Off

Invalid Address. Test Mode: Switches out the TEMP0 diode to the PENIRQ pin.

0

1

0

1

0

X+

Off

On

Y+

X+

Y–

X–

Invalid Address

X+ (Z1)

X+ Off

X– On

X+ Off

X– On

ON

Y+ On

Y– Off

Y+ On

Y– Off

Off

1

0

Y– (Z2)

Y+

1

0

1

0

1

0

Outputs Identity Code, 1000 0000 0000.

Invalid address. Test mode: Switches out the TEMP1 diode to the PENIRQ pin.

¹Internal node, not directly accessible by the user.

Rev. F | Page 1ꢀ of 28

Data Sheet

AD7873

Acquisition Time

time of the 2.5 V reference is typically 10 µs without a load;

however, a 0.1 µF capacitor on the V_REFpin is recommended for

optimum performance because it affects the power-up time (see

Figure 20).

The track-and-hold amplifier enters tracking mode on the

falling edge of the fifth DCLK after the start bit is detected (see

Figure 35). The time required for the track-and-hold amplifier

to acquire an input signal depends on how quickly the 37 pF

input capacitance is charged. With zero source impedance on

the analog input, three DCLK cycles are always sufficient to

acquire the signal to the 12-bit level. With a source impedance

(R_IN) on the analog input, the actual acquisition time required is

calculated using the formula:

X+

Y+

3-TO-1

MUX

ADC

260Ω

V

REF

SW1

t_ACQ= 8.4 ×

(

R_IN+ 100 Ω × 37 pF

)

2.5V

REF

BUF

where R_INis the source impedance of the input signal, and 100 Ω,

37 pF is the input RC. Depending on the frequency of DCLK

used, three DCLK cycles may or may not be sufficient to acquire

the analog input signal with various source impedance values.

Figure 27. On-Chip Reference Circuitry

Reference Input

The voltage difference between +REF and −REF (see Figure 26)

sets the analog input range. The AD7873 operates with a refer-

ence input in the range of 1 V to +V_CC. Figure 27 shows the

on-chip reference circuitry on the AD7873. The internal

reference on the AD7873 can be overdriven with an external

reference; for best performance, however, the internal reference

should be disabled when an external reference is applied,

because SW1 in Figure 27 opens on the AD7873 when the

internal reference is disabled. The on-chip reference always is

available at the V_REFpin as long as the reference is enabled. The

input impedance seen at the V_REFpin is approximately 260 Ω

when the internal reference is enabled. When it is disabled, the

input impedance seen at the V_REFpin is in the GΩ region.

Touch Screen Settling

In some applications, external capacitors could be required

across the touch screen to filter noise associated with it, for

example, noise generated by the LCD panel or backlight

circuitry. The value of these capacitors causes a settling time

requirement when the panel is touched. The settling time

typically appears as a gain error. There are several methods for

minimizing or eliminating this issue. The problem can be that

the input signal, reference, or both, have not settled to their

final value before the sampling instant of the ADC. Additionally,

the reference voltage could still be changing during the conversion

cycle. One option is to stop or slow down the DCLK for the

required touch screen settling time. This allows the input and

reference to stabilize for the acquisition time, resolving the issue

for both single-ended and differential modes.

When making touch screen measurements, conversions can be

made in differential (ratiometric) mode or single-ended mode.

DFR

If the SER/

bit is set to 1 in the control register, then a

The other option is to operate the AD7873 in differential mode

only for the touch screen, and program the AD7873 to keep

the touch screen drivers on and not go into power-down

(PD0 = PD1 = 1). Several conversions could be required,

depending on the settling time required and the AD7873 data

rate. Once the required number of conversions have been made,

the AD7873 can then be placed in a power-down state on the

last measurement. The last method is to use the 15-DCLK cycle

mode, maintaining the touch screen drivers on until it is

commanded by the processor to stop.

single-ended conversion is performed. Figure 28 shows the

configuration for a single-ended Y coordinate measurement.

The X+ input is connected to the analog-to-digital converter,

the Y+ and Y− drivers are turned on, and the voltage on X+ is

digitized. The conversion is performed with the ADC referenced

from GND to V_REF. This V_REFis either the on-chip reference or

the voltage applied at the V_REFpin externally, and is determined

by the setting of the power management Bit PD0 and Bit PD1

(see Table 7). The advantage of this mode is that the switches

that supply the external touch screen can be turned off once the

acquisition is complete, resulting in a power savings. However,

the on resistance of the Y drivers affects the input voltage that

can be acquired. The full touch screen resistance could be in the

order of 200 Ω to 900 Ω, depending on the manufacturer. Thus,

if the on resistance of the switches is approximately 6 Ω, true

full-scale and zero-scale voltages cannot be acquired, regardless

of where the pen/stylus is on the touch screen. Note that the

minimum touch screen resistance recommended for use with

Internal Reference

The AD7873 has an internal reference voltage of 2.5 V. The

internal reference is available on the V_REFpin for external use in

the system; however, it must be buffered before it is applied

elsewhere. The on-chip reference can be turned on or off with

the power-down address, PD1 = 1 (see Table 8 and Figure 27).

Typically, the reference voltage is only used in single-ended

mode for battery monitoring, temperature measurement, and

for using the auxiliary input. Optimal touch screen performance

is achieved when using the differential mode. The power-up

Rev. F | Page 15 of 28

AD7873

Data Sheet

the AD7873 is approximately 70 Ω. In this mode of operation,

therefore, some voltage is likely to be lost across the internal

switches, and it is unlikely that the internal switch resistance

will track the resistance of the touch screen over temperature

and supply, providing an additional source of error.

In the single conversion method, a diode voltage is digitized

and recorded at a fixed calibration temperature. Any subsequent

polling of the diode provides an estimate of the ambient tempera-

ture through extrapolation from the calibration temperature

diode result. This assumes a diode temperature drift of

approximately –2.1 mV/°C. This method provides a resolution

+V

CC

of approximately 0.3°C and a predicted accuracy of 3°C.

The differential conversion method is a two-point measurement.

The first measurement is performed with a fixed bias current

into a diode, and the second measurement is performed with a

fixed multiple of the bias current into the same diode. The

voltage difference in the diode readings is proportional to

absolute temperature and is given by the following formula:

Y+

X+

V

REF

REF+

IN+

ADC CORE

REF–

IN–

Y–

∆V_BE

where:

_BErepresents the diode voltage.

=

(

kT / q

)

×

(

ln N

)

GND

DFR

Figure 28. Single-Ended Reference Mode (SER/

= 1)

V

The alternative to this situation is to set the SER/

DFR

bit low.

N is the bias current multiple.

k is Boltzmann’s constant.

q is the electron charge.

Again, making a Y coordinate measurement is considered, but

now the +REF and –REF nodes of the ADC are connected

directly to the Y+ and Y– pins. This means the analog-to-digital

conversion is ratiometric. The result of the conversion is always

a percentage of the external resistance, independent of how it

could change with respect to the on resistance of the internal

switches. Figure 29 shows the configuration for a ratiometric

Y coordinate measurement.

This method provides more accurate absolute temperature

measurement of 2°C. However, the resolution is reduced to

approximately 1.6°C. Assuming a current multiple of 105

(typical for the AD7873) taking Boltzmann’s constant,

k = 1.38054 ×10^–23electrons volts/degrees Kelvin, the electron

charge q = 1.602189 × 10^–19, then T, the ambient temperature in

degrees centigrade, can be calculated as follows:

+V

CC

Y+

∆V_BE

T =

=

(

kT / q

)

×

(

ln N

)

(

∆V_BE× q

T(°C) = 2.49 × 10³× ∆V_BE/ 273 Κ

)

/

(

k × ln N

)

REF+

X+

Y–

IN+

ADC CORE

REF–

IN–

where ∆V_BEis calculated from the difference in readings from

the first conversion and second conversion.

Figure 30 shows a block diagram of the temperature

measurement mode.

GND

DFR

Figure 29. Differential Reference Mode (SER/

= 0)

TEMP0 TEMP1

The disadvantage of this mode of operation is that during both

the acquisition phase and conversion process, the external

touch screen must remain powered. This results in additional

supply current for the duration of the conversion.

105 × I

I

MUX

ADC

MEASUREMENTS

Temperature Measurement

Figure 30. Block Diagram of Temperature Measurement Circuit

Two temperature measurement options are available on the

AD7873, the single conversion method and the differential

conversion method. Both methods are based on an on-chip

diode measurement.

Rev. F | Page 1± of 28

Data Sheet

AD7873

Battery Measurement

Pressure Measurement

The AD7873 can monitor a battery voltage from 0 V to 6 V.

Figure 31 shows a block diagram of a battery voltage monitored

through the V_BATpin. The voltage to the +V_CCof the AD7873 is

maintained at the desired supply voltage via the dc-to-dc

regulator while the input to the regulator is monitored. This

voltage on V_BATis divided by 4 so that a 6 V battery voltage is

presented to the ADC as 1.5 V. To conserve power, the divider is

on only during the sampling of a voltage on V_BAT. Table 6 shows

the control bit settings required to perform a battery

measurement.

The pressure applied to the touch screen via a pen or finger

can also be measured with the AD7873 with some simple

calculations. The 8-bit resolution mode would be sufficient for

this measurement, but the following calculations are shown

with the 12-bit resolution mode. The contact resistance between

the X and Y plates is measured, providing a good indication of

the size of the depressed area and the applied pressure. The area

of the spot touched is proportional to the size of the object

touching it. The size of this resistance (R_TOUCH) can be calculated

using two different methods.

DC/DC

The first method requires the user to know the total resistance

of the X-plate tablet. Three touch screen conversions are

required, a measurement of the X-position, Z₁-position, and

Z₂-position (see Figure 32). The following equation calculates

the touch resistance:

CONVERTER

+

BATTERY

0V TO 6V

+V

CC

V

BAT

0V TO 1.5V

ADC CORE

7.5kΩ

2.5kΩ

R_TOUCH

=

(

R_XPLATE

)

×

(

X_POSITION/ 4095

)

×

[(

Z₂/ Z₁

)

/ 1

]

The second method requires that the resistance of both the

X-plate and Y-plate tablets are known. Again three touch screen

conversions are required, a measurement of the X-position,

Y-position, and Z₁-position (see Figure 32).

Figure 31. Block Diagram of Battery Measurement Circuit

The following equation also calculates the touch resistance:

R_TOUCH

=

{(

R_XPLATE/ Z₁

)

×

/

(

X_POSITION/ 4095

)

×

[

(

4096 / Z₁

)

/ 1

]}

[

R_YPLATEY_POSITION/ 4095

×

(

)

]

MEASURE X-POSITION

Y+

X+

TOUCH

+

–

X-POSITION

X–

Y–

MEASURE Z -POSITION

1

Y+

Y–

Y+

X+

TOUCH

+

–

Z -POSITION

2

Z -POSITION

1

X–

Y–

X–

MEASURE Z -POSITION

2

Figure 32. Pressure Measurement Block Diagram

Rev. F | Page 17 of 28

AD7873

Data Sheet

PEN INTERRUPT REQUEST

The pen interrupt equivalent circuitry is outlined in Figure 33.

By connecting a pull-up resistor (10 kΩ to 100 kΩ) between +V_CC

output again responds to a screen touch. The fact that

PENIRQ

returns high almost immediately after the fourth falling edge of

DCLK means the user avoids any spurious interrupts on the

microprocessor or DSP, which can occur if the interrupt request

line on the micro/DSP were unmasked during or toward the

and this CMOS logic open-drain output, the

output

PENIRQ

remains high normally. If

is enabled (see Table 8), when

PENIRQ

the touch screen connected to the AD7873 is touched by a pen

or finger, the output goes low, initiating an interrupt to

end of conversion and the

pin was still low. Once the

PENIRQ

next start bit is detected by the AD7843, the

is again disabled.

function

PENIRQ

a microprocessor. This can then instruct a control word to be

written to the AD7873 to initiate a conversion. This output can

also be enabled between conversions during power-down (see

Table 8), allowing power-up to be initiated only when the

screen is touched. The result of the first touch screen coordinate

conversion after power-up is valid, assuming any external

reference is settled to the 12-bit or 8-bit level as required.

If the control register write operation overlaps with the data

read, a start bit is always detected prior to the end of

conversion, meaning that even if the

function is

PENIRQ

enabled in the control register, it is disabled by the start bit

again before the end of the conversion is reached, so

Figure 34 assumes that the

function was enabled in

PENIRQ

the

function effectively cannot be used in this mode.

PENIRQ

However, as conversions are occurring continuously,

the function is not necessary and is therefore

the last write or that the part was just powered up so

enabled by default. Once the screen is touched, the

is

PENIRQ

redundant.

output goes low a time t_PENlater. This delay is approximately

5 µs, assuming a 10 nF touch screen capacitance, and varies

+V

CC

with the touch screen resistance actually used. Once the START

bit is detected, the pen interrupt function is disabled and

EXTERNAL

PULL-UP

100kΩ

the

cannot respond to screen touches. The

PENIRQ

Y+

+V

CC

output remains low until the fourth falling edge of DCLK after

the START bit is clocked in, at which point it returns high as

soon as possible, irrespective of the touch screen capacitance.

This does not mean that the pen interrupt function is now

enabled again because the power-down bits have not yet been

X+

TOUCH

SCREEN

PENIRQ

ENABLE

loaded to the control register. Regardless of whether

is

PENIRQ

Y–

ON

to be enabled again, the

output normally always idles

PENIRQ

is enabled again as shown in

high. Assuming the

PENIRQ

Figure 33.

Functional Block Diagram

Figure 34, then once the conversion is complete, the

PENIRQ

SCREEN

TOUCHED

HERE

PD1 = 1, PD0 = 0, PENIRQ

ENABLED AGAIN

t_PEN

NO RESPONSE TO TOUCH

PENIRQ

INTERRUPT

ROCESSOR

P

CS

1

8

1

13

16

DCLK

DIN

SER/

DFR

MODE

S

A2 A1 A0

1

0

(START)

PENIRQ

Figure 34.

Timing Diagram

Rev. F | Page 18 of 28

Data Sheet

AD7873

CONTROL REGISTER

The control word provided to the ADC via the DIN pin is

shown in Table 7. This provides the conversion start, channel

addressing, ADC conversion resolution, configuration, and

power-down of the AD7873. Table 7 provides detailed

information on the order and description of these control bits

within the control word.

converter is always the difference between the V_REFand GND

pins. See Table 6 and Figure 26 through Figure 29 for further

information.

If X-position, Y-position, and pressure touch are measured in

single-ended mode, an external reference voltage or +V_CCis

required for maximum dynamic range. The internal reference

can be used for these single-ended measurements; however, a

loss in dynamic range is incurred. If an external reference is

used, the AD7873 should also be powered from the external

reference. Because the supply current required by the device is

so low, a precision reference can be used as the supply source to

the AD7873. It might also be necessary to power the touch

screen from the reference, which can require 5 mA to 10 mA. A

REF19x voltage reference can source up to 30 mA, and, as such,

could supply both the ADC and the touch screen. Care must be

taken, however, to ensure that the input voltage applied to the

ADC does not exceed the reference voltage and therefore the

supply voltage. See the Absolute Maximum Ratings section.

Initiate START

The first bit, the S bit, must always be set to 1 to initiate the start

of the control word. The AD7873 ignores any inputs on the

DIN line until the start bit is detected.

Channel Addressing

The next three bits in the control register, A2, A1, and A0, select

the active input channel(s) of the input multiplexer (see Table 6

and Figure 26), touch screen drivers, and the reference inputs.

Mode

The MODE bit sets the resolution of the analog-to-digital

converter. With a 0 in this bit, the following conversion has

12 bits of resolution. With a 1 in this bit, the following

conversion has eight bits of resolution.

Note that the differential mode can only be used for X-position,

Y-position, and pressure touch measurements. All other

measurements require single-ended mode.

SER/

DFR

PD0 and PD1

The SER/

bit controls the reference mode, set to either

DFR

The power management options are selected by programming

the power management bits, PD0 and PD1, in the control

register. Table 8 summarizes the options available and the

internal reference voltage configurations. The internal reference

can be turned on or off independent of the analog-to-digital

converter, allowing power saving between conversions using the

power management options. On power-up, PD0 defaults to 0,

while PD1 defaults to 1.

single-ended or differential when a 1 or a 0 is written to this bit,

respectively. The differential mode is also referred to as the

ratiometric conversion mode. This mode is optimum for

X-position, Y-position, and pressure-touch measurements. The

reference is derived from the voltage at the switch drivers,

which is almost the same as the voltage to the touch screen. In

this case, a separate reference voltage is not needed because the

reference voltage to the ADC is the voltage across the touch

screen. In single-ended mode, the reference voltage to the

MSB

LSB

S

A2

A1

A0

MODE

SER/DFR

PD1

PD0

Table 7. Control Register Bit Function Description

Bit No.

Mnemonic Comment

7

S

Start Bit. The control word starts with the first high bit on DIN. A new control word can start every 15th DCLK cycle

when in the 12-bit conversion mode or every 11th DCLK cycle when in 8-bit conversion mode.

± to ꢀ

3

A2 to A0

MODE

SER/DFR

PD1, PD0

Channel Select Bits. These three address bits along with the SER/DFR bit control the setting of the multiplexer

input, switches, and reference inputs, as detailed in Table ±.

12-Bit/8-Bit Conversion Select Bit. This bit controls the resolution of the following conversion. With a 0 in this bit,

the conversion has 12-bit resolution or, with a 1 in this bit, 8-bit resolution.

Single-Ended/Differential Reference Select Bit. Together with Bit A2 to Bit A0, this bit controls the setting of the

multiplexer input, switches, and reference inputs as described in Table ±.

Power Management Bits. These two bits decode the power-down mode of the AD7873 as shown in Table 8.

2

1, 0

Rev. F | Page 19 of 28

AD7873

Data Sheet

Table 8. Power Management Options

PENIRQ

PD1 PD0

Description

0

Enabled This configuration results in immediate power-down of the on-chip reference as soon as PD1 is set to 0. The ADC

powers down only between conversions. When PD0 is set to 0, the conversion is performed first and the ADC

powers down upon completion of that conversion (or upon the rising edge of CS, if it occurs first). At the start of

the next conversion, the ADC instantly powers up to full power. This means if the device is being used in the

differential mode, or an external reference is used, there is no need for additional delays to ensure full operation

and the very first conversion is valid. The Y– switch is on while in power-down. When the device is performing

differential table conversions, the reference and reference buffer do not attempt to power up with Bit PD1 and

Bit PD0 programmed in this way.

0

1

0

Enabled This configuration results in switching the reference off immediately and the ADC on permanently. When the

device is performing differential tablet conversions, the reference and reference buffer do not attempt to power

up with Bit PD1 and Bit PD0 programmed in this way.

Enabled This configuration results in switching the reference on and powering the ADC down between conversions. The

ADC powers down only between conversions. When PD0 is set to 0, the conversion is performed first, and the

ADC powers down upon completion of the conversion (or upon the rising edge of CS if it occurs first). At the start

of the next conversion, the ADC instantly powers up to full power. There is no need for additional delays to ensure

full operation as the reference remains permanently powered up.

1

Disabled This configuration results in always keeping the device powered up. The reference and the ADC are on.

For example, if the AD7873 is operated in a 24-DCLK continuous

POWER VS. THROUGHPUT RATE

sampling mode, with a throughput rate of 10 kSPS and a DCLK

of 2 MHz, and the device is placed in the power-down mode

between conversions, (PD0, PD1 = 0, 0), that is, the ADC shuts

down between conversions but the reference remains powered

down permanently, then the current consumption is calculated

as follows. The current consumption during normal operation

with a 2 MHz DCLK is 210 µA (V_CC= 2.7 V). Assuming an

external reference is used, the power-up time of the ADC is

instantaneous, so when the part is converting, it consumes

210 µA. In this mode of operation, the part powers up on the

fourth falling edge of DCLK after the start bit is recognized. It

goes back into power-down at the end of conversion on the

20th falling edge of DCLK, meaning that the part consumes

210 µA for 16 DCLK cycles only, 8 µs during each conversion

cycle. If the throughput rate is 10 kSPS, the cycle time is 100 µs

and the average power dissipated during each cycle is

By using the power-down options on the AD7873 when not

converting, the average power consumption of the device

decreases at lower throughput rates. Figure 35 shows how, as

the throughput rate is reduced while maintaining the DCLK

frequency at 2 MHz, the device remains in its power-down state

longer and the average current consumption over time drops

accordingly.

1000

f_DCLK= 16 × f

SAMPLE

100

f_DCLK= 2MHz

10

(8/100) × (210 µA) = 16.8 µA.

V

= 2.7V

CC

= –40°C TO +85°C

T

A

1

0

20

40

60

80

100

120

THROUGHPUT (kSPS)

Figure 35. Supply Current vs. Throughput (µA)

Rev. F | Page 20 of 28

Data Sheet

AD7873

SERIAL INTERFACE

updated) and the converter enters conversion mode. At this

Figure 36 shows the typical operation of the serial interface of

the AD7873. The serial clock provides the conversion clock and

also controls the transfer of information to and from the AD7873.

One complete conversion can be achieved with 24 DCLK cycles.

point, track-and-hold goes into hold mode, the input signal is

sampled, and the BUSY output goes high (BUSY returns low on

the next falling edge of DCLK). The internal switches can also

turn off at this point if in single-ended mode, battery-monitor

mode, or temperature measurement mode.

The

signal initiates the data transfer and conversion process.

CS

The falling edge of

takes the BUSY output and the serial bus

CS

The next 12 DCLK cycles are used to perform the conversion

and to clock out the conversion result. If the conversion is

out of three-state. The first eight DCLK cycles are used to write

to the control register via the DIN pin. The control register is

updated in stages as each bit is clocked in. Once the converter

has enough information about the following conversion to set

the input multiplexer and switches appropriately, the converter

enters the acquisition mode and, if required, the internal switches

are turned on. During acquisition mode, the reference input

data is updated. After the three DCLK cycles of acquisition, the

control word is complete (the power management bits are now

ratiometric (SER/

low), the internal switches are on during

DFR

the conversion. A 13th DCLK cycle is needed to allow the

DSP/micro to clock in the LSB. Three more DCLK cycles clock

out the three trailing zeros and complete the 24 DCLK transfer.

The 24 DCLK cycles can be provided from a DSP or via three

bursts of eight clock cycles from a microcontroller.

CS

t_ACQ

1

8

1

8

1

8

DCLK

DIN

SER/

DFR

S

A2 A1 A0 MODE

IDLE

PD1 PD0

(START)

ACQUIRE

CONVERSION

IDLE

THREE-STATE

BUSY

DOUT

THREE-STATE

11

(MSB)

10

9

8

7

6

5

4

3

2

1

0

ZERO FILLED

(LSB)

1

X/Y SWITCHES

(SER/DFR HIGH)

OFF

ON

1, 2

X/Y SWITCHES

OFF

ON

(SER/DFR LOW)

NOTES

1

Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 101).

WHEN PD1, PD0 = 00, 01 OR 10, Y– WILL TURN ON AT THE END OF THE CONVERSION.

2

DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,

OR POWER-DOWN MODE IS CHANGED, OR CS IS HIGH.

Figure 36. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

CS

t₉

t₄

t₆

t₁

t₁₀

t₅

DCLK

t₈

t₇

PD0

DIN

t₂

t₁₁

t₁₂

BUSY

t₃

DOUT

DB11

DB10

Figure 37. Detail Timing Diagram

Rev. F | Page 21 of 28

AD7873

Data Sheet

16 Clocks per Cycle

using 12 DCLKs to perform the conversion and 3 DCLKs to

acquire the analog input. This effectively increases the

throughput rate of the AD7873 beyond that used for the

specifications that are tested using 16 DCLKs per cycle, and

DCLK = 2 MHz.

The control bits for the next conversion can be overlapped with

the current conversion to allow for a conversion every 16 DCLK

cycles, as shown in Figure 38. This timing diagram also allows

the possibility of communication with other serial peripherals

between each byte (eight DCLKs) transfer between the

8-Bit Conversion

processor and the converter. However, the conversion must

complete within a short enough time frame to avoid capacitive

droop effects that could distort the conversion result. It should

also be noted that the AD7873 is fully powered while other

serial communications are taking place between byte transfers.

The AD7873 can be set up to operate in an 8-bit mode rather

than a 12-bit mode by setting the MODE bit in the control

register to 1. This mode allows a faster throughput rate to be

achieved, assuming 8-bit resolution is sufficient. When using 8-bit

mode, a conversion is complete four clock cycles earlier than in

12-bit mode. This can be used with serial interfaces that provide

12 clock transfers, or two conversions can be completed with

three 8-clock transfers. The throughput rate increases by 25% as

a result of the shorter conversion cycle, but the conversion itself

can occur at a faster clock rate because the internal settling time

of the AD7873 is not as critical, because settling to eight bits is

all that is required. The clock rate can be as much as 50% faster.

The faster clock rate and fewer clock cycles combine to provide

double the conversion rate.

15 Clocks per Cycle

Figure 39 shows the fastest way to clock the AD7873. This

scheme does not work with most microcontrollers or DSPs

because they are not capable of generating a 15 clock cycle per

serial transfer. However, some DSPs allow the number of clocks

per cycle to be programmed. This method can also be used with

FPGAs (field programmable gate arrays) or ASICs (application

specific integrated circuits). As in the 16 clocks per cycle case,

the control bits for the next conversion are overlapped with the

current conversion to allow a conversion every 15 DCLK cycles

CS

1

8

1

8

1

8

1

DCLK

DIN

S

CONTROL BITS

BUSY

DOUT

11

10

9

8

7

6

5

4

3

2

1

0

11

10

9

Figure 38. Conversion Timing, 16 DCLKs per Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

CS

1

15

1

15

1

DCLK

SER/

DFR

SER/

MODE

A2 A1 A0

DFR

S

A2 A1 A0 MODE

PD1 PD0

DIN

S

5

PD1 PD0

S

A2

BUSY

DOUT

11

10

9

8

7

6

4

3

2

1

0

11 10

9

8

7

6

5

4

Figure 39. Conversion Timing, 15 DCLKs per Cycle, Maximum Throughput Rate

Rev. F | Page 22 of 28

Data Sheet

AD7873

GROUNDING AND LAYOUT

For information on grounding and layout considerations for the

AD7873, refer to Application Note AN-577, Layout and

Grounding Recommendations for Touch Screen Digitizers.

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper

to plug the via.

PCB DESIGN GUIDELINES FOR

CHIP SCALE PACKAGE

The lands on the chip scale package (CP-32) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This ensures that the solder joint size is maximized.

The user should connect the printed circuit board thermal

pad to GND.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

Rev. F | Page 23 of 28

AD7873

Data Sheet

OUTLINE DIMENSIONS

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

16

1

9

8

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

0.010 (0.25)

0.006 (0.15)

0.020 (0.51)

0.010 (0.25)

0.069 (1.75)

0.053 (1.35)

0.065 (1.65)

0.049 (1.25)

0.010 (0.25)

0.004 (0.10)

0.041 (1.04)

REF

SEATING

PLANE

8°

0°

0.025 (0.64)

BSC

0.050 (1.27)

0.016 (0.41)

COPLANARITY

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MO-137-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 40. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches and (millimeters)

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. F | Page 2ꢀ of 28

Data Sheet

AD7873

4.10

4.00 SQ

3.90

0.35

0.30

0.25

PIN 1

INDICATOR

PIN 1

INDICATOR

13

16

0.65

BSC

1

4

12

EXPOSED

PAD

2.25

2.10 SQ

1.95

9

8

5

0.70

0.60

0.50

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.

Figure 42. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-23)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD7873ARQZ

AD7873ARQZ-REEL

AD7873ARQZ-REEL7

AD7873BRQZ

AD7873BRQZ-REEL

AD7873BRQZ-REEL7

AD7873ARUZ

AD7873ARUZ-REEL

AD7873ARUZ-REEL7

AD7873ACPZ

AD7873ACPZ-REEL

AD7873ACPZ-REEL7

EVAL-AD7873EBZ

Temperature Range

–ꢀ0°C to +85°C

Package Description

1±-Lead QSOP

Linearity Error (LSB)²

Package Option³

±2

±1

±2

RQ-1±

1±-Lead QSOP

RQ-1±

1±-Lead TSSOP

1±-Lead LFCSP_WQ

Evaluation Board

RU-1±

CP-1±-23

¹Z = RoHS Compliant Part.

²Linearity error here refers to integral linearity error.

³RQ = QSOP = 0.15 inch quarter size outline package; RU = TSSOP, CP = LFCSP.

Rev. F | Page 25 of 28

AD7873

NOTES

Data Sheet

Rev. F | Page 2± of 28

Data Sheet

NOTES

AD7873

Rev. F | Page 27 of 28

AD7873

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02164-0-2/13(F)

Rev. F | Page 28 of 28


型号：	AD7873ARQZ-REEL7
厂家：	ADI
描述：	Touch Screen Digitizer 摸屏商用集成电路光电二极管
文件：	总29页 (文件大小：600K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7873ARQZ-REEL7 [ADI]

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