AD790BQ [ADI]
Fast, Precision Comparator; 快速，精密比较器
| 型号： | AD790BQ |
| 厂家： | 
ADI |
| 描述： | Fast, Precision Comparator |
| 文件： | 总8页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fast, Precision
Comparator
a
AD790
CO NNECTIO N D IAGRAMS
FEATURES
8-P in P lastic Mini-D IP (N)
and Cerdip (Q) P ackages
45 ns m ax Propagation Delay
Single +5 V or Dual ؎15 V Supply Operation
CMOS or TTL Com patible Output
250 V m ax Input Offset Voltage
500 V m ax Input Hysteresis Voltage
15 V m ax Differential Input Voltage
Onboard Latch
60 m W Pow er Dissipation
Available in 8-Pin Plastic and Herm etic Cerdip
Packages
+V
S
1
2
8
7
V
LOGIC
AD790
+IN
–IN
OUTPUT
+
–
3
4
6
5
GROUND
LATCH
–V
S
MIL-STD-883B Processing Available
Available in Tape and Reel in Accordance w ith
EIA-481A Standard
8-P in SO IC (R) P ackage
APPLICATIONS
GROUND
LATCH
1
2
3
4
OUTPUT
8
7
Zero-Crossing Detectors
Overvoltage Detectors
Pulse-Width Modulators
Precision Rectifiers
Discrete A/ D Converters
Delta-Sigm a Modulator A/ Ds
AD790
–
V
LOGIC
–V
S
6
5
+V
S
–IN
+IN
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
1. T he AD790’s combination of speed, precision, versatility
and low cost makes it suitable as a general purpose compara-
tor in analog signal processing and data acquisition systems.
T he AD790 is a fast (45 ns), precise voltage comparator, with a
number of features that make it exceptionally versatile and easy
to use. T he AD790 may operate from either a single +5 V sup-
ply or a dual ±15 V supply. In the single-supply mode, the
AD790’s inputs may be referred to ground, a feature not found
in other comparators. In the dual-supply mode it has the unique
ability of handling a maximum differential voltage of 15 V across
its input terminals, easing their interfacing to large amplitude
and dynamic signals.
2. Built-in hysteresis and a low-glitch output stage minimize the
chance of unwanted oscillations, making the AD790 easier to
use than standard open-loop comparators.
3. T he hysteresis combined with a wide input voltage range
enables the AD790 to respond to both slow, low level (e.g.,
10 mV) signals and fast, large amplitude (e.g., 10 V) signals.
T his device is fabricated using Analog Devices’ Complementary
Bipolar (CB) process–which gives the AD790’s combination of
fast response time and outstanding input voltage resolution
(1 mV max). T o preserve its speed and accuracy, the AD790
incorporates a “low glitch” output stage that does not exhibit
the large current spikes normally found in T T L or CMOS out-
put stages. Its controlled switching reduces power supply distur-
bances that can feed back to the input and cause undesired
oscillations. The AD790 also has a latching function which makes
it suitable for applications requiring synchronous operation.
4. A wide variety of supply voltages are acceptable for operation
of the AD790, ranging from single +5 V to dual +5 V/–12 V,
±5 V, or +5 V/±15 V supplies.
5. T he AD790’s power dissipation is the lowest of any compara-
tor in its speed range.
6. T he AD790’s output swing is symmetric between VLOGIC
and ground, thus providing a predictable output under a
wide range of input and output conditions.
T he AD790 is available in five performance grades. The AD790J
and the AD790K are rated over the commercial temperature
range of 0°C to +70°C. T he AD790A and AD790B are rated
over the industrial temperature range of –40°C to +85°C. T he
AD790S is rated over the military temperature range of –55°C to
+125°C and is available processed to MIL-ST D-883B, Rev. C.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD790–SPECIFICATIONS
(Operation @ +25؇C and +V = +15 V, –V = –15 V, VLOGIC = +5 V unless otherwise noted)
DUAL SUPPLY
S
S
AD 790J/A
Typ
AD 790K/B
AD 790S
Min Typ
P aram eter
Conditions
Min
Max
Min
Typ
Max
Max
Units
RESPONSE CHARACT ERIST IC
Propagation Delay, tPD
100 mV Step
5 mV Overdrive
T MIN to T MAX
40
45
45/50
40
45
45/50
40
45
60
ns
ns
OUT PUT CHARACT ERIST ICS
Output HIGH Voltage, VOH
1.6 mA Source
6.4 mA Source
T MIN to T MAX
1.6 mA Sink
6.4 mA Sink
T MIN to T MAX
4.65
4.45
4.65
4.45
4.65
4.45
4.3
4.3/4.3
4.3
4.3
4.3
4.3
V
V
V
V
V
Output LOW Voltage, VOL
0.35
0.44 0.5
0.5/0.5
0.35
0.44 0.5
0.35
0.44 0.5
0.5
0.5
INPUT CHARACT ERIST ICS
Offset Voltage1
0.2
1.0
0.05 0.25
0.2
1.0
1.5
0.65
5
mV
mV
mV
µA
T MIN to T MAX
T MIN to T MAX
Either Input
1.5
0.6
5
0.5
Hysteresis2
Bias Current
0.3
0.4
2.5
0.3
0.4
1.8
0.5
3.5
4.5
0.3
0.4
2.5
T MIN to T MAX
6.5
7
µA
Offset Current
0.04 0.25
0.02 0.15
0.04 0.25
µA
T MIN to T MAX
0.3
0.2
0.4
µA
Power Supply
Rejection Ratio DC
VS ±20%
T MIN to T MAX
80
76
90
88
88
85
100
93
80
76
90
85
dB
dB
Input Voltage Range
Differential Voltage
Common Mode
Common Mode
Rejection Ratio
VS ≤±15 V
؎VS
+VS–2 V –VS
؎VS
+VS–2 V –VS
؎VS
+VS–2 V V
V
–VS
80
–10 V<VCM
<+10 V
T MIN to T MAX
95
88
85
105
80
76
95
dB
76
90
100
88
dB
Input Impedance
20ʈ2
20ʈ2
20ʈ2
MΩʈpF
LAT CH CHARACT ERIST ICS
Latch Hold T ime, tH
Latch Setup T ime, tS
LOW Input Level, VIL
HIGH Input Level, VIH
Latch Input Current
25
5
35
10
0.8
1.6
5
25
5
35
10
0.8
1.6
3.5
5
25
5
35
10
0.8
ns
ns
V
V
µA
µA
T MIN to T MAX
T MIN to T MA X
1.6
2.3
2.3
2.3
5
8
T MIN to T MAX
7
SUPPLY CHARACT ERIST ICS
Diff Supply Voltage3
VLOGIC = 5 V
T MIN to T MAX
T MIN to T MAX
4.5
4.0
33
7
4.5
4.0
33
7
4.7
4.2
33
7
V
V
Logic Supply
Quiescent Current
+VS
–VS
VLOGIC
+VS = 15 V
–VS = –15 V
VLOGIC = 5 V
8
4
2
10
5
3.3
242
8
4
2
10
5
3.3
242
8
4
2
10
5
3.3
242
mA
mA
mA
mW
Power Dissipation
T EMPERAT URE RANGE
Rated Performance
T MIN to T MAX
0 to +70/–40 to +85
0 to +70/–40 to +85
–55 to +125
°C
NOT ES
1Defined as the average of the input voltages at the low to high and high to low transition points. Refer to Figure 14.
2Defined as half the magnitude between the input voltages at the low to high and high to low transition points. Refer to Figure 14.
3+VS must be no lower than (VLOGIC –0.5 V) in any supply operating conditions, except during power up.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final test.
Specifications subject to change without notice.
–2–
REV. B
AD790
(Operation @ +25؇C and +V = VLOGIC = +5 V, –V = 0 V unless otherwise noted)1
SINGLE SUPPLY
S
S
AD 790J/A
Typ
AD 790K/B
AD 790S
Min Typ
P aram eter
Conditions
Min
Max
Min
Typ
Max
Max
Units
RESPONSE CHARACT ERIST IC
Propagation Delay, tPD
100 mV Step
5 mV Overdrive
T MIN to T MAX
45
50
50/60
45
50
50/60
45
50
65
ns
ns
OUT PUT CHARACT ERIST ICS
Output HIGH Voltage, VOH
1.6 mA Source
6.4 mA Source
T MIN to T MAX
1.6 mA Sink
6.4 mA Sink
T MIN to T MAX
4.65
4.45
4.65
4.45
4.65
4.45
4.3
4.3
4.3
4.3
4.3
4.3
V
V
V
V
V
Output LOW Voltage, VOL
0.35
0.44 0.5
0.5
0.35
0.44 0.5
0.35
0.44 0.5
0.5
0.5
INPUT CHARACT ERIST ICS
Offset Voltage2
0.45 1.5
0.35 0.6
0.45 1.5
mV
mV
mV
µA
T MIN to T MAX
T MIN to T MAX
Either Input
2.0
0.85
2.0
Hysteresis3
Bias Current
0.3
0.5
2.7
0.75
5
7
0.3
0.5
2.0
0.65
3.5
5
0.3
0.7
2.7
1.0
5
T MIN to T MAX
8
µA
Offset Current
0.04 0.25
0.02 0.15
0.04 0.25
µA
T MIN to T MAX
0.3
0.2
0.4
µA
Power Supply
Rejection Ratio DC
4.5 V≤VS≤5.5 V
T MIN to T MAX
80
90
86
82
100
93
80
76
90
85
dB
dB
76/76 88
Input Voltage Range
Differential Voltage
Common Mode
؎VS
+VS–2 V
؎VS
+VS–2 V
؎VS
+VS–2 V V
V
0
0
0
Input Impedance
20ʈ2
20ʈ2
20ʈ2
MΩʈpF
LAT CH CHARACT ERIST ICS
Latch Hold T ime, tH
Latch Setup T ime, tS
LOW Input Level, VIL
HIGH Input Level, VIH
Latch Input Current
25
5
35
10
0.8
25
5
35
10
0.8
25
5
35
10
0.8
ns
ns
V
V
µA
µA
T MIN to T MAX
T MIN to T MAX
1.6
4.5
1.6
4.5
1.6
4.7
2.3
10
5
7
2.3
10
3.5
5
2.3
10
5
8
T MIN to T MAX
SUPPLY CHARACT ERIST ICS
Supply Voltage4
Quiescent Current
T MIN to T MAX
7
12
60
7
12
60
7
12
60
V
mA
mW
Power Dissipation
T EMPERAT URE RANGE
Rated Performance
T MIN to T MAX
0 to +70/–40 to +85
0 to +70/–40 to +85
–55 to +125
°C
NOT ES
1Pin 1 tied to Pin 8, and Pin 4 tied to Pin 6.
2Defined as the average of the input voltages at the low to high and high to low transition points. Refer to Figure 14.
3Defined as half the magnitude between the input voltages at the low to high and high to low transition points. Refer to Figure 14.
4–VS must not be connected above ground.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final test.
Specifications subject to change without notice.
REV. B
–3–
AD790
ABSO LUTE MAXIMUM RATINGS 1, 2
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
= 90°C/watt; ceramic Q-8
package: θJA = 110°C/watt, θJC = 30°C/watt. SOIC (R-8) package: θJA = 160°C
watt; θJC = 42°C/watt.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 500 mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±16.5 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range
(N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
(Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
2T hermal characteristics: plastic N-8 package: θJA
O RD ERING GUID E
Tem perature
Range
P ackage
D escription O ption
P ackage
METALIZATIO N P H O TO GRAP H
Contact factory for latest dimensions.
D imensions shown in inches and (mm).
Call factory for chip specifications.
Model
AD790JN
AD790JR
0°C to +70°C
0°C to +70°C
Plastic DIP
SOIC
N-8
SO-8
AD790JR-REEL 0°C to +70°C
AD790JR-REEL7 0°C to +70°C
Reel
SOIC
Plastic DIP
Cerdip
Cerdip
R-8
N-8
Q-8
Q-8
Q-8
Q-8
AD790KN
AD790AQ
AD790BQ
AD790SQ
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C Cerdip
AD790SQ/883B –55°C to +125°C Cerdip
AD790S Chips –55°C to +125°C Die
LATCH
5V
+
(OPTIONAL)
0.1µF
510
Ω
1
+
8
15V
+IN
–IN
2
3
LATCH
(OPTIONAL)
5
+ 5V
0.1µF
OUTPUT
7
AD790
0.1µF
6
510
Ω
4
1
8
2
3
+IN
–IN
5
OUTPUT
7
AD790
6
Figure 2. Basic Single Supply
4
Configuration (N, Q Package Pinout)
0.1µF
+15V
0.1µF
–
+5V
15V
0.1µF
Figure 1. Basic Dual Supply
Configuration (N, Q Package Pinout)
1
1k
–100mV
8
2
3
TEK
5
7904
SCOPE
7
AD790
25Ω
130Ω
0.1µF
6
4
MPS
571
–1.3V
–1.7V
0.1µF
PULSE
GENERATOR
–15V
HP2835
HP8112
50Ω
400Ω
650Ω
10kΩ
–
5V
VOLTAGE
–5mV
SOURCE
–5V
10Ω
Figure 3. Response Tim e Test Circuit (N, Q Package Pinout)
–4–
REV. B
Typical Characteristics–AD790
Figure 6. Propagation Delay vs.
Fanout (LSTTL and CMOS)
Figure 4. Propagation Delay vs.
Overdrive
Figure 5. Propagation Delay vs.
Load Capacitance
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
TEMP = +25°C
0
2
4
6
8
10
I
– mA
SINK
Figure 9. Output Low Voltage vs.
Sink Current
Figure 8. Propagation Delay vs.
Tem perature
Figure 7. Propagation Delay vs.
Source Resistance
t
H
5.0
4.9
0
INPUT
4.8
TEMP = +25°C
4.7
t
S
V
IH
4.6
4.5
LATCH
V
V
IL
4.4
4.3
t
PD
OH
OUTPUT
V
4.2
OL
0
2
4
6
8
10
I
– mA
SOURCE
t
t
= SETUP TIME
= HOLD TIME
S
Figure 11. Total Supply Current vs.
Tem perature
Figure 10. Output High Voltage vs.
Source Current
H
t
= COMPARATOR RESPONSE TIME
PD
Figure 12. Latch Tim ing
REV. B
–5–
AD790
CIRCUIT D ESCRIP TIO N
VOUT
T he AD790 possesses the overall characteristics of a standard
monolithic comparator: differential inputs, high gain and a logic
output. However, its function is implemented with an architec-
ture which offers several advantages over previous comparator
designs. Specifically, the output stage alleviates some of the limi-
tations of classic “T T L” comparators and provides a symmetric
output. A simplified representation of the AD790 circuitry is
shown in Figure 13.
VH
VH
VOH
VOL
+
IN
0
VOS
VLOGIC
VH = HYSTERESIS VOLTAGE
VOS = INPUT OFFSET VOLTAGE
+
+
IN
2
3
A1
Q1
–
VOUT
7
GND
+
IN
+
–
OUTPUT
Av
–
Figure 14. Hysteresis Definitions (N, Q Package Pinout)
IN
hysteresis range. T his built-in hysteresis allows the AD790 to
avoid oscillation when an input signal slowly crosses the ground
level.
–
+
Q2
GND
A2
SUP P LY VO LTAGE CO NNECTIO NS
GAIN STAGE
OUTPUT STAGE
T he AD790 may be operated from either single or dual supply
voltages. Internally, the VLOGIC circuitry and the analog front-
end of the AD790 are connected to separate supply pins. If dual
supplies are used, any combination of voltages in which +VS ≥
VLOGIC – 0.5 V and –VS ≤ 0 may be chosen. For single supply
operation (i.e., +VS = VLOGIC), the supply voltage can be oper-
ated between 4.5 V and 7 V. Figure 15 shows some other ex-
amples of typical supply connections possible with the AD790.
Figure 13. AD790 Block Diagram
T he output stage takes the amplified differential input signal and
converts it to a single-ended logic output. T he output swing is
defined by the pull-up PNP and the pull-down NPN. T hese pro-
duce inherent rail-to-rail output levels, compatible with CMOS
logic, as well as T T L, without the need for clamping to internal
bias levels. Furthermore, the pull-up and pull-down levels are
symmetric about the center of the supply range and are refer-
enced off the VLOGIC supply and ground. T he output stage has
nearly symmetric dynamic drive capability, yielding equal rise
and fall times into subsequent logic gates.
BYP ASSING AND GRO UND ING
Although the AD790 is designed to be stable and free from os-
cillations, it is important to properly bypass and ground the
power supplies. Ceramic 0.1 µF capacitors are recommended
and should be connected directly at the AD790’s supply pins.
T hese capacitors provide transient currents to the device during
comparator switching. T he AD790 has three supply voltage
pins, +VS, –VS and VLOGIC. It is important to have a common
ground lead on the board for the supply grounds and the GND
pin of the AD790 to provide the proper return path for the sup-
ply current.
Unlike classic T T L or CMOS output stages, the AD790 circuit
does not exhibit large current spikes due to unwanted current
flow between the output transistors. T he AD790 output stage
has a controlled switching scheme in which amplifiers A1 and
A2 drive the output transistors in a manner designed to reduce
the current flow between Q1 and Q2. T his also helps minimize
the disturbances feeding back to the input which can cause
troublesome oscillations.
LATCH O P ERATIO N
T he AD790 has a latch function for retaining input information
at the output. T he comparator decision is “latched” and the
output state is held when Pin 5 is brought low. As long as Pin 5
is kept low, the output remains in the high or low state, and
does not respond to changing inputs. Proper capture of the in-
put signal requires that the timing relationships shown in Fig-
ure 12 are followed. Pin 5 should be driven with CMOS or
T T L logic levels.
T he output high and low levels are well controlled values de-
fined by VLOGIC (+5 V), ground and the transistor equivalent
“Schottky” clamps and are compatible with T T L and CMOS
logic requirements. T he fanout of the output stage is shown in
Figure 6 for standard LST T L or HCMOS gates. Output drive
behavior vs. capacitive load is shown in Figure 5.
H YSTERESIS
T he AD790 uses internal feedback to develop hysteresis about
the input reference voltage. Figure 14 shows how the input off-
set voltage and hysteresis terms are defined. Input offset voltage
(VOS) is the difference between the center of the hysteresis
range and the ground level. T his can be either positive or nega-
tive. The hysteresis voltage (VH ) is one-half the width of the
T he output of the AD790 will respond to the input when Pin 5
is at a high logic level. When not in use, Pin 5 should be con-
nected to the positive logic supply. When using dual supplies, it
is recommended that a 510 Ω resistor be placed in series with
Pin 5 and the driving logic gate to limit input currents during
power up.
–6–
REV. B
Applying the AD790
+
+
5V
5V
10 mV reference level that is compared to the sense voltage.
T he minus supply current is proportional to absolute tempera-
ture and compensates for the change in the sense resistance
with temperature. T he width and length of the PC board trace
determine the resistance of the trace and consequently the trip
current level.
+
12V
1
0.1µF
0.1µF
0.1µF
+IN
1
510Ω
8
+IN
–IN
2
3
8
5
2
3
OUT
7
AD790
5
OUT
6
AD790
7
6
4
–IN
4
0.1µF
ILIMIT = 10 mV/RSENSE
–
15V
+VS = +12V, –VS = 0V
VLOGIC = +5V
+
5V
8
RSENSE = rho (trace length/trace width)
+VS = +5V, –VS = –15V
VLOGIC = +5V
0.1µF
rho = resistance of a unit square of trace
1
+IN
–IN
2
3
5
OUT
7
AD790
+V
S
6
4
0.1µF
L
O
A
D
–
5V
5V
1
+
0.1µF
+VS = +5V, –VS = –5V, VLOGIC = +5V
Figure 15. Typical Power Supply Connections
(N, Q Package Pinout)
510Ω
PC BOARD
TRACE
8
2
3
5
OUTPUT
Window Com par ator for O ver voltage D etection
7
AD790
6
T he wide differential input range of the AD790 makes it suit-
able for monitoring large amplitude signals. T he simple over-
voltage detection circuit shown in Figure 16 illustrates direct
connection of the input signal to the high impedance inputs of
the comparator without the need for special clamp diodes to
limit the differential input voltage across the inputs.
4
R
SENSE
2.7
Ω
≈ 10mV/100mA
+5V
0.1µF
0.1µF
+15V
1
Figure 17. Ground Referred Overload Detector Circuit
(N, Q Package Pinout)
510Ω
8
SIGN 1 = HIGH
0 = LOW
+7.5V
3
2
5
P r ecision Full-Wave Rectifier
7
AD790
T he high speed and precision of the AD790 make it suitable for
use in the wide dynamic range full-wave rectifier shown in Fig-
ure 18. T his circuit is capable of rectifying low level signals as
small as a few mV or as high as 10 V. Input resolution, propaga-
tion delay and op amp settling will ultimately limit the maximum
input frequency for a given accuracy level. T otal comparator
plus switch delay is approximately 100 ns, which limits the
maximum input frequency to 1 MHz for clean rectification.
6
4
OVERRANGE = 1
7432
–15V
0.1µF
V
IN
+15V
+5V
0.1µF
0.1µF
1
510Ω
Ω
10k
8
3
2
5
+15V
7
7
AD790
0.1µF
6
–7.5V
4
10kΩ
2
3
V
6
IN
AD711
V
20k
Ω
OUT
+15V
1
4
0.1µF
–15V
0.1µF
0.1µF
0.1µF
+5V
8
Figure 16. Overvoltage Detector
(N, Q Package Pinout)
–15V
510Ω
FET SWITCHES THE GAIN
FROM +1 TO –1
3
2
5
Single Supply Gr ound Refer r ed O ver load D etector
7
AD790
T he AD790 is useful as an overload detector for sensitive loads
that must be powered from a single supply. A simple ground
referenced overload detector is shown in Figure 16. T he com-
parator senses a voltage across a PC board trace and compares
that to a reference (trip) voltage established by the comparator’s
minus supply current through a 2.7 Ω resistor. T his sets up a
NMOS
FET
6
4
(R
< 20 )
Ω
ON
–15V
0.1µF
Figure 18. Precision Full-Wave Rectifier
(N, Q Package Pinout)
REV. B
–7–
AD790
Bipolar to CMO S/TTL
+ 5V
–
5V
It is sometimes desirable to translate a bipolar signal (e.g.,
±5 V) coming from a communications cable or another section
of the system to CMOS/T T L logic levels; such an application is
referred to as a line receiver. Previously, the interface to the bi-
polar signal required either a dual (±) power supply or a refer-
ence voltage level about which the line receiver would switch.
T he AD790 may be used in a simple circuit to provide a unique
capability: the ability to receive a bipolar signal while powered
from a single +5 V supply. Other comparators cannot perform
this task. Figure 19 shows a 1 kΩ resistor in series with the input
signal which is then clamped by a Schottky diode, holding the
input of the comparator at 0.4 V below ground. Although the
comparator is specified for a common mode range down to –VS,
(in this case ground) it is permissible to bring one of the inputs
a few hundred mV below ground. T he comparator switches
around this level and produces a CMOS/T T L compatible
swing. T he circuit will operate to switching frequencies of
20 MHz.
4.7V
0.3V
BIPOLAR
SIGNAL
INPUT
400Ω*
1
1k
Ω
8
2
3
TTL
LEVEL
OUTPUT
5
6
7
STANDARD
SCHOTTKY
DIODE
4
GND
*A RESISTOR UP TO 10kΩ MAYBE USED TO
REDUCE THE SOURCE AND SINK CURRENT OF
THE DRIVER. HOWEVER, THIS WILL SLIGHTLY
LOWER THE MAXIMUM USABLE CLOCK RATE.
Figure 19. A Bipolar to CMOS TTL Line Receiver (N, Q
Package Pinout)
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic Mini-D IP (N-8) P ackage
8-P in Cerdip (Q-8) P ackage
SO IC (SO -8) P ackage
–8–
REV. B
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