首页 |元器件品牌

AD7912AUJ-R2 [ADI]

2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs; 2通道， 2.35 V至5.25 V ， 1 MSPS ， 10位/ 12位ADC
AD7912AUJ-R2
型号： AD7912AUJ-R2
厂家： ADI    ADI
描述：

2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs
2通道， 2.35 V至5.25 V ， 1 MSPS ， 10位/ 12位ADC

转换器 模数转换器 光电二极管
文件： 总32页 (文件大小：386K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
2-Channel, 2.35 V to 5.25 V,  
1 MSPS, 10-/12-Bit ADCs  
AD7912/AD7922  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
V
DD  
Fast throughput rate: 1 MSPS  
Specified for VDD of 2.35 V to 5.25 V  
Low power:  
4.8 mW typ at 1 MSPS with 3 V supplies  
15.5mW typ at 1 MSPS with 5 V supplies  
Wide input bandwidth:  
V
V
IN0  
IN1  
10-/12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
MUX  
71 dB minimum SNR at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
SCLK  
CS  
High speed serial interface:  
AD7912/AD7922  
CONTROL LOGIC  
SPI®/QSPI™/MICROWIRE™/DSP compatible  
Standby mode: 1 µA maximum  
Daisy-chain mode  
DOUT  
DIN  
8-lead TSOT package  
GND  
8-lead MSOP package  
Figure 1.  
APPLICATIONS  
Several AD7912/AD7922 can be connected together in a daisy  
chain. The AD7912/AD7922 feature a daisy-chain mode that  
allows the user to read the conversion results from the ADCs  
contained in the chain. The AD7912/AD7922 use advanced  
design techniques to achieve very low power dissipation at high  
throughput rates. The reference for the part is taken internally  
from VDD, thereby allowing the widest dynamic input range to  
the ADC.  
Battery-powered systems:  
Personal digital assistants  
Medical instruments  
Mobile communications  
Instrumentation and control systems  
Data acquisition systems  
High speed modems  
Optical sensors  
PRODUCT HIGHLIGHTS  
GENERAL DESCRIPTION  
1. 2-channel, 1 MSPS, 10-/12-bit ADCs in TSOT package.  
2. High throughput with low power consumption.  
3. Flexible power/serial clock speed management.  
The conversion rate is determined by the serial clock. The  
parts also feature a power-down mode to maximize power  
efficiency at lower throughput rates. Average power  
consumption is reduced when the power-down mode is  
used while not converting. Current consumption is 1 µA  
maximum and 50 nA typically when in power-down mode.  
4. Daisy-chain mode.  
The AD7912/AD79221 are 10-bit and 12-bit, high speed, low  
power, 2-channel successive approximation ADCs, respectively.  
The parts operate from a single 2.35 V to 5.25 V power supply  
and feature throughput rates of up to 1 MSPS. The parts contain  
a low noise, wide bandwidth track-and-hold amplifier, which  
can handle input frequencies in excess of 6 MHz.  
The conversion process and data acquisition are controlled  
CS  
using  
and the serial clock, allowing the devices to interface  
with microprocessors or DSPs. The conversion rate is  
determined by the SCLK signal. The input signal is sampled on  
5. No pipeline delay.  
The parts feature a standard successive approximation ADC  
CS  
the falling edge of  
and the conversion is also initiated at this  
CS  
with accurate control of the sampling instant via a  
and once-off conversion control.  
input  
point. The channel to be converted is selected through the DIN  
CS  
pin, and the mode of operation is controlled by . The serial  
data stream from the DOUT pin has a channel identifier bit and  
mode identifier bit, which provide information about the  
converted channel and the current mode of operation.  
1 Protected by U.S. Patent Number 6,681,332.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
AD7912/AD7922  
TABLE OF CONTENTS  
Specifications..................................................................................... 3  
DIN Input.................................................................................... 17  
DOUT Output ............................................................................ 17  
Modes of Operation....................................................................... 18  
Normal Mode.............................................................................. 18  
Power-Down Mode.................................................................... 18  
Power-Up Time .......................................................................... 20  
Daisy-Chain Mode..................................................................... 20  
Daisy-Chain Example................................................................ 22  
Power vs. Throughput Rate........................................................... 24  
Serial Interface ................................................................................ 25  
Microprocessor Interfacing....................................................... 26  
Application Hints ........................................................................... 28  
Grounding and Layout .............................................................. 28  
Evaluating AD7912/AD7922 Performance................................. 29  
Outline Dimensions....................................................................... 30  
Ordering Guide .......................................................................... 30  
AD7912 Specifications................................................................. 3  
AD7922 Specifications................................................................. 5  
Timing Specifications .................................................................. 7  
Timing Diagrams.......................................................................... 7  
Timing Examples.......................................................................... 8  
Absolute Maximum Ratings............................................................ 9  
ESD Caution.................................................................................. 9  
Pin Configurations and Function Descriptions ......................... 10  
Terminology .................................................................................... 11  
Typical Performance Characteristics ........................................... 13  
Circuit Information........................................................................ 15  
Converter Operation.................................................................. 15  
ADC Transfer Function............................................................. 15  
Typical Connection Diagram ................................................... 16  
Analog Input ............................................................................... 16  
Digital Inputs .............................................................................. 17  
REVISION HISTORY  
Revision 0: Initial Version  
Rev. 0 | Page 2 of 32  
AD7912/AD7922  
SPECIFICATIONS  
AD7912 SPECIFICATIONS  
Temperature range for A Grade from −40°C to +85°C.  
VDD = 2.35 V to 5.25 V, fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted.  
Table 1.  
Parameter  
A Grade1  
Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE  
Signal-to- Noise + Distortion (SINAD)2  
Total Harmonic Distortion (THD)2  
Peak Harmonic or Spurious Noise (SFDR)2  
Intermodulation Distortion (IMD)2  
Second-Order Terms  
fIN = 100 kHz sine wave  
61  
−71  
−72  
dB min  
dB max  
dB max  
−82  
−83  
10  
dB typ  
dB typ  
ns typ  
fa = 100.73 kHz, fb = 90.7 kHz  
fa = 100.73 kHz, fb = 90.7 kHz  
Third-Order Terms  
Aperture Delay  
Aperture Jitter  
30  
90  
8.5  
1.5  
ps typ  
Channel-to-Channel Isolation2  
dB typ  
MHz typ  
MHz typ  
Full Power Bandwidth  
@ 3 dB  
@ 0.1 dB  
DC ACCURACY  
Resolution  
10  
Bits  
Integral Nonlinearity2  
Differential Nonlinearity2  
Offset Error2  
Offset Error Match2, 3  
Gain Error2  
Gain Error Match2, 3  
Total Unadjusted Error (TUE)2  
ANALOG INPUT  
0.5  
0.5  
0.5  
0.3  
0.5  
0.3  
0.5  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
Guaranteed no missed codes to 10 bits  
Input Voltage Ranges  
DC Leakage Current  
Input Capacitance  
LOGIC INPUTS  
0 to VDD  
0.3  
20  
V
µA max  
pF typ  
Input High Voltage, VINH  
0.7 (VDD)  
2
V min  
V min  
2.35 V ≤ VDD ≤ 2.7 V  
2.7 V < VDD ≤ 5.25 V  
VDD = 2.35 V  
2.35 V < VDD ≤ 2.7 V  
2.7 V < VDD ≤ 5.25 V  
Typically 8 nA, VIN = 0 V or VDD  
Input Low Voltage, VINL  
0.3  
0.2 (VDD)  
0.8  
0.3  
0.3  
0.3  
5
V max  
V max  
V max  
µA max  
µA max  
µA max  
pF max  
Input Current, IIN, SCLK Pin  
CS  
Input Current, IIN, Pin  
Input Current, IIN, DIN Pin  
3
Input Capacitance, CIN  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating-State Leakage Current  
Floating-State Output Capacitance3  
Output Coding  
VDD − 0.2  
V min  
ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V  
ISINK = 200 µA  
0.2  
0.3  
5
V max  
µA max  
pF max  
Straight (natural) binary  
Rev. 0 | Page 3 of 32  
 
 
 
AD7912/AD7922  
Parameter  
A Grade1  
Unit  
Test Conditions/Comments  
CONVERSION RATE  
Conversion Time  
Track-and-Hold Acquisition Time2  
Throughput Rate  
POWER REQUIREMENTS  
VDD  
777  
290  
1
ns max  
ns max  
MSPS max  
14 SCLK cycles with SCLK at 18 MHz  
2.35/5.25  
V min/max  
IDD  
Digital I/Ps = 0 V or VDD  
Normal Mode (Static)  
3
1.5  
4
2
1
mA typ  
mA typ  
mA max  
mA max  
µA max  
mA typ  
mA typ  
VDD = 4.75 V to 5.25 V, SCLK on or off  
VDD = 2.35 V to 3.6 V, SCLK on or off  
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS  
VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS  
SCLK on or off, typically 50 nA  
Normal Mode (Operational)  
Full Power-Down Mode (Static)  
Full Power-Down Mode (Dynamic)  
0.48  
0.26  
VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS  
VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS  
Power Dissipation4  
Normal Mode (Operational)  
20  
6
5
mW max  
mW max  
µW max  
VDD = 5 V, fSAMPLE = 1 MSPS  
VDD = 3 V, fSAMPLE = 1 MSPS  
VDD = 5 V  
Full Power-Down  
1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum.  
2 See the Terminology section.  
3 Guaranteed by characterization.  
4 See the Power vs. Throughput Rate section.  
Rev. 0 | Page 4 of 32  
AD7912/AD7922  
AD7922 SPECIFICATIONS  
Temperature range for A Grade from −40°C to +85°C.  
VDD = 2.35 V to 5.25 V, fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted.  
Table 2.  
Parameter  
A Grade1  
Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE  
Signal-to-Noise + Distortion (SINAD)2  
fIN = 100 kHz sine wave  
70  
72  
71  
72.5  
−81  
−84  
dB min  
dB typ  
dB min  
dB typ  
dB typ  
dB typ  
Signal-to-Noise Ratio (SNR)2  
Total Harmonic Distortion (THD)2  
Peak Harmonic or Spurious Noise (SFDR)2  
Intermodulation Distortion (IMD)2  
Second-Order Terms  
Third-Order Terms  
Aperture Delay  
−84  
−86  
10  
dB typ  
dB typ  
ns typ  
fa = 100.73 kHz, fb = 90.72 kHz  
fa = 100.73 kHz, fb = 90.72 kHz  
Aperture Jitter  
30  
90  
8.5  
1.5  
ps typ  
Channel-to-Channel Isolation2  
dB typ  
MHz typ  
MHz typ  
Full Power Bandwidth  
@ 3 dB  
@ 0.1dB  
DC ACCURACY  
Resolution  
12  
1.5  
0.7  
Bits  
LSB max  
LSB typ  
Integral Nonlinearity2  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
Guaranteed no missed codes to 12 bits  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
VDD = 2.35 V to 3.6V  
VDD = 4.75 V to 5.25V  
Differential Nonlinearity2  
−0.9/+1.5  
−0.7/+1.2  
1
LSB max  
LSB typ  
LSB max  
LSB typ  
LSB max  
LSB typ  
LSB max  
LSB typ  
LSB max  
LSB typ  
LSB max  
LSB typ  
Offset Error2  
0.1  
0.5  
0.02  
2
0.5  
1
0.2  
1.5  
0.5  
Offset Error Match2, 3  
Gain Error2  
Gain Error Match2, 3  
Total Unadjusted Error (TUE)2  
ANALOG INPUT  
Input Voltage Ranges  
DC Leakage Current  
Input Capacitance  
LOGIC INPUTS  
0 to VDD  
0.3  
20  
V
µA max  
pF typ  
Input High Voltage, VINH  
0.7 (VDD)  
2
V min  
V min  
2.35 V ≤ VDD ≤ 2.7 V  
2.7 V < VDD ≤ 5.25 V  
VDD = 2.35 V  
2.35 V < VDD ≤ 2.7 V  
2.7 V < VDD ≤ 5.25 V  
Typically 8 nA, VIN = 0 V or VDD  
Input Low Voltage, VINL  
0.3  
0.2 (VDD)  
0.8  
0.3  
0.3  
0.3  
5
V max  
V max  
V max  
µA max  
µA max  
µA max  
pF max  
Input Current, IIN, SCLK Pin  
CS  
Input Current, IIN, Pin  
Input Current, IIN, DIN Pin  
3
Input Capacitance, CIN  
Rev. 0 | Page 5 of 32  
 
 
AD7912/AD7922  
Parameter  
A Grade1  
Unit  
Test Conditions/Comments  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating-State Leakage Current  
Floating-State Output Capacitance3  
Output Coding  
VDD − 0.2  
V min  
ISOURCE = 200 µA; VDD = 2.35 V to 5.25 V  
ISINK = 200 µA  
0.2  
0.3  
5
V max  
µA max  
pF max  
Straight (natural) binary  
CONVERSION RATE  
Conversion Time  
888  
290  
1
ns max  
ns max  
MSPS max  
16 SCLK cycles with SCLK at 18 MHz  
See the Serial Interface section  
Track-and-Hold Acquisition Time2  
Throughput Rate  
POWER REQUIREMENTS  
VDD  
2.35/5.25  
V min/max  
IDD  
Digital I/Ps = 0 V or VDD  
Normal Mode (Static)  
3
1.5  
4
2
1
mA typ  
mA typ  
mA max  
mA max  
µA max  
mA typ  
mA typ  
VDD = 4.75 V to 5.25 V, SCLK on or off  
VDD = 2.35 V to 3.6 V, SCLK on or off  
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS  
VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS  
SCLK on or off, typically 50 nA  
Normal Mode (Operational)  
Full Power-Down Mode (Static)  
Full Power-Down Mode (Dynamic)  
0.5  
0.28  
VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS  
VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS  
Power Dissipation4  
Normal Mode (Operational)  
20  
6
5
mW max  
mW max  
µW max  
µW max  
VDD = 5 V, fSAMPLE = 1 MSPS  
VDD = 3 V, fSAMPLE = 1 MSPS  
VDD = 5 V  
Full Power-Down  
3
VDD = 3 V  
1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum.  
2 See the Terminology section.  
3 Guaranteed by characterization.  
4 See the Power vs. Throughput Rate section.  
Rev. 0 | Page 6 of 32  
AD7912/AD7922  
TIMING SPECIFICATIONS  
Guaranteed by characterization.  
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter  
Limit at TMIN  
TMAX  
,
Unit  
Description  
fSCLK  
10  
18  
kHz min2  
MHz max  
1
tCONVERT  
16 × tSCLK  
14 × tSCLK  
AD7922  
AD7912  
tQUIET  
t1  
30  
15  
ns min  
ns min  
ns min  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns min  
µs max  
Minimum quiet time required between bus relinquish and start of next conversion  
Minimum CS pulse width  
t2  
10  
CS to SCLK setup time  
3
t3  
30  
Delay from CS until DOUT three-state is disabled  
DOUT access time after SCLK falling edge  
SCLK low pulse width  
SCLK high pulse width  
SCLK to DOUT valid hold time  
DIN setup time prior to SCLK falling edge  
DIN hold time after SCLK falling edge  
SCLK falling edge to DOUT three-state  
SCLK falling edge to DOUT three-state  
Power-up time from full power-down  
3
t4  
45  
0.4 tSCLK  
0.4 tSCLK  
10  
5
t5  
t6  
t7  
4
t8  
t9  
t10  
6
5
30  
10  
1
6
tPOWER-UP  
1 Mark/space ratio for SCLK input is 40/60 to 60/40.  
2 Minimum fSCLK at which specifications are guaranteed.  
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage.  
4 Measured with a 50 pF load capacitor.  
5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated  
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish  
time of the part and is independent of the bus loading.  
6 See the Power-Up Time section.  
TIMING DIAGRAMS  
t7  
200µA  
I
OL  
SCLK  
DOUT  
TO OUTPUT  
PIN  
1.6V  
C
50pF  
L
V
IH  
V
IL  
200µA  
I
OH  
Figure 2. Load Circuit for Digital Output Timing Specifications  
Figure 4. Hold Time after SCLK Falling Edge  
t10  
t4  
SCLK  
SCLK  
DOUT  
V
V
IH  
1.6V  
DOUT  
IL  
Figure 3. Access Time after SCLK Falling Edge  
Figure 5. SCLK Falling Edge to DOUT Three-State  
Rev. 0 | Page 7 of 32  
 
 
 
 
 
 
 
AD7912/AD7922  
Timing Example 2  
TIMING EXAMPLES  
The AD7922 can also operate with slower clock frequencies. As  
shown in Figure 7, when fSCLK = 5 MHz and the throughput rate  
is 315 kSPS, the cycle time is  
Figure 6 and Figure 7 show some of the timing parameters from  
the Timing Specifications section.  
Timing Example 1  
t2 + 12.5(1/fSCLK) + tACQ = 3.17 µs  
As shown in Figure 7, when fSCLK = 18 MHz and the throughput  
is 1 MSPS, the cycle time is  
With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the  
requirement of 290 ns for tACQ  
.
t2 + 12.5(1/fSCLK) + tACQ = 1 µs  
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where  
With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the  
t
10 = 30 ns maximum. This allows a value of 134 ns for tQUIET  
,
requirement of 290 ns for tACQ  
.
satisfying the minimum requirement of 30 ns.  
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where  
In this example, as with other slower clock values, the signal  
might already be acquired before the conversion is complete,  
but it is still necessary to leave 30 ns minimum tQUIET between  
conversions. In this example, the signal should be fully acquired  
at approximately point C in Figure 7.  
t
10 = 30 ns maximum. This allows a value of 126 ns for tQUIET  
,
satisfying the minimum requirement of 30 ns.  
t1  
CS  
tCONVERT  
t2  
t6  
B
1
2
3
4
5
13  
14  
t5  
15  
16  
SCLK  
t7  
t10  
t4  
t3  
tQUIET  
Z
ZERO  
CHN  
t8  
MOD  
DB11  
DB10  
DB2  
DB1  
DB0  
DOUT  
DIN  
t9  
THREE-STATE  
X
THREE-STATE  
X
CHN  
STY  
X
X
X
X
X
Figure 6. AD7922 Serial Interface Timing Diagram  
CS  
tCONVERT  
t2  
B
C
SCLK  
1
2
3
4
5
13  
14  
15  
16  
t10  
tQUIET  
12.5(1/f  
)
tACQUISITION  
SCLK  
1/THROUGHPUT  
Figure 7. Serial Interface Timing Example  
Rev. 0 | Page 8 of 32  
 
 
AD7912/AD7922  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 4.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device at these or  
any other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
Rating  
VDD to GND  
−0.3 V to +7 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to +7 V  
−0.3 V to VDD + 0.3 V  
10 mA  
Analog Input Voltage to GND  
Digital Input Voltage to GND  
Digital Output Voltage to GND  
Input Current to Any Pin except Supplies1  
Operating Temperature Range  
Commercial (A Grade)  
Storage Temperature Range  
Junction Temperature  
TSOT Package  
−40°C to +85°C  
−65°C to +150°C  
150°C  
θJA Thermal Impedance  
MSOP Package  
207°C/W  
θJA Thermal Impedance  
θJC Thermal Impedance  
Lead Temperature Soldering  
Reflow (10 s to 30 s)  
205.9°C/W  
43.74°C/W  
235 (0/+5)°C  
1.5 kV  
ESD  
1 Transient currents of up to 100 mA do not cause SCR latch-up.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on  
the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. 0 | Page 9 of 32  
 
AD7912/AD7922  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
8-LEAD MSOP  
8-LEAD TSOT  
DOUT  
CS  
1
2
3
4
8
7
6
5
V
DIN  
SCLK  
CS  
1
2
3
4
8
7
6
5
V
V
DD  
IN1  
IN0  
AD7912/  
AD7922  
TOP VIEW  
(Not to Scale)  
AD7912/  
AD7922  
TOP VIEW  
(Not to Scale)  
GND  
SCLK  
DIN  
V
V
GND  
IN0  
IN1  
DOUT  
V
DD  
Figure 8. 8-Lead MSOP Pin Configuration  
Figure 9. 8-Lead TSOT Pin Configuration  
Table 5. Pin Function Descriptions  
MSOP  
Pin No.  
TSOT  
Pin No.  
Mnemonic Function  
1
4
DOUT  
Data Out. Logic output. The conversion result from the AD7912/AD7922 is provided on this output as  
a serial data stream. The bits are clocked out on the falling edge of the SCLK signal.  
For the AD7922, the data stream consists of two leading zeros, the channel identifier bit that identifies  
which channel the conversion result corresponds to, followed by the mode bit that indicates the  
current mode of operation, followed by the 12 bits of conversion data with MSB first.  
For the AD7912, the data stream consists of two leading zeros, the channel identifier bit that identifies  
which channel the conversion result corresponds to, followed by the mode bit that indicates the  
current mode of operation, followed by the 10 bits of conversion data with MSB first and two trailing  
zeros.  
2
3
CS  
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on  
the AD7912/AD7922 and framing the serial data transfer.  
3
2
SCLK  
DIN  
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock  
input is also used as the clock source for the AD7912/AD7922’s conversion process.  
Data In. Logic input. The channel to be converted is provided on this input and is clocked into an  
internal register on the falling edge of SCLK.  
4
1
6, 5  
7, 8  
VIN0, VIN1  
Analog Inputs. These two single-ended analog input channels are multiplexed into the on-chip  
track-and-hold amplifier. The analog input channel to be converted is selected by writing to the third  
MSB on the DIN pin. The input range is 0 to VDD.  
7
8
6
5
GND  
VDD  
Analog Ground. Ground reference point for all circuitry on the AD7912/AD7922. All analog input  
signals should be referred to this GND voltage.  
Power Supply Input. The VDD range for the AD7912/AD7922 is from 2.35 V to 5.25 V.  
Rev. 0 | Page 10 of 32  
AD7912/AD7922  
TERMINOLOGY  
Integral Nonlinearity  
Signal-to-Noise + Distortion Ratio (SINAD)  
The maximum deviation from a straight line passing through  
the endpoints of the ADC transfer function. For the AD7912/  
AD7922, the endpoints of the transfer function are zero scale, a  
point 1 LSB below the first code transition, and full scale, a  
point 1 LSB above the last code transition.  
The measured ratio of signal-to-noise and distortion at the  
output of the A/D converter. The signal is the rms value of the  
sine wave, and noise is the rms sum of all nonfundamental  
signals up to half the sampling frequency (fs/2), including  
harmonics but excluding dc.  
Differential Nonlinearity  
Signal-to-Noise Ratio (SNR)  
The difference between the measured and the ideal 1 LSB  
change between any two adjacent codes in the ADC.  
The measured ratio of signal to noise at the output to the A/D  
converter. The signal is the rms value of the sine wave input.  
Noise is the rms quantization error within the Nyquist  
bandwidth (fs/2). The rms value of a sine wave is one-half its  
peak-to-peak value divided by √2, and the rms value for the  
quantization noise is q/√12. The ratio is dependent on the  
number of quantization levels in the digitization process; the  
more levels, the smaller the quantization noise. For an ideal  
N-bit converter, the SNR is defined as  
Offset Error  
The deviation of the first code transition (00…000) to  
(00… 001) from the ideal, that is, AGND + 1 LSB.  
Offset Error Match  
The difference in offset error between any two channels.  
SNR = 6.02 N + 1.76 dB  
Gain Error  
Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit  
converter, SNR is 62 dB.  
The deviation of the last code transition (111…110) to  
(111…111) from the ideal, that is, VDD − 1 LSB after the offset  
error has been adjusted out.  
However, various error sources in the ADC cause the measured  
SNR to be less than the theoretical value. These errors occur due  
to integral and differential nonlinearities, internal ac noise  
sources, and so on.  
Gain Error Match  
The difference in gain error between any two channels.  
Total Unadjusted Error  
Total Harmonic Distortion (THD)  
The ratio of the rms sum of harmonics to the fundamental,  
which is defined as  
A comprehensive specification that includes gain error, linearity  
error, and offset error.  
2
2
2
2
2
Channel-to-Channel Isolation  
V2 +V3 +V4 +V5 +V6  
THD (dB) = 20 log  
V1  
A measure of the level of crosstalk between channels. It is  
measured by applying a full-scale sine wave signal of 20 kHz to  
500 kHz to the nonselected input channel and determining how  
much that signal is attenuated in the selected channel with a  
10 kHz signal. The figure is given worst case across both  
channels for the AD7912/AD7922.  
where:  
V1 is the rms amplitude of the fundamental.  
V2, V3, V4, V5, and V6 are the rms amplitudes of the second  
through the sixth harmonics.  
Track-and-Hold Acquisition Time  
Peak Harmonic or Spurious Noise  
The time required for the output of the track-and-hold  
amplifier to reach its final value within 1 LSB after the end of  
conversion. The track-and-hold amplifier returns to track mode  
at the end of conversion. See the Serial Interface section for  
more details.  
The ratio of the rms value of the next largest component in the  
ADC output spectrum (up to fs /2 and excluding dc) to the rms  
value of the fundamental. Normally, the value of this specifica-  
tion is determined by the largest harmonic in the spectrum, but  
for ADCs where the harmonics are buried in the noise floor, it is  
a noise peak.  
Rev. 0 | Page 11 of 32  
AD7912/AD7922  
Intermodulation Distortion  
The AD7912/AD7922 are tested using the CCIF standard,  
where two input frequencies are used (see fa and fb in the  
Specifications section). In this case, the second-order terms are  
usually distanced in frequency from the original sine waves,  
while the third-order terms are usually at a frequency close to  
the input frequencies. As a result, the second-order and third-  
order terms are specified separately. The calculation of the  
intermodulation distortion is as in the THD specification,  
where it is defined as the ratio of the rms sum of the individual  
distortion products to the rms amplitude of the sum of the  
fundamentals expressed in dB.  
With inputs consisting of sine waves at two frequencies, fa and  
fb, any active device with nonlinearities creates distortion  
products at sum and difference frequencies of mfa nfb, where  
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are  
those for which neither m nor n is equal to zero. For example,  
the second-order terms include (fa + fb) and (fa − fb), while the  
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and  
(fa − 2fb).  
Rev. 0 | Page 12 of 32  
AD7912/AD7922  
TYPICAL PERFORMANCE CHARACTERISTICS  
Figure 10 and Figure 11 show typical FFT plots for the AD7922  
and AD7912, respectively, at a 1 MSPS sample rate and 100 kHz  
input frequency.  
Figure 14 and Figure 15 show INL and DNL performance for  
the AD7922.  
Figure 16 shows a graph of the THD versus the analog input  
frequency for different source impedances when using a supply  
voltage of 3.6 V and a sampling rate of 1 MSPS. See the Analog  
Input section.  
Figure 12 shows the SINAD performance versus the input  
frequency for various supply voltages while sampling at 1 MSPS  
with a SCLK frequency of 18 MHz for the AD7922.  
Figure 13 shows the SNR performance versus the input fre-  
quency for various supply voltages while sampling at 1 MSPS  
with an SCLK frequency of 18 MHz for the AD7922.  
Figure 17 shows a graph of the THD versus the analog input  
frequency for various supply voltages while sampling at 1 MSPS  
with an SCLK frequency of 18 MHz.  
Figure 18 shows the shutdown current versus the voltage supply  
for different operating temperatures.  
5
–67  
8192 POINT FFT  
V
= 2.35V  
DD  
V
= 2.7V  
DD  
F
F
= 1MSPS  
–68  
–69  
–70  
–71  
–72  
–73  
–74  
SAMP  
= 100kHz  
–15  
–35  
IN  
V
= 4.75V  
DD  
SNR = 73.1dB  
SINAD = 72.55dB  
THD = –81.78dB  
SFDR = –83.03dB  
V
= 5.25V  
DD  
–55  
–75  
V
= 2.7V  
DD  
–95  
V
= 3.6V  
DD  
–115  
0
50  
100 150 200 250 300 350 400 450 500  
FREQUENCY (kHz)  
10  
100  
FREQUENCY (kHz)  
1000  
Figure 10. AD7922 Dynamic Performance at 1 MSPS  
Figure 12. AD7922 SINAD vs. Input Frequency at 1 MSPS  
–71.6  
–71.8  
–72.0  
–72.2  
–72.4  
–72.6  
–72.8  
–73.0  
–73.2  
–73.4  
–73.6  
8192 POINT FFT  
V
= 2.35V  
DD  
–10  
–30  
V
= 2.7V  
DD  
F
F
= 1MSPS  
SAMP  
= 100kHz  
IN  
SNR = 61.88dB  
SINAD = 61.83dB  
THD = –81.12dB  
SFDR = –84.92dB  
V
= 5.25V  
DD  
–50  
–70  
V
= 4.75V  
DD  
V
= 3.6V  
DD  
–90  
V
= 2.7V  
DD  
–110  
0
50  
100 150 200 250 300 350 400 450 500  
FREQUENCY (kHz)  
10  
100  
FREQUENCY (kHz)  
1000  
Figure 11. AD7912 Dynamic Performance at 1 MSPS  
Figure 13. AD7922 SNR vs. Input Frequency at 1 MSPS  
Rev. 0 | Page 13 of 32  
 
 
 
 
AD7912/AD7922  
1.0  
0.8  
–68  
–70  
–72  
–74  
–76  
–78  
–80  
–82  
–84  
–86  
–88  
V
F
= 2.7V  
DD  
= 1MSPS  
SAMP  
V
= 4.75V  
TEMPERATURE = 25°C  
DD  
0.6  
V
= 2.35V  
DD  
0.4  
V
= 2.7V  
DD  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
V
= 3.6V  
DD  
V
= 5.25V  
DD  
0
512  
1024  
1536  
2048  
2560  
3072  
3584  
4096  
10  
100  
FREQUENCY (kHz)  
1000  
CODE  
Figure 14. AD7922 INL Performance  
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages  
1.0  
0.8  
180  
160  
140  
V
F
= 2.7V  
= 1MSPS  
DD  
SAMP  
TEMPERATURE = 25  
°
C
0.6  
TEMP = +85°C  
0.4  
120  
0.2  
100  
80  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
60  
40  
TEMP = +25°C  
20  
TEMP = –40°C  
0
0
512  
1024  
1536  
2048  
2560  
3072  
3584  
4096  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
CODE  
SUPPLY VOLTAGE (V)  
Figure 18. Shutdown Current vs. Supply Voltage  
Figure 15. AD7922 DNL Performance  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
V
= 3.6V  
DD  
R
= 1kΩ  
IN  
R
= 100Ω  
IN  
R
= 500Ω  
IN  
R
= 50Ω  
IN  
R
= 10Ω  
IN  
R
= 0Ω  
IN  
10  
100  
1000  
FREQUENCY (kHz)  
Figure 16. THD vs. Analog Input Frequency for Various Source Impedances  
Rev. 0 | Page 14 of 32  
AD7912/AD7922  
CIRCUIT INFORMATION  
The AD7912/AD7922 are fast, 2-channel, 10-/12-bit, single  
supply, analog-to-digital converters (ADCs), respectively. The  
parts can be operated from a 2.35 V to 5.25 V supply. When  
operated from either a 5 V supply or a 3 V supply, the  
AD7912/AD7922 are capable of throughput rates of 1 MSPS  
when provided with an 18 MHz clock.  
When the ADC starts a conversion (see Figure 20), SW2 opens  
and SW1 moves to Position B, causing the comparator to  
become unbalanced. The control logic and the charge redistri-  
bution DAC are used to add and subtract fixed amounts of  
charge from the sampling capacitor to bring the comparator  
back into a balanced condition. When the comparator is  
rebalanced, the conversion is complete. The control logic  
generates the ADC output code. Figure 21 shows the ADC  
transfer function.  
The AD7912/AD7922 provide the user with an on-chip track-  
and-hold, an ADC, and a serial interface, all housed in a tiny  
8-lead TSOT package or 8-lead MSOP package, which offer the  
user considerable space-saving advantages over alternative  
solutions. The serial clock input accesses data from the parts,  
controls the transfer of data written to the ADC, and provides  
the clock source for the successive approximation ADC. The  
analog input range is 0 to VDD. An external reference is not  
required for the ADC, and neither is there a reference on-chip.  
The reference for the AD7912/AD7922 is derived from the  
power supply and, therefore, gives the widest dynamic input  
range.  
CHARGE  
REDISTRIBUTION  
DAC  
SAMPLING  
CAPACITOR  
A
V
V
IN0  
IN1  
CONTROL  
LOGIC  
SW2  
SW1  
CONVERSION  
PHASE  
B
COMPARATOR  
V
/2  
DD  
AGND  
Figure 20. ADC Conversion Phase  
The AD7912/AD7922 feature a power-down option that allows  
power saving between conversions. The power-down feature is  
implemented across the standard serial interface as described in  
the Modes of Operation section. The AD7912/AD7922 can also  
be used in daisy-chain mode when several AD7912/AD7922 are  
connected in a daisy chain. This mode of operation is selected  
ADC TRANSFER FUNCTION  
The output coding of the AD7912/AD7922 is straight binary.  
The designed code transitions occur at the successive integer  
LSB values, that is, 1 LSB, 2 LSBs, and so on. The LSB size is  
V
DD/4096 for the AD7922 and VDD/1024 for the AD7912. The  
CS  
by controlling the logic state of the  
signal. The fourth MSB  
ideal transfer characteristic for the AD7912/AD7922 is shown  
on the DOUT pin indicates if the ADC is in normal mode or  
daisy-chain mode.  
in Figure 21.  
CONVERTER OPERATION  
111...111  
111...110  
The AD7912/AD7922 are 10-/12-bit successive approximation  
ADCs based around a charge redistribution DAC. Figure 19 and  
Figure 20 show simplified schematics of the ADC. Figure 19  
shows the ADC during its acquisition phase. SW2 is closed and  
SW1 is in Position A, the comparator is held in a balanced  
condition, and the sampling capacitor acquires the signal on the  
selected VIN channel.  
111...000  
011...111  
1LSB = V  
1LSB = V  
/4096 (AD7922)  
/1024 (AD7912)  
REF  
REF  
000...010  
000...001  
000...000  
1LSB  
+V – 1LSB  
DD  
0V  
ANALOG INPUT  
CHARGE  
REDISTRIBUTION  
DAC  
Figure 21. AD7912/AD7922 Transfer Characteristic  
SAMPLING  
CAPACITOR  
A
V
V
IN0  
CONTROL  
LOGIC  
SW2  
SW1  
ACQUISITION  
PHASE  
IN1  
B
COMPARATOR  
V
/2  
DD  
AGND  
Figure 19. ADC Acquisition Phase  
Rev. 0 | Page 15 of 32  
 
 
 
AD7912/AD7922  
TYPICAL CONNECTION DIAGRAM  
Figure 22 shows a typical connection diagram for the AD7912/  
AD7922. VREF is taken internally from VDD and as such VDD  
should be well decoupled. This provides an analog input range  
of 0 V to VDD. The conversion result is output in a 16-bit word  
with two leading zeros, followed by the channel identifier bit  
that identifies the channel converted, followed by the mode bit  
that indicates the current mode of operation, and by the MSB of  
the 12-bit or 10-bit result. For the AD7912, the 10-bit result is  
followed by two trailing zeros. See the Serial Interface section.  
Table 6 provides some typical performance data with various  
references used as a VDD source and a 50 kHz input tone under  
the same setup conditions.  
Table 6. AD7922 Performance for Various Voltage  
References IC  
Reference Tied to VDD  
AD780 at 3 V  
REF193  
ADR433  
AD780 at 2.5 V  
REF192  
AD7922 SNR Performance (dB)  
−73  
−72.42  
−72.9  
−72.86  
−72.27  
−72.75  
Alternatively, because the supply current required by the  
AD7912/AD7922 is so low, a precision reference can be used as  
the supply source to the AD7912/AD7922. A REF19x voltage  
reference (REF195 for 5 V or REF193 for 3 V) can be used to  
supply the required voltage to the ADC (see Figure 22). This  
configuration is especially useful, if the power supply is quite  
noisy or if the system supply voltages are at some value other  
than 5 V or 3 V (for example, 15 V). The REF19x outputs a  
steady voltage to the AD7912/AD7922. If the low dropout  
REF193 is used, the current it needs to supply to the AD7912/  
AD7922 is typically1.5 mA. When the ADC is converting at a  
rate of 1 MSPS, the REF193 needs to supply a maximum of  
2 mA to the AD7912/AD7922. The load regulation of the  
REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which  
results in an error of 20 ppm (60 µV) for the 2 mA drawn from  
it. This corresponds to a 0.082 LSB error for the AD7922 with  
ADR421  
ANALOG INPUT  
Figure 23 shows an equivalent circuit of the analog input  
structure of the AD7912/AD7922. The two diodes, D1 and D2,  
provide ESD protection for the analog input. Care must be  
taken to ensure that the analog input signal never exceeds the  
supply rails by more than 300 mV, because this would cause  
these diodes to become forward biased and start conducting  
current into the substrate. The maximum current these diodes  
can conduct without causing irreversible damage to the part is  
10 mA.  
V
DD  
VDD = 3 V from the REF193 and a 0.061 LSB error for the  
C2  
20pF  
AD7912.  
D1  
R1  
V
IN  
For applications where power consumption is a concern, the  
power-down mode of the ADC and the sleep mode of the  
REF19x reference should be used to improve power perform-  
ance. See the Modes of Operation section.  
C1  
D2  
6pF  
Figure 23. Equivalent Analog Input Circuit  
3V  
5V  
REF193  
SUPPLY  
The capacitor C1 in Figure 23 is typically about 6 pF and can  
primarily be attributed to pin capacitance. The resistor R1 is  
a lumped component made up of the on resistance of the  
track-and-hold switch and also includes the on resistance of  
the input multiplexer. This resistor is typically about 100 Ω.  
The capacitor C2 is the ADC sampling capacitor and has a  
capacitance of 20 pF typically.  
1µF  
1.5mA  
0.1  
µF  
10µF  
0.1  
µF  
TANT  
680nF  
V
V
DD  
0V TO V  
INPUT  
DD  
IN0  
IN1  
SCLK  
CS  
AD7912/  
AD7922  
µC/  
µP  
V
DIN  
DOUT  
GND  
For ac applications, removing high frequency components from  
the analog input signal is recommended using a band-pass filter  
on the relevant analog input pin. In applications where har-  
monic distortion and signal-to-noise ratio are critical, the  
analog input should be driven from a low impedance source.  
Large source impedances can significantly affect the ac  
performance of the ADC. This might necessitate the use of an  
input buffer amplifier. The choice of the op amp is a function of  
the particular application.  
SERIAL  
INTERFACE  
Figure 22. REF193 as Power Supply to AD7912/AD7922  
Rev. 0 | Page 16 of 32  
 
 
 
AD7912/AD7922  
The fourth MSB, STY, is related to the mode of operation of the  
device. To keep the AD7912/ AD7922 in daisy-chain mode, the  
CHN and STY bits have to be inverted during the conversions  
(STY ≠ CHN). A conversion with STY = CHN on the input  
forces the device to normal mode in the next cycle. See the  
Daisy-Chain Mode section for more details.  
Table 7 provides some typical performance data with various  
op amps used as the input buffer, and a 50 kHz input tone under  
the same setup conditions.  
Table 7. AD7922 Performance for Various Input Buffers  
Op Amp in the Input  
Buffer  
AD7922 SNR Performance (dB)  
50 kHz Input , VDD = 3.6 V  
Single op amps  
AD8038  
AD8510  
If the AD7912/AD7922 are not going to be used in daisy-chain  
mode, it is recommended to keep STY and CHN the same  
(STY = CHN). In that case, the channel can be selected by tying  
DIN either high or low during a conversion cycle.  
−72.79  
−72.35  
−72.2  
AD8021  
Dual op amps  
AD712  
AD8022  
To summarize:  
−72.68  
−72.88  
CHN = 0, Channel 0 selected for next conversion.  
CHN = 1, Channel 1 selected for next conversion.  
CHN = STY, forces normal mode in the next cycle.  
CHN ≠ STY, keeps the AD7912/AD7922 in daisy-chain mode.  
When no amplifier is used to drive the analog input, the source  
impedance should be limited to low values. The maximum  
source impedance depends on the amount of total harmonic  
distortion (THD) that can be tolerated. The THD increases as  
the source impedance increases and performance degrades (see  
Figure 16).  
MSB  
X
LSB  
X
CHN STY  
DON'T CARE  
DIGITAL INPUTS  
Figure 24. AD7912/AD7922 DIN Word  
The digital inputs applied to the AD7912/AD7922 are not  
limited by the maximum ratings that limit the analog input.  
Instead, the digital inputs applied can go to 7 V and are not  
restricted by the VDD + 0.3 V limit as on the analog input. For  
example, if the AD7912/AD7922 are operated with a VDD of 3 V,  
then 5 V logic levels could be used on the digital inputs. How-  
ever, it is important to note that the data output on DOUT still  
has 3 V logic levels when VDD = 3 V. Another advantage of  
DOUT OUTPUT  
The conversion result from the AD7912/AD7922 is provided on  
this output as a serial data stream. The bits are clocked out on  
the SCLK falling edge at the same time that the conversion is  
taking place.  
The serial data stream for the AD7922 consists of two leading  
zeros followed by the bit that identifies the channel converted,  
the bit that indicates the current mode of operation, and the  
12-bit conversion result with MSB provided first.  
CS  
SCLK, DIN, and  
not being restricted by the VDD + 0.3 V limit  
CS  
is that power supply sequencing issues are avoided. If , DIN,  
or SCLK are applied before VDD, then there is no risk of latch-up  
as there would be on the analog inputs if a signal greater than  
For the AD7912, the serial data stream consists of two leading  
zeros followed by the bit that identifies the channel converted,  
the bit that indicates the current mode of operation, and the  
10-bit conversion result with MSB provided first, followed by  
two trailing zeros.  
0.3 V were applied prior to VDD  
.
DIN INPUT  
The channel to be converted on in the next conversion is  
selected by writing to the DIN pin. Data on the DIN pin is  
loaded into the AD7912/AD7922 on the falling edge of SCLK.  
The data is transferred into the part on the DIN pin at the same  
time that the conversion result is read from the part. Only the  
third and fourth bits of the DIN word are used; the rest are  
ignored by the ADC.  
The CHN and MOD bits on DOUT indicate to the user the  
current mode of operation of the ADC. If CHN = MOD,  
the AD7912/AD7922 are in normal mode. Otherwise, if  
CHN ≠ MOD, the AD7912/AD7922 are in daisy-chain mode.  
MSB  
0
LSB  
0
The third MSB is the channel identifier bit, which identifies the  
channel to be converted on in the next conversion,  
AD7912  
AD7922  
0
0
CHN MOD CONVERSION RESULT  
0
0
CHN MOD  
CONVERSION RESULT  
VIN0 (CHN = 0) or VIN1 (CHN = 1).  
Figure 25. AD7912/AD7922 DOUT Word  
Rev. 0 | Page 17 of 32  
 
 
AD7912/AD7922  
MODES OF OPERATION  
The three modes of operation of the AD7912/AD7922 are  
normal mode, power-down mode, and daisy-chain mode. The  
mode of operation is selected by controlling the logic state of  
CS  
CS  
can idle high until the next conversion or can idle low until  
returns high sometime prior to the next conversion  
CS  
(effectively idling  
(DOUT has returned to three-state), another conversion can be  
initiated after the quiet time, tQUIET, has elapsed by bringing  
low again.  
low). Once a data transfer is complete  
CS  
CS  
the  
signal. The point at which  
is pulled high after the  
conversion has been initiated determines whether the  
AD7912/AD7922 enter power-down mode or change to daisy-  
chain mode. Similarly, if already in daisy-chain mode,  
control whether the device returns to normal operation or  
enters power-down mode. The user can also change from daisy-  
chain mode to normal mode by writing to the DIN pin, as  
outlined in the DIN Input section.  
CS  
CS  
can  
POWER-DOWN MODE  
Power-down mode is intended for use in applications where  
slower throughput rates are required. Either the ADC is  
powered down between each conversion, or a series of  
conversions can be performed at a high throughput rate and  
then the ADC is powered down for a relatively long duration  
between these bursts of several conversions. When the AD7912/  
AD7922 are in power-down mode, all analog circuitry is  
powered down.  
Power-down mode is designed to provide flexible power  
management options and to optimize the ratio of power  
dissipation to throughput rate for different application  
requirements.  
Daisy-chain mode is intended for applications where fast  
throughput rate is not required and more than one  
AD7912/AD7922 have been connected in a daisy chain, as  
shown in Figure 33.  
To enter power-down mode, the conversion process must be  
CS  
interrupted by bringing  
falling edge of SCLK and before the 10th falling edge of SCLK,  
CS  
high any time after the second  
as shown in Figure 28. Once  
window of SCLKs, then the part enters power-down mode, the  
CS  
has been brought high in this  
NORMAL MODE  
conversion that was initiated by the falling edge of  
CS  
is termi-  
is brought  
Normal mode is intended for the fastest throughput rate  
performance. The user does not have to worry about any  
power-up time, because the AD7912/AD7922 remain fully  
powered all the time. Figure 26 shows the operation of the  
AD7912/AD7922 in this mode.  
nated, and DOUT goes back into three-state. If  
high before the second SCLK falling edge, then the part remains  
in normal mode and does not power down. This helps to avoid  
CS  
accidental power-down due to glitches on the  
line.  
To exit this mode of operation and power the AD7912/AD7922  
up again, a dummy conversion is performed. On the falling edge  
CS  
The conversion is initiated on the falling edge of  
described in the Serial Interface section. To ensure that the part  
CS  
as  
CS  
of , the device begins to power up and continues to power up  
remains fully powered up at all times,  
at least 10 SCLK falling edges have elapsed after the falling edge  
CS CS  
must remain low until  
CS  
as long as  
is held low until after the falling edge of the  
10th SCLK. The device is fully powered up once 16 SCLKs have  
elapsed and valid data results from the next conversion, as  
of . If  
is brought high after the 10th SCLK falling edge  
and before the 12th SCLK falling edge, then the device enters  
daisy-chain mode, as shown in Figure 27. The conversion is  
CS  
shown in Figure 29. If  
is brought high before the 10th falling  
edge of SCLK, then the AD7912/AD7922 go back into power-  
down mode. This helps to avoid accidental power-up due to  
CS  
terminated and DOUT goes back into three-state. If  
is  
brought high after the 13th SCLK falling edge, but before the  
end of tCONVERT, the conversion is terminated and DOUT goes  
back into three-state, but the part remains in normal mode.  
CS  
glitches on the  
line or an inadvertent burst of 8 SCLK cycles  
is low. Therefore, although the device might begin to  
CS  
CS  
while  
power up on the falling edge of , it powers down again on the  
For the AD7922, 16 serial clock cycles are required to complete  
the conversion and access the complete conversion result. For  
the AD7912, a minimum of 14 serial clock cycles are required  
to complete the conversion and access the complete  
conversion result.  
CS  
rising edge of , as long as this occurs before the 10th SCLK  
falling edge.  
Rev. 0 | Page 18 of 32  
AD7912/AD7922  
AD7912/AD7922  
16  
CS  
1
10  
12  
14  
16  
1
10  
12  
14  
SCLK  
DIN  
CHANNEL FOR NEXT CONVERSION  
CONVERSION RESULT  
CHANNEL FOR NEXT CONVERSION  
CONVERSION RESULT  
DOUT  
Figure 26. Normal Mode Operation  
THE PART ENTERS  
DAISY-CHAIN MODE  
CS  
1
2
10  
12  
16  
SCLK  
THREE-STATE  
THREE-STATE  
DIN  
INVALID DATA  
DOUT  
INVALID DATA  
Figure 27. Entering Daisy-Chain Mode  
CS  
1
2
10  
16  
SCLK  
THREE-STATE  
DIN  
INVALID DATA  
INVALID DATA  
THREE-STATE  
DOUT  
Figure 28. Entering Power- Down Mode  
THE PART BEGINS  
TO POWER UP  
THE PART IS FULLY  
POWERED UP WITH V  
FULLY ACQUIRED  
THE PART GOES  
INTO TRACK  
IN  
CS  
NORMAL MODE  
A
1
5
10  
13  
16  
1
16  
SCLK  
DIN  
CHANNEL FOR NEXT CONVERSION  
INVALID DATA  
CHANNEL FOR NEXT CONVERSION  
CONVERSION RESULT  
DOUT  
Figure 29. Exiting Power-Down Mode  
Rev. 0 | Page 19 of 32  
 
 
 
AD7912/AD7922  
the ADC. If the first valid conversion is then performed directly  
after the dummy conversion, care must be taken to ensure that  
adequate acquisition time has been allowed. When the ADC  
powers up initially after supplies are applied, the track-and-hold  
is in hold. It returns to track on the fifth SCLK falling edge that  
POWER-UP TIME  
The power-up time of the AD7912/AD7922 is 1 µs, which  
means that with any frequency of SCLK up to 18 MHz, one  
dummy cycle is always sufficient to allow the device to power  
up. Once the dummy cycle is complete, the ADC is fully  
powered up and the input signal is fully acquired. The quiet  
time, tQUIET, must still be allowed from the point at which the  
bus goes back into three-state after the dummy conversion to  
the next falling edge of . When running at a 1 MSPS  
throughput rate, the AD7912/AD7922 power up and acquire a  
signal within 1 LSB in one dummy cycle, that is, 1 µs.  
CS  
the part receives after the falling edge of  
.
DAISY-CHAIN MODE  
When the ADC is in this mode of operation, the part operates  
as a shift register. This mode is intended for applications where  
more than one ADC is used, connected in a daisy-chain  
configuration (see Figure 33). All ADCs are addressed by the  
CS  
CS  
same  
signal and the same serial clock. The conversion result  
When powering up from power-down mode with a dummy  
cycle, as in Figure 29, the track-and-hold that was in hold mode  
while the part was powered down returns to track mode on the  
fifth SCLK falling edge that the part receives after the falling  
stored in the internal shift register in each ADC is shifted from  
one device to the following in the chain. See the Daisy-Chain  
Example in the following section for more details.  
CS  
edge of . This is shown as point A in Figure 29. At this point,  
To enter daisy-chain mode, the conversion process must be  
the part starts to acquire the signal on the channel selected in  
the current dummy conversion.  
CS  
interrupted by bringing  
high after the 10th falling edge of  
SCLK and before the 12th falling edge of SCLK, as shown in  
Figure 27. To ensure that the AD7912/AD7922 are placed into  
Although at any SCLK frequency one dummy cycle is sufficient  
to power up the device and acquire VIN, it does not necessarily  
mean that a full dummy cycle of 16 SCLKs must always elapse  
to power up the device and acquire VIN fully. 1 µs is sufficient to  
power up the device and acquire the input signal. For example,  
if a 5 MHz SCLK frequency was applied to the ADC, the cycle  
time would be 3.2 µs. In one dummy cycle, 3.2 µs, the part  
would be powered up and VIN acquired fully. However, after 1 µs  
with a 5 MHz SCLK, only five SCLK cycles would have elapsed.  
At this stage, the ADC would be fully powered up and the signal  
CS  
daisy-chain mode,  
least 20 ns after the 10th SCLK falling edge and before the  
CS  
should not be brought high until at  
12th SCLK falling edge. Once  
has been brought high in  
this window of SCLKs, the part enters daisy-chain mode, the  
CS  
conversion that was initiated by the falling edge of  
terminated, and DOUT goes back into three-state.  
is  
CS  
If  
is brought high between the 10th and the 12th SCLK  
falling edge, the part enters daisy-chain mode and the data  
shifted from one ADC to the next one in the chain is valid data  
CS  
is acquired. Therefore, in this case,  
can be brought high after  
is brought high anytime after  
the 13th SCLK falling edge, the part enters normal mode for the  
CS  
CS  
(see Figure 34 and Figure 35). If  
is brought high between the  
CS  
the 10th SCLK falling edge. If  
12th and the 13th SCLK falling edge, the part enters daisy-chain  
mode, but the data shifted in the chain is invalid data.  
next conversion.  
has to be brought low again after a time,  
CS  
tQUIET, to initiate the conversion. However, if  
anytime after the 10th and before the 12th SCLK falling edge,  
the part enters daisy-chain mode.  
is brought high  
To keep the part in daisy-chain mode, the CHN and STY bits in  
the DIN word must be inverted relative to each other in each  
16 SCLKs cycle. A conversion with the CHN and STY bits set to  
the same value in the DIN word while the device is in daisy-  
chain mode forces the part to go back into normal mode in the  
next cycle, as shown in Figure 30.  
When power supplies are first applied to the AD7912/AD7922,  
the ADC can power up in either power-down mode, normal  
mode, or daisy-chain mode. Because of this, it is best to allow a  
dummy cycle to elapse to ensure that the part is fully powered  
up before attempting a valid conversion. Likewise, if the user  
wants to keep the part in power-down mode while not in use  
and to power up in power-down mode, then the dummy cycle  
can be used to ensure that the device is in power-down mode by  
executing a cycle such as that shown in Figure 28.  
To exit this mode of operation, the user can perform a dummy  
cycle or can set the STY bit to the CHN bit value on the DIN  
word during a conversion cycle. When performing a dummy  
CS  
conversion to exit this mode,  
must be brought high anytime  
after the 10th SCLK falling edge and before the 13th SCLK  
falling edge, as shown in Figure 31. The device enters normal  
mode, and valid data from the channel selected in the dummy  
cycle results in the next conversion.  
Once supplies are applied to the AD7912/AD7922, the power-  
up time is the same as when powering up from the power-down  
mode. It takes the part approximately 1 µs to power up fully in  
normal mode. It is not necessary to wait 1 µs before executing a  
dummy cycle to ensure the desired mode of operation. Instead,  
the dummy cycle can occur directly after power is supplied to  
Figure 32 summarizes the modes of operation, how to change  
between modes, the values for the bits in the DIN and DOUT  
words in different modes, and in the transitions between modes.  
Rev. 0 | Page 20 of 32  
AD7912/AD7922  
CS  
DAISY-CHAIN CYCLE  
10  
NORMAL MODE  
10  
1
12  
14  
16  
1
12  
14  
16  
SCLK  
DIN  
CH = STY  
CHANNEL FOR NEXT CONVERSION  
CONVERSION RESULT  
VALID DATA  
DOUT  
Figure 30. Exiting Daisy-Chain Mode with CH = STY in the DIN Pin  
THE PART ENTERS  
NORMAL MODE  
CS  
NORMAL MODE  
A
1
10  
13  
16  
1
16  
SCLK  
DIN  
CHANNEL FOR NEXT CONVERSION  
INVALID DATA  
CHANNEL FOR NEXT CONVERSION  
CONVERSION RESULT  
DOUT  
Figure 31. Exiting Daisy-Chain Mode  
CS HIGH BETWEEN  
THE 10TH–13TH SCLK  
CONVERSION CYCLE  
DIN: CHN STY  
≠
CONVERSION CYCLE  
DIN: CHN = STY  
NORMAL MODE  
DOUT: CHN = MOD  
DAISY-CHAIN MODE  
DOUT:CHN MOD  
CONVERSION  
CYCLE  
≠
*CS HIGH BETWEEN  
THE 10TH–12TH SCLK  
POWER-UP TIME AND CS  
HIGH AFTER THE 13TH SCLK  
CS HIGH BETWEEN  
THE 2ND–10TH SCLK  
CS HIGH BETWEEN  
THE 2ND–10TH SCLK  
POWER-UP TIME AND  
CS HIGH BETWEEN  
THE 10TH–12TH SCLK  
POWER-DOWN  
MODE  
*IF CS IS BROUGHT HIGH BETWEEN THE 10TH AND THE 12TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE  
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS VALID DATA.  
IF CS IS BROUGHT HIGH BETWEEN THE 12TH AND THE 13TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE  
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS INVALID DATA.  
Figure 32. Transitions between Modes of Operation  
Rev. 0 | Page 21 of 32  
AD7912/AD7922  
DAISY-CHAIN EXAMPLE  
tion data for the second last device in the chain, and so on.  
Then the selected channel for the first device in the chain is  
clocked in the cycle executed after all the data has been  
read, that is, in the short cycle used to change modes of  
operation. See Figure 34.  
In applications where fast throughput is not critical, connecting  
several ADCs in a daisy chain lets the user perform simultane-  
ous sampling on all the ADCs contained in the chain using the  
minimum number of I/O lines from the µC/DSP ports.  
The user needs to alternate modes of operation in the ADCs.  
While the parts are in normal mode, the conversion is per-  
formed and the result from each ADC is stored in its internal  
register. Following the conversion, the parts are placed into  
daisy-chain mode and the user can proceed to read the result  
from each ADC by shifting the data from one ADC to the next.  
4. Enter normal mode.  
After reading the conversion results from the AD7912/  
AD7922, the devices need to be placed into normal mode  
to perform a new conversion. Therefore, in this cycle  
brought high between the 10th and the 13th SCLK falling  
edge. The DOUT line contains invalid data and DIN  
contains the selected channel for the first device in the  
chain. The remaining devices in the chain have already set  
the channel for the next conversion as a result of the data  
shifted in during daisy-chain mode.  
CS  
is  
For clarity in the following example, only two devices are  
connected in a daisy chain. Both AD7912/AD7922 are  
CS  
addressed by the same  
and SCLK signal. The devices are  
configured as shown in Figure 33 for simultaneous conversion  
and shifting read operation later. The output of the device on  
the left, ADC1, feeds the input of the device on the right, ADC2.  
5. Normal conversion.  
A new conversion can be performed on the newly selected  
channels. The process can be repeated by following the  
previous steps.  
During a normal conversion, the conversion result is stored  
internally and output to the DOUT pin. In daisy-chain mode,  
the value internally stored is output through the DOUT pin and  
the information provided at the DIN pin is shifted into the  
internal register.  
Figure 34 shows the timing diagram for two AD7912/  
AD7922 connected in a daisy chain, as shown in Figure 33.  
The DIN signal corresponds to the DIN pin on the first  
AD7912/AD7922 in the chain, and the DOUT signal  
corresponds to the DOUT pin on the last AD7912/AD7922  
in the chain. The words clocked into the DIN pin, which  
set up the channel for the next conversion for the two  
AD7912/AD7922, are shown as COMMAND1 and  
COMMAND2. The first word clocked in, COMMAND3,  
does not remain in any of the ADCs in the chain and is  
eventually lost. The channel configuration data for the first  
device in the chain, COMMAND1, is clocked in while  
changing from daisy-chain mode to normal mode.  
When several AD7912/AD7922 are connected in a daisy chain,  
the sequence is as follows:  
1. Normal conversion.  
Every AD7912/AD7922 performs a conversion on its  
selected channel and the result is stored in the internal shift  
register.  
2. Entering daisy-chain mode.  
CS  
In this cycle,  
is brought high between the 10th and  
12th SCLK falling edges and all the devices enter daisy-  
chain mode.  
Figure 35 is a more detailed diagram that shows the data  
presented on the DIN pin and clocked out on the DOUT  
pin for each of the AD7912/AD7922 in Figure 33. If the  
DOUT1 (or DIN2) signal is ignored, Figure 35 brings  
about Figure 34.  
3. Daisy-chain cycles.  
While the AD7912/AD7922 are in daisy-chain mode, the  
conversion results from all the devices in the chain are  
read, and the parts are configured for the next conversion.  
CS  
FSX  
The user needs to perform as many read cycles as there are  
devices in the chain. To keep all the AD7912/AD7922 in  
daisy-chain mode, the CHN and STY bits in the DIN input  
must always be inverted. Data is shifted through the  
devices in the chain. Data is clocked into the device in the  
chain by the same clock used to clock data out. The first  
word clocked into the DIN pin once the devices are in  
daisy-chain mode is eventually lost. The second word  
clocked into the DIN pin contains the channel configura-  
tion data for the last device in the chain, the third word  
clocked into the DIN pin contains the channel configura-  
SCLK  
SCLK  
SCLK  
CS  
SCLK  
CS  
µC/DSP  
TX  
DIN  
DOUT  
DIN1 DOUT1  
ADC1  
DIN2 DOUT2  
ADC2  
DR  
Figure 33. AD7912/AD7922 Connected in Daisy Chain  
Rev. 0 | Page 22 of 32  
 
AD7912/AD7922  
CHANGE MODE  
CS HIGH  
BETWEEN THE  
10TH–12TH SCLK  
FALLING EDGE  
CHANGE MODE  
CS HIGH BETWEEN THE  
10TH–13TH SCLK  
DAISY-CHAIN MODE  
DATA IS SHIFTED  
FROM ONE ADC TO  
THE NEXT ONE  
DAISY-CHAIN MODE  
DATA IS SHIFTED  
FROM ONE ADC TO  
THE NEXT ONE  
NORMAL MODE  
CONVERSION ON THE  
TWO DEVICES  
NORMAL MODE  
CONVERSION ON THE  
TWO DEVICES  
FALLING EDGE  
CS  
SCLK  
THE DATA WILL BE  
EVENTUALLY LOST,  
COMMAND3  
SET CHANNEL  
FOR ADC2,  
COMMAND2  
SET CHANNEL  
FOR ADC1,  
COMMAND1  
DIN  
DON'T CARE  
DON'T CARE  
DON'T CARE  
DON'T CARE  
CH  
≠
STY  
CH  
≠
STY  
DON'T CARE  
DON'T CARE  
DON'T CARE  
KEEP THE DEVICES IN  
DAISY-CHAIN MODE  
DOUT  
VALID DATA ADC2  
VALID DATA ADC1  
DON'T CARE  
Figure 34. Daisy-Chain Diagrams—1  
THE PARTS ENTER  
DAISY-CHAIN MODE  
NORMAL CONVERSION  
DAISY-CHAIN CYCLE  
10 12  
CS  
1
16  
1
10 12  
1
14  
16  
SCLK  
DIN  
DON'T CARE  
DON'T CARE  
COMMAND3 WITH CHN  
≠
STY  
SHIFTED INTO THE ADC1 INTERNAL REGISTER,  
THIS DATA WILL BE EVENTUALLY LOST  
0, 0, CHN = MOD, VALID DATA ADC1  
(0, 0, CHN = STY, VALID DATA ADC1)  
0, 0, CHN  
(0, 0, CHN  
≠
MOD, VALID DATA ADC1  
STY, VALID DATA ADC1)  
DOUT1  
(DIN2)*  
DON'T CARE  
DON'T CARE  
≠
SHIFTED INTO THE ADC2  
INTERNAL REGISTER  
DOUT  
0, 0, CHN = MOD, VALID DATA ADC2  
0, 0, CHN  
≠ MOD, VALID DATA ADC2  
THE PARTS ENTER  
NORMAL MODE  
DAISY-CHAIN CYCLE  
NORMAL CONVERSION  
CS  
1
10  
12  
14  
16  
1
10  
13  
1
16  
SCLK  
DIN  
COMMAND2 WITH CHN  
≠
STY  
COMMAND1  
COMMAND2  
COMMAND3  
DON'T CARE  
SHIFTED INTO THE ADC1  
INTERNAL REGISTER  
SHIFTED INTO THE ADC1 INTERNAL REGISTER, IT  
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1  
0, 0, CHN = MOD, VALID DATA ADC1  
(0, 0, CHN = STY, VALID DATA ADC1)  
DOUT1  
(DIN2)*  
COMMAND3  
SHIFTED INTO THE ADC2  
INTERNAL REGISTER  
SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT  
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2  
DOUT  
NOTE  
0, 0, CHN ≠ MOD, VALID DATA ADC1  
0, 0, CHN = MOD, VALID DATA ADC2  
*INFORMATION IN BRACKETS CORRESPONDS TO DATA CLOCKED INTO DIN2 PIN  
Figure 35. Daisy-Chain Diagrams—II  
Rev. 0 | Page 23 of 32  
AD7912/AD7922  
POWER VS. THROUGHPUT RATE  
By using the power-down mode on the AD7912/AD7922 when  
not converting, the average power consumption of the ADC  
decreases at lower throughput rates. Figure 36 shows how, as the  
throughput rate is reduced, the device remains in its power-  
down state longer and the average power consumption over  
time drops.  
In the previous calculations, the power dissipation when the  
part is in power-down mode has not been taken into account.  
By placing the parts into power-down mode between conver-  
sions, the average power consumed by the ADC decreases as  
the throughput rate decreases, because the ADC remains in a  
power-down state for a longer time.  
For example, if the AD7912/AD7922 are operating in a continu-  
ous sampling mode with a throughput rate of 100 kSPS and a  
SCLK of 18 MHz (VDD = 5 V), and the devices are placed in the  
power-down mode between conversions, then the power  
consumption is calculated as follows. The power dissipation  
during normal operation is 20 mW (VDD = 5 V). If the power-up  
time is one dummy cycle (1 µs), and the remaining conversion  
time is another cycle (1 µs), then the AD7912/AD7922 dissipate  
20 mW for 2 µs during each conversion cycle. If the throughput  
rate is 100 kSPS and the cycle time is 10 µs, then the average  
power dissipated during each cycle is  
Figure 36 shows the power consumption versus throughput rate  
when using the power-down mode between conversions with  
both 5 V and 3 V supplies.  
Power-down mode is intended for use with throughput rates of  
approximately 330 kSPS and under, because at higher sampling  
rates the short time spent in power-down does not affect the  
average power consumed by the ADC.  
100  
V
= 5V, SCLK = 18MHz  
DD  
10  
1
(2/10) × (20 mW) = 4 mW  
If VDD = 3 V, SCLK = 18 MHz, and the device is again in power-  
down mode between conversions, then the power dissipation  
during normal operation is 6 mW. The AD7912/AD7922 now  
dissipate 6 mW for 2 µs during each conversion cycle. With a  
throughput rate of 100 kSPS, the average power dissipated  
during each cycle is  
V
= 3V, SCLK = 18MHz  
DD  
0.1  
0.01  
(2/10) × (6 mW) = 1.2 mW  
0
50  
100  
150  
200  
250  
300  
350  
THROUGHPUT (kSPS)  
Figure 36. Power Consumption vs. Throughput Rate  
Rev. 0 | Page 24 of 32  
 
AD7912/AD7922  
SERIAL INTERFACE  
Figure 37 and Figure 38 show the detailed timing diagrams for  
serial interfacing to the AD7922 and AD7912, respectively. The  
serial clock provides the conversion clock and also controls the  
transfer of information from the AD7912/AD7922 during  
conversion.  
CS  
occurs before 14 SCLKs have elapsed,  
If the rising edge of  
then the conversion is terminated and the DOUT line goes back  
into three-state. If 16 SCLKs are considered in the cycle, DOUT  
returns to three-state on the 16th SCLK falling edge, as shown  
in Figure 38.  
CS  
The  
signal initiates the data transfer and conversion process.  
CS  
CS  
going low clocks out the first leading zero to be read in by  
The falling edge of  
takes the bus out of three-state. The analog input is sampled at  
this point and the conversion is initiated.  
puts the track-and-hold into hold mode,  
the microcontroller or DSP. The remaining data is then clocked  
out by subsequent SCLK falling edges beginning with the  
second leading zero. Therefore, the first falling clock edge on  
the serial clock has the first leading zero provided and also  
clocks out the second leading zero. The final bit in the data  
transfer is valid on the 16th falling edge, having been clocked  
out on the previous (15th) falling edge.  
For the AD7922, the conversion requires 16 SCLK cycles to  
complete. Once 13 SCLK falling edges have elapsed, the track-  
and-hold goes back into track on the next SCLK rising edge, as  
shown in Figure 37 at Point B. On the 16th SCLK falling edge,  
the DOUT line goes back into three-state. If the rising edge of  
In applications with a slower SCLK, it is possible to read in data  
on each SCLK rising edge. In that case, the first falling edge of  
SCLK clocks out the second leading zero and it can be read in  
the first rising edge. However, the first leading zero that is  
clocked out when  
first falling SCLK edge. The 15th falling edge of SCLK clocks  
out the last bit and it can be read in the 15th rising SCLK edge.  
CS  
occurs before 16 SCLKs have elapsed, then the conversion is  
terminated and the DOUT line goes back into three-state.  
Otherwise, DOUT returns to three-state on the 16th SCLK  
falling edge, as shown in Figure 37. Sixteen serial clock cycles  
are required to perform the conversion process and to access  
data from the AD7922.  
CS  
goes low is missed, unless it is read on the  
For the AD7912, the conversion requires 14 SCLK cycles to  
complete. Once 13 SCLK falling edges have elapsed, the track-  
and-hold goes back into track on the next SCLK rising edge, as  
shown in Figure 38 at Point B.  
CS  
CS  
goes low just after the SCLK falling edge has elapsed,  
If  
clocks out the first leading zero as before and it can be read in  
the SCLK rising edge. The next SCLK falling edge clocks out  
the second leading zero and it can be read in the following  
rising edge.  
t1  
CS  
tCONVERT  
t2  
t6  
B
1
2
3
4
5
13  
14  
t5  
15  
16  
SCLK  
t7  
DB10  
t10  
t4  
t3  
tQUIET  
Z
ZERO  
CHN  
t8  
MOD  
DB11  
DB2  
DB1  
DB0  
DOUT  
DIN  
THREE-STATE  
X
THREE-STATE  
t9  
X
CHN  
STY  
X
X
X
X
X
Figure 37. AD7922 Serial Interface Timing Diagram  
t1  
CS  
tCONVERT  
t2  
t6  
B
1
2
3
4
5
13  
14  
t5  
15  
16  
SCLK  
t7  
DB8  
t10  
t4  
t3  
tQUIET  
Z
ZERO  
CHN  
t8  
MOD  
DB9  
DB0  
ZERO  
ZERO  
DOUT  
DIN  
THREE-STATE  
THREE-STATE  
t9  
TWO TRAILING ZEROS  
X
X
CHN  
STY  
X
X
X
X
X
Figure 38. AD7912 Serial Interface Timing Diagram  
Rev. 0 | Page 25 of 32  
 
 
AD7912/AD7922  
AD7912/AD7922 to ADSP-218x  
MICROPROCESSOR INTERFACING  
The ADSP-218x family of DSPs are interfaced directly to the  
AD7912/AD7922 without any glue logic required. The SPORT  
control register should be set up as follows:  
The serial interface on the AD7912/AD7922 allows the parts to  
be directly connected to a range of microprocessors. This  
section explains how to interface the AD7912/AD7922 with  
some of the more common microcontroller and DSP serial  
interface protocols.  
TFSW = RFSW = 1, alternate framing  
INVRFS = INVTFS = 1, active low frame signal  
DTYPE = 00, right-justify data  
AD7912/AD7922 to TMS320C541 Interface  
ISCLK = 1, internal serial clock  
TFSR = RFSR = 1, frame every word  
IRFS = 0, set up RFS as an input  
ITFS = 1, set up TFS as an output  
SLEN = 1111, 16 bits for the AD7922  
SLEN = 1101, 14 bits for the AD7912  
The serial interface on the TMS320C541 uses a continuous  
serial clock and frame synchronization signals to synchronize  
the data transfer operations with peripheral devices like the  
CS  
AD7912/AD7922. The  
input allows easy interfacing between  
the TMS320C541 and the AD7912/AD7922 without any glue  
logic required. The serial port of the TMS320C541 is set up to  
operate in burst mode (FSM = 1 in the serial port control  
register, SPC) with the internal serial clock CLKX (MCM = 1 in  
the SPC register) and the internal frame signal (TXM = 1 in the  
SPC register); therefore, both pins are configured as outputs. For  
the AD7922, the word length should be set to 16 bits (FO = 0 in  
the SPC register). This DSP allows frames with a word length of  
16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are  
required, the FO bit should be set up to 16 bits, and 16 SCLKs  
are needed. For the AD7912, two trailing zeros are clocked out  
in the last two clock cycles.  
To implement the power-down mode, SLEN should be set to  
0111 to issue an 8-bit SCLK burst. The connection diagram is  
shown in Figure 40. The ADSP-218x has the TFS and RFS of the  
SPORT tied together, with TFS set as an output and RFS set as  
an input. The DSP operates in alternate framing mode and the  
SPORT control register is set up as described previously. The  
frame synchronization signal generated on the TFS is tied to  
and, as with all signal processing applications, equidistant  
sampling is necessary. However, in this example, the timer  
CS  
interrupt is used to control the sampling rate of the ADC and,  
under certain conditions, equidistant sampling might not be  
achieved.  
The values in the SPC register are as follows:  
FO = 0  
ADSP-218x*  
AD7912/  
AD7922*  
FSM = 1  
MCM = 1  
TXM = 1  
SCLK  
SCLK  
DR  
DOUT  
DT  
DIN  
CS  
To implement the power-down mode on the AD7912/AD7922,  
the format bit, FO, can be set to 1, which sets the word length to  
8 bits.  
RFS  
TFS  
The connection diagram is shown in Figure 39. Note that, for  
signal processing applications, the frame synchronization signal  
from the TMS320C541 must provide equidistant sampling.  
*ADDITIONAL PINS REMOVED FOR CLARITY  
Figure 40. Interfacing to the ADSP-218x  
The timer registers are loaded with a value that provides an  
interrupt at the required sample interval. When an interrupt is  
received, a value is transmitted with TFS/DT (ADC control  
word). The TFS is used to control the RFS and, therefore, the  
reading of data. The frequency of the serial clock is set in the  
SCLKDIV register. When the instruction to transmit with TFS  
is given, that is, TX0 = AX0, the state of the SCLK is checked.  
The DSP waits until the SCLK has gone high, low, and high  
again before transmission starts. If the timer and SCLK values  
are chosen such that the instruction to transmit occurs on or  
near the rising edge of SCLK, the data might be transmitted or  
it might wait until the next clock edge.  
TMS320C541*  
AD7912/  
AD7922*  
SCLK  
CLKX  
CLKR  
DR  
DX  
DOUT  
DIN  
CS  
FSX  
FSR  
*ADDITIONAL PINS REMOVED FOR CLARITY  
Figure 39. Interfacing to the TMS320C541  
Rev. 0 | Page 26 of 32  
 
 
AD7912/AD7922  
low and a conversion starts. Likewise, by means of the Bits  
For example, the ADSP-2189 has a master clock frequency of  
40 MHz. If the SCLKDIV register is loaded with the value of 3,  
then an SCLK of 5 MHz is obtained, and eight master clock  
periods elapse for every one SCLK period. Depending on the  
throughput rate selected, if the timer register is loaded with the  
value 803 (803 + 1 = 804), then 100.5 SCLK occur between  
interrupts and subsequently between transmit instructions. This  
situation results in nonequidistant sampling, because the  
transmit instruction occurs on a SCLK edge. If the number of  
SCLKs between interrupts is a whole integer figure of N, then  
equidistant sampling is implemented by the DSP.  
SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the  
frame sync signal) and SCK in the serial port are configured as  
outputs, and the MSB is shifted first.  
The values are as follows:  
MOD = 0  
SYN = 1  
WL2, WL1, WL0 depend on the word length  
FSL1 = 0, FSL0 = 0  
FSP = 1, negative frame sync  
SCD2 = 1  
AD7912/AD7922 to DSP563xx Interface  
SCKD = 1  
The connection diagram in Figure 41 shows how the AD7912/  
AD7922 can be connected to the SSI (synchronous serial  
interface) of the DSP563xx family of DSPs from Motorola. The  
SSI is operated in synchronous and normal mode (SYN = 1 and  
MOD = 0 in the Control Register B, CRB) with internally  
generated word frame sync for both Tx and Rx (Bits FSL1 = 0  
and FSL0 = 0 in the CRB). Set the word length in the Control  
Register A (CRA) to 16 by setting bits WL2 = 0, WL1 = 1, and  
WL0 = 0 for the AD7922. This DSP does not offer the option for  
a 14-bit word length, so the AD7912 word length is set up to  
16 bits like the AD7922. For the AD7912, the conversion process  
uses 16 SCLK cycles, with the last two clock periods clocking  
out two trailing zeros to fill the 16-bit word.  
SHFD = 0  
Note that, for signal processing applications, the frame  
synchronization signal from the DSP563xx must provide  
equidistant sampling.  
DSP563xx*  
AD7912/  
AD7922*  
SCLK  
DOUT  
DIN  
SCK  
SRD  
STD  
SC2  
CS  
*ADDITIONAL PINS REMOVED FOR CLARITY  
To implement the power-down mode on the AD7912/AD7922,  
the word length can be changed to 8 bits by setting Bits  
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the  
CRB register can be set to 1, which means that the frame goes  
Figure 41. Interfacing to the DSP563xx  
Rev. 0 | Page 27 of 32  
 
AD7912/AD7922  
APPLICATION HINTS  
GROUNDING AND LAYOUT  
ground to avoid radiating noise to other sections of the board,  
and clock signals should never be run near the analog inputs.  
Avoid crossover of digital and analog signals. Traces on opposite  
sides of the board should run at right angles to each other to  
reduce the effects of feedthrough through the board. A micro-  
strip technique is by far the best, but is not always possible with  
a double-sided board. In this technique, the component side of  
the board is dedicated to ground planes, while signals are placed  
on the solder side.  
The printed circuit board that houses the AD7912/AD7922  
should be designed such that the analog and digital sections are  
separated and confined to certain areas of the board. This  
facilitates the use of ground planes that can be separated easily.  
A minimum etch technique is generally best for ground planes,  
because it gives the best shielding. Digital and analog ground  
planes should be joined at only one place. If the AD7912/  
AD7922 are in a system where multiple devices require an  
AGND-to-DGND connection, the connection should still be  
made at one point only, a star ground point that should be  
established as close as possible to the AD7912/AD7922.  
Good decoupling is also very important. The analog supply  
should be decoupled with 10 µF tantalum in parallel with 0.1 µF  
capacitors to AGND. To achieve the best performance from  
these decoupling components, the user should endeavor to keep  
the distance between the decoupling capacitor and the VDD and  
GND pins to a minimum with short track lengths connecting  
the respective pins.  
Avoid running digital lines under the device, because these  
couple noise onto the die. The analog ground plane should be  
allowed to run under the AD7912/AD7922 to avoid noise  
coupling. The power supply lines to the AD7912/AD7922  
should use as large a trace as possible to provide low impedance  
paths and reduce the effects of glitches on the power supply line.  
Fast-switching signals like clocks should be shielded with digital  
Rev. 0 | Page 28 of 32  
AD7912/AD7922  
EVALUATING AD7912/AD7922 PERFORMANCE  
The evaluation board package includes a fully assembled and  
tested evaluation board, documentation, and software for  
controlling the board from a PC via the EVAL-CONTROL  
BRD2.  
The software allows the user to perform ac (Fast Fourier  
Transform) and dc (histograms of codes) tests on the  
AD7912/AD7922.  
See the AD7912/AD7922 Technical Note for more information.  
The technical note is included in the software, and it can also be  
found on the www.analog.com website under the Design Tools  
link on the AD7912/AD7922 product page.  
The EVAL-CONTROL BRD2 can be used in conjunction with  
the AD7912CB/AD7922CB evaluation board, as well as many  
other Analog Devices evaluation boards ending in the CB  
designator to demonstrate and evaluate the ac and dc  
performance of the AD7912/AD7922.  
Rev. 0 | Page 29 of 32  
AD7912/AD7922  
OUTLINE DIMENSIONS  
2.90 BSC  
3.00  
BSC  
8
1
7
2
6
3
5
4
8
5
4
1.60 BSC  
2.80 BSC  
4.90  
BSC  
3.00  
BSC  
PIN 1  
INDICATOR  
0.65 BSC  
PIN 1  
1.95  
BSC  
0.65 BSC  
0.90  
0.87  
0.84  
1.10 MAX  
0.15  
0.00  
1.00 MAX  
0.20  
0.08  
0.80  
0.60  
0.40  
8°  
0°  
0.60  
0.45  
0.30  
0.38  
0.22  
0.23  
0.08  
8°  
4°  
0°  
0.38  
0.22  
0.10 MAX  
SEATING  
PLANE  
COPLANARITY  
0.10  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-193BA  
COMPLIANT TO JEDEC STANDARDS MO-187AA  
Figure 42. 8-Lead Mini Small Outline Package [MSOP]  
(RM-8)  
Figure 43. 8-Lead Thin Small Outline Transistor Package [TSOT]  
(UJ-8)  
Dimensions shown in millimeters  
Dimensions shown in millimeters  
ORDERING GUIDE  
Temperature  
Range  
Linearity  
Error (LSB)1  
0.5 max  
0.5 max  
0.5 max  
0.5 max  
0.5 max  
1.5 max  
1.5 max  
1.5 max  
1.5 max  
1.5 max  
Package  
Package  
Option  
RM-8  
RM-8  
RM-8  
UJ-8  
Model  
Description  
8-lead MSOP  
8-lead MSOP  
8-lead MSOP  
8-lead TSOT  
8-lead TSOT  
8-lead MSOP  
8-lead MSOP  
8-lead MSOP  
8-lead TSOT  
8-lead TSOT  
Evaluation Board  
Evaluation Board  
Branding  
C1A  
Quantity  
AD7912ARM  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
1
AD7912ARM-REEL  
AD7912ARM-REEL7  
AD7912AUJ-R2  
AD7912AUJ-REEL7  
AD7922ARM  
AD7922ARM-REEL  
AD7922ARM-REEL7  
AD7922AUJ-R2  
AD7922AUJ-REEL7  
EVAL-AD7912CB2  
EVAL-AD7922CB2  
EVAL-CONTROL BRD23  
C1A  
C1A  
C1A  
C1A  
3000  
1000  
250  
3000  
1
UJ-8  
RM-8  
RM-8  
RM-8  
UJ-8  
C1B  
C1B  
C1B  
C1B  
C1B  
3000  
1000  
250  
3000  
UJ-8  
Evaluation  
Control Board  
1 Linearity error here refers to integral nonlinearity.  
2 This evaluation board can be used standalone or in conjunction with the EVAL-CONTROL BRD2 for evaluation or demonstration purposes.  
3 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete  
evaluation kit, order a particular ADC evaluation board (EVAL-AD7922 CB, for example), the EVAL-CONTROL BRD2, and a 12 ac transformer. See the relevant evaluation  
board technical note for more information.  
Rev. 0 | Page 30 of 32  
 
 
 
 
AD7912/AD7922  
NOTES  
Rev. 0 | Page 31 of 32  
AD7912/AD7922  
NOTES  
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D04351–0–4/04(0)  
Rev. 0 | Page 32 of 32  

相关型号：

AD7912AUJ-REEL7

 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs
ADI

AD7912AUJZ-REEL

 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, ROHS COMPLIANT, MO-193BA, TSOT-8
ADI

AD7912AUJZ-REEL7

 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-Bit A/D Converter
ADI

AD7914

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI

AD7914BRU

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI

AD7914BRU-REEL

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI

AD7914BRU-REEL

 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, MO-153AB, TSSOP-16
ROCHESTER

AD7914BRU-REEL7

 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, MO-153AB, TSSOP-16
ROCHESTER

AD7914BRUZ

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI

AD7914BRUZ

 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
ROCHESTER

AD7914BRUZ-REEL7

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI

AD7914WYRUZ-REEL7

 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
ADI
©2020 ICPDF网 联系我们和版权申明