AD7927BRUZ-REEL [ADI]
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| 型号： | AD7927BRUZ-REEL |
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ADI |
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8-Channel, 200 kSPS, 12-Bit ADC
with Sequencer in 20-Lead TSSOP
AD7927
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast Throughput Rate: 200 kSPS
Specified for AVDD of 2.7 V to 5.25 V
Low Power:
3.6 mW Max at 200 kSPS with 3 V Supply
7.5 mW Max at 200 kSPS with 5 V Supply
8 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
70 dB Min SINAD at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI™/QSPI™/
MICROWIRE™/DSP Compatible
AV
DD
REF
IN
V
0
IN
T/H
•
•
•
•
•
•
•
•
•
•
•
•
•
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
I/P
MUX
Shutdown Mode: 0.5 A Max
V
7
20-Lead TSSOP Package
IN
SCLK
DOUT
DIN
CONTROL LOGIC
SEQUENCER
CS
GENERAL DESCRIPTION
The AD7927 is a 12-bit, high speed, low power, 8-channel,
successive-approximation ADC. The part operates from a single
2.7 V to 5.25 V power supply and features throughput rates up
to 200 kSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 8 MHz.
AD7927
V
DRIVE
GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption.
The AD7927 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7927
dissipates 3.6 mW of power maximum.
The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is also
initiated at this point. There are no pipeline delays associated
with the part.
2. Eight Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels, through which the ADC
will cycle and convert on, can be selected.
The AD7927 uses advanced design techniques to achieve very low
power dissipation at maximum throughput rates. At maximum
throughput rates, the AD7927 consumes 1.2 mA maximum
with 3 V supplies; with 5 V supplies, the current consumption is
1.5 mA maximum.
3. Single-Supply Operation with VDRIVE Function.
The AD7927 operates from a single 2.7 V to 5.25 V supply. The
VDRIVE function allows the serial interface to connect directly
to either 3 V or 5 V processor systems independent of AVDD
.
Through the configuration of the Control Register, the analog
input range for the part can be selected as 0 V to REFIN or 0 V to
2 ¥ REFIN, with either straight binary or twos complement output
coding. The AD7927 features eight single-ended analog inputs
with a channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The part also features various shutdown modes
to maximize power efficiency at lower throughput rates. Current
consumption is 0.5 mA maximum when in full shutdown.
The conversion time for the AD7927 is determined by the SCLK
frequency, as this is also used as the master clock to control the
conversion. The conversion time may be as short as 800 ns with
a 20 MHz SCLK.
5. No Pipeline Delay.
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless
AD7927–SPECIFICATIONS otherwise noted.)
Parameter
B Version1
Unit
Test Conditions/Comments
IN = 50 kHz Sine Wave, fSCLK = 20 MHz
@ 5 V
DYNAMIC PERFORMANCE
f
Signal-to-(Noise + Distortion) (SINAD)2
70
69
70
–77
–73
–78
–76
dB min
dB min
dB min
dB max
dB max
dB max
dB max
@ 3 V Typically 70 dB
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
@ 5 V Typically –84 dB
@ 3 V Typically –77 dB
@ 5 V Typically –86 dB
@ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz
Peak Harmonic or Spurious Noise
(SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
–90
–90
10
dB typ
dB typ
ns typ
Aperture Delay
Aperture Jitter
50
ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
–82
8.2
1.6
dB typ
MHz typ
MHz typ
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
12
± 1
–0.9/+1.5
Bits
LSB max
LSB max
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Typically ± 0.5 LSB
± 8
LSB max
LSB max
LSB max
LSB max
Offset Error Match
Gain Error
Gain Error Match
± 0.5
± 1.5
± 0.5
0 V to 2 ¥ REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
–REFIN to +REFIN Biased about REFIN with
Twos Complement Output Coding
± 1.5
± 0.5
± 8
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Typically ± 0.8 LSB
± 0.5
± 1
± 0.5
ANALOG INPUT
Input Voltage Ranges
0 to REFIN
V
RANGE Bit Set to 1
0 to 2 ¥ REFIN
V
RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
± 1
mA max
pF typ
20
fSAMPLE = 200 kSPS
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
2.5
± 1
36
V
± 1% Specified Performance
mA max
kW typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 ¥ VDRIVE
V min
0.3 ¥ VDRIVE
V max
mA max
pF max
± 1
10
Typically 10 nA, VIN = 0 V or VDRIVE
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDRIVE – 0.2
V min
ISOURCE = 200 mA, AVDD = 2.7 V to 5.25 V
ISINK = 200 mA
0.4
± 1
10
V max
mA max
pF max
Straight (Natural) Binary
Twos Complement
Coding Bit Set to 1
Coding Bit Set to 0
–2–
REV. 0
AD7927
Parameter
B Version1 Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
800
300
300
200
ns max
ns max
ns max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
Throughput Rate
kSPS max See Serial Interface Section
POWER REQUIREMENTS
AVDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
4
IDD
Digital I/Ps = 0 V or VDRIVE
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 2.7 V to 5.25 V, SCLK On or Off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
SCLK On or Off (20 nA typ)
During Conversion
2.7
2
600
mA max
mA max
mA typ
mA max
mA max
mA typ
mA typ
mA max
mA max
Normal Mode (Static)
Normal Mode (Operational) fSAMPLE = 200 kSPS 1.5
1.2
Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900
650
Auto Shutdown (Static)
Full Shutdown Mode
0.5
0.5
SCLK On or Off (20 nA typ)
Power Dissipation4
Normal Mode (Operational)
7.5
3.6
2.5
1.5
2.5
1.5
mW max
mW max
mW max
mW max
mW max
mW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
Auto Shutdown (Static)
Full Shutdown Mode
AVDD = 3 V
NOTES
1Temperature ranges as follows: B Version: –40∞C to +85∞C.
2See Terminology section.
3Sample tested @ 25∞C to ensure compliance.
4See Power versus Throughput Rate section.
Specifications subject to change without notice.
REV. 0
–3–
AD7927
TIMING SPECIFICATIONS1 (AVDD = 2.7 V to 5.25 V, VDRIVE Յ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX AD7927
Parameter
AVDD = 3 V
AVDD = 5 V
Unit
Description
2
fSCLK
10
10
kHz min
20
20
MHz max
tCONVERT
tQUIET
16 ¥ tSCLK
50
16 ¥ tSCLK
50
ns min
Minimum Quiet Time Required between CS Rising Edge
and Start of Next Conversion
t23
t33
t4
t5
t6
10
35
40
10
30
40
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
ms max
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
0.4 ¥ tSCLK
0.4 ¥ tSCLK
0.4 ¥ tSCLK
0.4 ¥ tSCLK
SCLK High Pulsewidth
t74
10
15/45
10
5
20
1
10
15/35
10
5
20
1
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto
Shutdown Mode
t8
t9
t10
t11
t12
NOTES
1Sample tested at 25∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ VDRIVE
.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the timing characteristics t8, is the true bus relinquish time
of the part and is independent of the bus loading.
Specifications subject to change without notice.
I
200A
OL
TO
OUTPUT
PIN
1.6V
C
50pF
L
I
200A
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
AD7927
ABSOLUTE MAXIMUM RATINGS1
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
(TA = 25∞C, unless otherwise noted.)
q
JA Thermal Impedance . . . . . . . . . . . . . . 143∞C/W (TSSOP)
JC Thermal Impedance . . . . . . . . . . . . . . . 45∞C/W (TSSOP)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
q
VDRIVE to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option
Package
Description
Model
Error (LSB)1
AD7927BRU
–40∞C to +85∞C
± 1
RU-20
TSSOP
Evaluation Board
Controller Board
EVAL-AD7927CB2
EVAL-CONTROL BRD23
NOTES
1 Linearity error here refers to integral linearity error.
2 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.
3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7927CB, the EVAL-CONTROL
BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7927 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD7927
PIN CONFIGURATION
20-Lead TSSOP
SCLK
DIN
1
2
20 AGND
19
V
DRIVE
3
18 DOUT
17 AGND
CS
AD7927
AGND
4
TOP VIEW
(Not to Scale)
AV
AV
5
16
15
14
13
12
11
V 0
IN
DD
DD
6
V 1
IN
REF
IN
7
V 2
IN
AGND
8
V 3
IN
V
7
9
V 4
IN
IN
V
6
10
V 5
IN
IN
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7927s conversion process.
2
3
DIN
Data In. Logic input. Data to be written to the AD7927s Control Register is provided on this input
and is clocked into the register on the falling edge of SCLK (see the Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7927 and framing the serial data transfer.
CS
4, 8, 17, 20 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input
signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.
5, 6
7
AVDD
Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the
0 V to 2 ¥ REFIN range, AVDD should be from 4.75 V to 5.25 V.
Reference Input for the AD7927. An external reference must be applied to this input. The voltage
range for the external reference is 2.5 V ± 1% for specified performance.
REFIN
16–9
V
IN0–VIN
7
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the
address bits ADD2 through ADD0 of the Control Register. The address bits in conjunction with the
SEQ and SHADOW bits allow the sequencer to be programmed. The input range for all input channels
can extend from 0 V to REFIN or 0 V to 2 ¥ REFIN, as selected via the RANGE bit in the Control Register.
Any unused input channels should be connected to AGND to avoid noise pickup.
18
19
DOUT
Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7927 consists of two leading zeros, two address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be
selected as straight binary or twos complement via the CODING bit in the Control Register.
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface
of the AD7927 will operate.
–6–
REV. 0
AD7927
TERMINOLOGY
Negative Gain Error Match
Integral Nonlinearity
This is the difference in Negative Gain Error between any two
channels.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero-scale, a point 1 LSB
below the first code transition, and full-scale, a point 1 LSB
above the last code transition.
Channel-to-Channel Isolation
Channel-to-Channel Isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 400 kHz
sine wave signal to all seven nonselected input channels and deter-
mining how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure is given worst case across all
eight channels for the AD7927.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
PSR (Power Supply Rejection)
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Characteristics.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
Track-and-Hold Acquisition Time
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the
offset error has been adjusted out.
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ± 1 LSB, after the end of conversion.
Gain Error Match
This is the difference in gain error between any two channels.
Signal-to-(Noise + Distortion) Ratio
Zero Code Error
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the midscale transition (all 0s to all 1s) from the ideal VIN volt-
age, i.e., REFIN – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two
channels.
Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB
Positive Gain Error
Thus for a 12-bit converter, this is 74 dB.
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REFIN
to +REFIN biased about the REFIN point. It is the deviation of
the last code transition (011. . .110) to (011 . . . 111) from the
ideal (i.e., +REFIN – 1 LSB) after the Zero Code Error has been
adjusted out.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7927, it is defined as:
V22 +V32 +V42 +V52 +V62
THD(dB) = 20log
V
1
Positive Gain Error Match
This is the difference in Positive Gain Error between any two
channels.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 ¥ REFIN input range with –REF IN
to +REFIN biased about the REFIN point. It is the deviation of
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has
been adjusted out.
REV. 0
–7–
AD7927–Typical Performance Characteristics
PERFORMANCE CURVES
TPC 4 shows a graph of total harmonic distortion versus analog
TPC 1 shows a typical FFT plot for the AD7927 at 200 kSPS
sample rate and 50 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 200 kSPS
with an SCLK of 20 MHz.
input frequency for various supply voltages, while TPC 5 shows
a graph of total harmonic distortion versus analog input frequency
for various source impedances. See the Analog Input section.
TPC 6 and TPC 7 show typical INL and DNL plots for the
AD7927.
TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7927 with no decoupling. The power
supply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency f, to the power of a 200 mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:
0
AV = 5V
DD
200mV p-p SINEWAVE ON AV
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
REF = 2.5V, 1F CAPACITOR
IN
T
= 25؇C
A
PSRR(dB) = 10log(Pf/Pfs)
Pf is equal to the power at frequency f in ADC output; PfS is equal
to the power at frequency fS coupled onto the ADC AVDD supply.
Here a 200 mV p-p sine wave is coupled onto the AVDD supply.
4096 POINT FFT
AV = 4.75V
DD
fSAMPLE = 200kSPS
fIN = 50kHz
SINAD = 70.714dB
THD = ؊82.853dB
SFDR = ؊84.815dB
–10
0
20
40
60
80
100 120 140 160 180 200
–30
–50
–70
SUPPLY RIPPLE FREQUENCY – kHz
TPC 3. PSRR vs. Supply Ripple Frequency
–50
fSAMPLE = 200kSPS
= 25؇C
T
A
–55
–60
–65
–70
–75
–80
–85
–90
RANGE = 0TO REF
IN
–90
–110
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY – kHz
AV =V
DD
= 2.7V
DRIVE
TPC 1. Dynamic Performance at 200 kSPS
AV =V
DD
= 3.6V
DRIVE
75
70
65
60
AV =V
= 5.25V
DD
DRIVE
DRIVE
AV =V
DD
= 4.75V
DRIVE
AV =V
AV =V
= 4.75V
DD
= 5.25V
DRIVE
DD
10
100
INPUT FREQUENCY – kHz
AV =V
= 3.6V
= 2.7V
DD
DRIVE
DRIVE
TPC 4. THD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS
AV =V
DD
–55
fSAMPLE = 200kSPS
T
= 25؇C
A
fSAMPLE = 200kSPS
= 25؇C
–60
–65
–70
–75
–80
–85
–90
–95
AV = 5.25V
DD
T
A
RANGE = 0TO REF
RANGE = 0TO REF
IN
IN
0
100
INPUT FREQUENCY – kHz
R
= 1000⍀
IN
TPC 2. SINAD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS
R
= 10⍀
R
= 100⍀
IN
IN
R
= 50⍀
IN
10
100
INPUT FREQUENCY – kHz
TPC 5. THD vs. Analog Input Frequency for Various
Source Impedances
–8–
REV. 0
AD7927
1.0
0.8
1.0
0.8
AV =V
DD
= 5V
DRIVE
TEMP = 25؇C
AV =V
DD
= 5V
DRIVE
TEMP = 25؇C
0.6
0.4
0.6
0.4
0.2
0
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.4
–0.6
–0.8
–1.0
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584 4096
CODE
CODE
TPC 7. Typical DNL
TPC 6. Typical INL
CONTROL REGISTER
The Control Register on the AD7927 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7927 on the falling
edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data
transferred on the DIN line corresponds to the AD7927 configuration for the next conversion. This requires 16 serial clocks for every
data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register.
MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
Table I. Control Register Bit Functions
MSB
LSB
WRITE
SEQ DONTC ADD2 ADD1 ADD0 PM1
PM0 SHADOW DONTC RANGE
CODING
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded
to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register; if it is
a 0, then the remaining 11 bits are not loaded to the Control Register and it remains unchanged.
10
SEQ
The SEQ bit in the Control Register is used in conjunction with the SHADOW bit to control the use of the
sequencer function and access the Shadow Register. (See Table IV.)
9
DONTC
Don’t Care
8–6
ADD2–ADD0 These three address bits are loaded at the end of the present conversion and select which analog input channel
is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence
as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits
corresponding to the conversion result are also output on DOUT prior to the 12 bits of data. (See the Serial
Interface section.) The next channel to be converted on will be selected by the mux on the 14th SCLK
falling edge.
5, 4
3
PM1, PM0
SHADOW
Power Management Bits. These two bits decode the mode of operation of the AD7927 as shown in Table III.
The SHADOW bit in the Control Register is used in conjunction with the SEQ bit to control the use of the
sequencer function and access the Shadow Register. (See Table IV.)
2
1
DONTC
RANGE
Don’t Care
This bit selects the analog input range to be used on the AD7927. If it is set to 0, the analog input range
will extend from 0 V to 2 ¥ REFIN. If it is set to 1, the analog input range will extend from 0 V to REFIN
(for the next conversion). For the 0 V to 2 ¥ REFIN range, AVDD = 4.75 V to 5.25 V.
0
CODING
This bit selects the type of output coding the AD7927 will use for the conversion result. If this bit is set to
0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the
part will be straight binary (for the next conversion).
REV. 0
–9–
AD7927
Table II. Channel Selection
ADD2
ADD1
ADD0
Analog Input Channel
IN0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V
VIN
VIN
VIN
VIN
VIN
VIN
VIN
1
2
3
4
5
6
7
Table III. Power Mode Selection
PM1 PM0 Mode
1
1
Normal Operation. In this mode, the AD7927 remains in full power mode, regardless of the status of any of the logic
inputs. This mode allows the fastest possible throughput rate from the AD7927.
1
0
Full Shutdown. In this mode, the AD7927 is in full shutdown mode with all circuitry on the AD7927 powering down.
The AD7927 retains the information in the Control Register while in full shutdown. The part remains in full shutdown
until these bits are changed.
0
0
1
0
Auto Shutdown. In this mode, the AD7927 automatically enters full shutdown mode at the end of each conversion
when the Control Register is updated. Wake-up time from full shutdown is 1 ms and the user should ensure that 1ms
has elapsed before attempting to perform a valid conversion on the part in this mode.
Invalid Selection. This configuration is not allowed.
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the
Control Register allows the user to select a particular mode of
operation of the sequencer function. Table IV outlines the four
modes of operation of the sequencer.
Table IV. Sequence Selection
SEQ SHADOW Sequence Type
0
0
This configuration means that the sequence function is not used. The analog input channel selected for each
individual conversion is determined by the contents of the channel address bits ADD0 through ADD2 in each
prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without
the sequencer function being used, where each write to the AD7927 selects the next channel for conversion. (See
Figure 2.)
0
1
This configuration selects the Shadow Register for programming. The following write operation will load the
contents of the Shadow Register. This will program the sequence of channels to be converted on continuously with
each successive valid CS falling edge. (See Shadow Register, Table V, and Figure 3.) The channels selected need
not be consecutive.
1
1
0
1
If the SEQ and SHADOW bits are set in this way, the sequence function will not be interrupted upon completion
of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while
in a sequence, without terminating the cycle.
This configuration is used in conjunction with the channel address bits ADD2 to ADD0 to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the
channel address bits in the Control Register. (See Figure 4.)
–10–
REV. 0
AD7927
SHADOW REGISTER
which the AD7927 will cycle with each consecutive conversion
after the write to the Shadow Register. Sequence One will be
performed first and then Sequence Two. If the user does not
wish to preform a second sequence option, then all 0s must be
written to the last eight LSBs of the Shadow Register. To select
a sequence of channels, the associated channel bit must be set for
each analog input. The AD7927 will continuously cycle through
the selected channels in ascending order, beginning with the
lowest channel, until a write operation occurs (i.e., the WRITE bit
is set to 1) with the SEQ and SHADOW bits configured in any
way except 1,0. (See Table IV.) The bit functions are outlined
in Table V.
The Shadow Register on the AD7927 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7927 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time that a conversion result is read from the part. This
requires 16 serial clock falling edges for the data transfer. The
information is clocked into the Shadow Register, provided that the
SEQ and SHADOW bits were set to 0,1, respectively, in the
previous write to the Control Register. MSB denotes the first bit
in the data stream. Each bit represents an analog input from
Channel 0 to Channel 7. Through programming the Shadow
Register, two sequences of channels may be selected, through
Table V. Shadow Register Bit Functions
VIN5 VIN6 VIN7 VIN0 VIN1 VIN2
MSB
VIN0
LSB
VIN6 VIN7
VIN1 VIN2
VIN3
VIN4
VIN3
VIN4
VIN5
------------------SEQUENCE ONE-------------------------------------------------------SEQUENCE TWO-----------------------
POWER-ON
POWER-ON
DUMMY CONVERSION
DIN = ALL 1s
DUMMY CONVERSION
DIN = ALL 1s
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
CS
CS
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 0 SHADOW = 1
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2–A0.
DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2–A0.
CS
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
CS
WRITE BIT = 1,
DIN: WRITE TO SHADOW REGISTER, SELECTING
WHICH CHANNELS TO CONVERT ON; CHANNELS
SELECTED NEED NOT BE CONSECUTIVE CHANNELS
SEQ = SHADOW = 0
SELECT CODING, RANGE, AND POWER MODE.
SELECT A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0
WRITE BIT = 0
WRITE BIT = 1
SEQ = 1 SHADOW = 0
Figure 2. SEQ Bit = 0, SHADOW Bit = 0 Flowchart
CONTINUOUSLY
CONVERTS ON THE
SELECTED
CONTINUOUSLY
CONVERTS ON THE
SELECTED
Figure 2 reflects the traditional operation of a multichannel ADC,
where each serial transfer selects the next channel for conversion.
In this mode of operation, the sequencer function is not used.
CS
SEQUENCE OF
CHANNELS
SEQUENCE OF
CHANNELS BUT
WILL ALLOW RANGE,
CODING, AND SO ON,
TO CHANGE IN THE
CONTROL REGISTER
WITHOUT INTERRUPT-
ING THE SEQUENCE,
PROVIDED SEQ = 1
SHADOW = 0
Figure 3 shows how to program the AD7927 to continuously
convert on a particular sequence of channels. To exit this mode
of operation and revert back to the traditional mode of operation
of a multichannel ADC (as outlined in Figure 2), ensure that the
WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial
transfer. Figure 4 shows how a sequence of consecutive chan-
nels can be converted on without having to program the Shadow
Register or write to the part on each serial transfer. Again, to exit
this mode of operation and revert back to the traditional mode
of operation of a multichannel ADC (as outlined in Figure 2),
ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on
the next serial transfer.
WRITE BIT = 0
WRITE BIT = 0
WRITE BIT = 1,
SEQ = 1,
SHADOW = 0
Figure 3. SEQ Bit = 0, SHADOW Bit = 1 Flowchart
REV. 0
–11–
AD7927
CAPACITIVE
DAC
POWER-ON
DUMMY CONVERSION
DIN = ALL 1s
A
4k⍀
V
0
7
IN
CONTROL
LOGIC
SW1
B
SW2
DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
V
IN
COMPARATOR
CS
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 1 SHADOW = 1
AGND
Figure 5. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 6), SW2 will
open and SW1 will move to position B, causing the comparator
to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 8 and 9 show the ADC transfer functions.
DOUT: CONVERSION RESULT FROM CHANNEL 0
CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A2–A0 IN THE CONTROL REGISTER
CS
WRITE BIT = 0
CAPACITIVE
DAC
CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING AND SO ON, TO CHANGE IN THE
CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0
CS
A
4k⍀
V
0
.
.
WRITE BIT = 1,
SEQ = 1,
IN
CONTROL
LOGIC
SW1
B
SW2
SHADOW = 0
V
7
IN
COMPARATOR
Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart
AGND
CIRCUIT INFORMATION
Figure 6. ADC Conversion Phase
The AD7927 is a high speed, 8-channel, 12-bit, single supply,
A/D converter. The part can be operated from a 2.7 V to 5.25 V
supply. When operated from either a 5 V or 3 V supply, the AD7927
is capable of throughput rates of 200 kSPS. The conversion time
may be as short as 800 ns when provided with a 20 MHz clock.
Analog Input
Figure 7 shows an equivalent circuit of the analog input structure
of the AD7927. The two diodes D1 and D2 provide ESD pro-
tection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 300 mV. This will cause these diodes to become forward
biased and start conducting current into the substrate. 10 mA is
the maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 7 is
typically about 4 pF and can primarily be attributed to pin capaci-
tance. The resistor R1 is a lumped component made up of the on
resistance of a switch (track-and-hold switch) and also includes
the on resistance of the input multiplexer. The total resistance is
typically about 400 W. The capacitor C2 is the ADC sampling
capacitor and has a capacitance of 30 pF typically. For ac appli-
cations, removing high frequency components from the analog
input signal is recommended by use of an RC low-pass filter on
the relevant analog input pin. In applications where harmonic
distortion and signal to noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances will significantly affect the ac performance of the ADC.
This may necessitate the use of an input buffer amplifier. The
choice of the op amp will be a function of the particular application.
The AD7927 provides the user with an on-chip track-and-hold,
A/D converter, and a serial interface housed in a 20-lead TSSOP
package. The AD7927 has eight single-ended input channels
with a channel sequencer, allowing the user to select a channel
sequence through which the ADC can cycle with each consecu-
tive CS falling edge. The serial clock input accesses data from
the part, controls the transfer of data written to the ADC, and
provides the clock source for the successive-approximation A/D
converter. The analog input range for the AD7927 is 0 V to
REFIN or 0 V to 2 ¥ REFIN, depending on the status of Bit 1 in
the Control Register. For the 0 to 2 ¥ REFIN range, the part
must be operated from a 4.75 V to 5.25 V supply.
The AD7927 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming the
Power Management bits, PM1 and PM0, in the Control Register.
CONVERTER OPERATION
The AD7927 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7927
can convert analog input signals in the range 0 V to REFIN or 0 V
to 2 ¥ REFIN. Figures 5 and 6 show simplified schematics of the
ADC. The ADC is comprised of Control Logic, SAR, and a
Capacitive DAC that are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. Figure 5 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in position A.
The comparator is held in a balanced condition and the sampling
capacitor acquires the signal on the selected VIN channel.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases, and performance will degrade. (See TPC 5.)
AV
DD
C2
D1
D2
30pF
R1
V
IN
C1
4pF
CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED
Figure 7. Equivalent Analog Input Circuit
–12–
REV. 0
AD7927
ADC TRANSFER FUNCTION
size is REFIN/4096 for the AD7927. The ideal transfer charac-
teristic for the AD7927 when straight binary coding is selected
is shown in Figure 8, and the ideal transfer characteristic for the
AD7927 when twos complement coding is selected is shown in
Figure 9.
The output coding of the AD7927 is either straight binary or
twos complement, depending on the status of the LSB in the
Control Register. The designed code transitions occur at suc-
cessive LSB values (i.e., 1 LSB, 2 LSBs, and so forth). The LSB
011…111
111…111
111…110
011…110
•
•
•
•
000…001
111…000
000…000
111…111
•
•
•
011…111
1LSB
؍
V /4096
REF
•
•
1LSB
؍
2 ؋
V ր4096
REF
100…010
100…001
100…000
000…010
000…001
000…000
–V
REF
؉ 1LSB
+V
REF
؊ 1LSB
1 LSB
+V
REF
؊ 1 LSB
0V
V
REF
؊ 1LSB
ANALOG INPUT
IS EITHER REF OR 2
؋
REF IN
ANALOG INPUT
NOTE: V
REF
IN
Figure 9. Twos Complement Transfer Characteristic with
REFIN ± REFIN Input Range
Figure 8. Straight Binary Transfer Characteristic
V
DD
V
REF
0.1F
AV
DD
REF
IN
V
DD
V
DRIVE
R4
R1
AD7927
DSP/P
V
R3
R2
TWOS
COMPLEMENT
V
0
DOUT
IN
V
0V
011…111
000…000
100…000
(= 2
؋
REF )
IN
+REF
IN
V
7
IN
R1
؍
R2 ؍
R3 ؍
R4 REF
IN
(= 0V)
–REF
IN
Figure 10. Handling Bipolar Signals
Handling Bipolar Input Signals
leading zero, three address bits indicating which channel the
conversion result corresponds to, followed by the 12 bits of
conversion data. For applications where power consumption is
of concern, the power-down modes should be used between
conversions or bursts of several conversions to improve power
performance. (See the Modes of Operation section.)
Figure 10 shows how useful the combination of the 2 ¥ REFIN
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal is
biased about REFIN and twos complement output coding is
selected, then REFIN becomes the zero code point, –REFIN is
negative full scale and +REFIN becomes positive full scale, with
5V
SUPPLY
a dynamic range of 2 ¥ REFIN
.
SERIAL
INTERFACE
0.1F
10F
TYPICAL CONNECTION DIAGRAM
Figure 11 shows a typical connection diagram for the AD7927.
In this setup, the AGND pin is connected to the analog ground
plane of the system. In Figure 11, REFIN is connected to a
decoupled 2.5 V supply from a reference source, the AD780, to
provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1)
or 0 V to 5 V (if RANGE bit is 0). Although the AD7927 is con-
nected to a AVDD of 5 V, the serial interface is connected to a 3 V
microprocessor. The VDRIVE pin of the AD7927 is connected to
the same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section). The conversion result is
output in a 16-bit word. This 16-bit data stream consists of one
AV
DD
V
0
•
•
SCLK
DOUT
CS
IN
0VTO REF
IN
C/P
AD7927
V
7
IN
AGND
DIN
REF
V
DRIVE
IN
0.1F
10F
0.1F
2.5V
AD780
3V
SUPPLY
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTEDTO AGND
Figure 11. Typical Connection Diagram
REV. 0
–13–
AD7927
Analog Input Selection
to easily interface to both 3 V and 5 V processors. For example,
if the AD7927 were operated with an AVDD of 5 V, the VDRIVE
pin could be powered from a 3 V supply. The AD7927 has a
larger dynamic range with an AVDD of 5 V while still being
able to interface to 3 V processors. Care should be taken to
ensure VDRIVE does not exceed AVDD by more than 0.3 V. (See
Absolute Maximum Ratings.)
Any one of eight analog input channels may be selected for
conversion by programming the multiplexer with the address bits
ADD2 though ADD0 in the Control Register. The channel con-
figurations are shown in Table II.
The AD7927 may also be configured to automatically cycle through
a number of channels as selected. The sequencer feature is
accessed via the SEQ and SHADOW bits in the Control Register
(see Table IV). The AD7927 can be programmed to continuously
convert on a selection of channels in ascending order. The analog
input channels to be converted on are selected through program-
ming the relevant bits in the Shadow Register (see Table V).
The next serial transfer will then act on the sequence programmed
by executing a conversion on the lowest channel in the selection.
The next serial transfer will result in the conversion on the next
highest channel in the sequence, and so on.
The Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7927. Errors in the reference source will result
in gain errors in the AD7927 transfer function and will add to the
specified full-scale errors of the part. A capacitor of at least 0.1 mF
should be placed on the REFIN pin. Suitable reference sources for
the AD7927 include the AD780, REF 193, and the AD1582.
If 2.5 V is applied to the REFIN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.
It is not necessary to write to the Control Register once a sequencer
operation has been initiated. The WRITE bit must be set to
zero or the DIN line tied low to ensure that the Control Register
is not accidently overwritten, or the sequence operation inter-
rupted. If the Control Register is written to at any time during
the sequence, the user must ensure that the SEQ and SHADOW
bits are set to 1,0 to avoid interrupting the automatic conversion
sequence. This pattern will continue until such time as the AD7927
is written to and the SEQ and SHADOW bits are configured with
any bit combination except 1,0. On completion of the sequence,
the AD7927 sequencer will return to the first selected channel
in the Shadow Register and commence the sequence again.
MODES OF OPERATION
The AD7927 has a number of different modes of operation,
which are designed to provide flexible power management options.
These options can be chosen to optimize the power dissipation/
throughput rate ratio for differing application requirements. The
mode of operation of the AD7927 is controlled by the power
management bits, PM1 and PM0, in the Control Register, as
detailed in Table III. When power supplies are first applied to
the AD7927, care should be taken to ensure that the part is
placed in the required mode of operation. (See the Powering
Up the AD7927 section.)
Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with Channel 0 may also be
programmed via the Control Register alone without needing to
write to the Shadow Register. This is possible if the SEQ and
SHADOW bits are set to 1,1. The channel address bits ADD2
through ADD0 will then determine the final channel in the con-
secutive sequence. The next conversion will be on Channel 0,
then Channel 1, and so on until the channel selected via the ad-
dress bits ADD2 through ADD0 is reached. The cycle will begin
again on the next serial transfer provided the WRITE bit is set
to low, or if high, that the SEQ and SHADOW bits are set to
1,0; then the ADC will continue its preprogrammed automatic
sequence uninterrupted.
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance as the user does not have to worry about any power-up
times with the AD7927 remaining fully powered at all times.
Figure 12 shows the general diagram of the operation of the
AD7927 in this mode.
The conversion is initiated on the falling edge of CS and the track
and hold will enter hold mode as described in the Serial Interface
section. The data presented to the AD7927 on the DIN line during
the first 12 clock cycles of the data transfer are loaded into the
Control Register (provided WRITE bit is 1). If data is to be
written to the Shadow Register (SEQ = 0, SHADOW = 1 on
previous write), data presented on the DIN line during the first
16 SCLK cycles is loaded into the Shadow Register. The part
will remain fully powered up in Normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in Normal mode, PM1 and PM0 are both loaded with 1 on every
data transfer. Sixteen serial clock cycles are required to complete
the conversion and access the conversion result. The track and
hold will go back into track on the 14th SCLK falling edge. CS
may then idle high until the next conversion or may idle low until
sometime prior to the next conversion (effectively idling CS low).
Regardless of which channel selection method is used, the 16-bit
word output from the AD7927 during each conversion will
always contain one leading zero, three channel address bits
that the conversion result corresponds to, followed by the 12-bit
conversion result. (See the Serial Interface section.)
Digital Inputs
The digital inputs applied to the AD7927 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the AVDD
+ 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the AVDD + 0.3 V limit is that possible power supply sequencing
issues are avoided. If CS, DIN, or SCLK are applied before
AVDD, there is no risk of latch-up as there would be on the analog
For specified performance, the throughput rate should not exceed
200 kSPS, which means there should be no less than 5 ms between
consecutive falling edges of CS when converting. The actual
frequency of SCLK used will determine the duration of the
conversion within this 5 ms cycle; however, once a conversion is
complete and CS has returned high, a minimum of the quiet
time, tquiet, must elapse before bringing CS low again to initiate
another conversion.
inputs if a signal greater than 0.3 V was applied prior to AVDD
.
VDRIVE
The AD7927 also has the VDRIVE feature. VDRIVE controls the voltage
at which the serial interface operates. VDRIVE allows the ADC
–14–
REV. 0
AD7927
CS
SCLK
DOUT
will be read if a conversion is initiated before this time. Figure 13
shows the general diagram for this sequence.
1
16
12
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7927 automatically enters shutdown at the
end of each conversion when the Control Register is updated. When
the part is in shutdown, the track and hold is in Hold Mode.
Figure 14 shows the general diagram of the operation of the
AD7927 in this mode. In Shutdown Mode all internal circuitry on
the AD7927 is powered down. The part retains information in
the Control Register during shutdown. The AD7927 remains in
shutdown until the next CS falling edge it receives. On this CS
falling edge, the track and hold that was in hold while the part
was in shutdown will return to track. Wake-up time from auto
shutdown is 1 ms maximum, and the user should ensure that
1 ms has elapsed before attempting a valid conversion. When
running the AD7927 with a 20 MHz clock, one dummy 16 SCLK
transfer should be sufficient to ensure the part is fully powered
up. During this dummy transfer the contents of the Control
Register should remain unchanged; therefore the WRITE bit
should be 0 on the DIN line.
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA INTO CONTROL REGISTER/
SHADOW REGISTER
DIN
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES
Figure 12. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7927 is powered down.
The part retains information in the Control Register during full
shutdown. The AD7927 remains in full shutdown until the power
management bits in the Control Register, PM1 and PM0, are
changed.
If a write to the Control Register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, Normal Mode, the part will begin to power up on the
CS rising edge. The track and hold that was in hold while the
part was in full shutdown will return to track on the 14th SCLK
falling edge. A full 16 SCLK transfer must occur to ensure the
Control Register contents are updated; however, the DOUT
line will not be driven during this wake-up transfer.
Depending on the SCLK frequency used, this dummy transfer
may affect the achievable throughput rate of the part, with every
other data transfer being a valid conversion result. If, for example,
the maximum SCLK frequency of 20 MHz was used, the auto
shutdown mode could be used at the full throughput rate of
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and the
dummy transfer for wake-up.
To ensure that the part is fully powered up, tPOWER UP should have
elapsed before the next CS falling edge; otherwise, invalid data
PART IS IN FULL
SHUTDOWN
PART BEGINSTO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
THE PART IS FULLY POWERED UP
ONCE tPOWER UP HAS ELAPSED
t12
CS
1
14
16
1
14
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER/SHADOW REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEPTHE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 13. Full Shutdown Mode Operation
PART ENTERS
PART ENTERS
SHUTDOWN ON CS TO POWER
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 PART BEGINS
SHUTDOWN ON CS
RISING EDGE AS
PM1
؍
0, PM0 ؍
1 PART IS FULLY
POWERED UP
UP ON CS
FALLING EDGE
CS
DUMMY CONVERSION
12
1
12
16
1
16
1
12
16
SCLK
DOUT
DIN
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL/SHADOW REGISTER
CONTROL REGISTER IS LOADED ONTHE
FIRST 12 CLOCKS, PM1
؍
0, PM0 ؍
1 CONTROL REGISTER SHOULD NOT
CHANGE,WRITE BIT
؍
0 TO KEEP PART INTHIS MODE, LOAD PM1
؍
0, PM0 ؍
1 IN CONTROL REGISTER OR SETWRITE BIT = 0
Figure 14. Auto Shutdown Mode Operation
–15–
REV. 0
AD7927
CORRECTVALUE IN CONTROL
REGISTER,VALID DATA FROM
NEXT CONVERSION, USER CAN
WRITETO SHADOW REGISTER
IN NEXT CONVERSION
CS
SCLK
DOUT
DUMMY CONVERSION
12
DUMMY CONVERSION
12
1
16
1
16
1
12
16
INVALID DATA
INVALID DATA
INVALID DATA
DATA INTO CONTROL REGISTER
DIN
KEEP DIN LINETIED HIGH FOR FIRSTTWO DUMMY CONVERSIONS
CONTROL REGISTER IS LOADED ONTHE FIRST
12 CLOCK EDGES
Figure 15. To Place AD7927 into the Required Operating Mode after Supplies Are Applied
In this mode the power consumption of the part is greatly reduced
with the part entering shutdown at the end of each conversion.
When the Control Register is programmed to move into Auto
Shutdown, it does so at the end of the conversion. The user can
move the ADC in and out of the low power state by controlling
the CS signal.
800 ns but the cycle time is 5 ms when the sampling rate is at a
maximum of 200 kSPS. If the AD7927 is placed into shutdown
for the remainder of the cycle time, then on average far less
power will be consumed in every cycle compared to leaving the
device in Normal Mode. Furthermore, Figure 16 shows how as
the throughput rate is reduced, the part remains in its shutdown
longer and the average power consumption drops accordingly
over time.
Powering Up the AD7927
When supplies are first applied to the AD7927, the ADC may
power up in any of the operating modes of the part. To ensure that
the part is placed into the required operating mode, the user
should perform a dummy cycle operation as outlined in Figure 15.
For example, if the AD7927 is operated in a continuous sampling
mode, with a throughput rate of 200 kSPS and an SCLK of
20 MHz (AVDD = 5 V), and the device is placed in Auto Shutdown
Mode i.e., if PM1 = 0 and PM0 = 1, then the power consumption
is calculated as follows:
The three dummy conversion operation outlined in Figure 15
must be performed to place the part into the Auto Shutdown
Mode. The first two conversions of this dummy cycle operation
are performed with the DIN line tied high, and for the third con-
version of the dummy cycle operation, the user should write the
desired Control Register configuration to the AD7927 in order to
place the part into the Auto Shutdown mode. On the third CS
rising edge after the supplies are applied, the Control Register
will contain the correct information and valid data will result from
the next conversion.
The maximum power dissipation during the conversion time is
13.5 mW (IDD = 2.7 mA max, AVDD = 5 V). If the power-up time
from Auto Shutdown is 1 ms and the remaining conversion time
is another cycle, i.e., 800 ns, the AD7927 can be said to dissipate
13.5 mW for 1.8 ms during each conversion cycle. For the remain-
der of the conversion cycle, 3.2 ms, the part remains in Shutdown.
The AD7927 can be said to dissipate 2.5 mW for the remaining
3.2 ms of the conversion cycle. If the throughput rate is 200 kSPS,
the cycle time is 5 ms and the average power dissipated during each
cycle is (1.8/5) ¥ (13.5 mW) + (3.2/5) ¥ (2.5 mW) = 4.8616 mW.
Therefore, to ensure the part is placed into the correct operating
mode, when supplies are first applied to the AD7927, the user
must first issue two serial write operations with the DIN line tied
high, and on the third conversion cycle the user can then write
to the Control Register to place to part into any of the operating
modes. The user should not write to the Shadow Register until
the fourth conversion cycle after the supplies are applied to the
ADC, in order to guarantee the Control Register contains the
correct data.
Figure 16 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 3 V and 5 V supplies.
10
AV = 5V
DD
AV = 3V
DD
1
If the user wishes to place the part into either the Normal or
Full Shutdown Mode, the second dummy cycle with DIN tied
high can be omitted from the three dummy conversion operation
outlined in Figure 15.
0.1
POWER VERSUS THROUGHPUT RATE
In Auto Shutdown Mode, the average power consumption of the
ADC may be reduced at any given throughput rate. The power
saving will depend on the SCLK frequency used, i.e., conversion
time. In some cases where the conversion time is quite a propor-
tion of the cycle time, the throughput rate would need to be
reduced in order to take advantage of the power-down modes.
Assuming a 20 MHz SCLK is used, the conversion time is
0.01
0
20
40
60
80
100 120 140 160 180 200
THROUGHPUT – kSPS
Figure 16. Power vs. Throughput Rate
–16–
REV. 0
AD7927
SERIAL INTERFACE
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB,
i.e., the WRITE bit, has been set to 1. If the Control Register is
programmed to use the Shadow Register, then the writing of
information to the Shadow Register will take place on all 16 SCLK
falling edges in the next serial transfer as shown for example on the
AD7927 in Figure 18. Two sequence options can be programmed
in the Shadow Register. If the user does not want to program a
second sequence, then the eight LSBs should be filled with zeros.
The Shadow Register will be updated upon the rising edge of
CS and the track and hold will begin to track the first channel
selected in the sequence.
Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7927. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7927 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. The track and hold will
go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of CS, i.e., point C in Figure 18. On
the 16th SCLK falling edge the DOUT line will go back into
three-state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the DOUT line
will go back into three-state and the Control Register will not be
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 17. Sixteen serial clock
cycles are required to perform the conversion process and to
access data from the AD7927. For the AD7927, the 12 bits of
data are preceded by a leading zero and the three channel address
bits ADD2 to ADD0, identifying which channel the result corre-
sponds to. CS going low provides the leading zero to be read in by
the microcontroller or DSP. The three remaining address bits and
data bits are then clocked out by subsequent SCLK falling edges
beginning with the first address bit ADD2, thus the first falling
clock edge on the serial clock has a leading zero provided and
also clocks out address bit ADD2. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
The 16-bit word read from the AD7927 will always contain a
leading zero, three channel address bits that the conversion
result corresponds to, followed by the 12-bit conversion result.
Writing Between Conversions
As outlined in the Operating Modes section, not less than 5 ms
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at least
5 ms should always be left between CS falling edges. Consider the
case when writing to the AD7927 to power it up from shutdown
prior to a valid conversion. The user must write to the part to tell
it to power up before it can convert successfully. Once the serial
write to power up has finished, one may wish to perform the con-
version as soon as possible and not have to wait a further 5 ms
before bringing CS low for the conversion. In this case, as long
as there is a minimum of 5 ms between each valid conversion, then
only the quiet time between the CS rising edge at the end of the
write to power up and the next CS falling edge for a valid con-
version needs to be met. Figure 19 illustrates this point. Note
CS
tCONVERT
t6
tQUIET
B
t2
1
2
3
4
5
13
14
t5
15
16
t11
SCLK
t7
t3
t8
t4
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
DOUT
DIN
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
WRITE
SEQ
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
Figure 17. Serial Interface Timing Diagram
C
CS
tCONVERT
t6
t2
SCLK
1
2
3
4
5
13
14
t5
15
16
t11
t7
t3
t8
t4
DOUT
DIN
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-
STATE
3 IDENTIFICATION BITS
t9
t10
ZERO
V
0
V
1
V
2
V
3
V
4
V
5
V
5
V
6
V 7
IN
IN
IN
IN
IN
IN
IN
IN
IN
SEQUENCE 1
SEQUENCE 2
Figure 18. Writing to Shadow Register Timing Diagram
REV. 0
–17–
AD7927
tCYCLE5s MIN
tQUIET MIN
CS
1
16
1
16
1
16
SCLK
DOUT
DIN
VALID DATA
VALID DATA
POWER-UP
Figure 19. General Timing Diagram
that when writing to the AD7927 between these valid conversions,
the DOUT line will not be driven during the extra write operation,
as shown in Figure 19.
AD7927 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7927 without any glue logic required. The VDRIVE pin of
the AD7927 takes the same supply voltage as that of the
ADSP-218x. This allows the ADC to operate at a higher voltage
than the serial interface, i.e., ADSP-218x, if necessary.
It is critical that an extra write operation as outlined above is
never issued between valid conversions when the AD7927 is
executing through a sequence function, as the falling edge of CS
in the extra write would move the mux on to the next channel in
the sequence. This means when the next valid conversion takes
place, a channel result would have been missed.
The SPORT0 Control Register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
MICROPROCESSOR INTERFACING
The serial interface on the AD7927 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7927 with some of the
more common microcontroller and DSP serial interface protocols.
ITFS = 1
AD7927 to TMS320C541
The connection diagram is shown in Figure 21. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in Alter-
nate Framing Mode and the SPORT Control Register is set up as
described. The frame synchronization signal generated on the TFS
is tied to CS, and as with all signal processing applications equi-
distant sampling is necessary. However, in this example the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling may not be achieved.
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7927. The
CS input allows easy interfacing between the TMS320C541 and
the AD7927 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode with internal
CLKX0 (TX serial clock on serial port 0) and FSX0 (TX frame
sync from serial port 0). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1, and
TXM = 1. The connection diagram is shown in Figure 20. It
should be noted that for signal processing applications, it is impera-
tive that the frame synchronization signal from the TMS320C541
provides equidistant sampling. The VDRIVE pin of the AD7927
takes the same supply voltage as that of the TMS320C541. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., TMS320C541, if necessary.
ADSP-218x*
AD7927
*
SCLK
DOUT
CS
SCLK
DR
RFS
TFS
DT
DIN
V
DRIVE
TMS320C541*
AD7927
*
CLKX
SCLK
CLKR
DR
*ADDITIONAL PINS REMOVED FOR CLARITY
DOUT
V
DD
DT
DIN
Figure 21. Interfacing to the ADSP-218x
FSX
FSR
CS
V
DRIVE
V
DD
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 20. Interfacing to the TMS320C541
–18–
REV. 0
AD7927
The Timer register, for instance, is loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in the
SCLKDIV Register. When the instruction to transmit with TFS
is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low, and
High before transmission will start. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.
APPLICATION HINTS
Grounding and Layout
The AD7927 has very good immunity to noise on the power
supplies as can be seen by the PSRR vs. Supply Ripple Frequency
plot, TPC 3. However, care should still be taken with regard to
grounding and layout.
The printed circuit board that houses the AD7927 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally best for ground planes as it gives the best
shielding. All three AGND pins of the AD7927 should be sunk
in the AGND plane. Digital and analog ground planes should be
joined at only one place. If the AD7927 is in a system where
multiple devices require an AGND to DGND connection, the
connection should still be made at one point only, a star ground
point that should be established as close as possible to the AD7927.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV Register is loaded with the
value 3, then an SCLK of 5 MHz is obtained and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the Timer Registers are loaded
with the value, say 803, 100.5 SCLKs will occur between inter-
rupts and subsequently between transmit instructions. This
situation will result in non-equidistant sampling as the transmit
instruction is occurring on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, then
equidistant sampling will be implemented by the DSP.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed to
run under the AD7927 to avoid noise coupling. The power supply
lines to the AD7927 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, like clocks,
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and clock signals should never be
run near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at right
angles to each other. This will reduce the effects of feedthrough
through the board. A microstrip technique is by far the best but
is not always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes
while signals are placed on the solder side.
AD7927 to DSP563xx
The connection diagram in Figure 22 shows how the AD7927
can be connected to the ESSI (Synchronous Serial Interface) of
the DSP563xx family of DSPs from Motorola. Each ESSI (two on
board) is operated in Synchronous mode (SYN bit in CRB = 1)
with internally generated word length frame sync for both Tx
and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation
of the ESSI is selected by making MOD = 0 in the CRB. Set the
word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.
The FSP bit in the CRB should be set to 1 so the frame sync is
negative. It should be noted that for signal processing applica-
tions, it is imperative that the frame synchronization signal from
the DSP563xx provides equidistant sampling.
Good decoupling is also important. All analog supplies should be
decoupled with 10 mF tantalum in parallel with 0.1 mF capacitors
to AGND. To achieve the best from these decoupling components,
they must be placed as close as possible to the device, ideally
right up against the device. The 0.1 mF capacitors should have
low Effective Series Resistance (ESR) and Effective Series Induc-
tance (ESI), such as the common ceramic types or surface mount
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
In the example shown in Figure 22, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output, SCKD = 1.
The VDRIVE pin of the AD7927 takes the same supply voltage as
that of the DSP563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP563xx, if necessary.
Evaluating the AD7927 Performance
DSP563xx*
AD7927
*
The recommended layout for the AD7927 is outlined in the
evaluation board for the AD7927. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, and software for controlling the board from the
PC via the Eval-Board Controller. The Eval-Board Controller
can be used in conjunction with the AD7927 Evaluation board
as well as many other Analog Devices evaluation boards ending
in the CB designator to demonstrate/evaluate the ac and dc
performance of the AD7927.
SCK
SCLK
DOUT
SRD
STD
SC2
CS
DIN
V
DRIVE
*ADDITIONAL PINS REMOVED FOR CLARITY
V
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7927.
The software and documentation are on a CD shipped with the
evaluation board.
DD
Figure 22. Interfacing to the DSP563xx
REV. 0
–19–
AD7927
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8؇
0؇
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AC
–20–
REV. 0
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
相关型号：
AD7927BRUZ-REEL7
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20, ROHS COMPLIANT, MO-153AC, TSSOP-20
ROCHESTER
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