AD7938BCPZ [ADI]
8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer; 8通道， 1.5 MSPS ，具有序12位和10位并行ADC
| 型号： | AD7938BCPZ |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 文件： | 总36页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 1.5 MSPS, 12-Bit and 10-Bit
Parallel ADCs with a Sequencer
Data Sheet
AD7938/AD7939
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
AGND
DD
Throughput rate: 1.5 MSPS
Specified for VDD of 2.7 V to 5.25 V
Power consumption
AD7938/AD7939
V
REFIN/
V
REFOUT
2.5V
6 mW maximum at 1.5 MSPS with 3 V supplies
13.5 mW maximum at 1.5 MSPS with 5 V supplies
8 analog input channels with a sequencer
Software-configurable analog inputs
8-channel single-ended inputs
VREF
V
0
IN
IN
CLKIN
CONVST
BUSY
12-/10-BIT
SAR ADC
AND
I/P
MUX
T/H
CONTROL
V
7
4-channel fully differential inputs
4-channel pseudo differential inputs
7-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
SEQUENCER
V
PARALLEL INTERFACE/CONTROL REGISTER
DRIVE
0.2% maximum @ 25°C, 25 ppm/°C maximum
69 dB SINAD at 50 kHz input frequency
No pipeline delays
DB0 DB11
CS RD WR W/B
DGND
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA maximum
32-lead LFCSP and TQFP packages
Figure 1.
GENERAL DESCRIPTION
The AD7938/AD7939 are 12-bit and 10-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to
5.25 V power supply and feature throughput rates up to
1.5 MSPS. The parts contain a low noise, wide bandwidth,
differential track-and-hold amplifier that can handle input
frequencies up to 50 MHz.
These parts use advanced design techniques to achieve very
low power dissipation at high throughput rates. They also
feature flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
PRODUCT HIGHLIGHTS
The AD7938/AD7939 feature eight analog input channels with
a channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. These parts can operate
with either single-ended, fully differential, or pseudo
differential analog inputs.
1. High throughput with low power consumption.
2. Eight analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential, or fully differential
analog inputs that are software selectable.
5. Single-supply operation with VDRIVE function. The VDRIVE
function allows the parallel interface to connect directly to
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
3 V or 5 V processor systems independent of VDD
6. No pipeline delay.
.
CONVST
falling edge of
this point.
and the conversion is also initiated at
CONVST
7. Accurate control of the sampling instant via a
input and once-off conversion control.
The AD7938/AD7939 have an accurate on-chip 2.5 V reference
that can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
Table 1. Related Devices
Device
No. of Bits
No. of Channels
Speed
AD7933/AD7934 12/10
4
8
4
1.5 MSPS
625 kSPS
625 kSPS
AD7938-6
AD7934-6
12
12
Rev. C
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
AD7938/AD7939
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information........................................................................ 18
Converter Operation.................................................................. 18
ADC Transfer Function............................................................. 18
Typical Connection Diagram ................................................... 19
Analog Input Structure.............................................................. 19
Analog Inputs.............................................................................. 20
Analog Input Selection .............................................................. 22
Reference ..................................................................................... 23
Parallel Interface......................................................................... 25
Power Modes of Operation....................................................... 28
Power vs. Throughput Rate....................................................... 29
Microprocessor Interfacing....................................................... 29
Application Hints ........................................................................... 31
Grounding and Layout .............................................................. 31
PCB Design Guidelines for Chip Scale Package .................... 31
Evaluating AD7938/AD7939 Performance ............................ 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 33
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7938 Specifications................................................................. 3
AD7939 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 13
On-Chip Registers.......................................................................... 15
Control Register.......................................................................... 15
Sequencer Operation ................................................................. 16
Shadow Register.......................................................................... 17
REVISION HISTORY
Changes to Analog Input Structure Section ............................... 18
Changes to Analog Inputs Section............................................... 19
Changes to Figure 17...................................................................... 17
Changes to Figure 20...................................................................... 18
Changes to Figure 21...................................................................... 19
Changes to Figure 22...................................................................... 19
Changes to Figure 24...................................................................... 19
Changes to Figure 28...................................................................... 21
Changes to Figure 29...................................................................... 21
Changes to Figure 41...................................................................... 28
Changes to Figure 43...................................................................... 28
Changes to Figure 44...................................................................... 29
Changes to Figure 45...................................................................... 29
Changes to Figure 46...................................................................... 29
Updated Outline Dimensions....................................................... 31
Changes to Ordering Guide.......................................................... 32
10/11—Rev. B to Rev. C
Changes to SINAD Specification in Features Section ................. 1
Changes to AD7938 Specifications Section .................................. 3
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide .......................................................... 33
2/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Sequencer Operation Section................................... 16
Updated Outline Dimensions....................................................... 32
7/05—Rev. 0 to Rev. A
Changes to Specifications ................................................................ 3
Added Figure 3.................................................................................. 9
Changes to Table 5.......................................................................... 10
Updated Typical Performance Characteristics ........................... 13
Changes to Table 11........................................................................ 16
10/04—Revision 0: Initial Version
Rev. C | Page 2 of 36
Data Sheet
AD7938/AD7939
SPECIFICATIONS
AD7938 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, fCLKIN= 25.5 MHz, fSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Value1
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)2
69
dB min
dB min
dB min
dB min
dB max
dB max
dB max
67
71
Signal-to-Noise Ratio (SNR)2
69
Single-ended mode
Total Harmonic Distortion (THD)2
−73
−69.5
−72
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
fa = 30 kHz, fb = 50 kHz
−6
−90
−85
5
dB typ
dB typ
dB typ
ns typ
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fIN = 50 kHz, fNOISE = 300 kHz
Aperture Jitter2
72
ps typ
Full Power Bandwidth2
50
MHz typ
MHz typ
@ 3 dB
10
@ 0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity2
12
1
Bits
LSB max
LSB max
Differential mode
1.5
Single-ended mode
Differential Nonlinearity2
Differential Mode
Single-Ended Mode
Single-Ended and Pseudo Differential Input
Offset Error2
Offset Error Match2
Gain Error2
0.95
−0.95/+1.5
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
12
3
LSB max
LSB max
LSB max
LSB max
3
Gain Error Match2
2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Twos complement output coding
3
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
1.5
9.5
1
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
3
1.5
Single-Ended Input Range
0 to VREF
0 to 2 × VREF
V
V
RANGE bit = 0
RANGE bit = 1
Pseudo Differential Input Range
VIN+
0 to VREF
V
V
V typ
V typ
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VIN−
VDD = 5 V
Fully Differential Input Range
VIN+ and VIN−
VCM VREF/2
V
VCM = common-mode voltage3 = VREF/2
VIN+ and VIN−
VCM VREF
V
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
DC Leakage Current4
Input Capacitance
1
45
10
µA max
pF typ
pF typ
When in track
When in hold
Rev. C | Page 3 of 36
AD7938/AD7939
Data Sheet
Parameter
Value1
Unit
Test Conditions/Comments
1% for specified performance
0.2% max @ 25°C
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
2.5
1
2.5
25
5
10
130
10
15
25
V
DC Leakage Current
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
µA max
V
ppm/°C max
ppm/°C typ
µV typ
µV typ
Ω typ
VREF Noise
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
pF typ
pF typ
When in track
When in hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
µA max
pF typ
Typically 10 nA, VIN = 0 V or VDRIVE
4
10
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
10
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF typ
Straight (natural) binary
Twos complement
CODING bit = 0
CODING bit = 1
CONVERSION RATE
Conversion Time
t2 + 13 tCLKIN
ns
Track-and-Hold Acquisition Time
125
80
ns max
ns typ
MSPS max
Full-scale step input
Sine wave input
Throughput Rate
1.5
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
fSAMPLE = 100 kSPS, VDD = 5 V
Static
Normal Mode (Static)
Normal Mode (Operational)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
µA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
µA max
SCLK on or off
Normal Mode (Operational)
13.5
6
800
480
10
mW max
mW max
µW typ
µW typ
µW max
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode (Static)
6
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 For full common-mode range, see Figure 26 and Figure 27.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more information.
6 Measured with a midscale dc analog input.
Rev. C | Page 4 of 36
Data Sheet
AD7938/AD7939
AD7939 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, fCLKIN = 25.5 MHz, fSAMPLE= 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Value1
Unit
Test Conditions/Comments
fIN = 50 kHz sine wave
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)2
61
dB min
dB min
dB max
dB max
60
−70
−72
Single-ended mode
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−75
5
72
50
dB typ
dB typ
dB typ
ns typ
fIN = 50 kHz, fNOISe = 300 kHz
Aperture Jitter2
Full Power Bandwidth2
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Single-Ended and Pseudo Differential Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0.5
0.5
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Straight binary output coding
2
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Twos complement output coding
1.5
0.5
2
0.5
1.5
0.5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Single-Ended Input Range
0 to VREF
0 to 2 × VREF
V
V
RANGE bit = 0
RANGE bit = 1
Pseudo Differential Input Range
VIN+
0 to VREF
V
V
V typ
V typ
RANGE bit = 0
RANGE bit =1
VDD = 3 V
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VIN−
VDD = 5 V
Fully Differential Input Range
VIN+ and VIN−
VCM VREF/2
V
VCM = common-mode voltage3 = VREF/2
VIN+ and VIN−
VCM VREF
V
VCM = VREF, VIN+ or VIN− must remain within GND/VDD
DC Leakage Current4
1
45
10
µA max
pF typ
pF typ
Input Capacitance
When in track
When in hold
Rev. C | Page 5 of 36
AD7938/AD7939
Data Sheet
Parameter
Value1
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Current4
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
2.5
1
2.5
25
5
10
130
10
15
25
V
1% for specified performance
External reference applied to pin
0.2% max @ 25°C
µA max
V
ppm/°C max
ppm/°C typ
µV typ
µV typ
Ω typ
VREF Noise
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
pF typ
pF typ
When in track
When in hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
µA max
pF typ
Typically 10 nA, VIN = 0 V or VDRIVE
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
10
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF typ
Straight (natural) binary
Twos complement
CODING bit = 0
CODING bit =1
CONVERSION RATE
Conversion Time
t2 + 13 tCLKIN
ns
Track-and-Hold Acquisition Time
125
80
1.5
ns max
ns typ
MSPS max
Full-scale step input
Sine wave input
Throughput Rate
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital inputs = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
fSAMPLE = 100 kSPS, VDD = 5 V
Static
Normal Mode (Static)
Normal Mode (Operational)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
µA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
µA max
SCLK on or off
Normal Mode (Operational)
13.5
6
800
480
10
mW max
mW max
µW typ
µW typ
µW max
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode (Static)
6
1 Temperature range is −40°C to +85°C.
2 See the Terminology section.
3 For full common-mode range, see Figure 26 and Figure 27.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference section for more details.
6 Measured with a midscale dc analog input.
Rev. C | Page 6 of 36
Data Sheet
AD7938/AD7939
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to
MAX, unless otherwise noted.
T
Table 4.
Limit at TMIN, TMAX
Parameter1 AD7938 AD7939 Unit
Description
2
fCLKIN
700
25.5
30
700
25.5
30
kHz min
MHz max
ns min
CLKIN frequency.
tQUIET
Minimum time between end of read and start of next conversion; in other words, time
from when the data bus goes into three-state until the next falling edge of CONVST.
t1
10
15
50
0
10
15
50
0
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
CONVST pulse width.
t2
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
t3
t4
t5
0
0
CS to WR hold time.
t6
10
10
10
10
0
10
10
10
10
0
WR pulse width.
t7
Data setup time before WR.
Data hold after WR.
t8
t9
New data valid before falling edge of BUSY.
CS to RD setup time.
t10
t11
t12
0
0
CS to RD hold time.
30
30
3
30
30
3
RD pulse width.
3
t13
Data access time after RD.
Bus relinquish time after RD.
Bus relinquish time after RD.
HBEN to RD setup time.
4
t14
50
0
50
0
t15
t16
t17
t18
t19
t20
t21
t22
0
0
HBEN to RD hold time.
10
0
10
0
Minimum time between reads/writes.
HBEN to WR setup time.
10
40
15.7
7.8
10
40
15.7
7.8
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2 Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. C | Page 7 of 36
AD7938/AD7939
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to AGND/DGND
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to DGND
VREFIN to AGND
AGND to DGND
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
10 mA
ESD CAUTION
Input Current to Any Pin
Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
108.2°C/W (LFCSP)
121°C/W (TQFP)
32.71°C/W (LFCSP)
45°C/W (TQFP)
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec) 255°C
ESD
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 8 of 36
Data Sheet
AD7938/AD7939
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
V
V
1
IN
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
2
3
4
5
6
7
8
24
23
22
V
V
V
1
0
PIN 1
IN
23
22
21
20
19
18
17
0
IN
PIN 1
INDICATOR
IN
/V
/V
REFIN REFOUT
REFIN REFOUT
AD7938/AD7939
TOP VIEW
21 AGND
20 CS
19 RD
18 WR
17 CONVST
AD7938/AD7939
AGND
CS
TOP VIEW
(Not to Scale)
(Not to Scale)
RD
WR
CONVST
9
10 11 12 13 14 15 16
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF
THE PACKAGE. CONNECT THE EPAD TO THE GROUND
PLANE OF THE PCB USING MULTIPLE VIAS.
Figure 2. LFCSP Pin Configuration
Figure 3. TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 8
DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow the control
and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs (DB0 and
DB1) are always 0 and the LSB of the conversion result is available on DB2.
9
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the
AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at VDD but should never exceed VDD by more than 0.3 V.
10
11
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by
CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data
being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four bits of the
data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to
DB6 of the high byte contains the ID of the channel to which the conversion result corresponds (see the channel
address bits in Table 10). When writing to the device, DB4 to DB7 of the high byte must be all 0s. Note that when
reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining six bits are conversion data.
DB8/HBEN
12 to
14
DB9 to
DB11
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR. The
logic high/low voltage levels for these pins are determined by the VDRIVE input.
15
BUSY
Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the
result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just
prior to the falling edge of BUSY on the 13th rising edge of CLKIN. See Figure 36.
16
17
CLKIN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following
power-down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power up
the device.
CONVST
18
19
WR
RD
Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
20
CS
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or to write data to
the internal registers.
Rev. C | Page 9 of 36
AD7938/AD7939
Data Sheet
Pin No. Mnemonic Description
21
AGND
Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
22
VREFIN/VREFOUT Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V, which appears at this pin. It is recommended that this pin is
decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input voltage
range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog input range
does not exceed VDD + 0.3 V. See the Reference section.
23 to
30
VIN0 to VIN7
Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track-and-
hold. The analog inputs can be programmed to be eight single-ended inputs, four fully differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs by setting the MODE bits in the control register
appropriately (see Table 10). The analog input channel to be converted can either be selected by writing to the
address bits (ADD2 to ADD0) in the control register prior to the conversion or the on-chip sequencer can be used.
The SEQ and SHDW bits in conjunction with the address bits in the control register allow the shadow register to be
programmed. The input range for all input channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can
be binary or twos complement, depending on the states of the RANGE and CODING bits in the control register.
Any unused input channels should be connected to AGND to avoid noise pickup.
31
32
VDD
Power Supply Input. The VDD range for the AD7938/AD7939 is 2.7 V to 5.25 V. The supply should be decoupled to
AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12-bit/10-bit
words on the DB0/DB2 to DB11 pins. When this pin is logic low, byte transfer mode is enabled. Data and the
channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data
lines when operating in byte transfer mode should be tied off to DGND.
W/B
EPAD
Exposed Pad. The exposed pad is located on the underside of the package. Connect the EPAD to the ground plane
of the PCB using multiple vias.
Rev. C | Page 10 of 36
Data Sheet
AD7938/AD7939
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100mV p-p SINE WAVE ON V AND/OR V
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
4096 POINT FFT
DD
DRIVE
V
F
= 5V
DD
= 1.5MSPS
–70
–80
SAMPLE
= 49.62kHz
F
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
INT REF
–90
EXT REF
–100
–110
–120
–100
–110
10
210
410
610
810
1010
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 7. AD7938 FFT @ VDD = 5 V
–70
1.0
0.8
0.6
INTERNAL/EXTERNAL REFERENCE
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
–75
0.4
0.2
–80
–85
0
–0.2
–0.4
–90
–95
–0.6
–0.8
–1.0
0
100
200
300
400
500
600
700
800
0
500
1000
1500 2000 2500 3000 3500
CODE
4000
NOISE FREQUENCY (kHz)
Figure 5. AD7938 Channel-to-Channel Isolation
Figure 8. AD7938 Typical DNL @ VDD = 5 V
80
70
60
50
40
30
20
1.0
0.8
0.6
V
= 5V
V
= 5V
DD
DIFFERENTIAL MODE
DD
V
= 3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
REF
DIFFERENTIAL MODE
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
0
500
1000
1500 2000 2500 3000 3500
CODE
4000
Figure 6. AD7938 SINAD vs. Analog Input Frequency
for Various Supply Voltages
Figure 9. AD7938 Typical INL @ VDD = 5 V
Rev. C | Page 11 of 36
AD7938/AD7939
Data Sheet
10000
9000
8000
7000
6000
5000
4000
3000
4
9997
CODES
INTERNAL
REF
DIFFERENTIAL MODE
SINGLE-ENDED MODE
3
2
1
POSITIVE DNL
NEGATIVE DNL
0
2000
1000
0
3 CODES
2049 2050
–1
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
2046
2047
2048
V
(V)
CODE
REF
Figure 13. AD7938 Histogram of Codes for
10k Samples @ VDD = 5 V with the Internal Reference
Figure 10. AD7938 DNL vs. VREF for VDD = 3 V
120
110
100
90
12
11
10
DIFFERENTIAL MODE
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
SINGLE-ENDED MODE
9
8
V
= 3V
DD
SINGLE-ENDED MODE
80
V
= 3V
DD
DIFFERENTIAL MODE
70
7
6
60
0
200
400
600
800
1000
1200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
RIPPLE FREQUENCY (kHz)
V
(V)
REF
Figure 14. CMRR vs. Ripple Frequency with VDD = 5 V and 3 V
Figure 11. AD7938 ENOB vs. VREF
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 5V
DD
V
= 3V
DD
–4.0
–4.5
–5.0
SINGLE-ENDED MODE
2.5 3.0 3.5
0
0.5
1.0
1.5
V
2.0
(V)
REF
Figure 12. AD7938 Offset vs. VREF
Rev. C | Page 12 of 36
Data Sheet
AD7938/AD7939
TERMINOLOGY
Integral Nonlinearity
Negative Gain Error
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, 1 LSB below
the first code transition, and full scale, 1 LSB above the last code
transition.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100…000) to (100…001) from the ideal (that is,
−VREFIN + 1 LSB) after the zero-code error has been adjusted out.
Differential Nonlinearity
Negative Gain Error Match
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
This is the difference in negative gain error between any two
channels.
Offset Error
Channel-to-Channel Isolation
This is the deviation of the first code transition (00…000) to
(00…001) from the ideal (that is, AGND + 1 LSB).
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to all seven nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF − 1 LSB) after the offset
error has been adjusted out.
varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × VREF
while the signal amplitude is at 1 × VREF. See Figure 5.
,
Gain Error Match
This is the difference in gain error between any two channels.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the noise varies from 1 kHz to 1 MHz.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage
(that is, VREF).
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency, fS.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the last
code transition (011…110) to (011…111) from the ideal (that
is, VREF − 1 LSB) after the zero-code error has been adjusted out.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Rev. C | Page 13 of 36
AD7938/AD7939
Data Sheet
Track-and-Hold Acquisition Time
Peak Harmonic or Spurious Noise
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ½ LSB, after the end of conversion.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fSAMPLE/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Signal-to-Noise and Distortion Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fSAMPLE/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), while
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),
and (fa − 2fb).
The theoretical signal-to-noise and distortion ratio for an ideal
N-bit converter with a sine wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB, and for a 10-bit
converter, it is 62 dB.
The AD7938/AD7939 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The intermodulation distortion is
calculated per the THD specification, as the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals, expressed in dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7938/AD7939, it is defined as
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD dB = −20 log
( )
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. C | Page 14 of 36
Data Sheet
AD7938/AD7939
ON-CHIP REGISTERS
The AD7938/AD7939 have two on-chip registers that are
necessary for the operation of the device. These are the control
register, which is used to set up different operating conditions,
and the shadow register, which is used to program the analog
input channels to be converted.
CONTROL REGISTER
The control register on the AD7938/AD7939 is a 12-bit, write-
CS
only register. Data is written to this register using the
and
pins. The control register is shown in Table 7 and the
WR
functions of the bits are described in Table 8. At power up, the
default bit settings in the control register are all 0s.
Table 7. Control Register Bits
MSB
LSB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PM1
PM0
CODING
REF
ADD2
ADD1
ADD0
MODE1
MODE0
SHDW
SEQ
RANGE
Table 8. Control Register Bit Function Description
Bit No. Mnemonic Description
11, 10
PM1, PM0
CODING
REF
Power Management Bits. These two bits are used to select the power mode of operation. The user can choose
between either normal mode or various power-down modes of operation, as shown in Table 9.
This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight
(natural) binary. If this bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an
external reference should be applied to the VREF pin. If this bit is Logic 1, the internal reference is selected. See the
Reference section.
9
8
7 to 5
4, 3
ADD2 to
ADD0
These three address bits are used to either select which analog input channel is converted in the next conversion if
the sequencer is not used, or to select the final channel in a consecutive sequence when the sequencer is used, as
described in Table 11. The selected input channel is decoded as shown in Table 10.
The two mode pins select the type of analog input on the eight VIN pins. The AD7938/AD7939 can have either eight
single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential
inputs. See Table 10.
MODE1,
MODE0
2
1
0
SHDW
SEQ
The SHDW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and
access the SHDW register. See Table 11.
The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and
access the SHDW register. See Table 11.
This bit selects the analog input range of the AD7938/AD7939. If it is set to 0, the analog input range extends from
0 V to VREF. If it is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, VDD must
be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains
within the supply rails. See the Analog Inputs section for more information.
RANGE
Table 9. Power Mode Selection Using the Power Management Bits in the Control Register
PM1 PM0 Mode
Description
0
0
0
1
Normal Mode
When operating in normal mode, all circuitry is fully powered up at all times.
Autoshutdown When operating in autoshutdown mode, the AD7938/AD7939 enter full shutdown mode at the end of
each conversion. In this mode, all circuitry is powered down.
1
1
0
1
Autostandby
When the AD7938/AD7939 enter this mode, all circuitry is powered down except for the reference and
reference buffer. This mode is similar to autoshutdown mode, but it allows the part to power up in 7 µs (or
600 ns if an external reference is used). See the Power Modes of Operation section for more information.
Full Shutdown When the AD7938/AD7939 enter this mode, all circuitry is powered down. The information in the control
register is retained.
Rev. C | Page 15 of 36
AD7938/AD7939
Data Sheet
periods, the conversion aborts. If a conversion is aborted after
applying 12.5 CLKIN periods to the ADC, ensure that a rising
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control
register allows the user to select a particular mode of operation
of the sequencer function. Table 11 outlines the four modes of
operation of the sequencer.
CONVST
edge of
or a falling edge of CLKIN is applied to the
part before writing to the control register to program the
sequencer. If these conditions are not met, the sequencer will
not be in the correct state to handle being reprogrammed for
another sequence of conversions and the performance of the
converter is not guaranteed.
Writing to the Control Register to Program the Sequencer
The AD7938/AD7939 need 13 full CLKIN periods to perform a
conversion. If the ADC does not receive the full 13 CLKIN
Table 10. Analog Input Type Selection
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
Four Pseudo Differential Input Seven Pseudo Differential Input
Channels (Pseudo Mode 1) Channels (Pseudo Mode 2)
MODE0 = 1, MODE1 = 1
Eight Single-Ended
Input Channels
Four Fully Differential
Input Channels
Channel Address
ADD2 ADD1 ADD0 VIN+
VIN−
VIN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN−
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
VIN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN−
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
VIN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN−
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
Not Allowed
Table 11. Sequence Selection
SEQ SHDW Sequence Type
0
0
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7938/AD7939 selects the next channel for conversion.
0
1
1
1
0
1
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This programs the sequence of channels to be converted continuously after each CONVST
falling edge. See the Shadow Register section and Table 12.
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
Rev. C | Page 16 of 36
Data Sheet
AD7938/AD7939
operating in fully differential mode or Pseudo Mode 1, the
associated pair of channel bits must be set for each pair of
analog inputs required in the sequence. With each consecutive
SHADOW REGISTER
The shadow register on the AD7938/AD7939 is an 8-bit, write-
only register. Data is loaded from DB0 to DB7 on the rising
CONVST
pulse after the sequencer has been set up, the
WR
. The eight LSBs load into the shadow register. The
edge of
AD7938/AD7939 progress through the selected channels in
ascending order, beginning with the lowest channel. This
continues until a write operation occurs with the SEQ and
SHDW bits configured in any way except 1, 0 (see Table 11).
When a sequence is set up in fully differential mode or Pseudo
Mode 1, the ADC does not convert on the inverse pairs (that is,
VIN1, VIN0). The bit functions of the shadow register are
outlined in Table 12. See the Analog Input Selection section for
further information on using the sequencer.
information is written into the shadow register provided that
the SEQ and SHDW bits in the control register were set to 0 and
1, respectively, in the previous write to the control register. Each
bit represents an analog input from Channel 0 through Channel 7.
A sequence of channels can be selected through which the
AD7938/AD7939 cycles with each consecutive conversion after
the write to the shadow register. To select a sequence of
channels to be converted, if operating in single-ended mode or
Pseudo Mode 2, the associated channel bit in the shadow
register must be set for each required analog input. When
Table 12. Shadow Register Bit Functions
MSB
LSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VIN0
Rev. C | Page 17 of 36
AD7938/AD7939
Data Sheet
CIRCUIT INFORMATION
The AD7938/AD7939 are fast, 8-channel, 12-bit and 10-bit,
single-supply, successive approximation analog-to-digital
converters. The parts can operate from a 2.7 V to 5.25 V
power supply and feature throughput rates up to 1.5 MSPS.
When the ADC starts a conversion (Figure 16), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
The AD7938/AD7939 provide the user with an on-chip track-
and-hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 32-lead LFCSP or
TQFP package.
The AD7938/AD7939 have eight analog input channels that
can be configured to be eight single-ended inputs, four fully
differential pairs, four pseudo differential pairs, or seven pseudo
differential inputs with respect to one common input. There is
an on-chip user-programmable channel sequencer that allows
the user to select a sequence of channels through which the
ADC can progress and cycle with each consecutive falling edge
CAPACITIVE
DAC
C
B
A
S
V
V
IN+
SW1
SW2
CONTROL
LOGIC
SW3
of
.
CONVST
A
B
IN–
C
S
The analog input range for the AD7938/AD7939 is 0 V to VREF
or 0 V to 2 × VREF, depending on the status of the RANGE bit in
the control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
V
REF
COMPARATOR
CAPACITIVE
DAC
Figure 16. ADC Conversion Phase
ADC TRANSFER FUNCTION
The AD7938/AD7939 provide flexible power management
options to allow the user to achieve the best power performance
for a given throughput rate. These options are selected by
programming the power management bits, PM1 and PM0, in
the control register.
The output coding for the AD7938/AD7939 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code
transitions occur at successive LSB values (1 LSB, 2 LSBs, and
so on) and the LSB size is VREF/4,096 for the AD7938 and
V
REF/1,024 for the AD7939. The ideal transfer characteristics
CONVERTER OPERATION
of the AD7938/AD7939 for both straight binary and twos
complement output coding are shown in Figure 17 and Figure 18,
respectively.
The AD7938/AD7939 are successive approximation ADCs
based around two capacitive digital-to-analog converters
(DACs). Figure 15 and Figure 16 show simplified schematics of
the ADC in acquisition and conversion phase, respectively. The
ADC comprises control logic, an SAR, and two capacitive DACs.
Both figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
111...111
111...110
V
IN− is internally tied to AGND. In acquisition phase, SW3 is
111...000
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
011...111
1 LSB = V
1 LSB = V
/4096 (AD7938)
/1024 (AD7939)
REF
REF
000...010
000...001
000...000
CAPACITIVE
DAC
C
B
A
S
1 LSB
+V
– 1 LSB
REF
V
V
0V
IN+
SW1
SW2
ANALOG INPUT
CONTROL
LOGIC
SW3
NOTES
1. V
A
B
IN–
IS EITHER V
REF
OR 2 × V .
REF
REF
C
S
V
REF
COMPARATOR
Figure 17. AD7938/AD7939 Ideal Transfer Characteristic
with Straight Binary Output Coding
CAPACITIVE
DAC
Figure 15. ADC Acquisition Phase
Rev. C | Page 18 of 36
Data Sheet
AD7938/AD7939
ANALOG INPUT STRUCTURE
1 LSB = 2 × V
1 LSB = 2 × V
/4096 (AD7938)
/1024 (AD7939)
REF
REF
Figure 20 shows the equivalent circuit of the analog input
structure of the AD7938/AD7939 in differential/pseudo
differential mode. In single-ended mode, VIN− is internally
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than
300 mV. Doing so causes these diodes to become forward-
biased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–V
+ 1 LSB
V
+V
– 1 LSB
REF
REF
REF
The C1 capacitors in Figure 20 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
Figure 18. AD7938/AD7939 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 19 shows a typical connection diagram for the
AD7938/AD7939. The AGND and DGND pins are connected
together at the device for good noise suppression. The
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac
performance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp is a function of
the particular application.
V
REFIN/VREFOUT pin is decoupled to AGND with a 0.47 μF
capacitor to avoid noise pickup if the internal reference is used.
Alternatively, VREFIN/VREFOUT can be connected to an external
reference source. In this case, the reference pin should be
decoupled with a 0.1 μF capacitor. In both cases, the analog
input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to
2 × VREF (RANGE bit = 1). The analog input configuration can
be either eight single-ended inputs, four differential pairs, four
pseudo differential pairs, or seven pseudo differential inputs
(see Table 10). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface. Here, it is connected to the same
3 V supply of the microprocessor to allow a 3 V logic interface
(see the Digital Inputs section).
V
DD
D
R1
C2
V
IN+
D
C1
3V/5V
SUPPLY
V
DD
+
+
10µF
0.1µF
D
D
R1
C2
V
IN–
V
V
DD
AD7938/AD7939
C1
W/B
0
IN
CLKIN
CS
0 TO V
REF
/
Figure 20. Equivalent Analog Input Circuit,
Conversion Phase: Switches Open, Track Phase: Switches Closed
0 TO 2 × V
REF
RD
WR
V
7
IN
BUSY
CONVST
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 21 and Figure 22 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and fully
differential mode, respectively.
DB0
AGND
DGND
DB11/DB9
V
/V
REFIN REFOUT
V
DRIVE
+
+
0.1µF
10µF
3V
SUPPLY
2.5V
V
REF
+
0.1µF EXTERNAL V
REF
0.47µF INTERNAL V
REF
Figure 19. Typical Connection Diagram
Rev. C | Page 19 of 36
AD7938/AD7939
Data Sheet
–40
F
= 50kHz
ANALOG INPUTS
IN
–45
–50
–55
–60
–65
–70
–75
–80
The AD7938/AD7939 have software-selectable analog input
configurations. The user can choose eight single-ended inputs,
four fully differential pairs, four pseudo differential pairs, or
seven pseudo differential inputs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 10).
V
= 3V
DD
Single-Ended Mode
V
= 5V
DD
The AD7938/AD7939 can have eight single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An op amp suitable for this function is
the AD8021. The analog input range of the AD7938/AD7939
–85
–90
10
100
1k
R
(Ω)
SOURCE
Figure 21. THD vs. Source Impedance in Single-Ended Mode
can be programmed to be either 0 V to VREF or 0 V to 2 × VREF
.
–60
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
F
= 50kHz
IN
–65
–70
–75
–80
–85
Figure 24 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude 1.25 V being preconditioned before it is
applied to the AD7938/AD7939. In cases where the analog
input amplitude is 2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7938/AD7939 is a signal ranging from 0 V to 5 V. In this
case, the 2 × VREF mode can be used.
V
DD
= 3V
–90
–95
V
= 5V
DD
–100
10
100
1k
+2.5V
R
R
(Ω)
SOURCE
+1.25V
0V
R
Figure 22. THD vs. Source Impedance in Fully Differential Mode
0V
V
IN
V
0
–1.25V
IN
IN
3R
AD7938/
AD7939*
Figure 23 shows a graph of the THD vs. the analog input
frequency for various supplies while sampling at 1.5 MHz
with an SCLK of 25.5 MHz. In this case, the source impedance
is 10 Ω.
R
V
7
V
REFOUT
R
–50
0.47µF
V
= 3V
DD
SINGLE-ENDED MODE
–60
–70
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
= 5V
DD
SINGLE-ENDED MODE
Figure 24. Single-Ended Mode Connection Diagram
–80
–90
Differential Mode
V
= 5V/3V
DD
DIFFERENTIAL MODE
The AD7938/AD7939 can have four differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
–100
–110
–120
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 25 defines the fully differential analog
input of the AD7938/AD7939.
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
REF
0
100
200
300
400
500
600
700
INPUT FREQUENCY (kHz)
Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. C | Page 20 of 36
Data Sheet
AD7938/AD7939
4.5
4.0
T
= 25°C
A
V
REF
p-p
V
V
IN+
AD7938/
AD7939*
3.5
3.0
V
REF
p-p
IN–
COMMON-MODE
VOLTAGE
2.5
2.0
1.5
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 25. Differential Input Definition
1.0
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals each of amplitude VREF (or
2 × VREF depending on the range chosen) that are 180° out of
phase. The amplitude of the differential signal is therefore −VREF
to +VREF peak-to-peak (that is, 2 × VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals (that is, (VIN+ + VIN−)/2) and is therefore the
voltage on which the two inputs are centered. This results in the
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
V
(V)
REF
Figure 27. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Since not
all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-
differential conversion.
span of each input being CM
VREF/2. This voltage has to be set
up externally and its range varies with the reference value VREF
As the value of VREF increases, the common-mode range
.
decreases. When driving the inputs with an amplifier, the actual
common-mode range is determined by the amplifier’s output
voltage swing.
Figure 26 and Figure 27 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 V
to VREF range or 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of
the AD7938/AD7939.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7938/AD7939.
The circuit configurations shown in Figure 28 and Figure 29
show how a dual op amp can be used to convert a single-ended
signal into a differential signal for both a bipolar and unipolar
input signal, respectively.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF, corresponding to the digital codes of 0 to 4096 for the
AD7938 and 0 to 1024 for the AD7939. If the 2 × VREF range is
used, the input signal amplitude extends from −2 VREF to +2 VREF
after conversion.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
that can be used in this configuration to provide differential
drive to the AD7938/AD7939 is the AD8022.
3.5
T
= 25°C
A
3.0
2.5
2.0
1.5
1.0
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 28 and Figure 29 are optimized for
dc coupling applications requiring best distortion performance.
The differential op amp driver circuit in Figure 28 is configured
to convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
0.5
0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
REF
The circuit configuration shown in Figure 29 converts a
unipolar, single-ended signal into a differential signal.
Figure 26. Input Common-Mode Range vs. VREF (0 V to VREF Range, VDD = 5 V)
Rev. C | Page 21 of 36
AD7938/AD7939
Data Sheet
220Ω
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground, allowing
dc common-mode voltages to be cancelled. Typically, this range
can extend from −0.3 V to +0.7 V when VDD = 3 V or −0.3 V to
+1.8 V when VDD = 5 V. Figure 30 shows a connection diagram
for pseudo differential mode.
2 × V
REF
p-p
V+
440Ω
3.75V
GND
27Ω
2.5V
1.25V
V–
V
IN+
220Ω
220Ω
220Ω
AD7938/
AD7939
V
V+
IN–
V
REF
3.75V
V
p-p
REF
V
2.5V
1.25V
IN+
27Ω
A
V–
AD7938/
AD7939*
0.47µF
V
+
IN–
10kΩ
20kΩ
V
REF
DC INPUT
VOLTAGE
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Differential Unipolar Signal
+
0.47µF
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. Pseudo Differential Mode Connection Diagram
220Ω
V
p-p
REF
ANALOG INPUT SELECTION
V
V+
REF
440Ω
3.75V
27Ω
2.5V
1.25V
As shown in Table 10, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are different ways of selecting the analog input to
be converted depending on the state of the SEQ and SHDW bits
in the control register.
GND
V–
V
V
IN+
220Ω
220Ω
AD7938/
AD7939
V+
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
V–
Traditional Multichannel Operation (SEQ = SHDW = 0)
0.47µF
Any one of eight analog input channels or four pairs of channels
can be selected for conversion in any order by setting the SEQ
and SHDW bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD2 to
ADD0, in the control register to program the multiplexer prior
to the conversion. This mode of operation is that of a traditional
multichannel ADC where each data write selects the next
channel for conversion. Figure 31 shows a flowchart of this
mode of operation. The channel configurations are shown in
Table 10.
+
10kΩ
20kΩ
Figure 29. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
Another method of driving the AD7938/AD7939 is to use the
AD8138 differential amplifier. The AD8138 can be used as a
single-ended-to-differential amplifier or as a differential-to-
differential amplifier. The device is as easy to use as an op amp
and greatly simplifies differential signal amplification and
driving.
POWER ON
Pseudo Differential Mode
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION.
The AD7938/AD7939 can have four pseudo differential pairs
(Pseudo Mode 1) or seven pseudo differential inputs (Pseudo
Mode 2) by setting the MODE0 and MODE1 bits in the control
register to 1, 0 and 1, 1, respectively. In the case of the four
pseudo differential pairs, VIN+ is connected to the signal source,
which must have an amplitude of VREF (or 2 × VREF depending
on the range chosen) to make use of the full dynamic range of
the part. A dc input is applied to the VIN− pin. The voltage
applied to this input provides an offset from ground or a pseudo
ground for the VIN+ input. In the case of the seven pseudo
differential inputs, the seven analog input signals inputs are
SET SEQ = SHDW = 0. SELECT THE DESIRED
CHANNEL TO CONVERT (ADD2 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ = SHDW = 0.
Figure 31. Traditional Multichannel Operation Flow Chart
referred to a dc voltage applied to VIN7
.
Rev. C | Page 22 of 36
Data Sheet
AD7938/AD7939
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1)
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register. This
is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. To set this mode up, the
next conversion, once the control register is written to, is on
Channel 0, then Channel 1, and so on, until the channel
selected by the address bits (ADD2 to ADD0) is reached. The
The AD7938/AD7939 can be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register
to 1 (see Table 12).
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed is on the next highest channel in the
sequence and so on. When the last channel in the sequence
is converted, the internal multiplexer returns to the first
channel selected in the shadow register and commences the
sequence again.
cycle begins again provided the
input is tied high. If low,
WR
the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 33
shows the flowchart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD2 TO ADD0) IN
CONSECUTIVE SEQUENCE.
It is not necessary to write to the control register again once a
WR
sequencer operation has been initiated. The
input must be
SET SEQ = 1 SHDW = 1.
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the sequence,
ensure that the SEQ and SHDW bits are set to 1, 0 to avoid
interrupting the conversion sequence. The sequence program
remains in force until such time as the AD7938/AD7939 is
written to and the SEQ and SHDW bits are configured with any
bit combination except 1, 0. Figure 32 shows a flow chart of the
programmable sequence operation.
CONTINUOUSLY CONVERT A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
WITH EACH CONVST PULSE.
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE CHANNELS SELECTED
WITH EACH CONVST PULSE BUT
ALLOWS THE RANGE, CODING, ANALOG
INPUT TYPE, ETC. BITS IN THE
CONTROL REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
POWER ON
THE SEQUENCE.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
Figure 33. Consecutive Sequence Mode Flow Chart
SET SEQ = 0 SHDW = 1.
REFERENCE
The AD7938/AD7939 can operate with either the on-chip
reference or external reference. The internal reference is
selected by setting the REF bit in the internal control register
to 1. A block diagram of the internal reference circuitry is
shown in Figure 34. The internal reference circuitry includes an
on-chip 2.5 V band gap reference and a reference buffer. When
using the internal reference, the VREFIN/VREFOUT pin should be
decoupled to AGND with a 0.47 μF capacitor. This internal
reference not only provides the reference for the analog-to-
digital conversion, but it can also be used externally in the
system. It is recommended that the reference output is buffered
using an external precision op amp before applying it anywhere
in the system.
INITIATE A WRITE CYCLE.
THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.
SET RELEVANT BITS TO SELECT
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
WR = HIGH
SEQ BIT = 0
SHDW BIT = 1
SEQ BIT = 1
SHDW BIT = 0
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
IN THE SHADOW REGISTER
WITH EACH CONVST PULSE.
CONTINUOUSLY CONVERT
CONSECUTIVE
CHANNELS SELECTED
WITH EACH CONVST PULSE
BUT ALLOWS THE RANGE,
CODING, ANALOG INPUT TYPE,
ETC BITS IN THE CONTROL
REGISTER TO BE CHANGED
WITHOUT INTERRUPTING
THE SEQUENCE.
Figure 32. Programmable Sequence Flow Chart
BUFFER
REFERENCE
V
/
REFIN
V
REFOUT
AD7938/
AD7939
ADC
Figure 34. Internal Reference Circuit Block Diagram
Rev. C | Page 23 of 36
AD7938/AD7939
Data Sheet
Alternatively, an external reference can be applied to the VREFIN
/
Digital Inputs
V
REFOUT pin of the AD7938/AD7939. An external reference
The digital inputs applied to the AD7938/AD7939 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog inputs.
input is selected by setting the REF bit in the internal control
register to 0. The external reference input range is 0.1 V to VDD
It is important to ensure that, when choosing the reference
value, the maximum analog input range (VIN MAX) is never
greater than VDD + 0.3 V, to comply with the maximum ratings
of the device. For example, if operating in differential mode and
the reference is sourced from VDD, the 0 V to 2 × VREF range
cannot be used. This is because the analog input signal range
now extends to 2 × VDD, which exceeds the maximum rating
conditions. In the pseudo differential modes, the user must
ensure that VREF + (VIN−) ≤ VDD when using the 0 V to VREF range,
.
Another advantage of the digital inputs not being restricted by
the VDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before VDD
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to VDD.
,
VDRIVE Input
or when using the 2 × VREF range that 2 × VREF + (VIN−) ≤ VDD
.
The AD7938/AD7939 have a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V and 5 V processors.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 10 to Figure 12. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7938/AD7939 transfer function and add to specified full-
scale errors on the part.
For example, if the AD7938/AD7939 are operated with an VDD
of 5 V and the VDRIVE pin is powered from a 3 V supply, the
AD7938/AD7939 have better dynamic performance with an
V
DD of 5 V while still being able to interface directly to 3 V
processors. Care should be taken to ensure VDRIVE does not
exceed VDD by more than 0.3 V (see the Absolute Maximum
Ratings section).
Table 13 lists examples of suitable voltage references available
from Analog Devices that can be used. Figure 35 shows a typical
connection diagram for an external reference.
Table 13. Examples of Suitable Voltage References
Output
Initial Accuracy Operating
Reference Voltage (V)
(% Max)
Current (µA)
AD780
ADR421
ADR420
2.5/3
2.5
2.048
0.04
0.04
0.05
1000
500
500
AD7938/
AD7939*
AD780
V
NC
1
2
3
4
O/P SELECT
8
7
6
5
NC
NC
REF
V
+V
DD
IN
2.5V
TEMP
V
OUT
0.1µF
10nF
0.1µF
0.1µF
GND
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. Typical VREF Connection Diagram
Rev. C | Page 24 of 36
Data Sheet
AD7938/AD7939
At the end of the conversion, BUSY goes low and can be used to
PARALLEL INTERFACE
CS
RD
activate an interrupt service routine. The
and
lines are
The AD7938/AD7939 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7938) or 10-bits
(AD7939) wide and is capable of operating in either word
then activated in parallel to read the 12- or 10-bits of conversion
data. When power supplies are first applied to the device, a
CONVST
rising edge on
into track. The acquisition time of 125 ns minimum must be
CONVST
is necessary to put the track-and-hold
B
B
CONVST
(W/ tied high) or byte (W/ tied low) mode. The
signal is used to initiate conversions; when operating in
autoshutdown or autostandby mode, it is used to initiate
power-up.
allowed before
is brought low to initiate a conversion.
CONVST
The ADC then goes into hold on the falling edge of
and back into track on the 13th rising edge of CLKIN after this
(see Figure 36). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
CONVST
A falling edge on the
conversions and it puts the ADC track-and-hold into track.
CONVST
signal is used to initiate
Once the
signal goes low, the BUSY signal goes high
CONVST
each conversion, a rising edge on the
power up the device.
signal is used to
for the duration of the conversion. In between conversions,
CONVST
must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
B
t1
A
CONVST
tCONVERT
1
2
3
4
5
12
13
14
t2
CLKIN
BUSY
t20
t3
t9
INTERNAL
TRACK/HOLD
tACQUISITION
CS
RD
t10
t11
t14
t12
t13
THREE-STATE
tQUIET
DB0 TO DB11
DATA
THREE-STATE
WITH CS AND RD TIED LOW
OLD DATA
DB0 TO DB11
DATA
B
Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/ = 1)
Rev. C | Page 25 of 36
AD7938/AD7939
Data Sheet
Reading Data from the AD7938/AD7939
CS
RD
The
triggered active low. In either word mode or byte mode,
RD
and
signals are gated internally and the level is
CS
and
can be tied together because the timing specifications for t10
and t11 are 0 ns minimum. This means the bus is constantly
driven by the AD7938/AD7939.
B
With the W/ pin tied logic high, the AD7938/AD7939
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word
on Pins DB0/DB2 to Pin DB11. The DB8/HBEN pin assumes
B
its DB8 function. With the W/ pin tied to logic low, the
CS
The data is placed onto the data bus a time t13 after both
and
rising edge can be used to latch data out of
the device. After a time, t14, the data lines become three-stated.
AD7938/AD7939 interface operates in byte mode. In this case,
the DB8/HBEN pin assumes its HBEN function. Conversion
data from the AD7938/AD7939 must be accessed in two read
operations with eight bits of data provided on DB0 to DB7 for
each of the read operations. The HBEN pin determines whether
the read operation accesses the high byte or the low byte of the
12-bit or 10-bit word. For a low byte read, DB0 to DB7 provide
the eight LSBs of the 12-bit word. For 10-bit operation, the two
LSBs of the low byte are 0s, followed by six bits of conversion
data. For a high byte read, DB0 to DB3 provide the four MSBs
of the 12-bit or10-bit word. DB5 to DB7 of the high byte
provide the channel ID. Figure 36 shows the read cycle timing
diagram for a 12-bit or 10-bit transfer. When operating in word
mode, the HBEN input does not exist, and only the first read
operation is required to access data from the device. When
operating in byte mode, the two read cycles shown in Figure 37
are required to access the full data-word from the device.
RD RD
go low. The
CS RD
can be tied permanently low and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Alternatively,
and
RD
Note that if
causes a degradation in linearity performance of approximately
CS
is pulsed during the conversion time, this
0.25 LSB. Reading during conversion by way of tying
and
RD
low does not cause any degradation.
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
RD
t13
t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 37. AD7938/AD7939 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. C | Page 26 of 36
Data Sheet
AD7938/AD7939
Writing Data to the AD7938/AD7939
Figure 38 shows the write cycle timing diagram of the
AD7938/AD7939 in word mode. When operating in word
mode, the HBEN input does not exist and only one write
operation is required to write the word of data to the device.
Data should be provided on DB0 to DB11. When operating in
byte mode, the two write cycles shown in Figure 39 are required
to write the full data-word to the AD7938/AD7939. In Figure 39,
the first write transfers the lower eight bits of the data-word
from DB0 to DB7, and the second write transfers the upper four
bits of the data-word. When writing to the AD7938/AD7939, the
top four bits in the high byte must be 0s.
B
With W/ tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938/AD7939. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7938/AD7939 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
B
of the data-word. With W/ tied logic low, the
AD7938/AD7939 requires two write operations to transfer a full
12-bit word. DB8/HBEN assumes its HBEN function. Data
written to the AD7938/AD7939 should be provided on the DB0
to DB7 inputs. HBEN determines whether the byte written is
high byte or low byte data. The low byte of the data-word
should be written first with DB0 being the LSB of the full data-
word. For the high byte write, HBEN should be high and the
data on the DB0 input should be data Bit 8 of the 12-bit word.
In both word and byte mode, a single write operation to the
shadow register is always sufficient since it is only eight bits
wide.
WR
The data is latched into the device on the rising edge of
.
WR
The data needs to be setup a time, t7, before the
rising edge
WR
CS
CS
can be tied
and held for a time, t8, after the
WR
rising edge. The
and
WR
signals are gated internally.
and
together as the timing specifications for t4 and t5 are 0 ns
CS
RD
minimum (assuming
together).
and
have not already been tied
CS
t4
t5
WR
t6
t8
t7
DATA
DB0 TO DB11
B
Figure 38. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
WR
t7
LOW BYTE
t8
DB0 TO DB11
HIGH BYTE
B
Figure 39. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. C | Page 27 of 36
AD7938/AD7939
Data Sheet
Autostandby (PM1 = 1; PM0 = 0)
POWER MODES OF OPERATION
In this mode of operation, the AD7938/AD7939 automatically
enter standby mode at the end of each conversion, which is
shown as Point A in Figure 36. When this mode is entered, all
circuitry on the AD7938/AD7939 is powered down except for
the reference and reference buffer. The track-and-hold goes into
hold at this point also and remains in hold as long as the device
is in standby. The parts remain in standby until the next rising
The AD7938/AD7939 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to
optimize the power dissipation/throughput rate ratio for
differing applications. The mode of operation is selected by the
power management bits, PM1 and PM0, in the control register,
as detailed in Table 9. When power is first applied to the
AD7938/AD7939, an on-chip, power-on reset circuit ensures
that the default power-up condition is normal mode.
CONVST
edge of
powers up the device. The power-up time
required depends on whether the internal or external reference
is used. With an external reference, the power-up time required
is a minimum of 600 ns, while when using the internal
reference, the power-up time required is a minimum of 7 μs.
The user should ensure this power-up time has elapsed before
initiating another conversion as shown in Figure 40. This
Note that, after power-on, the track-and-hold is in hold mode
CONVST
and the first rising edge of
into track mode.
places the track-and-hold
Normal Mode (PM1 = PM0 = 0)
CONVST
rising edge of
into track mode.
also places the track-and-hold back
This mode is intended for the fastest throughput rate
performance because the user does not have to worry about any
power-up times associated with the AD7938/AD7939. It
remains fully powered up at all times. At power-on reset, this
mode is the default setting in the control register.
Full Shutdown Mode (PM1 =1; PM0 = 1)
When this mode is programmed, all circuitry on the
AD7938/AD7939 is powered down upon completion of the
WR
write operation, that is, on the rising edge of
. The track-
Autoshutdown (PM1 = 0; PM0 = 1)
and-hold enters hold mode at this point. The parts retain
the information in the control register while the part is in
shutdown. The AD7938/AD7939 remain in full shutdown
mode, with the track-and-hold in hold mode, until the power
management bits (PM1 and PM0) in the control register are
changed. If a write to the control register occurs while the part
is in full shutdown mode, and the power management bits are
changed to PM0 = PM1 = 0 (normal mode), the part begins to
In this mode of operation, the AD7938/AD7939 automatically
enter full shutdown at the end of each conversion, which is
shown at Point A in Figure 36 and Figure 40. In shutdown
mode, all internal circuitry on the device is powered down.
The parts retain information in the control register during
shutdown. The track-and-hold also goes into hold at this point
and remains in hold as long as the device is in shutdown. The
AD7938/AD7939 remains in shutdown mode until the next
WR
power up on the
rising edge and the track-and-hold returns
CONVST
rising edge of
In order to keep the device in shutdown for as long as possible,
CONVST
(see Point B in Figure 36 or Figure 40).
to track. To ensure the part is fully powered up before a conversion
is initiated, the power-up time of 10 ms minimum should be
should idle low between conversions, as shown in
CONVST
allowed before the next
invalid data is read.
falling edge; otherwise,
Figure 40. On this rising edge, the part begins to power-up and
the track-and-hold returns to track mode. The power-up time
required is 10 ms minimum regardless of whether the user is
operating with the internal or external reference. The user
should ensure that the power-up time has elapsed before
initiating a conversion.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
CLKIN
BUSY
Figure 40. Autoshutdown/Autostandby Mode
Rev. C | Page 28 of 36
Data Sheet
AD7938/AD7939
10
POWER vs. THROUGHPUT RATE
T = 25°C
A
9
8
7
6
5
4
3
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938/AD7939 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 41
shows a plot of the power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the maximum CLKIN frequency of 25.5 MHz is used to
minimize the conversion time, this accounts for only 0.525 µs of
the overall cycle time while the AD7938/AD7939 remains in
standby mode for the remainder of the cycle. If the devices run
at a throughput rate of 10 kSPS, for example, the overall cycle
time is 100 µs.
V
= 5V
DD
V
= 3V
DD
2
1
0
0
200
400
600
800
1000
1200
1400
1600
THROUGHPUT (kSPS)
Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
Figure 42 shows a plot of the power vs. throughput rate when
operating in normal mode for both VDD = 5 V and VDD = 3 V. In
both plots, the figures apply when using the internal reference.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938/AD7939 remain in standby for a
greater time in every cycle. Additionally, the current consumption,
when converting, should be lower than the specified maximum
of 2.7 mA with VDD = 5 V, or 2.0 mA with VDD = 3 V.
AD7938/AD7939 to ADSP-21xx Interface
Figure 43 shows the AD7938/AD7939 interfaced to the ADSP-
21xx series of DSPs as a memory-mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (see the ADSP-21xx family
User’s Manual for details). The following instruction reads from
the AD7938/AD7939:
1.8
T
= 25°C
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
MR = DM (ADC)
V
= 5V
DD
where ADC is the address of the AD7938/AD7939.
DSP/USER SYSTEM
CONVST
A0 TO A15
ADDRESS BUS
V
= 3V
AD7938/
AD7939*
DD
ADSP-21xx*
DMS
ADDRESS
DECODER
CS
IRQ2
WR
BUSY
WR
0.2
0
0
20
40
60
80
100
120
140
RD
RD
THROUGHPUT (kSPS)
DB0 TO DB11
Figure 41. Power vs. Throughput in
Autostandby Mode Using Internal Reference
D0 TO D23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Interfacing to the ADSP-21xx
Rev. C | Page 29 of 36
AD7938/AD7939
Data Sheet
DSP/USER SYSTEM
AD7938/AD7939 to ADSP-21065L Interface
Figure 44 shows a typical interface between the
AD7938/AD7939 and the ADSP-21065L SHARC® processor.
This interface is an example of one of three DMA handshake
CONVST
A0 TO A15
ADDRESS BUS
ADDRESS
TMS32020/
TMS320C25/
TMS320C50*
AD7938/
AD7939*
MS
modes. The
X control line is actually three memory select
IS
EN
CS
DECODER
MS
lines. Internal ADDR25-24 are decoded into
lines are then asserted as chip selects. The
3 to 0, and these
DMAR
READY
1 (DMA
TMS320C25
ONLY
MSC
request 1) is used in this setup as the interrupt to signal the end
of conversion. The rest of the interface is a standard
handshaking operation.
STRB
WR
RD
R/W
DSP/USER SYSTEM
INT
X
BUSY
DMD0 TO DMD15
DB11 TO DB0
CONVST
DATA BUS
ADDR TO ADDR
ADDRESS BUS
0
23
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
LATCH
AD7938/
AD7939*
Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x
MS
X
ADDRESS BUS
AD7938/AD7939 to 80C186 Interface
ADSP-21065L*
DMAR
ADDRESS
DECODER
CS
Figure 46 shows the AD7938/AD7939 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938/AD7939 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next conversion.
BUSY
RD
1
RD
WR
WR
DB0 TO DB11
D0 TO D31
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Interfacing to the ADSP-21065L
AD7938/AD7939 to TMS32020, TMS320C25, and
TMS320C5x Interface
MICROPROCESSOR/
USER SYSTEM
Parallel interfaces between the AD7938/AD7939 and the
TMS32020, TMS320C25, and TMS320C5x family of DSPs are
shown in Figure 45. The memory mapped address chosen for
the AD7938/AD7939 should be chosen to fall in the I/O
memory space of the DSPs. The parallel interface on the
AD7938/AD7939 is fast enough to interface to the TMS32020
with no extra wait states. If high speed glue logic, such as 74AS
CONVST
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
ADDRESS
LATCH
AD7938/
AD7939*
ALE
ADDRESS BUS
80C186*
DRQ1
ADDRESS
DECODER
CS
RD
WR
lines when
devices, is used to drive the
and the
Q
R
S
interfacing to the TMS320C25, no wait states are necessary.
However, if slower logic is used, data accesses can be slowed
sufficiently when reading from, and writing to, the part to
require the insertion of one wait state. Extra wait states are
necessary when using the TMS320C5x at their fastest clock
speeds (see the TMS320C5x User’s Guide for details).
BUSY
RD
RD
WR
WR
DATA BUS
DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Interfacing to the 80C186
Data is read from the ADC using the following instruction
IN D, ADC
where:
D is the data memory address.
ADC is the AD7938/AD7939 address.
Rev. C | Page 30 of 36
Data Sheet
AD7938/AD7939
APPLICATION HINTS
GROUNDING AND LAYOUT
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The printed circuit board that houses the AD7938/AD7939
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
Generally, a minimum etch technique is best for ground planes
since it gives the best shielding. Digital and analog ground
planes should be joined in only one place, and the connection
should be a star ground point established as close to the ground
pins on the AD7938/AD7939 as possible. Avoid running digital
lines under the device as this couples noise onto the die. The
analog ground plane should be allowed to run under the
AD7938/AD7939 to avoid noise coupling. The power supply
lines to the AD7938/AD7939 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line.
The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the chip scale package has a thermal pad. The
thermal pad on the printed circuit board should be at least as
large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided. Thermal vias can be used on the printed
circuit board thermal pad to improve thermal performance of
the package. If vias are used, they should be incorporated in the
thermal pad at 1.2 mm pitch grid. The via diameter should be
between 0.3 mm and 0.33 mm, and the via barrel should be
plated with 1 oz copper to plug the via. The user should connect
the printed circuit board thermal pad to AGND.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
EVALUATING AD7938/AD7939 PERFORMANCE
The recommended layout for the AD7938/AD7939 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7938/AD7939
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate and
evaluate the ac and dc performance of the AD7938/AD7939.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best performance
from these decoupling components, they must be placed as
close as possible to the device, ideally right up against the
device. The 0.1 µF capacitors should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types or surface-mount types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the
AD7938/AD7939. The software and documentation are on the
CD that ships with the evaluation board.
Rev. C | Page 31 of 36
AD7938/AD7939
Data Sheet
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
32
1
24
0.50
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
0.30
0.25
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
1.20
0.75
0.60
0.45
MAX
9.00 BSC SQ
25
32
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
8
17
3.5°
0°
0.15
0.05
9
16
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.80
0.45
0.37
0.30
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABA
Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
Rev. C | Page 32 of 36
Data Sheet
AD7938/AD7939
ORDERING GUIDE
Model1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Linearity Error (LSB)2
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead TQFP
Package Option
CP-32-2
CP-32-2
SU-32-2
SU-32-2
AD7938BCPZ
AD7938BCPZ-REEL7
AD7938BSUZ
AD7938BSUZ-REEL7
EVAL-AD7938CBZ
AD7939BCPZ
AD7939BCPZ-REEL7
AD7939BSUZ
1
1
1
1
32-Lead TQFP
Evaluation Board
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead TQFP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1
1
1
1
CP-32-2
CP-32-2
SU-32-2
SU-32-2
AD7939BSUZ-REEL7
32-Lead TQFP
1 Z = RoHS Compliant Part.
2 Linearity error here refers to integral linearity error.
Rev. C | Page 33 of 36
AD7938/AD7939
NOTES
Data Sheet
Rev. C | Page 34 of 36
Data Sheet
NOTES
AD7938/AD7939
Rev. C | Page 35 of 36
AD7938/AD7939
NOTES
Data Sheet
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03715-0-10/11(C)
Rev. C | Page 36 of 36
相关型号：
AD7938BCPZ-REEL7
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32, LEAD FREE, MO-220-VHHD-2, LFCSP-32
ROCHESTER
AD7938BSU
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP32, PLASTIC, MS-026-ABA, TQFP-32
ROCHESTER
AD7938BSUZ
8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP32, LEAD FREE, PLASTIC, MS-026-ABA, TQFP-32
ROCHESTER
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