AD797 [ADI]
Ultralow Distortion, Ultralow Noise Op Amp; 超低失真，超低噪声运算放大器
| 型号： | AD797 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion, Ultralow Noise Op Amp |
| 文件： | 总16页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion,
Ultralow Noise Op Amp
a
AD797*
FEATURES
Low Noise
CO NNECTIO N D IAGRAM
8-P in P lastic Mini-D IP (N),
Cerdip (Q) and SO IC (R) P ackages
0.9 nV/ √Hz typ (1.2 nV/ √Hz m ax) Input Voltage
Noise at 1 kHz
50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz
Low Distortion
DECOMPENSATION &
DISTORTION
NEUTRALIZATION
–120 dB Total Harm onic Distortion at 20 kHz
Excellent AC Characteristics
800 ns Settling Tim e to 16 Bits (10 V Step)
110 MHz Gain Bandw idth (G = 1000)
8 MHz Bandw idth (G = 10)
1
2
3
4
8
7
6
5
OFFSET NULL
AD797
+V
S
–IN
+IN
OUTPUT
–V
S
OFFSET NULL
280 kHz Full Pow er Bandw idth at 20 V p-p
20 V/ s Slew Rate
TOP VIEW
Excellent DC Precision
80 V m ax Input Offset Voltage
1.0 V/ ؇C VOS Drift
Specified for ؎5 V and ؎15 V Pow er Supplies
High Output Drive Current of 50 m A
necessary for preamps in microphones and mixing consoles.
Furthermore, the AD797’s excellent slew rate of 20 V/µs and
110 MHz gain bandwidth make it highly suitable for low fre-
quency ultrasound applications.
APPLICATIONS
Professional Audio Pream plifiers
IR, CCD, and Sonar Im aging System s
Spectrum Analyzers
Ultrasound Pream plifiers
Seism ic Detectors
⌺⌬ ADC/ DAC Buffers
T he AD797 is also useful in IR and Sonar Imaging applications
where the widest dynamic range is necessary. T he low distor-
tion and 16-bit settling time of the AD797 make it ideal for
buffering the inputs to Σ∆ ADCs or the outputs of high resolu-
tion DACs especially when they are used in critical applications
such as seismic detection and spectrum analyzers. Key features
such as a 50 mA output current drive and the specified power
supply voltage range of ±5 to ±15 volts make the AD797 an
excellent general purpose amplifier.
P RO D UCT D ESCRIP TIO N
T he AD797 is a very low noise, low distortion operational
amplifier ideal for use as a preamplifier. T he low noise of
0.9 nV/√Hz and low total harmonic distortion of –120 dB at
audio bandwidths give the AD797 the wide dynamic range
5
4
3
2
1
0
–90
–100
–110
–120
0.001
0.0003
0.0001
MEASUREMENT
LIMIT
–130
10
100
1k
10k
100k
1M
10M
100
300
1k
3k
10k
30k
100k
300k
FREQUENCY – Hz
FREQUENCY – Hz
THD vs. Frequency
AD797 Voltage Noise Spectral Density
*P atent pending.
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(@ T = +25؇C and V = ؎15 V dc, unless otherwise noted)
AD797–SPECIFICATIONS
A
S
AD 797A/S1
AD 797B
Typ Max Units
Model
Conditions
VS
Min
Typ
Max
Min
INPUT OFFSET VOLT AGE
±5 V, ±15 V
25
50
0.2
80
125/180
1.0
10
30
0.2
40
60
0.6
µV
µV
µV/°C
T MIN to T MAX
Offset Voltage Drift
±5 V, ±15 V
±5 V, ±15 V
INPUT BIAS CURRENT
0.25 1.5
0.5
0.25 0.9
0.25 2.0
µA
µA
T MIN to T MAX
3.0
INPUT OFFSET CURRENT
OPEN-LOOP GAIN
±5 V, ±15 V
±15 V
100
120
400
600/700
80
200
nA
nA
T MIN to T MAX
120 300
VOUT = ±10 V
RLOAD = 2 kΩ
T MIN to T MAX
RLOAD = 600 Ω
T MIN to T MAX
@ 20 kHz2
1
1
1
1
20
6
15
5
2
2
2
2
20
10
15
7
V/µV
V/µV
V/µV
V/µV
V/V
14000
20000
14000 20000
DYNAMIC PERFORMANCE
Gain Bandwidth Product
G = 1000
±15 V
±15 V
±15 V
110
450
8
110
450
8
MHz
MHz
MHz
G = 10002
G = 10
–3 dB Bandwidth
Full Power Bandwidth3
VO = 20 V p-p,
RLOAD = 1 kΩ
RLOAD = 1 kΩ
10 V Step
±15 V
±15 V
±15 V
280
20
800
280
12.5 20
kHz
V/µs
Slew Rate
Settling T ime to 0.0015%
12.5
1200
800 1200 ns
COMMON-MODE REJECT ION
POWER SUPPLY REJECT ION
INPUT VOLT AGE NOISE
VCM = CMVR
T MIN to T MAX
±5 V, ±15 V
114
110
130
120
120
114
130
120
dB
dB
VS = ±5 V to ±18 V
T MIN to T MAX
114
110
130
120
120
114
130
120
dB
dB
f = 0. 1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
±15 V
±15 V
±15 V
±15 V
50
50
nV p-p
nV/√Hz
nV/√Hz
µV rms
1.7
0.9
1.0
1.7
0.9
1.0
2.5
1.2
1.2
1.2
1.3
f = 10 Hz–1 MHz
INPUT CURRENT NOISE
f = 1 kHz
±15 V
2.0
2.0
pA/√Hz
INPUT COMMON-MODE
VOLT AGE RANGE
±15 V
±5 V
±11
±2.5
±12
±3
±11
±2.5 ±3
±12
V
V
OUT PUT VOLT AGE SWING
RLOAD = 2 kΩ
RLOAD = 600 Ω
RLOAD = 600 Ω
±15 V
±15 V
±5 V
±12
±11
±2.5
±13
±13
±3
±12
±11
±2.5 ±3
±13
±13
V
V
V
Short-Circuit Current
Output Current4
±5 V, ±15 V
±5 V, ±15 V
80
50
80
50
mA
mA
30
30
TOTAL HARMONIC DISTORTION
RLOAD = 1 kΩ, CN = 50 pF ±15 V
–98
–90
–98 –90
dB
f = 250 kHz, 3 V rms
RLOAD = 1 kΩ
±15 V
–120 –110
–120 –110 dB
f = 20 kHz, 3 V rms
INPUT CHARACT ERIST ICS
Input Resistance (Differential)
Input Resistance (Common Mode)
Input Capacitance (Differential)5
Input Capacitance (Common Mode)
7.5
100
20
5
7.5
100
20
5
kΩ
MΩ
pF
pF
OUT PUT RESIST ANCE
AV = +1, f = 1 kHz
3
3
mΩ
POWER SUPPLY
Operating Range
Quiescent Current
±5
±18
10.5
±5
±18
10.5 mA
V
±5 V, ±15 V
8.2
8.2
NOT ES
1See standard military drawing for 883B specifications.
2Specified using external decompensation capacitor, see Applications section.
3Full Power Bandwidth = Slew Rate/2 π VPEAK
.
4Output Current for | VS – VOUT| >4 V, AOL > 200 kΩ.
5Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.
Specifications subject to change without notice.
–2–
REV. C
AD797
ABSO LUTE MAXIMUM RATINGS 1
3T he AD797’s inputs are protected by back-to-back diodes. T o achieve low noise,
internal current limiting resistors are not incorporated into the design of this
amplifier. If the differential input voltage exceeds ±0.7 V, the input current should
be limited to less than 25 mA by series protection resistors. Note, however, that this
will degrade the low noise performance of the device.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation @ +25°C2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . ±0.7 V
Output Short Circuit Duration . . . . . . . Indefinite Within max
Internal Power Dissipation
Storage Temperature Range (Cerdip) . . . . . . –65°C to +150°C
Storage Temperature Range (N, R Suffix) . . –65°C to +125°C
Operating T emperature Range
AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD797S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD SUSCEP TIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD797 features proprietary ESD pro-
tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. T herefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Internal Power Dissipation:
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
8-Pin SOIC = 0.9 Watts (T A–25°C)/θJA
8-Pin Plastic DIP and Cerdip = 1.3 Watts – (T A–25°C)/θJA
T hermal Characteristics
8-Pin Plastic DIP Package: θJA = 95°C/W
8-Pin Cerdip Package: θJA = 110°C/W
AD797AN
AD797BN
AD797BR
AD797BR-REEL
AD797BR-REEL7
AD797AR
AD797AR-REEL
AD797AR-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Cerdip
N-8
N-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
Q-8
8-Pin Small Outline Package: θJA = 155°C/W
5962-9313301MPA –55°C to +125°C
METALIZATIO N P H O TO
Contact factory for latest dimensions.
D imensions shown in inches and (mm).
NOT E
T he AD797 has double layer metal. Only one layer is shown here for clarity.
REV. C
–3–
AD797–Typical Characteristics
20
15
10
5
0
0
5
10
15
20
HORIZONTAL SCALE – 5 sec/DIV
SUPPLY VOLTAGE – ±Volts
Figure 4. 0.1 Hz to 10 Hz Noise
Figure 1. Com m on-Mode Voltage Range vs. Supply
0.0
20
15
10
–0.5
–1.0
+V
OUT
–V
OUT
5
0
–1.5
–2.0
0
5
10
SUPPLY VOLTAGE – ±Volts
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE – °C
Figure 5. Input Bias Current vs. Tem perature
Figure 2. Output Voltage Swing vs. Supply
140
30
20
10
0
V
= ±15V
S
120
100
80
SOURCE CURRENT
SINK CURRENT
V
= ±5V
S
60
40
–60 –40 –20
0
20
40
60
100 120 140
80
10
100
1k
10k
TEMPERATURE – °C
LOAD RESISTANCE –
Ω
Figure 6. Short Circuit Current vs. Tem perature
Figure 3. Output Voltage Swing vs. Load Resistance
REV. C
–4–
AD797
11
10
9
140
120
100
+125°C
PSR
+SUPPLY
PSR
–SUPPLY
150
125
100
75
80
60
+25°C
–55°C
8
CMR
7
40
20
6
0
50
1M
5
15
20
10
SUPPLY VOLTAGE – ±Volts
1
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 10. Power Supply and Com m on-Mode Rejection
vs. Frequency
Figure 7. Quiescent Supply Current vs. Supply Voltage
–60
12
R
= 600
Ω
L
FREQ = 1kHz
G = +10
FREQ = 10kHz
NOISE BW = 100kHz
R
= 600Ω
L
G = +10
9
6
3
0
–80
–100
–120
V
= ±5V
S
V
= ±15V
S
0.01
0.1
1.0
10
0
±5
±10
±15
±20
OUTPUT LEVEL – Volts
SUPPLY VOLTAGE – Volts
Figure 11. Total Harm onic Distortion (THD) + Noise vs.
Output Level
Figure 8. Output Voltage vs. Supply for 0.01% Distortion
30
1.0
0.8
±15V SUPPLIES
RL = 600Ω
0.0015%
20
0.6
0.01%
0.4
10
±5V SUPPLIES
0.2
0.0
0
0
2
4
6
8
10
STEP SIZE – Volts
Figure 12. Large Signal Frequency Response
Figure 9. Settling Tim e vs. Step Size (±)
REV. C
–5–
AD797–Typical Characteristics
5
120
110
100
35
GAIN/BANDWIDTH PRODUCT
4
3
2
1
30
25
SLEW RATE
RISING EDGE
SLEW RATE
FALLING EDGE
20
15
90
80
0
–60 –40 –20
0
20
40
60
80
100 120 140
10
100
1k
10k
100k
1M
10M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 13. Input Voltage Noise Spectral Density
Figure 16. Slew Rate & Gain/Bandwidth Product vs.
Tem perature
120
+100
160
140
120
100
PHASE MARGIN
100
80
60
40
20
0
+80
+60
WITHOUT
R *
S
WITH R *
S
+40
+20
GAIN
WITHOUT
*R = 100
S
R *
S
0
SEE FIGURE 22
WITH R *
S
100
10k
100
1k
10k
100k
1M
10M
100M
1k
FREQUENCY – Hz
LOAD RESISTANCE – Ohms
Figure 17. Open-Loop Gain vs. Resistive Load
Figure 14. Open-Loop Gain & Phase vs. Frequency
100
300
OVER COMPENSATED
150
10
* SEE FIGURE 29
1
0
WITHOUT C
*
N
0.1
–150
UNDER COMPENSATED
WITH C
100k
*
N
0.01
–300
–60 –40 –20
0
20
40
60
80
100 120 140
10
100
1k
10k
1M
TEMPERATURE – °C
FREQUENCY – Hz
Figure 15. Input Offset Current vs. Tem perature
Figure 18. Magnitude of Output Im pedance vs. Frequency
REV. C
–6–
AD797
20pF
50mV
100ns
1µs
1kΩ
100
90
100
90
+V
S
**
1kΩ
V
2
3
7
IN
V
6
OUT
AD797
10
10
4
**
0%
0%
5V
–V
S
** SEE FIGURE 32
Figure 21. Inverter Sm all Signal
Pulse Response
Figure 19. Inverter
Connection
Figure 20. Inverter Large Signal
Pulse Response
100Ω
1µs
5V
50mV
100ns
+V
S
100
90
100
90
**
2
3
7
V
OUT
6
AD797
R
S
*
V
600Ω
IN
4
**
10
10
0%
0%
–V
S
* VALUE OF SOURCE RESISTANCE –
SEE TEXT
** SEE FIGURE 32
Figure 23. Follower Large Signal
Pulse Response
Figure 22. Follower
Connection
Figure 24. Follower Sm all Signal
Pulse Response
5mV
500ns
5mV
500ns
100
90
100
90
See Figure 40 for settling time
test circuit.
10
10
0%
0%
Figure 25. 16-Bit Settling Tim e
Positive Input Pulse
Figure 26. 16-Bit Settling Tim e
Negative Input Pulse
REV. C
–7–
AD797
TH EO RY O F O P ERATIO N
T his matching benefits not just dc precision but since it holds
up dynamically, both distortion and settling time are also
reduced. T his single stage has a voltage gain of >5 × 106 and
VOS <80 µV, while at the same time providing T HD + noise of
less than –120 dB and true 16 bit settling in less than 800 ns.
T he elimination of second stage noise effects has the additional
benefit of making the low noise of the AD797 (<0.9 nV/√Hz)
extend to beyond 1 MHz. T his means new levels of perfor-
mance for sampled data and imaging systems. All of this perfor-
mance as well as load drive in excess of 30 mA are made
possible by Analog Devices’ advanced Complementary Bipolar
(CB) process.
T he new architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous pre-
cision amplifiers used three stages to ensure high open-loop
gain, Figure 27b, at the expense of additional frequency com-
pensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not ad-
equate beyond audio frequencies. As can be seen in Figure 27b,
the first stage gain is rolled off at high frequencies by the com-
pensation network. Second stage noise and distortion will then
appear at the input and degrade performance. T he AD797 on
the other hand, uses a single ultrahigh gain stage to achieve dc
as well as dynamic precision. As shown in the simplified sche-
matic (Figure 28), nodes A, B, and C all track in voltage forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated
on the same IC chip, high open-loop gain, CMRR, PSRR, and
low VOS are all guaranteed by pairwise device matching (i.e.,
NPN to NPN & PNP to PNP), and not absolute parameters
such as beta and early voltage.
Another unique feature of this circuit is that the addition of a
single capacitor, CN (Figure 28), enables cancellation of distor-
tion due to the output stage. T his can best be explained by
referring to a simplified representation of the AD797 using ide-
alized blocks for the different circuit elements (Figure 29).
A single equation yields the open-loop transfer function of this
amplifier, solving it (at Node B) yields:
VO
VIN
gm
=
CN
A
CC
A
gm
BUFFER
V
OUT
jω –CN jω –
jω
R
R1
C1
L
gm = the transconductance of Q1 and Q2
A = the gain of the output stage, (~1)
VO = voltage at the output
6
GAIN = gmR1 5 x 10
VIN = differential input voltage
a.
When CN is equal to CC this gives the ideal single pole op amp
C2
A3
response:
VO
gm
=
VIN
jωC
gm
A2
C1
V
OUT
BUFFER
T he terms in A, which include the properties of the output
stage such as output impedance and distortion, cancel by
simple subtraction, and therefore the distortion cancellation
does not affect the stability or frequency response of the ampli-
fier. With only 500 µA of output stage bias the AD797 delivers
a 1 kHz sine wave into 600 Ω at 7 V rms with only 1 ppm of
distortion.
R1
R
L
R2
GAIN = gmR1 *A2 *A3
b.
Figure 27. Model of AD797 vs. That of a Typical
Three-Stage Am plifier
VCC
I1
I2
C
N
R2
R3
CN
R1
I5
Q4
B
A
OUT
Q10
Q11
Q3
Q7
A
A
B
OUT
–IN
+IN
C
C
Q9
CURRENT
MIRROR
Q2
I3
Q1
–IN
+IN
Q8
Q12
Q1 Q2
Q5
C
Q6
CC
1
I4
C
I6
I1
I7
I4
VSS
Figure 29. AD797 Block Diagram
Figure 28. AD797 Sim plified Schem atic
–8–
REV. C
AD797
NO ISE AND SO URCE IMP ED ANCE CO NSID ERATIO NS
T he AD797’s ultralow voltage noise of 0.9 nV/√Hz is achieved
with special input transistors running at nearly 1 mA of collector
current. It is important then to consider the total input referred
noise (eNtotal), which includes contributions from voltage noise
(eN), current noise (iN), and resistor noise (√4 kTrS).
2
LO W FREQ UENCY NO ISE
Analog Devices specifies low frequency noise as a peak to peak
(p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several tech-
niques can be used to make this measurement. T he usual tech-
nique involves amplifying, filtering, and measuring the amplifiers
noise for a predetermined test time. T he noise bandwidth of the
filter is corrected for and the test time is carefully controlled
since the measurement time acts as an additional low frequency
roll-off.
eNtotal = [eN + 4 kTrS + 4 (iNrS)2]l/2
Equation 1
where rS = total input source resistance.
T his equation is plotted for the AD797 in Figure 30. Since opti-
mum dc performance is obtained with matched source resis-
tances, this case is considered even though it is clear from
Equation 1 that eliminating the balancing source resistance will
lower the total noise by reducing the total rS by a factor of two.
T he plot in Figure 4 was made using a slightly different tech-
nique. Here an FFT based instrument (Figure 31) is used to
generate a 10 Hz “brickwall” filter. A low frequency pole at
0.1 Hz is generated with an external ac coupling capacitor, the
instrument being dc coupled.
At very low source resistance (rS <50 Ω), the amplifiers’ voltage
noise dominates. As source resistance increases the Johnson
noise of rS dominates until at higher resistances (rS >2 kΩ) the
current noise component is larger than the resistor noise.
Several precautions are necessary to get optimum low frequency
noise performance:
1. Care must be used to account for the effects of rS, even a
10 Ω resistor has 0.4 nV/√Hz of noise (an error of 9% when
root sum squared with 0.9 nV/√Hz).
100
2. T he test set up must be fully warmed up to prevent eOS drift
from erroneously contributing to input noise.
3. Circuitry must be shielded from air currents. Heat flow out
of the package through its leads creates the opportunity for a
thermoelectric potential at every junction of different metals.
Selective heating and cooling of these by random air currents
will appear as 1/f noise and obscure the true device noise.
TOTAL NOISE
10
RESISTOR
NOISE
ONLY
1
4. T he results must be interpreted using valid statistical
techniques.
100kΩ
0.1
+VS
10
100
1000
10000
**
SOURCE RESISTANCE – Ω
1Ω
Figure 30. Noise vs. Source Resistance
2
3
7
HP 3465
1.5µF
DYNAMIC SIGNAL
ANALYZER
(10Hz)
T he AD797 is the optimum choice for low noise performance
provided the source resistance is kept <1 kΩ. At higher values of
source resistance, optimum performance with respect to noise
alone is obtained with other amplifiers from Analog Devices (see
T able I).
6
AD797
VOUT
4
**
–VS
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
Table I. Recom m ended Am plifiers for D ifferent Source
Im pedances
WID EBAND NO ISE
rS, ohm s
Recom m ended Am plifier
T he AD797, due to its single stage design, has the property that
its noise is flat over frequencies from less than 10 Hz to beyond
1 MHz. T his is not true of most dc precision amplifiers where
second stage noise contributes to input referred noise beyond
the audio frequency range. T he AD797 offers new levels of per-
formance in wideband imaging applications. In sampled data
systems, where aliasing of out of band noise into the signal band
is a problem, the AD797 will out perform all previously avail-
able IC op amps.
0 to <1 k
AD797
1 k to <10 k
10 k to <100 k
>100 k
AD707, AD743/AD745, OP27/OP37, OP07
AD705, AD743/AD745, OP07
AD548, AD549, AD645, AD711, AD743/
AD745
REV. C
–9–
AD797
follower. Operation on 5 volt supplies allows the use of a 100 Ω
or less feedback network (R1 + R2). Since the AD797 shows
no unusual behavior when operating near its maximum rated
current, it is suitable for driving the AD600/AD602 (Figure 47)
while preserving their low noise performance.
BYP ASSING CO NSID ERATIO NS
T o take full advantage of the very wide bandwidth and dynamic
range capabilities of the AD797 requires some precautions.
First, multiple bypassing is recommended in any precision
application. A 1.0 µF–4.7 µF tantalum in parallel with 0.1 µF
ceramic bypass capacitors are sufficient in most applications.
When driving heavy loads a larger demand is placed on the sup-
ply bypassing. In this case selective use of larger values of tanta-
lum capacitors and damping of their lead inductance with small
value (1.1 Ω to 4.7 Ω) carbon resistors can be an improvement.
Figure 32 summarizes bypassing recommendations. T he symbol
(**) is used throughout this data sheet to represent the parallel
combination of a 0.1 µF and a 4.7 µF capacitor.
Optimum flatness and stability at noise gains >1 sometimes
requires a small capacitor (CL) connected across the feedback
resistor (R1, Figure 35). T able II includes recommended values
of CL for several gains. In general, when R2 is greater than
100 Ω and CL is greater than 33 pF, a 100 Ω resistor should
be placed in series with CL. Source resistance matching is
assumed, and the AD797 should never be operated with unbal-
anced source resistance >200 kΩ/G.
V
S
V
S
C
L
0.1µF
4.7 – 22.0µF
OR
Ω
100
4.7µF
0.1µF
1.1 – 4.7Ω
+V
S
KELVIN RETURN
KELVIN RETURN
**
USE SHORT
LEAD RETURNS
(<5mm)
USE SHORT
LEAD LENGTHS
(<5mm)
2
3
7
LOAD
CURRENT
LOAD
CURRENT
6
V
OUT
AD797
R
*
S
V
IN
4
**
Ω
600
Figure 32. Recom m ended Power Supply Bypassing
C
*
S
–V
S
TH E NO NINVERTING CO NFIGURATIO N
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Ultralow noise requires very low values of rBB’ (the internal
parasitic resistance) for the input transistors (≈6 Ω). T his im-
plies very little damping of input and output reactive interac-
tions. With the AD797, additional input series damping is
required for stability with direct input to output feedback. A
100 Ω resistor in the inverting input (Figure 33) is sufficient;
the 100 Ω balancing resistor (R2) is recommended, but is not
required for stability. T he noise penalty is minimal (eNtotal
≈2.1 nV/√Hz), which is usually insignificant. Best response
flatness is obtained with the addition of a small capacitor
(CL < 33 pF) in parallel with the 100 Ω resistor (Figure 34).
T he input source resistance and capacitance will also affect the
response slightly and experimentation may be necessary for best
results.
Figure 34. Alternative Voltage Follower Connection
C
L
R2
+V
S
**
R1
7
2
3
V
6
AD797
OUT
V
4
IN
R
**
L
R1
100Ω
–V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
+VS
**
Figure 35. Low Noise Pream plifier
2
3
7
Table II. Values for Follower With Gain Circuit
Noise
R2
100Ω
6
VOUT
AD797
VIN
RL
4
**
600Ω
Gain
R1
R2
CL
(Excluding rS)
–VS
2
2
10
20
>35
1 kΩ
1 kΩ
300 Ω
300 Ω
316 Ω
≈20 pF
≈10 pF
≈5 pF
3.0 nV/√Hz
1.8 nV/√Hz
1.2 nV/√Hz
1.0 nV/√Hz
0.98 nV/√Hz
300 Ω
33.2 Ω
16.5 Ω
10 Ω
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 33. Voltage Follower Connection
Low noise preamplification is usually done in the noninverting
mode (Figure 35). For lowest noise the equivalent resistance of
the feedback network should be as low as possible. T he 30 mA
minimum drive current of the AD797 makes it easier to achieve
this. T he feedback resistors can be made as low as possible with
due consideration to load drive and power consumption. T able
II gives some representative values for the AD797 as a low noise
(G–1) • 10 Ω
T he I-to-V converter is a special case of the follower configura-
tion. When the AD797 is used in an I-to-V converter, for in-
stance as a DAC buffer, the circuit of Figure 36 should be used.
The value of CL depends on the DAC and again, if CL is
–10–
REV. C
AD797
20–120pF
D RIVING CAP ACITIVE LO AD S
Ω
100
T he capacitive load driving capabilities of the AD797 are dis-
played in Figure 38. At gains over 10 usually no special precau-
tions are necessary. If more drive is desirable the circuit in
Figure 39 should be used. Here a 5000 pF load can be driven
R1
+V
S
**
I
IN
cleanly at any noise gain
≥
2.
2
3
7
V
6
100nF
AD797
OUT
4
Ω
600
**
C
*
R
*
S
S
10nF
1nF
–V
S
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 36. I-to-V Converter Connection
100pF
10pF
greater than 33 pF a 100 Ω series resistor is required. A by-
passed balancing resistor (RS and CS) can be included to mini-
mize dc errors.
1pF
1
TH E INVERTING CO NFIGURATIO N
10
100
1k
T he inverting configuration (Figure 37) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 will make it
the preferred choice in many inverting applications, and with care-
ful selection of feedback resistors the noise penalties will be mini-
mal. Some examples are presented in T able II and Figure 37.
CLOSED-LOOP GAIN
Figure 38. Capacitive Load Drive Capability vs. Closed
Loop Gain
20pF
Ω
1k
200pF
100
Ω
C
L
+V
S
R2
**
1k
Ω
2
+V
S
7
**
V
33Ω
IN
V
6
AD797
OUT
R1
2
7
C1
3
4
**
V
IN
6
V
OUT
AD797
–V
S
4
3
R
**
L
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
R
*
S
–V
S
Figure 39. Recom m ended Circuit for Driving a High
Capacitance Load
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
SETTLING TIME
Figure 37. Inverting Am plifier Connection
T he AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 µV) in less than 800 ns. Measuring this
performance presents a challenge. A special test setup (Figure
40) was developed for this purpose. T he input signal was ob-
tained from a resonant reed switch pulse generator, available
from T ektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. T he low repetition rate
signal was captured on a digital oscilloscope after being ampli-
fied and clamped twice. T he selection of plug-in for the oscillo-
scope was made for minimum overload recovery.
Table III. Values for Inverting Circuit
Noise
Gain
R1
R2
C L
(Excluding rS)
–1
–1
–10
1 kΩ
300 Ω
150 Ω
1 kΩ
300 Ω
1500 Ω
≈20 pF
≈10 pF
≈5 pF
3.0 nV/√Hz
1.8 nV/√Hz
1.8 nV/√Hz
REV. C
–11–
AD797
R1
TO TEKTRONIX
7A26
1MΩ
20pF
OSCILLOSCOPE
PREAMP INPUT
SECTION
50pF
R2
226
Ω
4.26kΩ
2
3
8
(VIA LESS THAN 1FT
50 COAXIAL CABLE)
Ω
6
AD797
2
3
V
X 5
250Ω
A2
AD829
V
IN
ERROR
6
7
2x
HP2835
4
a.
2x
HP2835
0.47µF
0.47µF
R1
+V
S
C2
C1
–V
S
1k
1k
Ω
Ω
R2
NOTE:
USE CIRCUIT
BOARD
WITH GROUND
PLANE
Ω
100
Ω
1k
2
3
8
TEKTRONIX
CALIBRATION
FIXTURE
6
AD797
V
IN
20pF
6
V
IN
1kΩ
2
3
C1, SEE TABLE
C2 = 50pF – C1
A1
AD797
51pF
7
b.
4
Figure 41. Recom m ended Connections for Distortion
Cancellation and Bandwidth Enhancem ent
0.1µF
1µF
0.1µF
–V
1µF
+V
S
S
Table IV. Recom m ended External Com pensation
Figure 40. Settling Tim e Test Circuit
D ISTO RTIO N RED UCTIO N
The AD797 has distortion performance (T H D < –120 dB, @
20 kH z, 3 V rms, RL = 600 Ω) unequaled by most voltage
feedback amplifiers.
A/B
R1 R2 C1 C2 3 dB
(pF) BW
A
B
C1 C2 3 dB
(pF) BW
Ω
Ω
G = 10
909 100
G = 100 1 k 10
G = 1000 10 k 10
0
0
0
50 6 MHz
50 1 MHz
50 110 kHz 33 15 450 kHz
0
50 6 MHz
15 33 1.5 MHz
At higher gains and higher frequencies T HD will increase due
to reduction in loop gain. However in contrast to most conven-
tional voltage feedback amplifiers the AD797 provides two effec-
tive means of reducing distortion, as gain and frequency are
increased; cancellation of the output stage’s distortion and gain
bandwidth enhancement by decompensation. By applying these
techniques gain bandwidth can be increased to 450 MH z at
G = 1000 and distortion can be held to –100 dB at 20 kHz for
G = 100.
0.01
–80
–90
G=1000
R =600Ω
L
0.003
NOISE LIMIT, G=1000
NOISE LIMIT, G=100
G=1000
R =10kΩ
L
0.001
–100
–110
–120
G=100
R =600Ω
T he unique design of the AD797 provides for cancellation of the
output stage’s distortion (patent pending). T o achieve this a ca-
pacitance equal to the effective compensation capacitance, usu-
ally 50 pF, is connected between Pin 8 and the output (C2 in
Figure 41). Use of this feature will improve distortion perfor-
mance when the closed loop gain is more than 10 or when fre-
quencies of interest are greater than 30 kHz.
L
0.0003
0.0001
G=10
R =600Ω
L
100
300
1k
3k
10k
30k
100k
300k
Bandwidth enhancement via decompensation is achieved by
connecting a capacitor from Pin 8 to ground (C1 in Figure 41)
effectively subtracting from the value of the internal compensa-
tion capacitance (50 pF), yielding a smaller effective compensa-
tion capacitance and, therefore, a larger bandwidth. T he
benefits of this begin at closed loop gains of 100 and up. A
maximum value of ≈33 pF at gains of 1000 and up is recom-
mended. At a gain of 1000 the bandwidth is 450 kHz.
FREQUENCY – Hz
Figure 42. Total Harm onic Distortion (THD) vs. Frequency
@ 3 V rm s for Figure 41b
T able IV and Figure 42 summarize the performance of the
AD797 with distortion cancellation and decompensation.
–12–
REV. C
AD797
D iffer ential Line Receiver
A Gener al P ur pose ATE/Instr um entation Input/O utput
T he differential receiver circuit of Figure 43 is useful for many
applications from audio to MRI imaging. It allows extraction of
a low level signal in the presence of common-mode noise. As
shown in Figure 44, the AD797 provides this function with only
9 nV/√Hz noise at the output. Figure 45 shows the AD797’s
20-bit T HD performance over the audio band and 16-bit accu-
racy to 250 kHz.
D r iver
T he ultralow noise and distortion of the AD797 may be com-
bined with the wide bandwidth, slew rate, and load drive of a
current feedback amplifier to yield a very wide dynamic range
general purpose driver. T he circuit of Figure 46 combines the
AD797 with the AD811 in just such an application. Using the
–90
–100
–110
–120
–130
0.003
20pF
WITHOUT
OPTIONAL
1kΩ
1kΩ
0.001
50pF C
N
+VS
**
50pF*
6
DIFFERENTIAL
INPUT
7
0.0003
0.0001
MEASUREMENT
LIMIT
2
3
8
AD797
OUTPUT
4
WITH
OPTIONAL
50C
*OPTIONAL
**
–VS
N
USE POWER SUPPLY
BYPASSING SHOWN IN
FIGURE 32.
**
1kΩ
1kΩ
100
300
1k
3k
10k
30k
100k
300k
FREQUENCY – Hz
Figure 45. Total Harm onic Distortion (THD) vs. Frequency
for Differential Line Receiver
20pF
Figure 43. Differential Line Receiver
component values shown, this circuit is capable of better than
–90 dB T HD with a ±5 V, 500 kHz output signal. T he circuit is
therefore suitable for driving high resolution A/D converters and
as an output driver in automatic test equipment (AT E) systems.
Using a 100 kHz sine wave, the circuit will drive a 600 Ω load to
a level of 7 V rms with less than –109 dB T HD, and a 10 kΩ
load at less than –117 dB T HD.
16
14
12
10
8
22pF
R2
+V
S
2kΩ
**
+V
S
**
2
3
7
3
6
7
AD797
6
1kΩ
10
100
1k
10k
100k
1M
10M
4
6
AD811
FREQUENCY — Hz
**
INPUT
OUTPUT
2
4
**
Figure 44. Output Voltage Noise Spectral Density for
Differential Line Receiver
–V
S
–V
649Ω
S
USE POWER SUPPLY
**
BYPASSING SHOWN IN
FIGURE 32.
649Ω
Figure 46. A General Purpose ATE/lnstrum entation Input/
Output Driver
REV. C
–13–
AD797
Ultr asound/Sonar Im aging P r eam p
–30
–40
–50
–60
–70
–80
100
80
60
40
20
0
T he AD600 variable gain amplifier provides the time controlled
gain (T CG) function necessary for very wide dynamic range so-
nar and low frequency ultrasound applications. Under some cir-
cumstances, it is necessary to buffer the input of the AD600 to
preserve its low noise performance. T o optimize dynamic range
this buffer should have at most 6 dB of gain. T he combination
of low noise and low gain is difficult to achieve. T he input
buffer circuit shown in Figure 47 provides 1 nV/√Hz noise per-
formance at a gain of two (dc to 1 MHz) by using 26.1 Ω resistors
in its feedback path. Distortion is only –50 dBc @ 1 MHz at a
2 volt p-p output level and drops rapidly to better than
–70 dBc at an output level of 200 mV p-p.
V
OUT
NOISE
26.1Ω
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
**
+V
S
Figure 49. Total Integrated Voltage Noise & VOUT of
Am orphous Detector Pream p
**
26.1
Ω
7
AD797
4
2
3
P r ofessional Audio Signal P r ocessing—D AC Buffer s
6
AD600
V
T he low noise and low distortion of the AD797 make it an ideal
choice for professional audio signal processing. An ideal I-to-V
converter for a current output DAC would simply be a resistor
to ground, were it not for the fact that most DACs do not oper-
ate linearly with voltage on their output. Standard practice is to
operate an op amp as an I-to-V converter creating a virtual
ground at its inverting input. Normally, clock energy and cur-
rent steps must be absorbed by the op amp’s output stage.
However, in the configuration of Figure 50, Capacitor CF
shunts high frequency energy to ground, while correctly repro-
ducing the desired output with extremely low T HD and IMD.
INPUT
OUT
**
**
–V
S
V
= ±6Vdc
* USE POWER SUPPLY
** BYPASSING SHOWN IN FIGURE 32.
S
Figure 47. An Ultrasound Pream plifier Circuit
Am or phous (P hotodiode) D etector
Large area photodiodes CS ≥ 500 pF and certain image detec-
tors (amorphous Si), have optimum performance when used in
conjunction with amplifiers with very low voltage rather than
very low current noise. Figure 48 shows the AD797 used with
an amorphous Si (CS = 1000 pF) detector. T he response is ad-
justed for flatness using capacitor CL, while the noise is domi-
nated by voltage noise amplified by the ac noise gain. T he 797’s
excellent input noise performance gives 27 µV rms total noise in
a 1 MHz bandwidth, as shown by Figure 49.
C
F
82pF
100Ω
3kΩ
+V
S
**
C
L
50pF
100Ω
AD1862
DAC
2
3
7
C1
2000pF
6
10kΩ
AD797
4
**
+V
S
**
–V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
2
3
7
6
Figure 50. A Professional Audio DAC Buffer
C
AD797
S
I
S
1000pF
4
**
–V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 48. Am orphous Detector Pream p
Figure 51. Offset Null Configuration
–14–
REV. C
AD797
OPERATIONAL AMPLIFIERS
LOW NOISE
LOW CURRENT NOISE – I
LOW VO LTAG E N O ISE – V
N
N
≤
√
(V
10 n V/ H z @ 1 k H z)
LOW INPUT BIAS CURRENT – I
N
BIAS
≤
√
≤
100 pA)
BIAS
(I
10 fA/ Hz @ 1 kHz, I
N
AUDIO
AMPLIFIERS
FET INPUT
PRECISION
LOW
POWER
LOW VN
ELECTROMETER
AD797
AD OP27
AD OP37
OP27
AD645
AD743
AD795
AD796 (Dual)
AD797
OP275
AD645
AD795
AD796 (Dual)
AD548
AD795
OP80
SSM2015
SSM2016
SSM2017
SSM2134
SSM2139
OP37
AD648 (Dual)
AD796 (Dual)
OP227 (Dual)
OP270 (Dual)
OP271 (Dual)
OP275 (Dual)
OP467 (Quad)
OP470 (Quad)
OP471 (Quad)
Fast
Lower V
N
AD743
AD745
Faster
Faster
(Slew Rate
≥
8 V/µs)
AD745
OP282 (Dual)
OP482 (Quad)
Low
FAST
Power
(Slew Rate 45 V/µs)
≥
High Output
Current
OP80
PRECISION
FAST
OP61
OP467 (Quad)
AD797
OP50
AD548
AD795
AD820
AD648 (Dual)
AD796 (Dual)
AD822 (Dual)
AD711
General
Purpose
AD712 (Dual)
OP249 (Dual)
AD713 (Quad)
Faster
AD515A
AD545A
AD546
≥
(Slew Rate 230 V/µs)
AD829
Faster
AD840
AD844
AD846
AD848
AD849
AD5539
ULTRALOW V
0.9 nV/ √Hz
N
Ultrafast
Lowest I BIA S
60 fA Max
AD744
OP42
OP44
(Slew Rate
≥ 1000 V/µs)
AD797
AD810
AD549
AD811
AD844
AD9610
AD9617
AD9618
AD746 (Dual)
REV. C
–15–
AD797
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Cerdip (Q) P ackage*
0.055 (1.4) MAX
5
0.005 (0.13) MIN
8
0.310 (7.87)
0.220 (5.59)
1
4
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.200
0.060 (1.52)
0.015 (0.38)
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0
- 15
SEATING PLANE
P lastic Mini-D IP
(N) P ackage
5
8
0.25
0.31
(6.35) (7.87)
1
4
0.30 (7.62)
0.39 (9.91)
MAX
REF
0.035 ± 0.01
(0.89 ± 0.25)
0.165 ± 0.01
(4.19 ± 0.25)
SEATING PLANE
0.011 ± 0.003
(4.57 ± 0.76)
0.125 (3.18)
MIN
0.18 ± 0.03
(4.57 ± 0.76)
0.10
0.018 ± 0.003
(0.46 ± 0.08)
0
- 15
(2.54)
TYP
0.033
(0.84)
NOM
8-P in SO IC (R) P ackage
0.198 (5.03)
0.188 (4.77)
5
8
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
0.228 (5.80)
4
1
0.018 (0.46)
0.014 (0.36)
0.050 (1.27)
TYP
0.205 (5.20)
0.181 (4.60)
0.069 (1.75)
0.053 (1.35)
0.010 (0.25)
0.004 (0.10)
0.015 (0.38)
0.007 (0.18)
0.045 (1.15)
0.020 (0.50)
*See m ilitar y data sheet for 883B specifications.
–16–
REV. C
相关型号：
AD797ACHIPS
IC OP-AMP, 125 uV OFFSET-MAX, 110 MHz BAND WIDTH, UUC8, DIE-8, Operational Amplifier
ADI
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