AD7982 [ADI]
18-bit, 1 MSPS PulSAR ADC in MSOP/QFN; 18位， 1 MSPS的PulSAR ADC ，采用MSOP / QFN
| 型号： | AD7982 |
| 厂家： | 
ADI |
| 描述： | 18-bit, 1 MSPS PulSAR ADC in MSOP/QFN |
| 文件： | 总23页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18-bit, 1 MSPS PulSAR™ ADC in MSOP/QFN
AD7982
Preliminary Technical Data
18-bit resolution with no missing codes
Throughput: 1MSPS
APPLICATION DIAGRAM EXAMPLE
2.5 TO 5V 2.5V
Low Power dissipation: 7.5 mW @ 1MSPS, 75 μW @ 10kSPS
INL: ±1 LSB typ, ±2.5 LSB max
Dynamic range: 99 dB
VIO
SDI
1.8 TO 5V
3- OR 4-WIRE
INTERFACE
(SPI, , CS
REF VDD
IN+
True differential analog input range: ±±REF
0 ± to ±REF with ±REF between 2.5± to 5.0±
Any input range and easy to drive with the ADA4941
No pipeline delay
SCK
SDO
CNV
AD7982
±10V, ±5V, ..
IN–
DAISY CHAIN)
GND
ADA4941
Single-supply 2.5± operation with 1.8 ±/2.5 ±/3 ±/5 ± logic
interface
Figure 1.
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
10-lead package: MSOP (MSOP-8 size) and
GENERAL DESCRIPTION
The AD7982 is a 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 18-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, it samples the voltage difference between IN+ and
IN− pins. The voltages on these pins usually swing in opposite
phase between 0 V and REF. The reference voltage, REF, is
applied externally and can be set independently of the supply
voltage, VDD.
QFN (LFCSP), 3 mm × 3 mm same space as SOT-23
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Seismic Data Acquisition Systems
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
Table 1. MSOP, QFN(LFCSP)/SOT-23 14, 16 and18-Bit ADC
100
kSPS
250
kSPS
400-
500
1000
kSPS
ADC
Driver
Type
kSPS
18Bit
AD76911 AD76901 AD79821 ADA4941
ADA4841
The AD7982 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
16Bit AD7680 AD76851 AD76861 AD79801 ADA4941
AD7683 AD76871 AD76881
ADA4841
AD7684 AD7694
AD76931
14Bit AD7940 AD79421 AD79461
1 Pin-for-pin compatible.
Rev PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7982
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Voltage Reference Input ............................................................ 13
Power Supply............................................................................... 13
Digital Interface.......................................................................... 14
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Circuit Information.................................................................... 10
Converter Operation.................................................................. 10
Typical Connection Diagram ................................................... 11
Analog Input ............................................................................... 12
Driver Amplifier Choice............................................................ 12
Single-to-Differential Driver..................................................... 13
Single-to-Differential Driver..................................................... 13
CS
CS
CS
MODE 3-Wire, No BUSY Indicator .................................. 15
Mode 3-Wire with BUSY Indicator ................................... 16
Mode 4-Wire with BUSY Indicator ................................... 18
Chain Mode, No BUSY Indicator ............................................ 19
Chain Mode with BUSY Indicator........................................... 20
Application Hints ........................................................................... 21
Layout .......................................................................................... 21
Evaluating the AD7982’s Performance.................................... 21
Outline Dimensions....................................................................... 22
RE±ISION HISTORY
Rev PrC | Page 2 of 23
Preliminary Technical Data
AD7982
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5V, VREF = 5V, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
IN+ − IN−
IN+, IN−
fIN = 1 MHz
Acquisition phase
−VREF
−0.1
+VREF
VREF + 0.1
V
V
dB
uA
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
66
150
See the Analog Input section
ACCURACY
No Missing Codes
18
−1
−2.5
Bits
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Zero Error2, TMIN to TMAX
Zero Temperature Drift
Power Supply Sensitivity
0.5
1
1.05
2
1
1
+2
+2.5
LSB1
LSB
LSB
LSB
ppm/°C
mV
REF = 5 V
1
0.1
ppm/°C
LSB
VDD = 2.5V ± 5%
THROUGHPUT
Conversion Rate
Transient Response
0
1
250
MSPS
ns
Full-scale step
AC ACCURACY
Dynamic Range
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Intermodulation Distortion4
VREF = 5 V
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz, VREF = 5 V
99
dB3
dB
dB
dB
dB
−120
−117
98
115
1 LSB means least significant bit. With the 5 V input range, one LSB is 38.15 μV.
2 See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale.
Rev PrC | Page 3 of 23
AD7982
Preliminary Technical Data
VDD = 2.5 V, VIO = 2.3 V to 5.5V, VREF = 5V, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions
Min
Typ
Max
Unit
2.4
5.1
V
μA
1MSPS, REF = 5 V
VDD = 2.5 V
500
10
2.5
MHz
ns
–0.3
0.7 × VIO
−1
0.3 × VIO
VIO + 0.3
+1
V
V
μA
μA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 18 bits twos complement
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK= +500 μA
ISOURCE= −500 μA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
2.37
2.3
2.5
2.63
5.5
V
V
Specified performance
VIO Range
Standby Current1, 2
Power Dissipation
1.8
5.5
V
nA
μW
mW
VDD and VIO = 2.5 V, 25°C
10 kSPS throughput
1 MSPS throughput
1
75
7.5
7.5
Energy per conversion
TEMPERATURE RANGE3
Specified Performance
nJ/sample
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
Rev PrC | Page 4 of 23
Preliminary Technical Data
AD7982
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated.
Table 4. 1
Parameter
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
350
250
1000
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
750
CS
CNV Pulse Width ( Mode )
CS
SCK Period ( Mode or Chain mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.7 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
10
10.5
11.5
12.5
14.5
3
tSCKL
tSCKH
tHSDO
tDSDO
3
3
7.5
8
9
10
13
ns
ns
ns
ns
ns
VIO Above 2.3 V
VIO Above 1.7 V
CS
tEN
CNV or SDI Low to SDO D15 MSB Valid ( Mode)
VIO Above 3 V
VIO Above 2.3 V
10
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS
tDIS
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance ( Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
2.5
3
15
1 See Figure 2 and Figure 3 for load conditions.
Rev PrC | Page 5 of 23
AD7982
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Analog Inputs
IN+1, IN−1 to GND
−0.3 V to VREF + 0.3 V
or 130 mA
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
−0.3 V to +6.0V
−0.3 V to +3.0 V
+3V to −6V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature Range
Vapor Phase (60 sec)
Infrared (15 sec)
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W (MSOP-10)
44°C/W (MSOP-10)
215°C
220°C
1 See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500μA
I
OL
1.4V
TO SDO
C
L
20pF
500μA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
Figure 3. Voltage Levels for Timing
Rev PrC | Page 6 of 23
Preliminary Technical Data
AD7982
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
REF 1
VDD 2
IN+ 3
10 VIO
9
8
7
6
SDI
AD7982
TOP VIEW
9
8
7
6
SDI
AD7982
SCK
SDO
CNV
SCK
SDO
CNV
(Not to Scale)
TOP VIEW
IN–
IN– 4
GND
GND 5
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Figure 4. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1
REF
AI
Reference Input Voltage. The REF range is from 2.3 V to 5.5V. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
AI
AI
P
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
CS
CS
selects the interface mode of the part, chain or
mode. In mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 18 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power
Rev PrC | Page 7 of 23
AD7982
Preliminary Technical Data
TERMINOLOGY
Noise-free-code-resolution
It is the number of bits beyond which it is impossible to
distinctly resolve individual codes. It is calculated as :
Integral Nonlinearity Error (INL)
It refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 12).
Noise-Free Code resolution = log2(2N/peak-to-peak noise)
and is expressed in bits.
Effective resolution
Differential Nonlinearity Error (DNL)
It is calculated as :
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Effective resolution = log2(2N/rms input noise)
and is expressed in bits.
Zero Error
Total Harmonic Distortion (THD)
The difference between the ideal midscale voltage, that is, 0 V,
from the actual voltage producing the midscale output code,
that is, 0 LSB.
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Gain Error
Dynamic Range
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the 5 V range). The last transition (from 011…10 to
011…11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the 5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
It is the ratio of the rms value of the full scale to the total rms
noise measured with the inputs shorted together. The value for
dynamic range is expressed in dB. It is measured with a signal at
-60dBFs to include all noise sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
ENOB = (S/[N + D]dB − 1.76)/6.02
Aperture Delay
and is expressed in bits.
The measure of the acquisition performance and is the time
between the rising edge of the CNV input and when the input
signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
Rev PrC | Page 8 of 23
Preliminary Technical Data
AD7982
TYPICAL PERFORMANCE CHARACTERISTICS: VDD=2.5V, VREF=5.0V, VIO=3.3V
Figure 9. Differential Nonlinearity vs. Code
Figure 6. Integral Nonlinearity vs. Code
Figure 10. Histogram of a DC Input at the Code Transition
Figure 7. Histogram of a DC Input at the Code Center
0
-20
fS = 1 MSPS
fIN
= 2kHz
SNR = 96dB
THD = -117dB
SFDR = 120dB
SINAD = 96dB
-40
-60
-80
-100
-120
-140
-160
-180
0
100
200
300
400
500
FREQUENCY (kHz)
Figure 8. FFT Plot
Rev PrC | Page 9 of 23
AD7982
Preliminary Technical Data
IN+
SWITCHES CONTROL
MSB
LSB
LSB
SW+
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
GND
OUTPUT CODE
32,768C 16,384C
MSB
SW–
CNV
IN–
Figure 11. ADC Simplified Schematic
CIRCUIT INFORMATION
CON±ERTER OPERATION
The AD7982 is a fast, low power, single-supply, precise 18-bit
ADC using a successive approximation architecture.
The AD7982 is a successive approximation ADC based on a
charge redistribution DAC. Figure 11 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors, which are
connected to the two comparator inputs.
The AD7982 is capable of converting 1,000,000 samples per
second (1MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it consumes 75 μW typically,
ideal for battery-powered applications.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/262144).
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced
The AD7982 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7982 can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN
(LFCSP) that combines space savings and allows flexible
configurations.
It is pin-for-pin-compatible with the 16-bit AD7980.
condition. After the completion of this process, the part returns
to the acquisition phase and the control logic generates the
ADC output code and a BUSY signal indicator.
Because the AD7982 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev PrC | Page 10 of 23
Preliminary Technical Data
AD7982
Transfer Functions
TYPICAL CONNECTION DIAGRAM
The ideal transfer characteristic for the AD7982 is shown in
Figure 12 and Table 7.
Figure 13 shows an example of the recommended connection
diagram for the AD7982 when multiple supplies are available.
011...111
011...110
011...101
100...010
100...001
100...000
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
–FS + 0.5 LSB
ANALOG INPUT
Figure 12. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
Description
±REF = 5 ±
Digital Output Code Hexa
FSR – 1 LSB
+4.999962 V
1FFFF1
00001
00000
3FFFF
20001
200002
Midscale + 1 LSB +38.15 μV
Midscale 0 V
Midscale – 1 LSB −38.15 μV
–FSR + 1 LSB
–FSR
−4.999962 V
−5 V
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF
−
VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
1
V+
V+
REF
2.5V
2
10μF
100nF
1.8V TO 5V
100nF
20Ω
REF
VDD
VIO
SDI
0 TO VREF
IN+
IN–
2.7nF
4
SCK
SDO
CNV
V-
AD7982
3-WIRE INTERFACE
V+
GND
20Ω
VREF TO 0
2.7nF
4
ADA4841-2 or
note 3
V-
1
SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2
3
4
C
IS USUALLY A 10μF CERAMIC CAPACITOR (X5R).
REF
SEE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
Figure 13. Typical Application Diagram with Multiple Supplies
Rev PrC | Page 11 of 23
AD7982
Preliminary Technical Data
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7982. The noise
coming from the driver is filtered by the AD7982 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used. Because the typical
noise of the AD7982 is 40 μV rms, the SNR degradation
due to the amplifier is
ANALOG INPUT
Figure 14 shows an equivalent circuit of the input structure of
the AD7982.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forward-
bias and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit, current limitation can be used to
protect the part.
⎛
⎜
⎞
⎟
40
⎜
⎜
⎟
⎟
SNRLOSS = 20log
π
402 + f−3dB (NeN )2
⎜
⎝
⎟
⎠
2
REF
where:
D1
f
–3dB is the input bandwidth in MHz of the AD7982
C
IN
R
IN
IN+
OR IN–
(10MHz) or the cutoff frequency of the input filter, if one is
used.
C
PIN
D2
GND
N is the noise gain of the amplifier (for example, +1 in
buffer configuration).
Figure 14. Equivalent Analog Input Circuit
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7982.
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 400 Ω and is a lumped component made up of
some serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a 1-
pole, low-pass filter that reduces undesirable aliasing effects and
limits the noise.
For multichannel multiplexed applications, the driver
amplifier and the AD7982 analog input circuit must settle
for a full-scale step onto the capacitor array at a 18-bit level
(0.0004%, 4 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 18-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier
Typical Application
ADA4941
Very low noise, low power single to
Differential
When the source impedance of the driving circuit is low, the
AD7982 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
ADA4841
AD8021
AD8022
OP184
AD8655
Very low noise, small and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low noise
AD8605, AD8615
5 V single-supply, low power
DRI±ER AMPLIFIER CHOICE
Although the AD7982 is easy to drive, the driver amplifier
needs to meet the following requirements:
Rev PrC | Page 12 of 23
Preliminary Technical Data
AD7982
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
SINGLE-TO-DIFFERENTIAL DRI±ER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941 single-ended-to-differential
driver allows for a differential input into the part. The
schematic is shown in Figure 15.
POWER SUPPLY
It uses two power supply pins: a core supply VDD and a digital
input/output interface supply VIO. VIO allows direct interface
with any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together. The AD7982 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range.
R1, R2 set the attenuation ratio between the input range and the
ADC range (VREF). R1, R2 and CF shall be chosen depending on
the desired input resistance, signal bandwidth, anti-aliasing and
noise contribution.
– e.g.: for +/-10V range with 4k Ω impedance, R2=1k Ω and
R1= 4k Ω
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example if REF is 5.0V,
VDD should be set to 2.5V (+/-5%).
R3, R4 and R5, R6 set the common mode on, respectively, the
IN- and IN+ inputs of the ADC which should be close to
VREF/2.
The AD7982 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (even a few Hz) and low battery-powered applications.
– e.g.: for +/-10V range with single supply, R3=8.45k Ω, R4=
11.8k Ω and R5=10.5kΩ, R6= 9.76kΩ
R5
R6
R3
R4
5V REF
10μF
5.2V
2.5V
VDD
100nF
100nF
REF
20Ω
20Ω
IN+
IN–
2.7nF
2.7nF
AD7982
GND
ADA4941
-0.2V
R2
±10V, ±5V, ..
R1
C
F
Figure 15. Single-Ended-to-Differential Driver Circuit
±OLTAGE REFERENCE INPUT
The AD7982 voltage reference input, REF, has a dynamic, input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Rev PrC | Page 13 of 23
AD7982
Preliminary Technical Data
DIGITAL INTERFACE
Though the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
The AD7982, when in
mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-
219x. This interface can use either 3-wire or 4-wire. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7982, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
CS
when the CNV rising edge occurs. The
mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7982 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
The BUSY indicator feature is enabled as:
CS
• In the
mode, if CNV or SDI is low when the ADC
conversion ends (Figure 19 and Figure 23).
• In the chain mode, if SCK is high during the CNV rising edge
(Figure 27).
Rev PrC | Page 14 of 23
Preliminary Technical Data
AD7982
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 18th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI compatible digital host. The connection diagram is
shown in Figure 16 and the corresponding timing is given in
Figure 17.
CONVERT
With SDI tied to VIO, a rising edge on CNV initiates a
DIGITAL HOST
CNV
CS
conversion, selects the
mode, and forces SDO to high
VIO
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7982
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
SDI
SDO
DATA IN
AD7982
SCK
CLK
CS
Figure 16. Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
16
17
18
tHSDO
tSCKH
tDSDO
tEN
tDIS
D17
D16
D15
D1
D0
SDO
CS
Figure 17. Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev PrC | Page 15 of 23
AD7982
Preliminary Technical Data
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 19th SCK falling edge, or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI compatible digital host having an interrupt input.
The connection diagram is shown in Figure 18 and the
corresponding timing is given in Figure 19.
If multiple AD7982s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7982 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
CONVERT
VIO
DIGITAL HOST
CNV
AD7982
SCK
VIO
47k
Ω
SDI
SDO
DATA IN
IRQ
CLK
CS
Figure 18. Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
17
18
19
tHSDO
tSCKH
tDSDO
tDIS
D17
D16
D1
D0
SDO
CS
Figure 19. Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev PrC | Page 16 of 23
Preliminary Technical Data
AD7982
time and held high until the maximum conversion time to
CS
Mode 4-Wire, No BUSY Indicator
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7982 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
18th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7982
can be read.
This mode is usually used when multiple AD7982s are
connected to an SPI compatible digital host.
A connection diagram example using two AD7982s is shown in
Figure 20 and the corresponding timing is given in Figure 21.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
AD7982
SDO
SDI
SDO
SDI
AD7982
SCK
SCK
DATA IN
CLK
CS
Figure 20. Mode 4-Wire, No BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
16
17
18
19
20
34
35
36
tHSDO
tSCKH
tDSDO
tDIS
tEN
SDO
D17
D16
D15
D1
D0
D17
D16
D1
D0
CS
Figure 21. Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev PrC | Page 17 of 23
AD7982
Preliminary Technical Data
the digital host. The AD7982 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 19th SCK falling edge, or SDI going high, whichever is
earlier, the SDO returns to high impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 22 and the
corresponding timing is given in Figure 23.
CS1
CONVERT
With SDI high, a rising edge on CNV initiates a conversion,
VIO
DIGITAL HOST
CNV
SDI AD7982 SDO
SCK
CS
selects the
mode, and forces SDO to high impedance. In this
47kΩ
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
DATA IN
IRQ
CLK
CS
Figure 22. Mode 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
17
18
19
tHSDO
tDSDO
tSCKH
tDIS
tEN
D17
D16
D1
D0
CS
Figure 23. Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev PrC | Page 18 of 23
Preliminary Technical Data
AD7982
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7982 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and, consequently more AD7982s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy chain multiple AD7982s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, e.g., in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register.
A connection diagram example using two AD7982s is shown in
Figure 24 and the corresponding timing is given in Figure 25.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
CNV
DIGITAL HOST
SDI AD7982 SDO
SDI
SDO
DATA IN
AD7982
A
B
SCK
SCK
CLK
Figure 24. Chain Mode, No BUSY Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
16
17
18
19
20
34
35
36
tHSCKCNV
tSSDISCK
tSCKH
tHSDISC
tEN
D 17
A
D 16
A
D 15
A
D 1
A
D 0
A
SDO = SDI
A
B
tHSDO
tDSDO
D 17
B
D 16
B
D 15
B
D 1
B
D 0
B
D 17
A
D 16
A
D 1
A
D 0
A
SDO
B
Figure 25. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev PrC | Page 19 of 23
AD7982
Preliminary Technical Data
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC ( ADC C in
Figure 26) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7982 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 18 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and,
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy chain multiple AD7982s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, e.g., in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7982s is shown
in Figure 26 and the corresponding timing is given in Figure 27.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
consequently more AD7982s in the chain, provided the digital
host has an acceptable hold time.
CONVERT
CNV
CNV
CNV
DIGITAL HOST
DATA IN
SDI
SDO
SDI
SDO
SDI
SDO
AD7982
AD7982
AD7982
A
B
C
IRQ
SCK
SCK
SCK
CLK
Figure 26. Chain Mode with BUSY Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
4
17
18
19
20
21
35
36
37
38
39
53
54
55
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISC
tEN
SDO = SDI
D 17 D 16 D 15
D 1 D 0
A A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D 17 D 16 D 15
D 1 D 0 D 17 D 16
D 1 D 0
A A
C
B
B
B
B
B
A
A
tDSDOSDI
SDO
D 17 D 16 D 15
D 1 D 0 D 17 D 16
D 1 D 0 D 17 D 16
D 1 D 0
C
C
C
C
C
C
B
B
B
B
A
A
A
A
Figure 27. Chain Mode with BUSY Indicator Serial Interface Timing
Rev PrC | Page 20 of 23
Preliminary Technical Data
AD7982
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7982 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7982, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
AD7982
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7982 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided
At least one ground plane should be used. It could be common
or split between the digital and analog section. In the latter case,
the planes should be joined underneath the AD7982s.
The AD7982 voltage reference input REF has a dynamic, input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connected with wide, low impedance traces.
Figure 28. Example of Layout of the AD7982 (Top Layer)
Finally, the power supplies VDD and VIO of the AD7982
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7982 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 28 and Figure 29.
E±ALUATING THE AD7982’S PERFORMANCE
Other recommended layouts for the AD7982 are outlined
in the documentation of the evaluation board for the AD7982
(EVAL-AD7982-CB). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Figure 29. Example of Layout of the AD7982 (Bottom Layer)
Rev PrC | Page 21 of 23
AD7982
Preliminary Technical Data
OUTLINE DIMENSIONS
3.00 BSC
6
10
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 30.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
ELECTRICAL PERFORMANCES
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 31. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev PrC | Page 22 of 23
Preliminary Technical Data
NOTES
AD7982
Rev PrC | Page 23 of 23
PR06513-0-11/06(PrC)
相关型号：
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