AD7997BRU-0REEL_技术文档

8-Channel, 10- and 12-Bit ADCs with I²C-

Compatible Interface in 20-Lead TSSOP

AD7997/AD7998

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

AGND

REF

IN

CONVST

DD

10- and 12-bit ADC with fast conversion time: 2 µs typ

8 single-ended analog input channels

Specified for V_DDof 2.7 V to 5.5 V

Low power consumption

Fast throughput rate: up to 188 kSPS

Sequencer operation

AD7997/AD7998

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

V

1

IN

CONTROL

LOGIC

T/H

8:1

I/P

MUX

OSCILLATOR

8

IN

Automatic cycle mode

I²C®-compatible serial interface supports standard, fast,

and high speed modes

CONVERSION

RESULT

REGISTER

DATA

LIMIT

LOW

REGISTER CH1–CH4

Out-of-range indicator/alert function

Pin-selectable addressing via AS

Shutdown mode: 1 µA max

Temperature range: −40°C to +85°C

20-lead TSSOP package

CONFIGURATION

REGISTER

ALERT/BUSY

DATA

HIGH

LIMIT

REGISTER CH1–CH4

ALERT STATUS

REGISTER

HYSTERESIS

CYCLE TIMER

REGISTER

REGISTER CH1–CH4

See the AD7992 and AD7994 for 2-channel and 4-channel

equivalent devices, respectively

AS

SCL

SDA

2

I C INTERFACE

AGND

GENERAL DESCRIPTION

Figure 1.

The AD7997/AD7998 are 8-channel, 10- and 12-bit, low power,

successive approximation ADCs with an I²C-compatible

interface. The parts operate from a single 2.7 V to 5.5 V power

supply and feature a 2 µs conversion time. The parts contain an

8-channel multiplexer and track-and-hold amplifier that can

handle input frequencies up to 11 MHz.

On-chip limit registers can be programmed with high and

low limits for the conversion result, and an open-drain, out-of-

range indicator output (ALERT) becomes active when the

programmed high or low limits are violated by the conversion

result. This output can be used as an interrupt.

PRODUCT HIGHLIGHTS

The AD7997/AD7998 provide a 2-wire serial interface that is

compatible with I²C interfaces. Each part comes in two versions,

AD7997-0/AD7998-0 and AD7997-1/AD7998-1, and each

version allows at least two different I²C addresses. The I²C

interface on the AD7997-0/AD7998-0 supports standard and

fast I²C interface modes. The I²C interface on the AD7997-1/

AD7998-1 supports standard, fast, and high speed I²C interface

modes.

1. 2 µs conversion time with low power consumption.

2. I²C-compatible serial interface with pin-selectable

addresses. Two AD7997/AD7998 versions allow five

AD7997/AD7998 devices to be connected to the same

serial bus.

3. The parts feature automatic shutdown while not converting

to maximize power efficiency. Current consumption is 1 µA

max when in shutdown mode at 3V.

The AD7997/AD7998 normally remain in a shutdown state

while not converting, and power up only for conversions. The

4. Reference can be driven up to the power supply.

conversion process can be controlled using the

pin,

CONVST

by a command mode where conversions occur across I²C write

operations or an automatic conversion interval mode selected

through software control.

5. Out-of-range indicator that can be software disabled or

enabled.

6. One-shot and automatic conversion rates.

The AD7997/AD7998 require an external reference that should

be applied to the REF_INpin and can be in the range of 1.2 V to

V_DD. This allows the widest dynamic input range to the ADC.

7. Registers store minimum and maximum conversion

results.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD7997/AD7998

TABLE OF CONTENTS

AD7997 Specifications..................................................................... 3

AD7998 Specifications..................................................................... 5

I²C Timing Specifications................................................................ 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Pin Function Descriptions.................... 10

Terminology .................................................................................... 11

Typical Performance Characteristics ........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical Connection Diagram ................................................... 16

Analog Input ............................................................................... 16

Internal Register Structure ............................................................ 18

Address Pointer Register ........................................................... 18

Configuration Register .............................................................. 19

Conversion Result Register ....................................................... 20

Limit Registers ............................................................................ 20

Alert Status Register (CH1 to CH4) ........................................ 21

Cycle Timer Register.................................................................. 22

Sample Delay and Bit Trial Delay............................................. 22

Serial Interface ................................................................................ 23

Serial Bus Address...................................................................... 23

Writing to the AD7997/AD7998 .................................................. 24

Writing to the Address Pointer Register for a Subsequent

Read.............................................................................................. 24

Writing a Single Byte of Data to the Alert Status Register or

Cycle Register.............................................................................. 24

Writing Two Bytes of Data to a Limit, Hysteresis, or

Configuration Register .............................................................. 24

Reading Data from the AD7997/AD7998................................... 26

ALERT/BUSY Pin .......................................................................... 27

SMBus ALERT............................................................................ 27

BUSY............................................................................................ 27

Placing the AD7997-1/AD7998-1 into High Speed Mode ... 27

The Address Select (AS) Pin ..................................................... 27

Modes of Operation ....................................................................... 28

CONVST

Mode 1—Using the

Pin ........................................... 28

Mode 2 – COMMAND MODE ............................................... 29

Mode 3—Automatic Cycle Interval Mode.............................. 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Related Parts in I²C-Compatible ADC Product Family........ 31

REVISION HISTORY

9/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7997/AD7998

AD7997 SPECIFICATIONS

Temperature range for B version is −40°C to +85°C. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; REF_IN= 2.5 V; For the AD7997-0, all

specifications apply for f_SCLup to 400 kHz; for the AD7997-1, all specifications apply for f_SCLup to 3.4 MHz, unless otherwise noted;

T_A= T_MINto T_MAX

.

Table 1.

Parameter

DYNAMIC PERFORMANCE¹

B Version

Unit

Test Conditions/Comments

F_IN= 10 kHz sine wave for f_SCLfrom 1.7 MHz to

3.4 MHz

F_IN= 1 kHz sine wave for f_SCLup to 400 kHz

Signal to Noise + Distortion (SINAD)²

Total Harmonic Distortion (THD) ²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

61

–75

–76

dB min

dB max

fa = 10.1 kHz, fb = 9.9 kHz for f_SCLfrom 1.7 MHz

to 3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f_SCLup to 400 kHz

Second-Order Terms

Third-Order Terms

–86

10

dB typ

ns max

ps typ

Aperture Delay²

Aperture Jitter²

50

Channel-to-Channel Isolation²

Full-Power Bandwidth²

–90

11

2

dB typ

MHz typ

F_IN= 108 Hz, see the Terminology section

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

10

Bits

Integral Nonlinearity^{1, 2}

Differential Nonlinearity^{1, 2}

Offset Error²

0.5

1.5

2.5

0.5

1.5

0.5

LSB max

Guaranteed no missed codes to 10 bits

Mode 1 (CONVST Mode)

Mode 2 (Command Mode)

Offset Error Match²

Gain Error²

Gain Error Match²

ANALOG INPUT

Input Voltage Range

DC Leakage Current

Input Capacitance

0 to REF_IN

1

30

V

µA max

pF typ

REFERENCE INPUT

REF_INInput Voltage Range

DC Leakage Current

Input Impedance

1.2 to V_DD

1

69

V min/V max

µA max

kΩ typ

During a conversion

V_IN= 0 V or V_DD

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current, I_IN

0.7 (V_DD)

0.3 (V_DD)

1

10

0.1 (V_DD)

V min

V max

µA max

pF max

V min

3

Input Capacitance, C_IN

Input Hysteresis, V_HYST

Rev. 0 | Page 3 of 32

AD7997/AD7998

Parameter

B Version

Unit

Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V_INH

2.4

2.0

0.8

0.4

1

V min

V max

µA max

pF max

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

Input Low Voltage, V_INL

Input Leakage Current, I_IN

V_IN= 0 V or V_DD

3

Input Capacitance, C_IN

10

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, V_OL

0.4

0.6

1

V max

µA max

pF max

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

10

Straight (Natural) Binary

CONVERSION RATE

See the Modes of Operation section

Conversion Time

2

µs typ

Throughput Rate

Mode 1 (Reading after the Conversion)

5

21

kSPS typ

f_SCL= 100 kHz

f_SCL= 400 kHz

121

5.5

22

kSPS typ

f_SCL= 3.4 MHz

f_SCL= 100 kHz

f_SCL= 400 kHz

f_SCL= 3.4 MHz, 188 kSPS typ @ 5 V

Mode 2

147

POWER REQUIREMENTS

V_DD

2.7/5.5

V min/max

I_DD

Digital inputs = 0 V or V_DD

V_DD= 3.3 V/5.5 V

Power-Down Mode, Interface Inactive

Power-Down Mode, Interface Active

1/2

µA max

mA max

mA typ

0.07/0.3

0.3/0.6

0.06/0.1

0.3/0.6

0.15/0.4

0.6/1.1

0.7/1.4

0.7/1.5

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 1

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 2

V_DD= 3.3 V/5.5 V

Operating, Interface Inactive

Operating, Interface Active

Mode 3 (I²C Inactive, T_CONVERTx 32)

Power Dissipation

mA max

Fully Operational

Operating, Interface Active

0.495/2.2

1.98/6.05

2.31/7.7

3.3/11

mW max

mW typ

µW max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 1

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 2

V_DD= 3.3 V/5.5 V

Power Down, Interface Inactive

¹Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I²C Hs-Mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

²See the Terminology section.

³Guaranteed by initial characterization.

Rev. 0 | Page 4 of 32

AD7997/AD7998

AD7998 SPECIFICATIONS

Temperature range for B version is −40°C to +85°C. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; REF_IN= 2.5 V; For the AD7998-0, all

specifications apply for f_SCLup to 400 kHz; for the AD7998-1, all specifications apply for f_SCLup to 3.4 MHz, unless otherwise noted;

T_A= T_MINto T_MAX

.

Table 2.

Parameter

DYNAMIC PERFORMANCE¹

B Version

Unit

Test Conditions/Comments

F_IN= 10 kHz sine wave for f_SCLfrom 1.7 MHz to

3.4 MHz

F_IN= 1 kHz sine wave for f_SCLup to 400 kHz

Signal-to-Noise + Distortion (SINAD)²

Signal to Noise Ratio (SNR)²

Total Harmonic Distortion (THD)²

Peak Harmonic or Spurious Noise (SFDR)²

Intermodulation Distortion (IMD)²

70.5

71

–78

–79

dB min

dB max

fa = 10.1 kHz, fb = 9.9 kHz f_SCLfrom 1.7 MHz to

3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f_SCLup to 400 kHz

Second-Order Terms

Third-Order Terms

–90

10

dB typ

ns max

ps typ

Aperture Delay²

Aperture Jitter²

50

Channel-to-Channel Isolation²

Full-Power Bandwidth²

–90

11

2

dB typ

MHz typ

F_IN= 108 Hz, see the Terminology section

@ 3 dB

@ 0.1 dB

DC ACCURACY

Resolution

Integral Nonlinearity^1,2

12

1

Bits

LSB max

LSB typ

LSB max

LSB typ

LSB max

0.2

+1/–0.9

0.2

4

Differential Nonlinearity^1,2

Offset Error²

Guaranteed no missed codes to 12 bits

Mode 1 (CONVST Mode)

Mode 2 (Command Mode)

6

1

2

1

Offset Error Match²

Gain Error²

Gain Error Match²

ANALOG INPUT

Input Voltage Range

DC Leakage Current

Input Capacitance

0 to REF_IN

1

30

V

µA max

pF typ

REFERENCE INPUT

REF_INInput Voltage Range

DC Leakage Current

Input Impedance

1.2 to V_DD

1

69

V min/V max

µA max

kΩ typ

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current, I_IN

Input Capacitance, C_IN

Input Hysteresis, V_HYST

0.7 (V_DD)

0.3 (V_DD)

1

10

0.1 (V_DD)

V min

V max

µA max

pF max

V min

V_IN= 0 V or V_DD

3

Rev. 0 | Page 5 of 32

AD7997/AD7998

Parameter

B Version

Unit

Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V_INH

2.4

2.0

0.8

0.4

1

V min

V max

µA max

pF max

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

Input Low Voltage, V_INL

Input Leakage Current, I_IN

V_IN= 0 V or V_DD

3

Input Capacitance, C_IN

10

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, V_OL

0.4

0.6

1

V max

µA max

pF max

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance³

Output Coding

10

Straight (Natural) Binary

CONVERSION RATE

See the Modes of Operation section

Conversion Time

2

µs typ

Throughput Rate

Mode 1 (Reading after the Conversion)

5

21

121

5.5

22

kSPS typ

f_SCL= 100 kHz

f_SCL= 400 kHz

f_SCL= 3.4 MHz

f_SCL= 100 kHz

f_SCL= 400 kHz

f_SCL= 3.4 MHz , 188 kSPS typ @ 5 V

Mode 2

147

POWER REQUIREMENTS

V_DD

2.7/5.5

V min/max

I_DD

Digital inputs = 0 V or V_DD

V_DD= 3.3 V/5.5 V

Power-Down Mode, Interface Inactive

Power-Down Mode, Interface Active

1/2

µA max

mA max

mA typ

0.07/0.3

0.3/0.6

0.06/0.1

0.3/0.6

0.15/0.4

0.6/1.1

0.7/1.4

0.7/1.5

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCL

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 1

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 2

V_DD= 3.3 V/5.5 V

Operating, Interface Inactive

Operating, Interface Active

Mode 3 (I²C Inactive, T_CONVERTx 32)

Power Dissipation

mA max

Fully Operational

Operating, Interface Active

0.495/2.2

1.98/6.05

2.31/7.7

3.3/11

mW max

mW typ

µW max

V_DD= 3.3 V/5.5 V, 400 kHz f_SCL

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 1

V_DD= 3.3 V/5.5 V, 3.4 MHz f_SCLMode 2

V_DD= 3.3 V/5.5 V

Power Down, Interface Inactive

¹Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I²C Hs-Mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

²See the Terminology section.

³Guaranteed by initial characterization.

Rev. 0 | Page 6 of 32

AD7997/AD7998

I²C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values measured with input filtering enabled. C_Brefers to capacitive load on the bus line. t_rand

t_fmeasured between 0.3 VDD and 0.7 VDD.

High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to

both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, V_DD= 2.7 V to 5.5 V; REF_IN= 2.5 V;

T_A=T_MINto T_MAX

.

Table 3.

AD7997/AD7998 Limit at T_MIN, T_MAX

Parameter

Conditions

Min

Max

100

400

Unit

kHz

Description

f_SCL

Standard mode

Fast mode

Serial clock frequency

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

3.4

1.7

MHz

µs

t₁

t₂

t₃

4

0.6

t_HIGH, SCL high time

t_LOW, SCL low time

µs

60

ns

µs

120

4.7

1.3

160

320

250

100

10

ns

µs

t_SU;DAT, data setup time

t_HD;DAT, data hold time

1

t₄

0

3.45

0.9

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

0

70²

150

ns

µs

ns

µs

ns

µs

ns

t₅

t₆

4.7

0.6

160

4

0.6

160

4.7

1.3

4

t_SU;STA, setup time for a repeated start condition

t_HD;STA, hold time (repeated) start condition

High speed mode

Standard mode

Fast mode

t₇

t₈

t_BUF, bus free time between a stop and a start condition

t_SU;STO, setup time for stop condition

Standard mode

Fast mode

High speed mode

Standard mode

Fast mode

0.6

160

t₉

1000

300

t_RDA, rise time of SDA signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

10

20

80

160

ns

Rev. 0 | Page 7 of 32

AD7997/AD7998

AD7997/AD7998 Limit at T_MIN, T_MAX

Parameter

Conditions

Min

Max

300

Unit

ns

Description

t₁₀

Standard mode

Fast mode

t_FDA, fall time of SDA signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

10

20

80

ns

160

1000

300

t₁₁

t_RCL, rise time of SCL signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

10

20

40

80

ns

t_11A

1000

t_RCL1, rise time of SCL signal after a repeated start

condition and after an Acknowledge bit

Fast mode

20 + 0.1 C_B

300

ns

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Standard mode

Fast mode

10

20

80

ns

160

300

t₁₂

t_FCL, fall time of SCL signal

20 + 0.1 C_B

High speed mode

C_B= 100 pF max

C_B= 400 pF max

Fast mode

10

20

0

40

80

50

10

ns

t_SP

ns

Pulse width of suppressed spike

Power-up time

High speed mode

0

t_POWER-UP

1

typ µs

¹A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

²For 3 V supplies, the maximum hold time with C_B= 100 pF max is 100 ns max.

t

11

12

t

6

2

SCL

SDA

t

6

t

3

t

5

8

4

t

1

t

9

t

10

t

7

S

P

S

P

S = START CONDITION

P = STOP CONDITION

Figure 2. Timing Diagram for 2-Wire Serial Interface

Rev. 0 | Page 8 of 32

AD7997/AD7998

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

−0.3 V to 7 V

Analog Input Voltage to GND

Reference Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

Commercial (B Version)

Storage Temperature Range

Junction Temperature

20-Lead TSSOP

−0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DD+ 0.3 V

10 mA

−40°C to +85°C

−65°C to +150°

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Pb/SN Temperature, Soldering

Reflow (10 s to 30 s)

143°C/W

45°C/W

240 (+0/-5)°C

Pb-free Temperature, Soldering

Reflow

ESD

260 (+0)°C

1.5 kV

¹Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 9 of 32

AD7997/AD7998

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

AGND

1

2

20 AGND

19 SCL

V

DD

AD7997/

AD7998

TOP VIEW

AGND

SDA

3

18

17

16

15

14

13

12

11

ALERT/BUSY

4

V

(Not to Scale)

CONVST

AS

5

DD

REF

IN

6

V

1

3

5

7

V

2

4

6

8

7

IN

8

9

10

Figure 3. AD7998/AD7997 Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 3,

4, 20

AGND

Analog Ground. Ground reference point for all circuitry on the AD7997/AD7998. All analog input signals should be

referred to this AGND voltage.

2, 5

6

V_DD

REF_IN

Power Supply Input. The V_DDrange for the AD7997/AD7998 is from 2.7 V to 5.5 V.

Voltage Reference Input. The external reference for the AD7997/AD7998 should be applied to this input pin. The

voltage range for the external reference is 1.2 V to V_DD. A 0.1 µF and 1 µF capacitors should be placed between REF_IN

and AGND. See Typical Connection Diagram.

7

8

9

10

11

12

13

14

15

V_IN1

V_IN3

V_IN5

V_IN7

V_IN8

V_IN6

V_IN4

V_IN2

AS

Analog Input 1. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 3. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 5. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 7. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 8. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 6. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 4. Single-ended analog input channel. The input range is 0 V to REF_IN.

Analog Input 2. Single-ended analog input channel. The input range is 0 V to REF_IN.

Logic Input. Address select input that selects one of three I²C addresses for the AD7997/AD7998, as shown in Table 6.

The device address depends on the voltage applied to this pin.

16

CONVST

Logic Input Signal. Convert start signal. This is an edge-triggered logic input. The rising edge of this signal powers up

CONVST

the part. The power-up time for the part is 1 µs. The falling edge of

places the track/hold into hold mode and

CONVST

initiates a conversion. A power-up time of at least 1 µs must be allowed for the

conversion result is invalid (see the Modes of Operation section).

high pulse; otherwise, the

17

ALERT/BUSY

Digital Output. Selectable as an ALERT or BUSY output function. When configured as an ALERT, this pin acts as an out-

of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW

register values. See the Limit Registers section. When configured as a BUSY output, this pin becomes active when a

conversion is in progress. Open-drain output.

18

19

SDA

SCL

Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required.

Digital Input. Serial bus clock. Open-drain input. External pull-up resistor required.

Table 6. I²C Address Selection

Part Number

AD7997-0

AD7997-1

AD7997-x¹

AD7998-0

AS Pin

AGND

V_DD

AGND

V_DD

Float

AGND

V_DD

AGND

V_DD

I²C Address

010 0001

010 0010

010 0011

010 0100

010 0000

010 0001

010 0010

010 0011

010 0100

010 0000

AD7998-1

AD7998-x¹

Float

¹If the AS pin is left floating on any of the AD7997/AD7998 parts, the device address is 010 0000.

Rev. 0 | Page 10 of 32

AD7997/AD7998

TERMINOLOGY

Signal-to-Noise and Distortion Ratio (SINAD)

Channel-to-Channel Isolation

The measured ratio of signal-to-noise and distortion at the out-

put of the A/D converter. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

to half the sampling frequency (f_S/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digiti-

zation process; the more levels, the smaller the quantization

noise. The theoretical signal-to-noise and distortion ratio for

an ideal N-bit converter with a sine wave input is given by

A measure of the level of crosstalk between channels, taken

by applying a full-scale sine wave signal to the unselected input

channels, and determining how much the 108 Hz signal is

attenuated in the selected channel. The sine wave signal applied

to the unselected channels is then varied from 1 kHz up to

2 MHz, each time determining how much the 108 Hz signal in

the selected channel is attenuated. This figure represents the

worst-case level across all channels.

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Aperture Delay

The measured interval between the sampling clock’s leading

edge and the point at which the ADC takes the sample.

Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB

for a 12-bit converter.

Aperture Jitter

Total Harmonic Distortion (THD)

This is the sample-to-sample variation in the effective point in

time at which the sample is taken.

The ratio of the rms sum of harmonics to the fundamental. For

the AD7997/AD7998, it is defined as

Full-Power Bandwidth

The input frequency at which the amplitude of the reconstructed

fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

2

V²+V³+V⁴+V⁵+V⁶

THD (dB) = 20 log

V1

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through

sixth harmonics.

Power Supply Rejection Ratio (PSRR)

The ratio of the power in the ADC output at the full-scale

frequency, f, to the power of a 200 mV p-p sine wave applied

to the ADC V_DDsupply of frequency f_S:

Peak Harmonic or Spurious Noise

PSRR (dB) = 10 log (Pf/Pf_S)

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to f_S/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification

is determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is a

noise peak.

where Pf is the power at frequency f in the ADC output; Pf_Sis

the power at frequency f_Scoupled onto the ADC V_DDsupply.

Integral Nonlinearity

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints are

zero scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n equal zero. For example,

second-order terms include (fa + fb) and (fa − fb), while

third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb) and

(fa − 2fb).

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to

(00…001) from the ideal—that is, AGND + 1 LSB.

The AD7997/AD7998 is tested using the CCIF standard where

two input frequencies near the top end of the input bandwidth

are used. In this case, the second-order terms are usually dis-

tanced in frequency from the original sine waves while the

third-order terms are usually at a frequency close to the input

frequencies. As a result, the second and third-order terms are

specified separately. The calculation of intermodulation distor-

tion is, like the THD specification, the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

sum of the fundamentals, expressed in dB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to

(111…111) from the ideal (that is, REF_IN− 1 LSB) after the

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Rev. 0 | Page 11 of 32

AD7997/AD7998

TYPICAL PERFORMANCE CHARACTERISTICS

0

75

70

65

60

55

50

45

40

V

= 5.5V

= 5V

DD

FS = 121kSPS

DD

FSCL = 3.4MHz

FIN = 10kHz

SNR = 71.84dB

–20

SINAD = 71.68dB

THD = 86.18dB

V

= 4.5V

DD

–40

–60

SFDR = –88.70dB

V

= 3V

DD

V

= 3.3V

DD

V

= 2.7V

DD

–80

–100

–120

1

10

FREQUENCY(kHz)

100

1000

0

20

FREQUENCY (kHz)

40

60

Figure 4. AD7998 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

Figure 7. AD7998 SINAD vs. Analog Input Frequency for

Various Supply Voltages, 3.4 MHz f_SCL, 136 kSPS

1.0

0.8

FS = 121kSPS

FSCL = 3.4MHz

FIN = 10kHz

SINAD = 61.63dB

THD = 91.82dB

SFDR = –94.95dB

–10

–30

0.6

0.4

0.2

–50

0

–0.2

–0.4

–0.6

–0.8

–1.0

–70

–90

–110

0

10

20

30

40

50

60

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

INPUT FREQUENCY (kHz)

Figure 5. AD7997 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

Figure 8. Typical INL, V_DD= 5.5 V, Mode 1, 3.4 MHz f_SCL, 121 kSPS

100

90

80

70

60

50

40

30

20

1.0

V

= 5V

DD

0.8

0.6

V

= 3V

DD

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 3V/5V

DD

200mV p-p SINE WAVE

ON V

ꢀ

DD

2nF CAPACITOR ON V

DD

10

100

SUPPLY RIPPLE FREQUENCY(kHz)

1000

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. PSRR vs. Supply Ripple Frequency

Figure 9. Typical DNL, V_DD= 5.5 V, Mode 1, 3.4 MHz f_SCL, 121 kSPS

Rev. 0 | Page 12 of 32

AD7997/AD7998

1.0

0.8

1.0

0.8

0.6

0.4

POSITIVE DNL

NEGATIVE DNL

0.2

0

–0.2

–0.4

-0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

1.2

1.7

2.2

2.7

3.2

3.7

4.2

4.7

REFERENCE VOLTAGE (V)

Figure 13. AD7998 Change in DNL vs. Reference Voltage V_DD= 5 V,

Mode 1, 121 kSPS

Figure 10. Typical INL, V_DD= 2.7 V, Mode 1, 3.4 MHz f_SCL, 121 kSPS

0.0007

1.0

0.8

0.6

0.0006

0.0005

0.0004

0.0003

0.0002

0.0001

0

0.4

–40°C

+25°C

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

2.7

3.2

3.7

4.2

4.7

5.2

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

SUPPLY VOLTAGE (V)

Figure 11. Typical DNL, V_DD= 2.7 V, Mode 1, 3.4 MHz f_SCL, 121 kSPS

Figure 14. AD7998 Shutdown Current vs. Supply Voltage,

–40°C, +25°C, and +85°C

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.0

0.8

0.6

0.4

0.2

POSITIVE INL

NEGATIVE INL

MODE 2

VDD = 5V

0

MODE 2

VDD = 3V

–0.2

–0.4

-0.6

–0.8

–1.0

MODE 1

VDD = 5V

MODE 1

VDD = 3V

1.2

1.7

2.2

2.7

3.2

3.7

4.2

4.7

100

600

1100

1600

2100

2600

3100

REFERENCE VOLTAGE (V)

SCL FREQUENCY (kHz)

Figure 12. AD7998 Change in INL vs. Reference Voltage V_DD= 5 V,

Mode 1, 121 kSPS

Figure 15. AD7998 Average Supply Current vs. I²C Bus Rate for

_DD= 3 V and 5 V

V

Rev. 0 | Page 13 of 32

AD7997/AD7998

2.0

12.0

11.8

11.6

11.4

11.2

11.0

10.8

10.6

10.4

74

73

72

71

70

69

68

TEMPERATURE = +85

°

C

ENOB V = 5V

DD

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

TEMPERATURE = +25

TEMPERATURE = –40

°

ENOB V = 3V

DD

TEMPERATURE = +85

TEMPERATURE = +25

°

SINAD V = 5V

DD

MODE 2 - 147kSPS

MODE 1 - 121kSPS

TEMPERATURE = –40°C

SINAD V = 3V

DD

2.7

3.2

3.7

4.2

4.7

5.2

1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000

REFERENCE VOLTAGE (V)

SUPPLY VOLTAGE (V)

Figure 16. AD7998 Average Supply Current vs. Supply Voltage

for Various Temperatures

Figure 17. SINAD/ENOB vs. Reference Voltage, Mode 1, 121 kSPS

Rev. 0 | Page 14 of 32

AD7997/AD7998

CIRCUIT INFORMATION

The AD7997/AD7998 are low power, 10- and 12-bit, single-

supply, 8-channel A/D converters. The parts can be operated

from a 2.7 V to 5.5 V supply.

At the beginning of a conversion, SW2 opens and SW1 moves

to position B, causing the comparator to become unbalanced, as

shown in Figure 19. The input is disconnected once the con-

version begins. The control logic and the capacitive DAC are

used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 20 shows the ADC transfer characteristic.

The AD7997/AD7998 have an 8-channel multiplexer, an on-

chip track-and-hold, an A/D converter, an on-chip oscillator,

internal data registers, and an I²C-compatible serial interface, all

housed in a 20-lead TSSOP. This package offers considerable

space-saving advantages over alternative solutions. The

AD7997/AD7998 require an external reference in the range of

CAPACITIVE

DAC

1.2 V to V_DD

.

The AD7997/AD7998 typically remain in a power-down state

while not converting. When supplies are first applied, the parts

come up in a power-down state. Power-up is initiated prior to

a conversion, and the device returns to shutdown when the

conversion is complete. Conversions can be initiated on the

A

V

IN

CONTROL

LOGIC

SW1

B

SW2

COMPARATOR

AGND

AD7997/AD7998 by pulsing the

signal, using an

CONVST

Figure 19. ADC Conversion Phase

automatic cycle interval mode, or a command mode where

wake-up and a conversion occur during a write address

function (see the Modes of Operation section). When the

conversion is complete, the AD7997/AD7998 again enter

shutdown mode. This automatic shutdown feature allows power

saving between conversions. This means any read or write

operation across the I²C interface can occur while the device is

in shutdown.

ADC Transfer Function

The output coding of the AD7997/AD7998 is straight binary.

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). The LSB size is REF_IN/1024 for

the AD7997 and REF_IN/4096 for the AD7998. Figure 20 shows

the ideal transfer characteristic for the AD7997/AD7998.

111...111

111...110

CONVERTER OPERATION

The AD7997/AD7998 are successive approximation analog-to-

digital converters based around a capacitive DAC. Figure 18

and Figure 19 show simplified schematics of the ADC during

the acquisition and conversion phase, respectively. Figure 18

shows the acquisition phase. SW2 is closed and SW1 is in

position A, the comparator is held in a balanced condition,

and the sampling capacitor acquires the signal on V_IN.

111...000

011...111

AD7997 1LSB = REF /1024

IN

AD7998 1LSB = REF /4096

IN

000...010

000...001

000...000

AGND + 1LSB

+REF – 1LSB

IN

ANALOG INPUT

0V TO REF

IN

CAPACITIVE

DAC

Figure 20. AD7997/AD7998 Transfer Characteristic

A

V

IN

CONTROL

LOGIC

SW1

B

SW2

COMPARATOR

AGND

Figure 18. ADC Acquisition Phase

Rev. 0 | Page 15 of 32

AD7997/AD7998

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

The typical connection diagram for the AD7997/AD7998 is

shown in Figure 22. In this figure, the address select pin (AS)

is tied to V_DD; however, AS can also be tied to AGND or left

floating, allowing the user to select up to five AD7997/AD7998

devices on the same serial bus. An external reference must be

applied to the AD7997/AD7998. This reference can be in the

range of 1.2 V to V_DD. A precision reference like the REF 19x

family, AD780, ADR03, or ADR381 can be used to supply the

reference voltage to the ADC.

Figure 21 shows an equivalent circuit of the AD7997/AD7998

analog input structure. The two diodes, D1 and D2, provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signal does not exceed the supply

rails by more than 300 mV. This causes the diodes to become

forward biased and start conducting current into the substrate.

These diodes can conduct a maximum current of 10 mA

without causing irreversible damage to the part.

V

DD

SDA and SCL form the 2-wire I²C-/SMBus-compatible

interface. External pull-up resisters are required for both SDA

and SCL lines.

D1

D2

C2

30pF

R1

V

IN

The AD7998-0/AD7997-0 support standard and fast I²C

interface modes. The AD7998-1/AD7997-1 support standard,

fast, and high speed I²C interface modes. Therefore if operating

in either standard or fast mode, up to five AD7997/AD7998

devices can be connected to the bus, as noted:

C1

4pF

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

Figure 21. Equivalent Analog Input Circuit

Capacitor C1 in Figure 21 is typically about 4 pF and can

primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance (R_ON) of

a track-and-hold switch, and also includes the R_ONof the

input multiplexer. The total resistance is typically about 400 Ω.

C2, the ADC sampling capacitor, has a typical capacitance of

30 pF.

3 × AD7997-0/AD7998-0 and 2 × AD7997-1/ AD7998-1

or

3 × AD7997-1/AD7998-1 and 2 × AD7997-0/AD7998-0

In high speed mode, up to three AD7997-1/AD7998-1 devices

can be connected to the bus.

Wake-up from shutdown and acquisition prior to a conversion

is approximately 1 µs, and conversion time is approximately

2 µs. The AD7997/AD7998 enters shutdown mode again after

each conversion, which is useful in applications where power

consumption is a concern.

5V SUPPLY

10µF

0.1µF

2-WIRE SERIAL

INTERFACE

R

P

V

1

DD

IN

SDA

SCL

0V to REF

INPUT

IN

AD7997/

AD7998

µC/µP

8

IN

ALERT

CONVST

AGND

V

REF

AS

REF 19x

0.1µF

DD

IN

1µF

Figure 22. AD7997/AD7998 Typical Connection Diagram

Rev. 0 | Page 16 of 32

AD7997/AD7998

–40

–50

–60

–70

–80

–90

–100

For ac applications, removing high frequency components from

the analog input signal is recommended, by using an RC band-

pass filter on the relevant analog input pin. In applications where

harmonic distortion and signal-to-noise ratio are critical, the

analog input should be driven from a low impedance source.

Large source impedances significantly affect the ac performance

of the ADC. This may necessitate the use of an input buffer

amplifier. The choice of the op amp is a function of the particular

application.

V

= 3V

DD

V

= 3.3V

DD

V

= 2.7V

DD

V

= 4.5V

= 5V

DD

V

= 5.5V

DD

V

DD

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance depends on the amount of total harmonic distortion

(THD) that can be tolerated. THD increases as the source imped-

ance increases, and performance degrades. Figure 23 shows the

THD vs. the analog input signal frequency when using supply

voltages of 3 V 10% and 5 V 10%. Figure 24 shows the THD

vs. the analog input signal frequency for different source

impedances.

10

100

INPUT FREQUENCY(kHz)

1000

Figure 23. THD vs. Analog Input Frequency for Various

Supply Voltages, F_S= 136 kSPS, Mode 1

–40

V

= 5V

DD

–50

–60

R

= 1000Ω

IN

–70

R

= 100Ω

IN

–80

R

= 50Ω

IN

R

= 10Ω

–90

IN

–100

10

100

INPUT FREQUENCY(kHz)

1000

Figure 24. THD vs. Analog Input Frequency for Various

Source Impedances for V_DD= 5 V, 136 kSPS, Mode 1

Rev. 0 | Page 17 of 32

AD7997/AD7998

INTERNAL REGISTER STRUCTURE

The AD7997/AD7998 contain 17 internal registers that are used

to store conversion results, high and low conversion limits, and

information to configure and control the device (see Figure 25).

Sixteen are data registers and one is an address pointer register.

CONVERSION

RESULT REGISTER

ALERT STATUS

REGISTER

CONFIGURATION

REGISTER

Each data register has an address that the address pointer register

points to when communicating with it. The conversion result

register is the only data register that is read only.

CYCLE TIMER

REGISTER

DATA

LOW

ADDRESS POINTER REGISTER

REGISTER CH1

Because it is the register to which the first data byte of every

write operation is written automatically, the address pointer

register does not have and does not require an address. The

address pointer register is an 8-bit register in which the 4 LSBs

are used as pointer bits to store an address that points to one of

the AD7997/AD7998’s data registers. The 4 MSBs are used as

command bits when operating in Mode 2 (see the Modes of

Operation section). The first byte following each write address

is to the address pointer register, containing the address of one

of the data registers. The 4 LSBs select the data register to which

subsequent data bytes are written. Only the 4 LSBs of this register

are used to select a data register. On power-up, the address

pointer register contains all 0s, pointing to the conversion result

register.

DATA

HIGH

REGISTER CH1

D

A

T

HYSTERESIS

REGISTER CH1

DATA

LOW

ADDRESS

POINTER

REGISTER

A

REGISTER CH2

DATA

HIGH

REGISTER CH2

HYSTERESIS

REGISTER CH2

DATA

LOW

REGISTER CH3

DATA

HIGH

REGISTER CH3

HYSTERESIS

REGISTER CH3

Table 7. Address Pointer Register

DATA

LOW

C4

C3

C2

C1

P3

P2

P1

P0

REGISTER CH4

DATA

HIGH

0

Register Select

REGISTER CH4

HYSTERESIS

REGISTER CH4

Table 8. AD7997/AD7998 Register Addresses

P3 P2 P1 P0 Registers

SDA

SCL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Conversion Result Register (Read)

Alert Status Register (Read/Write)

SERIAL BUS INTERFACE

Figure 25. AD7997/AD7998 Register Structure

Configuration Register (Read/Write)

Cycle Timer Register (Read/Write)

DATA_LOWReg CH1 (Read/Write)

DATA_HIGHReg CH1 (Read/Write)

Hysteresis Reg CH1 (Read/Write)

DATA_LOWReg CH2 (Read/Write)

DATA_HIGHReg CH2 (Read/Write)

Hysteresis Reg CH2 (Read/Write)

DATA_LOWReg CH3 (Read/Write)

DATA_HIGHReg CH3 (Read/Write)

Hysteresis Reg CH3 (Read/Write)

DATA_LOWReg CH4 (Read/Write)

DATA_HIGHReg CH4 (Read/Write)

Hysteresis Reg CH4 (Read/Write)

Rev. 0 | Page 18 of 32

AD7997/AD7998

CONFIGURATION REGISTER

The configuration register is a 16-bit read/write register that is used to set the operating mode of the AD7997/AD7998. The 4 MSBs of the

register are unused. The bit functions of all 12 LSBs of the configuration register are outlined in Table 9. A 2-byte write is necessary when

writing to the configuration register.

Table 9. Configuration Register Bits and Default Settings at Power-Up

D15

D14

D13

D12

D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALERT BUSY/

ALERT/BUSY

POLARITY

DONTC DONTC DONTC DONTC CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 FLTR EN

ALERT

0

1

0

Table 10. Bit Function Descriptions

Bit Mnemonic Comment

D11 to D4 CH8 to CH1

These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D11 to D4

selects a channel for conversion. If more than one channel bit is set to 1, the AD7997/AD7998 sequence

through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Prior

to initiating a conversion, a channel or channels for conversion must be selected in the configuration register.

D3

D2

FLTR

The value written to this bit of the control register determines whether the filtering on SDA and SCL is

enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed.

The hardware ALERT function is enabled if this bit is set to 1, and disabled if this bit is set to 0. This bit is used

in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin acts as an ALERT or a BUSY

output (see Table 12).

ALERT EN

D1

D0

BUSY/ALERT

This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/ BUSY output, Pin 17, acts as

an ALERT or BUSY output (see Table 12), and if Pin 17 is configured as an ALERT output pin, if it is to be reset.

This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an

ALERT or BUSY output. It is active low if this bit is set to 0, and active high if set to 1.

BUSY/ALERT

POLARITY

Table 11. Channel Selection

D11

D10

D9

D8

D7

0

1

0

D6

0

1

0

D5

0

1

0

D4

1

0

Selected Analog Input Channel Comments

0

1

0

1

0

1

0

1

0

Convert on Channel 1 (V_IN1)

Convert on Channel 2 (V_IN2)

Convert on Channel 3 (V_IN3)

Convert on Channel 4 (V_IN4)

Convert on Channel 5 (V_IN5)

Convert on Channel 6 (V_IN6)

Convert on Channel 7 (V_IN7)

Convert on Channel 8 (V_IN8)

If more than one channel is

selected, the AD7997/AD7998

start converting on the selected

sequence of channels starting with

the lowest channel in the

sequence.

Table 12. ALERT/BUSY Function

D2

D1

ALERT/BUSY Pin Configuration

0

1

Pin does not provide any interrupt signal.

Pin configured as a BUSY output.

1

0

Pin configured as an ALERT output.

Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register

(if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit,

and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back.

1

Rev. 0 | Page 19 of 32

AD7997/AD7998

DATA_HIGHRegister CH1/CH2/CH3/CH4

CONVERSION RESULT REGISTER

The DATA_HIGHregisters for CH1 to CH 4 are 16-bit read/write

registers; only the 12 LSBs of each register are used. This

register stores the upper limit that activates the ALERT output

and/or the Alert_Flag bit in the conversion result register. If the

value in the conversion result register is greater than the value

in the DATA_HIGHregister, an ALERT occurs for that channel.

When the conversion result returns to a value at least N LSBs

below the DATA_HIGHregister value, the ALERT output pin and

Alert_Flag bit are reset. The value of N is taken from the

hysteresis register associated with that channel. The ALERT pin

can also be reset by writing to Bits D2 and D1 in the

The conversion result register is a 16-bit, read-only register that

stores the conversion result from the ADC in straight binary

format. A 2-byte read is necessary to read data from this register.

Table 13 shows the contents of the first byte to be read from the

AD7997/AD7998, and Table 14 shows the contents of the second

byte to be read.

Table 13. Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10 D9 D8

Alert_Flag CH _ID2CH _ID1CH _ID0M S B B10

B9 B8

Table 14. Conversion Value Register (Second Read)

configuration register. For the AD7997, D1 and D0 of the

DATA_HIGHregister should contain 0s.

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

Table 15. DATA_HIGHRegister (First Read/Write)

D15

D14

D13

D12

D11

D10

D9

D8

The AD7997/AD7998 conversion result consists of an Alert_Flag

bit, three channel identifier bits, and the 10- and 12-bit data

result (MSB first). For the AD7997, the 2 LSBs (D1 and D0) of

the second read contain two 0s. The three channel identification

bits can be used to identify to which of the eight analog input

channels the conversion result corresponds.

0

B11

B10

B9

B8

Table 16. DATA_HIGHRegister (Second Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

DATA_LOWRegister CH1/CH2/CH3/CH4

The Alert_Flag bit indicates whether the conversion result being

read or any other channel result has violated the limit registers

associated with it. If an ALERT occurs, the master can read the

ALERT status register to obtain more information on where the

ALERT occurred.

The DATA_LOWregister for each channel is a 16-bit read/write

register; only the 12 LSBs of each register are used. The register

stores the lower limit that activates the ALERT output and/or

the Alert_Flag bit in the conversion result register. If the value

in the conversion result register is less than the value in the

DATA_LOWregister, an ALERT occurs for that channel. When the

conversion result returns to a value at least N LSBs above the

DATA_LOWregister value, the ALERT output pin and Alert_Flag

bit are reset. The value of N is taken from the hysteresis register

associated with that channel. The ALERT output pin can also be

reset by writing to Bits D2 and D1 in the configuration register.

For the AD7997, D1 to D0 of the DATA_LOWregister should

contain 0s.

LIMIT REGISTERS

The AD7997/AD7998 have four pairs of limit registers. Each

pair stores high and low conversion limits for the first four

analog input channels, CH1 to CH4. Each pair of limit registers

has one associated hysteresis register. All 12 registers are 16 bits

wide; only the 12 LSBs of the registers are used for the AD7997

and AD7998. For the AD7997, the 2 LSBs, D1 and D0 in these

registers, should contain 0s. On power-up, the contents of the

DATA_HIGHregister for each channel is full scale, while the

contents of the DATA_LOWregisters is zero scale by default. The

AD7997/AD7998 signal an alert (in either hardware, software,

or both depending on configuration) if the conversion result

moves outside the upper or lower limit set by the limit registers.

There are no limit registers or hysteresis registers associated

with CH5 to CH8.

Table 17. DATA_LOWRegister (First Read/Write)

D15

D14

D13

D12

D11

D10

D9

D8

0

B11

B10

B9

B8

Table 18. DATA_LOWRegister (Second Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

Rev. 0 | Page 20 of 32

AD7997/AD7998

Hysteresis Register (CH1/CH2/CH3/CH4)

ALERT STATUS REGISTER (CH1 TO CH4)

Each hysteresis register is a 16-bit read/write register, of which

only the 12 LSBs are used. The hysteresis register stores the

hysteresis value, N, when using the limit registers. Each pair of

limit registers has a dedicated hysteresis register. The hysteresis

value determines the reset point for the ALERT pin/Alert_Flag

if a violation of the limits has occurred. For example, if a

hysteresis value of 8 LSBs is required on the upper and lower

limits of Channel 1, the 12-bit word, 0000 0000 0000 1000,

should be written to the hysteresis register of CH1, the address

of which is shown in Table 8. On power-up, the hysteresis

registers contain a value of 2 for the AD7997 and a value of 8

for the AD7998. If a different hysteresis value is required, that

value must be written to the hysteresis register for the channel

in question. For the AD7997, D1 and D0 of the hysteresis

register should contain 0s.

The alert status register is an 8-bit, read/write register that

provides information on an alert event. If a conversion result

activates the ALERT pin or the Alert_Flag bit in the conversion

result register, as described in the Limit Registers section, the

alert status register may be read to gain further information.

The Alert Status Register contains two status bits per channel,

one corresponding to the DATA_HIGHlimit and the other to the

DATA_LOWlimit. The bit with a status of 1 shows where the

violation occurred—that is, on which channel—and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on the other channel between receiving the

first alert and interrogating the alert status register, the

corresponding bit for that alert event is also set.

The alert status register only contains information for CH1 to

CH4 because these are the only channels with associated limit

registers.

Table 19. Hysteresis Register (First Read/Write)

D15

D14

D13

D12

D11

D10

D9

D8

0

B11

B10

B9

B8

The entire contents of the alert status register can be cleared by

writing 1,1, to Bits D2 and D1 in the configuration register, as

shown in Table 12. This may also be done by writing all 1s to

the alert status register itself. Thus, if the alert status register is

addressed for a write operation, which is all 1s, the contents of

the alert status register are cleared or reset to all 0s.

Table 20. Hysteresis Register (Second Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

Using the Limit Registers to Store Min/Max Conversion

Results for CH1 to CH4

Table 21. Alert Status Register

D7

D6

D5

D4

D3

D2

D1

D0

If full scale, that is, all 1s, is written to the hysteresis register for

a particular channel, the DATA_HIGHand DATA_LOWregisters for

that channel no longer act as limit registers as previously

described, but instead act as storage registers for the maximum

and minimum conversion results returned from conversions on

a channel over any given period of time. This function is useful

in applications where the widest span of actual conversion

results is required rather than using the ALERT to signal that an

intervention is necessary. This function could be useful for

monitoring temperature extremes during refrigerated goods

transportation. It must be noted that on power-up, the contents

of the DATA_HIGHregister for each channel are full scale, while the

contents of the DATA_LOWregisters are zero scale by default.

Therefore, minimum and maximum conversion values being

stored in this way are lost if power is removed or cycled.

CH4_HICH4_LOCH3_HICH3_LOCH2_HICH2_LOCH1_HICH1_LO

Table 22. Alert Status Register Bit Function Description

Bit

Mnemonic

If bit is set to 1, violation of…

D0

CH1_LO

DATA_LOWlimit on Channel 1.

No violation if bit is set to 0.

D1

D2

D3

D4

D5

D6

D7

CH1_HI

CH2_LO

CH2_HI

CH3_LO

CH3_HI

CH4_LO

CH4_HI

DATA_HIGHlimit on Channel 1.

No violation if bit is set to 0.

DATA_LOWlimit on Channel 2.

No violation if bit is set to 0.

DATA_HIGHlimit on Channel 2.

No violation if bit is set to 0.

DATA_LOWlimit on Channel 3.

No violation if bit is set to 0.

DATA_HIGHlimit on Channel 3.

No violation if bit is set to 0.

DATA_LOWlimit on Channel 4.

No violation if bit is set to 0.

DATA_HIGHlimit on Channel 4.

No violation if bit is set to 0.

Rev. 0 | Page 21 of 32

AD7997/AD7998

SAMPLE DELAY AND BIT TRIAL DELAY

CYCLE TIMER REGISTER

It is recommended that no I²C bus activity occurs when a

conversion is taking place. However, if this is not possible, for

example when operating in Mode 2 or Mode 3, then in order to

maintain the performance of the ADC, Bits D7 and D6 in the

cycle timer register are used to delay critical sample intervals

and bit trials from occurring while there is activity on the I²C

bus. This results in a quiet period for each bit decision. In

certain cases where there is excessive activity on the interface

lines, this may have the effect of increasing the overall

conversion time. However, if bit trial delays extend longer than

1 µs, the conversion terminates.

The cycle timer register is an 8-bit, read/write register that

stores the conversion interval value for the automatic cycle

interval mode of the AD7997/AD7998 (see the Modes of

Operation section). D5 to D3 of the cycle timer register are

unused and should contain 0s at all times. On power-up, the

cycle timer register contains all 0s, thus disabling automatic

cycle operation of the AD7997/AD7998. To enable automatic

cycle mode, the user must write to the cycle timer register,

selecting the required conversion interval by programming Bits

D2 to D0. Table 23 shows the structure of the cycle timer

register, while Table 24 shows how the bits in this register are

decoded to provide various automatic sampling intervals.

When Bits D7 and D6 are both 0, the bit trial and sample

interval delaying mechanism is implemented. The default

setting of D7 and D6 is 0. To turn off both delay mechanisms,

set D7 and D6 to 1.

Table 23. Cycle Timer Register and Defaults at Power-Up

D7

D6

D5 D4 D3 D2

D1

D0

Sample

Delay

Bit Trial

Delay

Cyc

Bit2

Cyc

Bit1

Cyc

Bit0

0

Table 25. Cycle Timer Register and Defaults at Power-up

0

D7

D6

D5 D4 D3 D2

D1

D0

Sample

Delay

Bit Trial

Delay

Cyc

Bit 2

Cyc

Bit 1

Cyc

Bit 0

0

Table 24. Cycle Timer Intervals

Typical Conversion Interval

(T_CONVERT= Conversion Time)

0

D2

0

D1

0

D0

0

Mode Not Selected

T_CONVERT× 32

0

1

0

1

0

T_CONVERT× 64

0

1

0

1

0

1

0

T_CONVERT× 128

T_CONVERT× 256

T_CONVERT× 512

T_CONVERT× 1024

T_CONVERT× 2048

1

Rev. 0 | Page 22 of 32

AD7997/AD7998

SERIAL INTERFACE

Control of the AD7997/AD7998 is carried out via the I²C-

compatible serial bus. The devices are connected to this bus as

slave devices under the control of a master device, such as the

processor.

Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit from

the receiver of data. Transitions on the data line must occur

during the low period of the clock signal and remain stable

during the high period because a low-to-high transition when

the clock is high may be interpreted as a stop signal.

SERIAL BUS ADDRESS

Like all I²C-compatible devices, the AD7997/AD7998 have a

7-bit serial address. The 3 MSBs of this address for the AD7997/

AD7998 are set to 010. The AD7997/AD7998 come in two

versions, the AD7997-0/AD7997-0 and AD7997-1AD7998-1.

The two versions have three different I²C addresses available,

which are selected by either tying the address select pin, AS, to

AGND or V_DD, or by letting the pin float (see Table 6). By giving

different addresses for the two versions, up to five AD7997/

AD7998 devices can be connected to a single serial bus, or the

addresses can be set to avoid conflicts with other devices on the

bus. (See Table 6.)

When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line

high during the 10th clock pulse to assert a stop condition. In

read mode, the master device pulls the data line high during the

low period before the ninth clock pulse. This is known as No

Acknowledge. The master then takes the data line low during

the low period before the 10th clock pulse, then high during the

10th clock pulse to assert a stop condition.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation, because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

The serial bus protocol operates as follows.

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line, SCL, remains high.

This indicates that an address/data stream follows. All slave

peripherals connected to the serial bus responds to the start

condition and shift in the next eight bits, consisting of a

7-bit address (MSB first) plus an R/ bit that determines the

W

direction of the data transfer, that is, whether data is written to

or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowledge

bit. All other devices on the bus remain idle while the selected

device waits for data to be read from or written to it. If the R/

W

bit is a 0, the master writes to the slave device. If the R/ bit is a

W

1, the master reads from the slave device.

Rev. 0 | Page 23 of 32

AD7997/AD7998

WRITING TO THE AD7997/AD7998

Depending on the register being written to, there are three

different writes for the AD7997/AD7998.

WRITING TWO BYTES OF DATA TO A LIMIT,

HYSTERESIS, OR CONFIGURATION REGISTER

Each of the four limit registers are 16-bit registers, so two bytes

of data are required to write a value to any one of them. Writing

two bytes of data to one of these registers consists of the serial

bus write address, the chosen limit register address written to

the address pointer register, followed by two data bytes written

to the selected data register. See Figure 28.

WRITING TO THE ADDRESS POINTER REGISTER

FOR A SUBSEQUENT READ

In order to read from a particular register, the address pointer

register must first contain the address of that register. If it does

not, the correct address must be written to the address pointer

register by performing a single-byte write operation, as shown

in Figure 26. The write operation consists of the serial bus

address followed by the address pointer byte. No data is written

to any of the data registers. A read operation may be subsequently

performed to read the register of interest.

If the master is write addressing the AD7997/AD7998, it can

write to more than one register without readdressing the ADC.

After the first write operation has completed for the first data

register, during the next byte the master simply writes to the

address pointer byte to select the next data register for a write

operation. This eliminates the need to readdress the device in

order to write to another data register.

WRITING A SINGLE BYTE OF DATA TO THE ALERT

STATUS REGISTER OR CYCLE REGISTER

The alert status register and cycle register are both 8-bit registers,

so only one byte of data can be written to each. Writing a single

byte of data to one of these registers consists of the serial bus

write address, the chosen data register address written to the

address pointer register, followed by the data byte written to the

selected data register. See Figure 27.

1

9

1

9

SCL

P3

0

1

0

A3

A2

A1

A0

C4

C3

C2

P2

P1

P0

R/W

C1

SDA

START BY

MASTER

ACK. BY

AD7997/AD7998

ACK. BY

AD7997/AD7998 MASTER

STOP BY

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

Figure 26. Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

1

9

1

9

SCL

P3

0

1

0

A3

A2

A1

A0

C4

C3

C2

P2

P1

P0

R/W

C1

SDA

START BY

MASTER

ACK. BY

AD7997/AD7998

ACK. BY

AD7997/AD7998

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 1

SERIAL BUS ADDRESS BYTE

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D3

D7

D6

D5

D2

D1

D0

D4

ACK. BY

STOP BY

AD7997/AD7998 MASTER

FRAME 3

DATA BYTE

Figure 27. Single-Byte Write Sequence

Rev. 0 | Page 24 of 32

AD7997/AD7998

1

0

9

1

9

SCL

SDA

P3

1

0

A3

A2

A1

A0

C4

C3

C2

C1

P2

P1

P0

R/W

START BY

MASTER

ACK. BY

AD7997/AD7998

ACK. BY

AD7997/AD7998

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER

9

1

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

0

D11

D3

0

D10

D9

D8

D7

D6

D5

D2 D1/0 D0/0

0

D4

ACK. BY

AD7997/AD7998

LEAST SIGNIFICANT DATA BYTE

ACK. BY

AD7997/AD7998

STOP BY

MASTER

MOST SIGNIFICANT DATA BYTE

Figure 28. 2-Byte Write Sequence

Rev. 0 | Page 25 of 32

AD7997/AD7998

READING DATA FROM THE AD7997/AD7998

Reading data from the AD7997/AD7998 is a 1- or 2-byte

operation. Reading back the contents of the alert status register

or the cycle timer register is a single-byte read operation, as

shown in Figure 29. This assumes the particular register address

has previously been set up by a single-byte write operation to

the address pointer register, as shown in Figure 26. Once the

register address has been set up, any number of reads can be

performed from that particular register without having to write

to the address pointer register again.

Reading data from the configuration register, conversion result

register, DATA_HIGHregisters, DATA_LOWregisters, or hysteresis

registers is a 2-byte operation, as shown in Figure 30. The same

rules apply for a 2-byte read as a single-byte read.

When reading data back from a register, for example the

conversion result register, if more than two read bytes are

supplied, the same or new data is read from the AD7997/

AD7998 without the need to readdress the device. This allows

the master to continuously read from a data register without

having to readdress the AD7997/AD7998.

If a read from a different register is required, the relevant

register address has to be written to the address pointer register,

and again any number of reads from this register may then be

performed.

1

9

1

9

SCL

SDA

0

D3

1

0

A3

A2

A1

A0

D7

D6

D5

D2

D1

D0

R/W

D4

START BY

MASTER

ACK. BY

AD7997/AD7998

NO ACK. BY STOP BY

MASTER MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

SINGLE DATA BYTE FROM AD7997/AD7998

Figure 29. Reading a Single Byte of Data from a Selected Register

1

9

1

9

SCL

0

1

0

A3

A2

A1

A0

D11

D10

D9

D8

R/W

SDA

ACK. BY

AD7997/AD7998

ACK. BY

MASTER

START BY

MASTER

ALERT

FLAG

CHID2 CH

ID1

CH

ID0

FRAME 2

FRAME 1

SERIAL BUS ADDRESS BYTE

MOST SIGNIFICANT DATA BYTE FROM

AD7997/AD7998

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D1/0 D0/0

D3

D7

D6

D5

D2

D4

NO ACK. BY STOP BY

MASTER MASTER

FRAME 2

MOST SIGNIFICANT DATA BYTE FROM

AD7997/AD7998

Figure 30. Reading Two Bytes of Data from the Conversion Result Register

Rev. 0 | Page 26 of 32

AD7997/AD7998

ALERT/BUSY PIN

The ALERT/BUSY pin may be configured as an alert output or

as a busy output, as shown in Table 12.

BUSY

When the ALERT/BUSY pin is configured as a BUSY output the

pin is used to indicate when a conversion is taking place. The

polarity of the BUSY pin is programmed through bit D0 in the

Configuration register.

SMBus ALERT

The AD7997/AD7998 ALERT output is an SMBus interrupt line

for devices that want to trade their ability to master for an extra

pin. The AD7997/AD7998 is a slave-only device that uses the

SMBus ALERT to signal the host device that it wants to talk.

The SMBus ALERT on the AD7997/AD7998 is used as an out-

of-range indicator (a limit violation indicator).

PLACING THE AD7997-1/AD7998-1 INTO

HIGH SPEED MODE

High speed mode communication commences after the master

addresses all devices connected to the bus with the master code,

00001XXX, to indicate that a high speed mode transfer is to

begin. No device connected to the bus is allowed to acknowledge

the high speed master code; therefore, the code is followed by a

not-acknowledge (see Figure 31). The master must then issue a

The ALERT pin has an open-drain configuration that allows

the ALERT outputs of several AD7997/AD7998s to be wired-

AND’ed together when the ALERT pin is active low. D0 of the

configuration register is used to set the active polarity of the

ALERT output. The power-up default is active low. The ALERT

function can be enabled or disabled by setting D2 of the con-

figuration register to 1 or 0, respectively.

repeated start followed by the device address with an R/ bit.

W

The selected device then acknowledges its address.

All devices continue to operate in high speed mode until such a

time as the master issues a stop condition. When the stop condi-

tion is issued, the devices all return to fast mode.

The host device can process the alert interrupt and simultane-

ously access all SMBus alert devices through the alert response

address. Only the device that pulled the alert low acknowledges

the alert response address (ARA). If more than one device pulls

the ALERT pin low, the highest priority (lowest address) device

wins communication rights via standard I²C arbitration during

the slave address transfer.

THE ADDRESS SELECT (AS) PIN

The address select pin on the AD7997/AD7998 is used to set

the I²C address for the AD7997/AD7998 device. The AS pin can

be tied to V_DD, to AGND, or left floating. The selection should

be made as close as possible to the AS pin; avoid having long

tracks introducing extra capacitance on to the pin. This is

important for the float selection, as the AS pin has to charge to a

midpoint after the start bit during the first address byte. Extra

capacitance on the AS pin increases the time taken to charge to

the midpoint and may cause an incorrect decision on the device

address. When the AS pin is left floating, the AD7997/AD7998

can work with a capacitive load up to 40 pF.

The ALERT output becomes active when the value in the

conversion result register exceeds the value in the DATA_HIGH

register or falls below the value in the DATA_LOWregister for a

selected channel. It is reset when a write operation to the

configuration register sets D1 to a 1, or when the conversion

result returns N LSB below or above the value stored in the

DATA_HIGHregister or the DATA_LOWregister, respectively. N is the

value in the hysteresis register (see the Limit Registers section).

The ALERT output requires an external pull-up resistor that can

be connected to a voltage different from V_DDprovided the maxi-

mum voltage rating of the ALERT output pin is not exceeded.

The value of the pull-up resistor depends on the application, but

should be as large as possible to avoid excessive sink currents at

the ALERT output.

HIGH SPEED MODE

9

FAST MODE

1

9

1

SCL

A3

0

1

X

0

1

A2

A1

A0

0

SDA

NACK Sr

ACK. BY

AD7997/AD7998

START BY

MASTER

HS MODE MASTER CODE

SERIAL BUS ADDRESS BYTE

Figure 31. Placing the Part into High Speed Mode

Rev. 0 | Page 27 of 32

AD7997/AD7998

MODES OF OPERATION

When supplies are first applied to the AD7997/AD7998, the

ADC powers up in sleep mode and normally remains in this

shutdown state while not converting. There are three methods

of initiating a conversion on the AD7997/AD7998.

If the

the falling edge of

result is invalid because the AD7997/AD7998 are not fully

powered-up when the conversion takes place. To maintain the

performance of the AD7997/AD7998 in this mode it is

recommended that the I²C bus is quiet when a conversion is

taking place.

pulse does not remain high for more than 1 µs,

CONVST

still initiates a conversion but the

CONVST

MODE 1—USING THE CONVST PIN

A conversion can be initiated on the AD7997/AD7998 by

pulsing the

signal. The conversion clock for the part

CONVST

The cycle timer register and Bits C4 to C1 in the address pointer

register should contain all 0s when operating the AD7997/

AD7998 in this mode. The

is internally generated so no external clock is required, except

when reading from or writing to the serial port. On the rising

pin should be tied low for

CONVST

edge of

, the AD7997/AD7998 begins to power up (see

CONVST

point A in Figure 32). The power-up time from shutdown mode

for the AD7997/AD7998 is approximately 1 µs; the

all other modes of operation.

CONVST

signal must remain high for 1 µs for the part to power up fully.

can be brought low after this time. This power-up

To select an analog input channel for conversion in this mode,

the user must write to the configuration register and select the

corresponding channel for conversion. To set up a sequence of

channels to be converted with each

corresponding channel bits in the configuration register (see

Table 11).

CONVST

time also includes the acquisition time of the ADC. The falling

edge of the signal places the track-and-hold into hold

pulse, set the

CONVST

mode; a conversion is also initiated at this point (point B in

Figure 32). When the conversion is complete, approximately

2 µs later, the part returns to shutdown (point C in Figure 32)

Once a conversion is complete, the master can address the

AD7997/AD7998 to read the conversion result. If further

conversions are required, the SCL line can be taken high while

and remains there until the next rising edge of

. The

CONVST

master can then read the ADC to obtain the conversion result.

The address pointer register must be pointing to the conversion

result register in order to read back the conversion result.

the

signal is pulsed again; then an additional 18 SCL

CONVST

pulses are required to read the conversion result.

When operating the AD7997-1/AD7998-1 in Mode 1 and

reading after conversion with a 3.4 MHz f_SCL, the ADCs can

achieve a typical throughput rate of up to 121 kSPS.

A

B

C

t_POWER-UP

CONVST

t_CONVERT

9

1

9

1

9

SCA

SDA

S

7-BIT ADDRESS

R

A

P

A

FIRST DATA BYTE (MSBs)

SECOND DATA BYTE (LSBs)

Figure 32. Mode 1 Operation

Rev. 0 | Page 28 of 32

AD7997/AD7998

MODE 2 – COMMAND MODE

This mode allows a conversion to be automatically initiated any

time a write operation occurs. In order to use this mode, the

Command Bits C4 to C1 in the address pointer byte shown in

Table 7 must be programmed.

Table 26 shows the channel selection in this mode via

Command Bits C4 to C1 in the address pointer register. The

wake-up, acquisition, and conversion times combined should

take approximately 3 µs. Following the write operation, the

AD7997/AD7998 must be addressed again to indicate that a

read operation is required. The read then takes place from the

conversion result register. This read accesses the conversion

result from the channel selected via the command bits. If

Command Bits C4 to C1 were set to 0111, and Bits D4 and D5

were set in the configuration register, a 4-byte read would be

necessary. The first read accesses the data from the conversion

on V_IN1. While this read takes place, a conversion occurs on

V_IN2. The second read accesses this data from V_IN2. Figure 34

illustrates how this mode operates; the user would first have

written to the configuration register to select the sequence of

channels to be converted before write addressing the part with

the command bits set to 0111.

To select a single analog input for conversion in this mode, the

user must set Bits C4 to C1 of the address pointer byte to

indicate which channel to convert on (see Table 26). When all

four command bits are 0, this mode is not in use.

To select a sequence of channels for conversion in this mode,

first select the channels to be included in the sequence by

setting the channel bits in the configuration register. Next, set

the command bits in the address pointer byte to 0111. With the

command bits of the address pointer byte set to 0111, the ADC

knows to look in the configuration register for the sequence of

channels to be converted. The ADC starts converting on the

lowest channel in the sequence and then the next lowest until all

the channels in the sequence are converted. The ADC stops

converting the sequence when it receives a STOP bit.

When operating the AD7997-1/AD7998-1 in Mode 2 with a

high speed mode, 3.4 MHz SCL, the conversion may not be

complete before the master tries to read the conversion result.

If this is the case, the AD7997-1/AD7998-1 holds the SCL line

low during the ACK clock after the read address, until the con-

version is complete. When the conversion is complete, the

AD7997-1/AD7998-1 releases the SCL line and the master can

then read the conversion result.

Figure 29 illustrates a 2-byte read operation from the

conversion result register. This operation is preceded typically

by a write to the address pointer register so that the following

read accesses the desired register, in this case the conversion

result register (see Figure 26). If Command Bits C4 to C1 are set

when the contents of the address pointer register are being

loaded, the AD7997/AD7998 begins to power up and convert

upon the selected channel(s). Power-up begins on the fifth SCL

falling edge of the address point byte, (see point A in Figure 33).

After the conversion is initiated by setting the command bits

in the address pointer byte, if the AD7997/AD7998 receives a

STOP or NACK from the master, the AD7997/AD7998 stops

converting.

Table 26. Address Pointer Byte

C4

C3

C2

C1

P3

P2

P1

0

P0

0

Mode 2, Convert On

Comments

0

1

0

Not selected

V_IN1

1

0

1

0

V_IN2

1

0

1

0

V_IN3

1

0

1

0

1

0

1

0

V_IN4

V_IN5

V_IN6

With the pointer Bits P3–P0 set to all 0s,

the next read accesses the results of the

conversion result register.

1

0

V_IN7

1

0

V_IN8

0

1

0

Sequence of channels selected in the

configuration register, Bits D11 to D4.

Rev. 0 | Page 29 of 32

AD7997/AD7998

1

8

9

1

A

9

SCL

SDA

COMMAND/ADDRESS

POINT BYTE

7-BIT ADDRESS

W

A

S

ACK BY

AD7997/AD7998

ACK BY

AD7997/AD7998

1

9

1

9

SCL

SDA

FIRST DATA BYTE

(MSBs)

SECOND DATA BYTE

(LSBs)

Sr

7-BIT ADDRESS

R

A

Sr/P

ACK BY

AD7997/AD7998

ACK BY

MASTER

NACK BY

MASTER

Figure 33. Mode 2 Operation

1

8

9

1

9

SCL

SDA

COMMAND/ADDRESS

POINT BYTE

7-BIT ADDRESS

A

S

W

A

ACK BY

AD7997/AD7998

9

AD7997/AD7998

9

1

9

SCL

SDA

SECOND DATA BYTE

FIRST DATA BYTE

(MSBs)

SECOND DATA BYTE

(LSBs)

FIRST DATA BYTE

(MSBs)

A

Sr

7-BIT ADDRESS

R

A

A/A

(LSBs)

ACK BY

AD7997/AD7998

ACK BY

MASTER

ACK BY

MASTER

ACK BY

MASTER

RESULT FROM CH1

RESULT FROM CH2

Figure 34. Mode 2 Sequence Operation

MODE 3—AUTOMATIC CYCLE INTERVAL MODE

An automatic conversion cycle can be selected and enabled by

writing a value to the cycle timer register. A conversion cycle

interval can be set up on the AD7997/AD7998 by programming

the relevant bits in the 8-bit cycle timer register, as decoded in

Table 24. Only the 3 LSBs are used to select the cycle interval;

the 5 MSBs should contain 0s. When the 3 LSBs of the register

are programmed with any configuration other than all 0s, a

conversion takes place every X ms; the cycle interval, X,

depends on the configuration of these three bits in the cycle

timer register. There are seven different cycle time intervals to

choose from, as shown in Table 24. Once the conversion has

taken place, the part powers down again until the next conver-

sion occurs. To exit this mode of operation, the user must

program the 3 LSBs of the cycle timer register to contain all 0s.

To select a channel(s) for operation in the cycle mode, set the

corresponding channel bit(s), D11 to D4, of the configuration

register. If more than one channel bit is set in the configuration

register, the ADC automatically cycles through the channel

sequence starting with the lowest channel and working its way

up through the sequence. Once the sequence is complete, the

ADC starts converting on the lowest channel again, continuing

to loop through the sequence until the cycle timer register

contents are set to all 0s. This mode is useful for monitoring

signals, such as battery voltage and temperature, alerting only

when the limits are violated.

Rev. 0 | Page 30 of 32

AD7997/AD7998

OUTLINE DIMENSIONS

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

COPLANARITY

0.10

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-153AC

Figure 35. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Linearity Error²(Max)

0.5 LSB

1 LSB

Package Option

Package Description

AD7997BRU-0

–40°C to +85°C

RU-20

TSSOP

AD7997BRU-0REEL

AD7997BRUZ-0³

AD7997BRUZ-0REEL³

AD7997BRU-1

AD7997BRU-1REEL

AD7997BRUZ-1³

AD7997BRUZ-1REEL³

AD7998BRU-0

AD7998BRU-0REEL

AD7998BRUZ-0³

AD7998BRUZ-0REEL³

AD7998BRU-1

AD7998BRU-1REEL

AD7998BRUZ-1³

AD7998BRUZ-1REEL³

EVAL-AD7997CB

EVAL-AD7998CB

Standalone Evaluation Board

¹The AD7997-0/AD7998-0 support standard and fast I²C interface modes. The AD7997-1/AD7998-1 support standard, fast, and high speed I²C interface modes.

²Linearity error here refers to integral nonlinearity.

³Z = Pb-free part.

RELATED PARTS IN I²C-COMPATIBLE ADC PRODUCT FAMILY

Part Number

Resolution

Number of Input Channels

Package

16 TSSOP

10 MSOP

AD7994

AD7993

AD7992

12

10

12

4

2

Rev. 0 | Page 31 of 32

AD7997/AD7998

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

©

registered trademarks are the property of their respective owners.

D03473–0–9/04(0)

Rev. 0 | Page 32 of 32


型号：	AD7997BRU-0REEL
厂家：	ADI
描述：	8-Channel, 10- and 12-Bit ADCs with I2CCompatible 8通道， 10位和12位ADC， I2CCompatible
文件：	总32页 (文件大小：1434K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7997BRU-0REEL [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E