AD8000YCPZ-R2 [ADI]
1.5 GHz Ultrahigh Speed Op Amp; 1.5 GHz的超高速运算放大器
| 型号： | AD8000YCPZ-R2 |
| 厂家： | 
ADI |
| 描述： | 1.5 GHz Ultrahigh Speed Op Amp |
| 文件： | 总20页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.5 GHz Ultrahigh Speed Op Amp
AD8000
CONNECTION DIAGRAMS
AD8000
FEATURES
High speed
1.5 GHz, −3 dB bandwidth (G = +1)
650 MHz, full power bandwidth (G = +2, VO = 2 V p-p)
Slew rate: 4100 V/µs
0.1% settling time: 12 ns
Excellent video specifications
0.1 dB flatness: 170 MHz
POWER DOWN
FEEDBACK
–IN
1
2
3
4
8
+V
S
7
OUTPUT
6 NC
5 –V
+IN
S
Differential gain: 0.02%
NC = NO CONNECT
Differential phase: 0.01°
Figure 1. 8-Lead AD8000, 3 mm × 3 mm LFCSP (CP-8-2)
Output overdrive recovery: 22 ns
Low noise: 1.6 nV/√Hz input voltage noise
Low distortion over wide bandwidth
75 dBc SFDR @ 20 MHz
AD8000
FEEDBACK
–IN
1
2
3
4
8
7
6
5
POWER DOWN
+V
S
62 dBc SFDR @ 50 MHz
+IN
OUTPUT
NC
Input offset voltage: 1 mV typ
High output current: 100 mA
Wide supply voltage range: 4.5 V to 12 V
Supply current: 13.5 mA
–V
S
NC = NO CONNECT
Power-down mode
Figure 2. 8-Lead AD8000 SOIC/EP (RD-8-1)
APPLICATIONS
Professional video
High speed instrumentation
Video switching
3
2
V
R
V
= ±5V
= 150Ω
S
L
= 2V p-p
OUT
1
IF/RF gain stage
0
CCD imaging
–1
–2
–3
–4
–5
–6
–7
GENERAL DESCRIPTION
The AD8000 is an ultrahigh speed, high performance, current
feedback amplifier. Using ADI’s proprietary eXtra Fast Com-
plementary Bipolar (XFCB) process, the amplifier can achieve a
small signal bandwidth of 1.5 GHz and a slew rate of 4100 V/µs.
G = +2, R = 432Ω
F
The AD8000 has low spurious-free dynamic range (SFDR) of
75 dBc @ 20 MHz and input voltage noise of 1.6 nV/√Hz. The
AD8000 can drive over 100 mA of load current with minimal
distortion. The amplifier can operate on +5 V to 6 V. These
specifications make the AD8000 ideal for a variety of applica-
tions, including high speed instrumentation.
1
10
100
1000
FREQUENCY (MHz)
Figure 3. Large Signal Frequency Response
The AD8000 power-down mode reduces the supply current to
1.3 mA. The amplifier is available in a tiny 8-lead LFCSP pack-
age, as well as in an 8-lead SOIC package. The AD8000 is rated
to work over the extended industrial temperature range (−40°C
to +125°C). A triple version of the AD8000 (AD8003) is under-
development.
With a differential gain of 0.02%, differential phase of 0.01°, and
0.1 dB flatness out to 170 MHz, the AD8000 has excellent video
specifications, which ensure that even the most demanding
video systems maintain excellent fidelity.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8000
TABLE OF CONTENTS
Specifications with 5 V Supply ..................................................... 3
Video Line Driver....................................................................... 14
Low Distortion Pinout............................................................... 15
Exposed Paddle........................................................................... 15
Printed Circuit Board Layout ................................................... 15
Signal Routing............................................................................. 15
Power Supply Bypassing............................................................ 15
Grounding................................................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Specifications with +5 V Supply ..................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ..................................................................................... 13
Applications..................................................................................... 14
Circuit Configurations............................................................... 14
REVISION HISTORY
1/05—Rev. 0: Initial Version
Rev. 0 | Page 2 of 20
AD8000
SPECIFICATIONS WITH 5 ꢀ SUPPLY
At TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p, SOIC/LFCSP
G = +2, VO = 2 V p-p, SOIC/LFCSP
VO = 2 V p-p, SOIC/LFCSP
G = +2, VO = 4 V step
1580/1350
650/610
190/170
4100
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic
Second/Third Harmonic
Input Voltage Noise
G = +2, VO = 2 V step
12
VO = 2 V p-p, f = 5 MHz, LFCSP only
VO = 2 V p-p, f = 20 MHz, LFCSP only
f = 100 kHz
f = 100 kHz, −IN
f = 100 kHz, +IN
86/89
75/79
1.6
26
3.4
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
NTSC, G = +2
NTSC, G = +2
0.02
0.01
Degree
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current (Enabled)
1
10
mV
µV/°C
µA
µA
kΩ
11
−5
−3
890
+IB
−IB
+4
+45
1600
Transimpedance
570
−52
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Overdrive Recovery
2/3.6
−3.5 to +3.5
−54
MΩ/pF
V
dB
ns
VCM
=
2.5 V
−56
G = +1, f = 1 MHz, triangle wave
30
POWER DOWN PIN
Power-Down Input Voltage
Power-down
Enabled
50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
< +VS – 3.1
> +VS – 1.9
150
V
V
ns
Turn-Off Time
Turn-On Time
300
ns
Input Bias Current
Enabled
Power-Down
−1.1
−300
+0.17
−235
+1.4
−160
µA
µA
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing
Linear Output Current
Overdrive Recovery
RL = 100 Ω
RL = 1 kΩ
VO = 2 V p-p, second HD < −50 dBc
G = + 2, f = 1 MHz, triangle wave
G = +2, VIN = 2.5 V to 0 V step
3.7
3.9
3.9
4.1
100
45
V
V
mA
ns
ns
22
POWER SUPPLY
Operating Range
4.5
12
V
Quiescent Current
Quiescent Current (Power-Down)
Power Supply Rejection Ratio
12.7
1.1
−56/−61
13.5
1.3
−59/−63
14.3
1.65
mA
mA
dB
−PSRR/+PSRR
Rev. 0 | Page 3 of 20
AD8000
SPECIFICATIONS WITH +5 ꢀ SUPPLY
At TA = 25°C, VS = +5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +10, VO = 0.2 V p-p
VO = 0.2 V p-p
VO = 2 V p-p
G = +2, VO = 2 V step
G = +2, VO = 2 V step
980
477
328
136
136
2700
16
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic
Second/Third Harmonic
Input Voltage Noise
VO = 2 V p-p, 5 MHz, LFCSP only
VO = 2 V p-p, 20 MHz, LFCSP only
f = 100 kHz
f = 100 kHz, −IN
f = 100 kHz, +IN
71/71
60/62
1.6
26
3.4
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
NTSC, G = +2
NTSC, G = +2
0.01
0.06
Degree
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current (Enabled)
1.3
18
−5
−1
800
10
mV
µV/°C
µA
µA
kΩ
+IB
−IB
+3
+45
1500
Transimpedance
440
−51
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Overdrive Recovery
2/3.6
1.5 to 3.6
−52
MΩ/pF
V
dB
ns
VCM
=
2.5 V
−54
G = +1, f = 1 MHz, triangle wave
60
POWER DOWN PIN
Power-Down Input Voltage
Power-down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
< +VS − 3.1
> +VS − 1.9
200
V
V
ns
Turn-Off Time
Turn-On Time
300
ns
Input Current
Enabled
Power-Down
−1.1
−50
+0.17
−40
+1.4
−30
µA
µA
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 100 Ω
RL = 1 kΩ
VO = 2 V p-p, second HD < −50 dBc
G = +2, f = 100 kHz, triangle wave
1.1 to 3.9
1 to 3.1
1.05 to 4.1
0.85 to 4.15
70
V
V
mA
ns
Linear Output Current
Overdrive Recovery
65
POWER SUPPLY
Operating Range
4.5
12
V
Quiescent Current
Quiescent Current (Power-Down)
Power Supply Rejection Ratio
11
0.7
−55/−60
12
0.95
−57/−62
13
1.25
mA
mA
dB
−PSRR/+PSRR
Rev. 0 | Page 4 of 20
AD8000
ABSOLUTE MAXIMUM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the
Parameter
Rating
quiescent power dissipation and the power dissipated in the die
due to the AD8000 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Supply Voltage
12.6 V
Power Dissipation
See Figure 4
−VS − 0.7 V to +VS + 0.7 V
±VS
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature
Operating Temperature Range
PD = Quiescent Power + (Total Drive Power – Load Power)
−VS
−65°C to +125°C
−40°C to +125°C
300°C
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
PD =
(
VS × IS
)
+
×
–
2
RL
Lead Temperature Range
(Soldering, 10 sec)
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
VS /4
RL
)
PD =
(
VS ×IS +
)
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
THERMAL RESISTANCE
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduces θJA.
θJA is specified for the worst-case conditions, that is, θJA is speci-
fied for device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
θJA
80
93
θJC
30
35
Unit
°C/W
°C/W
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
SOIC-8
3 mm × 3 mm LFCSP
3.0
2.5
2.0
Maximum Power Dissipation
The maximum safe power dissipation for the AD8000 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the AD8000. Exceeding a junction temperature of
175°C for an extended period of time can result in changes
in silicon devices, potentially causing degradation or loss of
functionality.
SOIC
1.5
LFCSP
1.0
0.5
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
Rev. 0 | Page 5 of 20
AD8000
TYPICAL PERFORMANCE CHARACTERISTICS
9
6
3
3
V
R
V
= ±5V
= 150Ω
S
G = +1, R = 432Ω
F
2
1
L
= 200mV p-p
OUT
R
= 392Ω
F
0
–1
–2
–3
–4
–5
–6
–7
G = +2, R = 432Ω, R = 432Ω
F
G
R
= 432Ω
F
R
= 487Ω
F
G = +10, R = 357Ω, R = 40.2Ω
F
G
V
= ±5V
S
0
G = +2
= 150Ω
R
L
V
= 200mV p-p
OUT
LFCSP
–3
1
10
100
1000
1
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response vs. RF
Figure 5. Small Signal Frequency Response vs. Various Gains
3
9
6
3
V
R
V
= ±5V
= 150Ω
G = –1, R = R = 249Ω
S
F
G
2
1
L
= 200mV p-p
OUT
R
= 392Ω
F
0
–1
–2
–3
–4
–5
–6
–7
R = 432Ω
F
R
= 487Ω
F
G = –10, R = 432Ω, R = 43.2Ω
F
G
V
= ±5V
S
0
G = +2
= 150Ω
R
L
G = –2, R = 432Ω, R = 215Ω
F
G
V
= 2V p-p
OUT
LFCSP
–3
1
10
100
FREQUENCY (MHz)
1000
1
10
100
FREQUENCY (MHz)
1000
Figure 9. Large Signal Frequency Response vs. RF
Figure 6. Small Signal Frequency Response vs. Various Gains
1000
100
10
3
200
150
V
R
V
= ±5V
= 150Ω
V
R
= ±5V
S
G = +1, R = 432Ω
S
F
2
1
= 100Ω
L
L
= 2V p-p
OUT
0
100
50
0
–1
–2
–3
–4
–5
–6
–7
G = +4, R = 357Ω, R = 121Ω
F
G
PHASE
G = +10, R = 357Ω, R = 40.2Ω
F
G
TZ
G = +2, R = R = 432Ω
F
G
1
50
100
0.1
0.1
1
10
100
1000
10000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Transimpedance and Phase vs. Frequency
Figure 7. Large Signal Frequency Response vs. Various Gains
Rev. 0 | Page 6 of 20
AD8000
9
6
3
3
2
R
= 1kΩ
L
V
= +5V, R = 0Ω
S
S
G = +1
R
V
= 432Ω
= 200mV p-p
F
1
OUT
LFCSP
0
V
= ±5V, R = 0Ω
S
S
–1
–2
–3
–4
–5
–6
–7
–40°C
V
= +5V, R = 50Ω
S
S
V
= ±5V
0
S
G = +2
= 150Ω
OUT
LFCSP
R
V
L
V
= ±5V, R = 50Ω
S
S
+125°C
+25°C
= 200mV p-p
–3
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response vs. Temperature
Figure 11. Small Signal Frequency Response vs. Supply Voltage
9
9
R
= 150Ω
L
G = +1
= 432Ω
R
F
6
3
V
= 200mV p-p
OUT
6
LFCSP
V
= ±5V
S
+25°C
–40°C
3
0
V
= +5V
S
–3
–6
–9
V
= ±5V
0
S
G = +2
= 1kΩ
+125°C
R
L
V
= 200mV p-p
OUT
LFCSP
–3
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response vs. Temperature
Figure 12. Small Signal Frequency Response vs. Supply Voltage
9
6.5
V
R
V
= ±5V
= 150Ω
S
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
L
= 2V p-p
OUT
G = +2
= 432Ω
6
R
F
SOIC
3
–40°C
LFCSP
+25°C
V
= ±5V
0
S
G = +2
= 150Ω
OUT
LFCSP
R
V
L
+125°C
= 2V p-p
–3
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Large Signal Frequency Response vs. Temperature
Figure 13. 0.1 dB Flatness
Rev. 0 | Page 7 of 20
AD8000
–40
–50
9
V
V
= ±5V
OUT
S
= 2V p-p
V
= 1V p-p
OUT
G = +1
= 1kΩ
R
L
–60
6
3
0
LFCSP
–70
SECOND HD
–80
V
= 2V p-p
= 4V p-p
OUT
–90
THIRD HD
–100
–110
–120
V
OUT
V
= ±5V
S
G = +2
R
LFCSP
= 150Ω
L
–3
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. Large Signal Frequency Response vs. Various Outputs
Figure 20. Harmonic Distortion vs. Frequency
–40
–20
–30
V
V
= ±5V
OUT
V
V
= ±5V
S
OUT
S
= 2V p-p
= 4V p-p
–50
–60
G = +1
R
LFCSP
G = +1
R = 1kΩ
L
= 150Ω
L
–40 LFCSP
SECOND HD
–70
–50
–60
–70
–80
–90
THIRD HD
SECOND HD
THIRD HD
–80
–90
–100
–110
–120
–100
1
10
FREQUENCY (MHz)
100
1
10
100
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency
Figure 21. Harmonic Distortion vs. Frequency
–40
–50
–60
–70
–80
–90
–100
–40
–50
V
= ±5V
V
V
= ±5V
= 2V p-p
S
S
G = +10
OUT
G = +2
= 150Ω
V
= 2V p-p
= 1kΩ
OUT
R
R
L
L
LFCSP
–60
LFCSP SECOND HD
SOIC SECOND HD
–70
SECOND HD
–80
THIRD HD
–90
–100
–110
–120
LFCSP THIRD HD
SOIC THIRD HD
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 22. Harmonic Distortion vs. Frequency
Figure 19. Harmonic Distortion vs. Frequency
Rev. 0 | Page 8 of 20
AD8000
–20
–30
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
V
= ±2.5V
V
V
= 5V
S
S
= 2V p-p
= 2V p-p
OUT
OUT
G = –1
= 150Ω
G = +2
= 150Ω
R
–40
R
L
L
LFCSP
LFCSP
SECOND HD
–50
–60
THIRD HD
THIRD HD
–70
SECOND HD
–80
–90
–100
–110
–120
1
10
FREQUENCY (MHz)
100
1
1
1
10
100
100
100
FREQUENCY (MHz)
Figure 23. Harmonic Distortion vs. Frequency
Figure 26. Harmonic Distortion vs. Frequency
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
V
V
= 5V
V
V
= 5V
S
S
= 2V p-p
= 2V p-p
OUT
OUT
G = –1
= 1kΩ
G = +2
= 1kΩ
R
R
–40
L
L
LFCSP
LFCSP
–50
THIRD HD
THIRD HD
–60
–70
SECOND HD
–80
SECOND HD
–90
–100
–110
–120
10
FREQUENCY (MHz)
1
10
FREQUENCY (MHz)
100
Figure 24. Harmonic Distortion vs. Frequency
Figure 27. Harmonic Distortion vs. Frequency
–20
–30
–40
–50
V
V
= ±5V
V
V
= ±5V
S
S
= 2V p-p
= 2V p-p
OUT
OUT
G = –1
R = 150Ω
L
G = +2
= 1kΩ
R
–40
L
LFCSP
LFCSP
–60
–50
SECOND HD
SECOND HD
THIRD HD
–60
–70
–70
THIRD HD
–80
–80
–90
–90
–100
–110
–120
–100
–110
1
10
FREQUENCY (MHz)
100
10
FREQUENCY (MHz)
Figure 28. Harmonic Distortion vs. Frequency
Figure 25. Harmonic Distortion vs. Frequency
Rev. 0 | Page 9 of 20
AD8000
–40
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
V
V
= ±5V
OUT
S
V
V
R
= ±5V
= 2V p-p
= 100Ω
S
= 2V p-p
IN
–50
G = –1
= 1kΩ
L
R
L
G = +1
LFCSP
–60
R
= 432Ω
F
–PSRR
SECOND HD
–70
–80
+PSRR
THIRD HD
–90
–100
–110
–120
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 29. Harmonic Distortion vs. Frequency
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency
1k
100
10
–25
V
V
R
= ±5V
= 1V p-p
= 100Ω
V
V
R
= ±5V
S
S
= 0.2V p-p
= 432Ω
IN
IN
–30
–35
–40
–45
–50
–55
–60
–65
L
F
LFCSP
LFCSP
1
G = +1
0.1
OR G = +2
0.01
0.1
0.1
1
10
100
1000
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 33. Common-Mode Rejection Ratio vs. Frequency
Figure 30. Output Impedance vs. Frequency
0.175
2.65
2.60
2.55
2.50
2.45
2.40
0.150
0.125
0.100
0.075
0.050
0.025
0
G = +1
G = +1
G = +2
G = +2
–0.025
–0.050
–0.075
–0.100
–0.125
V
= 5V
S
V
= ±5V
S
R
R
R
= 432Ω
= 0Ω
= 100Ω
F
S
L
R
R
R
= 432Ω
= 0Ω
= 100Ω
F
S
L
–0.150
–0.175
2.35
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
TIME (ns)
TIME (ns)
Figure 34. Small Signal Transient Response
Figure 31. Small Signal Transient Response
Rev. 0 | Page 10 of 20
AD8000
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
5
4
V
= ±5V, V
IN
S
G = +1
V
= ±5V, V
OUT
3
S
2
1
G = +2
V
= ±2.5V, V
OUT
S
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1
–2
–3
–4
–5
V
= ±2.5V, V
S
IN
V
= ±5V
= 432Ω
= 0Ω
S
R
R
R
F
S
L
G = +1
L
F
R
R
= 150Ω
= 432Ω
–1.50
–1.75
= 100Ω
0
5
10
15
20
25
30
35
40
45
50
0
200
400
600
800
1000
TIME (ns)
TIME (ns)
Figure 35. Large Signal Transient Response
Figure 38. Input Overdrive
6
5
0.5
0.4
0.3
0.2
G = +2
V
= ±5V, 2 × V
IN
S
V
IN
V
= ±5V, V
OUT
S
4
3
1V
2
0.1
0
1
0
–1
–2
–3
–4
–5
–6
V
= ±2.5V, 2 × V
IN
–0.1
–0.2
–0.3
–0.4
–0.5
S
V
= ±2.5V, V
S
OUT
G = +2
= 150Ω
= 432Ω
R
R
L
F
t
= 0s
–3
5ns/DIV
2 3
–5
–4
–2
–1
(V)
0
1
0
200
400
600
800
1000
TIME (ns)
V
CM
Figure 39. Output Overdrive
Figure 36. Settling Time
6k
5k
4k
3k
2k
1k
0
100
10
1
G = +2
V
= ±5V
S
SOIC, V = ±5V
R
R
= 432Ω
= 150Ω
G = +10
R
R
S
F
L
= 432Ω
= 47.5Ω
F
N
LFCSP, V = ±5V
S
SOIC, V = +5V
S
LFCSP, V = +5V
S
0.1
10
0
1
2
3
4
5
6
7
100
1k
10k
100k
1M
10M
100M
V
(V p-p)
FREQUENCY (Hz)
OUT
Figure 40. Input Voltage Noise
Figure 37. Slew Rate vs. Output Level
Rev. 0 | Page 11 of 20
AD8000
1000
0
–5
V
= ±5V
S
–10
–15
–20
–25
–30
–35
–40
–45
–50
V
= ±5V
S
V
= +5V
100
10
1
S
INVERTING CURRENT NOISE, R = 1kΩ
F
NONINVERTING CURRENT NOISE, R = 432Ω
F
0.1
10
100
1k
10k
100k
1M
10M
100M
1G
–5
–4
–3
–2
–1
0
1
2
3
4
5
FREQUENCY (Hz)
V
(V)
CM
Figure 41. Input Current Noise
Figure 44. Input Bias Current vs. Common-Mode Voltage
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
20
15
10
5
R
TERM = 50
BACK
= ±5V
V
S
G = +2
= –10dBm
P
OUT
SOIC
V
= ±5V
S
0
–5
–10
–15
V
= +5V
S
–20
–5
–4
–3
–2
–1
0
1
2
3
4
5
10
100
1000
V
(V)
CM
FREQUENCY (MHz)
Figure 45. Output Voltage Standing Wave Ratio (S22)
Figure 42. Input VOS vs. Common-Mode Voltage
25
20
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
G = +10
G = +2
15
10
5
G = +1
0
V
= ±5V
S
–5
–10
–15
–20
INPUT R = 0Ω
S
V
= +5V
S
V
P
= ±5V
OUT
S
= –10dBm
SOIC
–25
–5
–4
–3
–2
–1
0
1
2
3
4
5
10
100
FREQUENCY (MHz)
1000
V
(V)
OUT
Figure 46. Input Voltage Standing Wave Ratio (S11)
Figure 43. Input Bias Current vs. Output Voltage
Rev. 0 | Page 12 of 20
AD8000
TEST CIRCUITS
+V
S
10µF
0.1µF
R
F
432Ω
50Ω
TRANSMISSION
LINE
50Ω
TRANSMISSION
LINE
AD8000
432Ω
49.9Ω
V
IN
60.4Ω
200Ω
200Ω
49.9Ω
0.1µF
10µF
–V
S
Figure 47. CMRR
V
= V + V
IN
P
S
49.9Ω
50Ω
TRANSMISSION
LINE
AD8000
50Ω
TRANSMISSION
LINE
49.9Ω
TERMINATION
49.9Ω
50Ω
TERMINATION
50Ω
R
432Ω
F
0.1µF
R
G
432Ω
10µF
–V
S
Figure 48. Positive PSRR
+V
S
10µF
0.1µF
50Ω
AD8000
50Ω
TRANSMISSION
LINE
TRANSMISSION
LINE
49.9Ω
TERMINATION
50Ω
49.9Ω
TERMINATION
50Ω
R
F
432Ω
R
G
432Ω
49.9Ω
= –V + V
V
N
S
IN
Figure 49. Negative PSRR
Rev. 0 | Page 13 of 20
AD8000
APPLICATIONS
+V
S
All current feedback amplifier operational amplifiers are
affected by stray capacitance at the inverting input pin. As a
practical consideration, the higher the stray capacitance on
the inverting input to ground, the higher RF needs to be to
minimize peaking and ringing.
10µF
+
R
F
0.1µF
FB
R
G
V
–
+V
IN
AD8000
V
O
V
O
R
+
L
CIRCUIT CONFIGURATIONS
–V
0.1µF
Figure 50 and Figure 51 show typical schematics for non-
inverting and inverting configurations. For current feedback
amplifiers, the value of feedback resistance determines the
stability and bandwidth of the amplifier. The optimum
performance values are shown in Table 5 and should not be
deviated from by more than 10% to ensure stable operation.
Figure 8 shows the influence varying RF has on bandwidth. In
noninverting unity-gain configurations, it is recommended that
an RS of 50 Ω be used, as shown in Figure 50.
10µF
+
–V
S
Figure 51. Inverting Configuration
VIDEO LINE DRIVER
The AD8000 is designed to offer outstanding performance as a
video line driver. The important specifications of differential
gain (0.02%), differential phase (0.01°), and 650 MHz band-
width at 2 V p-p meet the most exacting video demands. Figure 52
shows a typical noninverting video driver with a gain of +2.
Table 5 provides a quick reference for the circuit values, gain,
and output voltage noise.
+V
S
10µF
+
R
432Ω
432Ω
F
+V
4.7µF
S
0.1µF
FB
+
R
G
+V
0.1µF
–
FB
75Ω
CABLE
V
AD8000
+
O
R
S
V
O
75Ω
R
V
L
IN
V
OUT
AD8000
+
–V
0.1µF
75Ω
0.1µF
75Ω
CABLE
10µF
+
4.7µF
V
IN
+
–V
S
75Ω
–V
S
NONINVERTING
Figure 52. Video Line Driver
Figure 50. Noninverting Configuration
Table 5. Typical Values (LFCSP/SOIC)
−3 dB SS
Bandwidth
(MHz)
−3 dB LS
Bandwidth
(MHz)
Total Output
Noise Including
Resistors (nV/√Hz)
Component
Values (Ω)
Slew Rate
(V/µsec)
Output Noise
(nV/√Hz)
Gain
RF
RG
LFCSP
1380
600
550
350
SOIC
1580
650
550
365
LFCSP
550
610
350
370
SOIC
600
650
350
370
1
2
4
10
432
432
357
357
---
2200
3700
3800
3200
10.9
11.3
10
11.2
11.9
12
432
120
40
18.4
19.9
Rev. 0 | Page 14 of 20
AD8000
LOW DISTORTION PINOUT
PRINTED CIRCUIT BOARD LAYOUT
The AD8000 LFCSP features ADI’s new low distortion pinout.
The new pinout lowers the second harmonic distortion and
simplifies the circuit layout. The close proximity of the non-
inverting input and the negative supply pin creates a source of
second harmonic distortion. Physical separation of the non-
inverting input pin and the negative power supply pin reduces
this distortion significantly, as seen in Figure 22.
Laying out the printed circuit board (PCB) is usually the last
step in the design process and often proves to be one of the
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Since the AD8000 can operate into
the RF frequency spectrum, high frequency board layout con-
siderations must be taken into account. The PCB layout, signal
routing, power supply bypassing, and grounding all must be
addressed to ensure optimal performance.
By providing an additional output pin, the feedback resistor
can be connected directly across Pin 2 and Pin 3. This greatly
simplifies the routing of the feedback resistor and allows a more
compact circuit layout, which reduces its size and helps to
minimize parasitics and increase stability.
SIGNAL ROUTING
The AD8000 LFCSP features the new low distortion pinout
with a dedicated feedback pin and allows a compact layout. The
dedicated feedback pin reduces the distance from the output to
the inverting input, which greatly simplifies the routing of the
feedback network.
The SOIC also features a dedicated feedback pin. The feedback
pin is brought out on Pin 1, which is typically a No Connect on
standard SOIC pinouts.
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which
degrades phase margin. Signals that are susceptible to noise
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding.
Existing applications that use the standard SOIC pinout can
take full advantage of the performance offered by the AD8000.
For drop-in replacements, ensure that Pin 1 is not connected to
ground or to any other potential because this pin is connected
internally to the output of the amplifier. For existing designs,
Pin 6 can still be used for the feedback resistor.
POWER SUPPLY BYPASSING
EXPOSED PADDLE
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8000 power supply pins
need to be properly bypassed.
The AD8000 features an exposed paddle, which can lower the
thermal resistance by 25% compared to a standard SOIC plastic
package. The paddle can be soldered directly to the ground plane
of the board. Figure 53 shows a typical pad geometry for the
LFCSP, the same type of pad geometry can be applied to the
SOIC package.
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps to ensure that the power supply
pins “see” a low ac impedance across a wide band of frequencies.
This is important for minimizing the coupling of noise into the
amplifier. Starting directly at the power supply pins, the smallest
value and sized component should be placed on the same side
of the board as the amplifier, and as close as possible to the
amplifier, and connected to the ground plane. This process
should be repeated for the next larger value capacitor. It is
recommended for the AD8000 that a 0.1 µF ceramic 0508 case
be used. The 0508 offers low series inductance and excellent
high frequency performance. The 0.1 µF case provides low
impedance at high frequencies. A 10 µF electrolytic capacitor
should be placed in parallel with the 0.1 µF. The 10 µf capacitor
provides low ac impedance at low frequencies. Smaller values
of electrolytic capacitors can be used, depending on the circuit
requirements. Additional smaller value capacitors help to
provide a low impedance path for unwanted noise out to higher
frequencies but are not always necessary.
Thermal vias or “heat pipes” can also be incorporated into the
design of the mounting pad for the exposed paddle. These addi-
tional vias improve the thermal transfer from the package to
the PCB. Using a heavier weight copper on the surface to which
the amplifier’s exposed paddle is soldered also reduces the over-
all thermal resistance “seen” by the AD8000.
Figure 53. LFCSP Exposed Paddle Layout
Rev. 0 | Page 15 of 20
AD8000
Placement of the capacitor returns (grounds), where the capaci-
tors enter into the ground plane, is also important. Returning
the capacitors grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Ground and power planes should not be used under
any of the pins of the AD8000. The mounting pads and the
ground or power planes can form a parasitic capacitance at the
amplifiers input. Stray capacitance on the inverting input and
the feedback resistor form a pole, which degrades the phase
margin, leading to instability. Excessive stray capacitance on the
output also forms a pole, which degrades phase margin.
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. This is as another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduce the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distor-
tion due to high frequency compression at the output. The use
of vias should be minimized in the direct path to the amplifier
power supply pins since vias can introduce parasitic inductance,
which can lead to instability. When required, use multiple large
diameter vias because this lowers the equivalent parasitic
inductance.
Rev. 0 | Page 16 of 20
AD8000
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
BOTTOM VIEW
(PINS UP)
2.29 (0.092)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
2.29 (0.092)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
1.27 (0.05)
BSC
0.50 (0.020)
0.25 (0.010)
× 45°
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
1.27 (0.050)
0.40 (0.016)
0.51 (0.020)
0.31 (0.012)
0.25 (0.0098)
0.17 (0.0068)
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters and (inches)
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
0.45
1
PIN 1
INDICATOR
1.90
1.75
1.60
2.75
BSC SQ
TOP
VIEW
1.50
REF
EXPOSED
PAD
0.50
BSC
(BOTTOM VIEW)
4
5
0.25
MIN
1.60
1.45
1.30
0.80 MAX
0.65TYP
0.90
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body (CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8000YRDZ1
AD8000YRDZ-REEL1
AD8000YRDZ-REEL71
AD8000YCPZ-R21
AD8000YCPZ-REEL1
AD8000YCPZ-REEL71
Minimum Ordering Quantity
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead SOIC/EP
8-Lead SOIC/EP
8-Lead SOIC/EP
8-Lead LFCSP
Branding Package Option
1
RD-8-1
RD-8-1
RD-8-1
2,500
1,000
250
5,000
1,500
HNB
HNB
HNB
CP-8-2
CP-8-2
CP-8-2
8-Lead LFCSP
8-Lead LFCSP
1 Z = Pb-free part.
Rev. 0 | Page 17 of 20
AD8000
NOTES
Rev. 0 | Page 18 of 20
AD8000
NOTES
Rev. 0 | Page 19 of 20
AD8000
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05321–0–1/05(0)
Rev. 0 | Page 20 of 20
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