AD8001ANZ [ADI]
800 MHz, 50 mW Current Feedback Amplifier; 800兆赫， 50毫瓦电流反馈放大器
| 型号： | AD8001ANZ |
| 厂家： | 
ADI |
| 描述： | 800 MHz, 50 mW Current Feedback Amplifier |
| 文件： | 总17页 (文件大小：562K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
800 MHz, 50 mW
Current Feedback Amplifier
a
AD8001
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Excellent Video Specifications (RL = 150 ꢀ, G = +2)
Gain Flatness 0.1 dB to 100 MHz
0.01% Differential Gain Error
0.025ꢁ Differential Phase Error
Low Power
5.5 mA Max Power Supply Current (55 mW)
High Speed and Fast Settling
880 MHz, –3 dB Bandwidth (G = +1)
440 MHz, –3 dB Bandwidth (G = +2)
1200 V/ꢂs Slew Rate
5-Lead SOT-23-5
(RT-5)
8-Lead PDIP (N-8),
CERDIP (Q-8) and SOIC (R-8)
AD8001
NC
–IN
+IN
V–
8
7
6
5
NC
V+
1
2
3
4
+V
5
4
V
1
2
S
OUT
–V
S
OUT
NC
3
–IN
+IN
AD8001
10 ns Settling Time to 0.1%
Low Distortion
–65 dBc THD, fC = 5 MHz
33 dBm Third Order Intercept, F1 = 10 MHz
–66 dB SFDR, f = 5 MHz
High Output Drive
NC = NO CONNECT
transimpedance linearization circuitry. This allows it to drive
video loads with excellent differential gain and phase perfor-
mance on only 50 mW of power. The AD8001 is a current
feedback amplifier and features gain flatness of 0.1 dB to 100 MHz
while offering differential gain and phase error of 0.01% and
0.025°. This makes the AD8001 ideal for professional video
electronics such as cameras and video switchers. Additionally,
the AD8001’s low distortion and fast settling make it ideal for
buffer high speed A-to-D converters.
70 mA Output Current
Drives Up to 4 Back-Terminated Loads (75 ꢀ Each)
While Maintaining Good Differential Gain/Phase
Performance (0.05%/0.25ꢁ)
APPLICATIONS
A-to-D Drivers
Video Line Drivers
Professional Cameras
Video Switchers
Special Effects
The AD8001 offers low power of 5.5 mA max (VS = 5 V) and
can run on a single +12 V power supply, while being capable of
delivering over 70 mA of load current. These features make this
amplifier ideal for portable and battery-powered applications
where size and power are critical.
RF Receivers
The outstanding bandwidth of 800 MHz along with 1200 V/µs
of slew rate make the AD8001 useful in many general-purpose
high speed applications where dual power supplies of up to 6 V
and single supplies from 6 V to 12 V are needed. The AD8001 is
available in the industrial temperature range of –40°C to +85°C.
GENERAL DESCRIPTION
The AD8001 is a low power, high speed amplifier designed
to operate on 5 V supplies. The AD8001 features unique
9
V
R
= ꢃ5V
S
= 820ꢀ
6
3
FB
G = +2
= 100ꢀ
R
L
0
V
R
= ꢃ5V
S
–3
–6
= 1kꢀ
FB
–9
–12
10M
100M
FREQUENCY – Hz
1G
Figure 1. Frequency Response of AD8001
Figure 2. Transient Response of AD8001; 2 V Step, G = +2
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD8001*
Last content update 08/18/2013 12:37 am
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AD8001A SPICE Macro Model
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AD8001AR SPICE Macro Model
DOCUMENTATION
AD8001: Military Data Sheet
AN-692: Universal Precision Op Amp Evaluation Board
AN-649: Using the Analog Devices Active Filter Design Tool
AN-358: Noise and Operational Amplifier Circuits
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AN-356: User’s Guide to Applying and Measuring Operational
Collaborate Online with the ADI support team and other designers
about select ADI products.
Amplifier Specifications
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Constraints in Low Voltage High Speed Systems
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AN-257: Careful Design Tames High Speed Op Amps
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MT-057: High Speed Current Feedback Op Amps
MT-051: Current Feedback Op Amp Noise Considerations
MT-034: Current Feedback (CFB) Op Amps
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
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SOT-23-5/SOT-23-6 Packages
UG-101: Evaluation Board User Guide
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1800-419-0108
8-800-555-45-90
ADI Warns Against Misuse of COTS Integrated Circuits
Two-Stage Current-Feedback Amplifier
Russia:
Quality and Reliability
Lead(Pb)-Free Data
Choosing High-Speed Signal Processing Components for Ultrasound
Systems
Current Feedback Amplifiers Part 1: Ask The Applications Engineer-22
Current Feedback Amplifiers Part 2: Ask The Applications Engineer-23
PCN#00-406
SAMPLE & BUY
AD8001
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EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for documentation and
purchasing
Symbols and Footprints
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
(@ T = + 25ꢁC, V = ꢃ5 V, R = 100
ꢀ
, unless otherwise noted.)
AD8001–SPECIFICATIONS
A
S
L
AD8001A
Model
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, N Package
G = +2, < 0.1 dB Peaking, RF = 750 Ω
G = +1, < 1 dB Peaking, RF = 1 kΩ
G = +2, < 0.1 dB Peaking, RF = 681 Ω
G = +1, < 0.1 dB Peaking, RF = 845 Ω
G = +2, < 0.1 dB Peaking, RF = 768 Ω
G = +1, < 0.1 dB Peaking, RF = 1 kΩ
350
650
350
575
300
575
440
880
440
715
380
795
MHz
MHz
MHz
MHz
MHz
MHz
R Package
RT Package
Bandwidth for 0.1 dB Flatness
N Package
G = +2, RF = 750 Ω
85
110
125
145
1000
1200
10
MHz
MHz
MHz
V/µs
V/µs
ns
R Package
RT Package
G = +2, RF = 681 Ω
100
120
800
960
G = +2, RF = 768 Ω
Slew Rate
G = +2, VO = 2 V Step
G = –1, VO = 2 V Step
G = –1, VO = 2 V Step
G = +2, VO = 2 V Step, RF = 649 Ω
Settling Time to 0.1%
Rise and Fall Time
1.4
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p
G = +2, RL = 100 Ω
f = 10 kHz
f = 10 kHz, +In
–In
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
f = 10 MHz
–65
dBc
Input Voltage Noise
Input Current Noise
2.0
2.0
18
0.01
0.025
33
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
dBm
Differential Gain Error
Differential Phase Error
Third Order Intercept
1 dB Gain Compression
SFDR
0.025
0.04
f = 10 MHz
f = 5 MHz
14
–66
dBm
dB
DC PERFORMANCE
Input Offset Voltage
2.0
2.0
10
5.5
9.0
mV
mV
µV/°C
µA
TMIN–TMAX
Offset Drift
–Input Bias Current
5.0
25
35
6.0
10
TMIN–TMAX
TMIN–TMAX
µA
+Input Bias Current
3.0
µA
µA
Open-Loop Transresistance
VO
=
2.5 V
250
175
900
kΩ
TMIN–TMAX
kΩ
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
10
50
1.5
3.2
MΩ
Ω
Input Capacitance
pF
V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Offset Voltage
–Input Current
+Input Current
VCM
VCM
VCM
=
=
=
2.5 V
2.5 V, TMIN–TMAX
2.5 V, TMIN–TMAX
50
54
0.3
0.2
dB
µA/V
µA/V
1.0
0.7
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
RL = 150 Ω
RL = 37.5 Ω
2.7
50
85
3.1
70
110
V
mA
mA
Short Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
3.0
6.0
5.5
V
mA
dB
dB
µA/V
µA/V
TMIN–TMAX
5.0
75
56
0.5
0.1
+VS = +4 V to +6 V, –VS = –5 V
–VS = – 4 V to –6 V, +VS = +5 V
TMIN–TMAX
60
50
–Input Current
+Input Current
2.5
0.5
TMIN–TMAX
Specifications subject to change without notice.
–2–
REV. D
AD8001
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
The maximum power that can be safely dissipated by the
AD8001 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-
perature of the plastic, approximately 150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
Internal Power Dissipation @ 25°C2
PDIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W
8-Lead CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . .0.5 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
While the AD8001 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
2.0
T
= +150ꢁC
J
8-LEAD
PDIP PACKAGE
8-LEAD
CERDIP PACKAGE
1.5
8-Lead PDIP Package: θJA = 90°C/W
8-LEAD
SOIC PACKAGE
8-Lead SOIC Package: θJA = 155°C/W
8-Lead CERDIP Package: θJA = 110°C/W
5-Lead SOT-23-5 Package: θJA = 260°C/W
1.0
0.5
0
5-LEAD
SOT-23-5 PACKAGE
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢁC
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
Branding
AD8001AN
AD8001AQ
AD8001AR
AD8001AR-REEL
AD8001AR-REEL7
AD8001ART-REEL
AD8001ART-REEL7
AD8001ACHIPS
5962-9459301MPA*
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Lead PDIP
8-Lead CERDIP
8-Lead SOIC
13" Tape and REEL
7" Tape and REEL
13" Tape and REEL
7" Tape and REEL
Die Form
N-8
Q-8
R-8
R-8
R-8
RT-5
RT-5
HEA
HEA
8-Lead CERDIP
Q-8
*Standard Military Drawing Device.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8001 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
AD8001–Typical Performance Characteristics
806ꢀ
0.001ꢂF
0.1ꢂF
+V
S
V
TO
OUT
TEKTRONIX
CSA 404 COMM.
SIGNAL
806ꢀ
50ꢀ
ANALYZER
AD8001
0.1ꢂF
R
= 100ꢀ
V
L
IN
HP8133A
PULSE
GENERATOR
0.001ꢂF
T
/T = 50ps
F
R
–V
S
400mV
5ns
TPC 4. 2 V Step Response, G = +2
TPC 1. Test Circuit , Gain = +2
909ꢀ
0.001ꢂF
0.1ꢂF
+V
S
V
TO
OUT
TEKTRONIX
CSA 404 COMM.
SIGNAL
ANALYZER
AD8001
0.1ꢂF
R
= 100ꢀ
V
L
IN
LeCROY 9210
PULSE
GENERATOR
50ꢀ
0.001ꢂF
T
/T = 350ps
F
R
–V
S
TPC 2. 1 V Step Response, G = +2
TPC 5. Test Circuit, Gain = +1
0.5V
5ns
TPC 3. 2 V Step Response, G = +1
TPC 6. 100 mV Step Response, G = +1
REV. D
–4–
AD8001
1000
800
600
400
200
0
9
6
V
R
= ꢃ5V
S
V
R
= ꢃ5V
= 100ꢀ
S
= 820ꢀ
FB
L
G = +2
G = +2
= 100ꢀ
3
R
L
N
0
PACKAGE
V
R
= ꢃ5V
= 1kꢀ
S
–3
–6
FB
R
PACKAGE
–9
–12
10M
500
600
700
800
900
1000
100M
1G
FREQUENCY – Hz
VALUE OF FEEDBACK RESISTOR (R ) – ꢀ
F
TPC 7. Frequency Response, G = +2
TPC 10. –3 dB Bandwidth vs. RF
–50
–60
0.1
R
649ꢀ
=
F
ꢃ5V SUPPLIES
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
R
= 698ꢀ
F
V
= 2V p-p
OUT
R
= 100ꢀ
L
R
= 750ꢀ
F
G = +2
–70
G = +2
L
R
= 100ꢀ
SECOND HARMONIC
V
= 50mV
IN
–80
THIRD HARMONIC
–90
–100
10k
100k
1M
FREQUENCY – Hz
10M
100M
1M
10M
FREQUENCY – Hz
100M
TPC 8. 0.1 dB Flatness, R Package (for N Package Add
50 Ω to RF)
TPC 11. Distortion vs. Frequency, RL = 100 Ω
0.08
–50
G = +2
0.06
ꢃ5V SUPPLIES
R
= 806ꢀ
V
= 2V p-p
F
OUT
2 BACK TERMINATED
–60
–70
R
= 1kꢀ
L
0.04
0.02
0.00
LOADS (75ꢀ)
G = +2
SECOND HARMONIC
1 BACK TERMINATED
LOAD (150ꢀ)
–80
0.02
0.01
1 AND 2 BACK TERMINATED
LOADS (150ꢀ AND 75ꢀ)
–90
THIRD HARMONIC
0.00
–100
–0.01
–0.02
–110
0
100
10k
100k
1M
FREQUENCY – Hz
10M
100M
IRE
TPC 12. Differential Gain and Differential Phase
TPC 9. Distortion vs. Frequency, RL = 1 kΩ
REV. D
–5–
AD8001
5
1000
900
800
700
600
500
0
N PACKAGE
R PACKAGE
–5
–10
–15
–20
–25
–30
–35
V
= –26dBm
IN
R
= 909ꢀ
F
V
= 50mV
IN
R
= 100ꢀ
L
G = +1
1100
100M
900
1G
3G
700
800
1000
600
FREQUENCY – Hz
VALUE OF FEEDBACK RESISTOR (R ) – ꢀ
F
TPC 13. Frequency Response, G = +1
TPC 16. –3 dB Bandwidth vs. RF, G = +1
1
0
–40
–50
–60
–70
–80
–90
–100
R
= 649ꢀ
F
R
= 100ꢀ
L
–1
–2
–3
–4
–5
–6
–7
–8
–9
G = +1
= 2V p-p
V
R
= 953ꢀ
OUT
F
SECOND HARMONIC
G = +1
L
R
= 100ꢀ
V
= 50mV
IN
THIRD HARMONIC
2M
10M
100M
1G
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 14. Flatness, R Package, G = +1 (for N Package Add
100 Ω to RF)
TPC 17. Distortion vs. Frequency, RL = 100 Ω
3
0
–40
G = +1
–50
–60
R
= 1kꢀ
= 2V p-p
L
–3
–6
V
OUT
–9
–70
SECOND HARMONIC
–12
–80
–15
–18
THIRD HARMONIC
–90
R
= 100ꢀ
L
–21
–24
–27
G = +1
–100
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
1M
10M
FREQUENCY – Hz
100M
TPC 15. Distortion vs. Frequency, RL = 1 kΩ
TPC 18. Large Signal Frequency Response, G = +1
REV. D
–6–
AD8001
45
40
35
30
25
20
15
10
5
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
DEVICE NO. 1
G = +100
G = +10
R
= 1000ꢀ
F
DEVICE NO. 2
DEVICE NO. 3
R
= 470ꢀ
F
0
–5
–10
–15
–20
–25
R
= 100ꢀ
L
1M
10M
100M
1G
–60
–40
–20
0
20
40
60
80
100
FREQUENCY – Hz
JUNCTION TEMPERATURE – ꢁC
TPC 19. Frequency Response, G = +10, G = +100
TPC 22. Input Offset vs. Temperature
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
3.35
3.25
3.15
3.05
2.95
2.85
2.75
2.65
2.55
+V
OUT
R
V
= 150ꢀ
= ꢃ5V
L
S
|
–V
|
OUT
V
= ꢃ5V
S
+V
OUT
R
= 50ꢀ
= ꢃ5V
L
S
V
|
–V
|
OUT
–60 –40 –20
0
20
40
60
80
100 120 140
–60
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE – ꢁC
JUNCTION TEMPERATURE – ꢁC
TPC 23. Supply Current vs. Temperature
TPC 20. Output Swing vs. Temperature
5
4
125
120
115
110
105
100
95
3
SOURCE I
SC
–IN
2
|
SINK I
|
1
SC
0
–1
–2
–3
–4
+IN
60
90
85
–60
–40
–20
0
20
40
60
80
100
–60 –40 –20
0
20
40
80
100 120 140
JUNCTION TEMPERATURE – ꢁC
JUNCTION TEMPERATURE – ꢁC
TPC 24. Short Circuit Current vs. Temperature
TPC 21. Input Bias Current vs. Temperature
REV. D
–7–
AD8001
6
1k
100
10
5
4
3
2
1
0
V
R
= ꢃ5V
= 150ꢀ
= ꢃ2.5V
S
L
V
OUT
1
–T
Z
G = +2
0.1
0.01
+T
Z
R
= 909ꢀ
F
–60 –40 –20
0
20
40
60
80
100 120 140
10M
100M
10k
1M
100k
JUNCTION TEMPERATURE – ꢁC
FREQUENCY – Hz
TPC 25. Transresistance vs. Temperature
TPC 28. Output Resistance vs. Frequency
100
10
1
100
10
1
1
0
R
= 576ꢀ
F
–1
–2
–3
–4
–5
–6
–7
–8
–9
INVERTING CURRENT V = ꢃ5V
S
R
= 649ꢀ
F
G = –1
R
= 750ꢀ
F
R
= 100ꢀ
L
V
= 50mV
IN
NONINVERTING CURRENT V = ꢃ5V
S
VOLTAGE NOISE V = ꢃ5V
S
100
1k
10k
100k
10
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 26. Noise vs. Frequency
TPC 29. –3 dB Bandwidth vs. Frequency, G = –1
–48
–49
–50
–51
–52
–53
–54
–55
–56
–52.5
–55.0
–PSRR
–CMRR
–57.5
–60.0
–62.5
–65.0
–67.5
–70.0
–72.5
–75.0
–77.5
3V SPAN
+CMRR
CURVES ARE FOR WORST-
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
2.5V SPAN
+PSRR
0
–60 –40 –20
0
20
40
60
80
100 120 140
–60
–40
–20
20
40
60
80
100
JUNCTION TEMPERATURE – ꢁC
JUNCTION TEMPERATURE – ꢁC
TPC 27. CMRR vs. Temperature
TPC 30. PSRR vs. Temperature
REV. D
–8–
AD8001
30
20
–10
–20
CURVES ARE FOR WORST-
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.
910ꢀ
150ꢀ
+PSRR
910ꢀ
150ꢀ
V
IN
10
51ꢀ
V
OUT
0
62ꢀ
–10
–20
–30
–40
–50
–60
–30
–40
–50
–PSRR
–PSRR
+PSRR
R
= 909ꢀ
F
G = +2
1M
10M
100M
1G
300k
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
TPC 31. CMRR vs. Frequency
TPC 34. PSRR vs. Frequency
1
0
R
= 549ꢀ
F
–1
–2
–3
–4
–5
–6
–7
–8
–9
R
= 649ꢀ
F
G = –2
R
= 100ꢀ
L
V
= 50mV
R = 750ꢀ
F
IN
rms
1M
10M
100M
1G
FREQUENCY – Hz
TPC 35. 2 V Step Response, G = –1
TPC 32. –3 dB Bandwidth vs. Frequency, G = –2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3 WAFER LOTS
COUNT = 895
MEAN = 1.37
STD DEV = 1.13
CUMULATIVE
MIN = –2.45
MAX = +4.69
FREQ DIST
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT OFFSET VOLTAGE – mV
TPC 36. Input Offset Voltage Distribution
TPC 33. 100 mV Step Response, G = –1
REV. D
–9–
AD8001
THEORY OF OPERATION
A very simple analysis can put the operation of the AD8001, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8001’s open-loop behavior is expressed
as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop transimped-
ance behaves just as the open-loop voltage gain of a voltage
feedback amplifier, that is, it has a large dc value and decreases
at roughly 6 dB/octave in frequency.
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice,
parasitic capacitance at Pin 2 will also add phase in the feedback
loop, so picking an optimum value for RF can be difficult.
Figure 6 illustrates this problem. Here the fine scale (0.1 dB/
div) flatness is plotted versus feedback resistance. These plots
were taken using an evaluation card which is available to cus-
tomers so that these results may readily be duplicated.
Since the RIN is proportional to 1/gM, the equivalent voltage
gain is just TZ × gM, where the gM in question is the trans-
conductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 4, basic
analysis yields the following result.
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
0.1
VO
VIN
TZ (S)
TZ (S) + G × RIN + R1
R
649ꢀ
=
F
= G ×
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
R
= 698ꢀ
F
R1
R2
G = 1 +
RIN = 1/gM ≈ 50 Ω
G = +2
R
= 750ꢀ
F
R1
R2
R
IN
V
OUT
V
IN
1M
10M
FREQUENCY – Hz
100M
Figure 6. 0.1 dB Flatness vs. Frequency
Figure 4. Follower with Gain
Choice of Feedback and Gain Resistors
Recognizing that G × RIN << R1 for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G). This simple analysis in conjunction with Figure 5
can, in fact, predict the behavior of the AD8001 over a wide
range of conditions.
Because of the above-mentioned relationship between the band-
width and feedback resistor, the fine scale gain flatness will, to
some extent, vary with feedback resistance. It, therefore, is
recommended that once optimum resistor values have been
determined, 1% tolerance values should be used if it is desired to
maintain flatness over a wide range of production lots. In addition,
resistors of different construction have different associated parasitic
capacitance and inductance. Surface-mount resistors were used
for the bulk of the characterization for this data sheet. It is not
recommended that leaded components be used with the AD8001.
1M
100k
10k
1k
100
10
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 5. Transimpedance vs. Frequency
REV. D
–10–
AD8001
Printed Circuit Board Layout Considerations
Driving Capacitive Loads
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than
5 mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.
The AD8001 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance, as shown in Figure 8. The accompanying graph
shows the optimum value for RSERIES versus capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of RSERIES and CL.
909ꢀ
Power Supply Bypassing
R
SERIES
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈4.7 Ω for
optimum results.
I
N
R
500ꢀ
L
C
L
Figure 8. Driving Capacitive Loads
40
G = +1
DC Errors and Noise
30
20
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors, refer to the equation
below. For noise error the terms are root-sum-squared to give a
net output error. In the circuit in Figure 7 they are input offset
(VIO), which appears at the output multiplied by the noise gain
of the circuit (1 + RF/RI), noninverting input current (IBN × RN)
also multiplied by the noise gain, and the inverting input current,
which when divided between RF and RI and subsequently
multiplied by the noise gain always appears at the output as
IBN ×RF. The input voltage noise of the AD8001 is a low 2 nV/
√Hz. At low gains though the inverting input current noise times
RF is the dominant noise source. Careful layout and device
matching contribute to better offset and drift specifications for
the AD8001 compared to many other current feedback ampli-
fiers. The typical performance curves in conjunction with the
following equations can be used to predict the performance of
the AD8001 in any application.
10
0
5
10
15
20
25
0
C
– pF
L
Figure 9. Recommended RSERIES vs. Capacitive Load
RF
RF
VOUT = VIO × 1 +
IBN × RN × 1 +
IBI × RF
RI
RI
R
F
I
BI
R
I
V
OUT
I
BN
R
N
Figure 7. Output Offset Voltage
REV. D
–11–
AD8001
Communications
Operation as a Video Line Driver
Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamentals
and do not lend themselves to filtering. Theory predicts that the
third order harmonic distortion components increase in power at
three times the rate of the fundamental tones. The specification
of third order intercept as the virtual point where fundamental and
harmonic power are equal is one standard measure of distortion
performance. Op amps used in closed-loop applications do not
always obey this simple theory. At a gain of +2, the AD8001
has performance summarized in Figure 10. Here the worst third
order products are plotted versus input power. The third order
intercept of the AD8001 is +33 dBm at 10 MHz.
The AD8001 has been designed to offer outstanding perfor-
mance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.025°) meet
the most exacting HDTV demands for driving one video load.
The AD8001 also drives up to two back terminated loads as
shown in Figure 11, with equally impressive performance (0.01%,
0.07°). Another important consideration is isolation between
loads in a multiple load application. The AD8001 has more
than 40 dB of isolation at 5 MHz when driving two 75 Ω back
terminated loads.
75ꢀ
CABLE
909ꢀ
909ꢀ
75ꢀ
V
NO. 1
OUT
75ꢀ
+V
0.001ꢂF
S
+
0.1ꢂF
–45
75ꢀ
CABLE
G = +2
75ꢀ
F
= 10MHz
–50
–55
–60
–65
–70
–75
–80
1
75ꢀ
CABLE
V
NO. 2
OUT
AD8001
F
= 12MHz
2
75ꢀ
V
0.1ꢂF
2F – F
IN
2
1
75ꢀ
0.001ꢂF
2F – F
1
2
–V
S
Figure 11. Video Line Driver
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
INPUT POWER – dBm
Figure 10. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
REV. D
–12–
AD8001
Driving A-to-D Converters
ADC. Using the AD9058’s internal +2 V reference connected
to both ADCs as shown in Figure 12 reduces the number of
external components required to create a complete data
acquisition system. The 20 Ω resistors in series with ADC inputs
are used to help the AD8001s drive the 10 pF ADC input
capacitance. The AD8001 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.
The AD8001 is well suited for driving high speed analog-to-
digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below, the AD8001 is
shown driving the inputs of the AD9058, which are configured
for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified
(–2×), and offset (by +1.0 V) into the proper input range of the
1kꢀ
ENCODE
74ACT04
10pF
50ꢀ
10
36
ENCODE A
ENCODE B
8
649ꢀ
–V
5, 9, 22,
REF A
REF B
+5V
+V
S
38
24, 37, 41
–V
0.1ꢂF
ANALOG
IN A
324ꢀ
AD9058
RZ1
(J-LEAD)
20ꢀ
6
ꢃ0.5V
18
17
16
15
14
13
12
11
A
AD8001
IN A
D
(LSB)
0A
1.3kꢀ
2
3
–2V
+V
+V
+V
8
INT
AD707
20kꢀ
0.1ꢂF
0.1ꢂF
REF A
REF B
43
20kꢀ
649ꢀ
D
(MSB)
(LSB)
7A
1.3kꢀ
324ꢀ
RZ2
28
29
30
31
32
33
34
35
D
0B
ANALOG
IN B
ꢃ0.5V
20ꢀ
40
1
8
A
AD8001
IN B
COMP
0.1ꢂF
D
(MSB)
7B
7, 20,
26, 39
CLOCK
–V
–5V
1N4001
S
RZ1, RZ2 = 2,000ꢀ SIP (8-PKG)
0.1ꢂF
4,19, 21 25, 27, 42
Figure 12. AD8001 Driving a Dual A-to-D Converter
REV. D
–13–
AD8001
Layout Considerations
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.
The specified high speed performance of the AD8001 requires
careful attention to board layout and component selection. Proper
RF design techniques and low parasitic component selection
are mandatory.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the area
near the input pins to reduce stray capacitance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Chip capacitors should be used for supply bypassing (see Figure 13).
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large
R
F
R
F
+V
+V
S
S
+V
S
R
C1
0.1ꢂF
C3
10ꢂF
R
G
G
IN
R
R
O
O
OUT
OUT
R
T
IN
C2
0.1ꢂF
C4
10ꢂF
R
S
R
T
–V
–V
S
S
–V
S
Inverting Configuration
Supply Bypassing
Noninverting Configuration
Figure 13. Inverting and Noninverting Configurations for Evaluation Boards
Table I. Recommended Component Values
AD8001AN (PDIP)
Gain
AD8001AR (SOIC)
Gain
AD8001ART (SOT-23-5)
Gain
Component
–1
+1
+2
+10
+100
–1
+1
+2
+10
+100
–1
+1
+2
+10
+100
RF (Ω)
649
649
1050
750
750
49.9
470
51
49.9
1000
10
49.9
604
604
49.9
0
54.9
370
953
681
681
49.9
470
51
49.9
1000
10
49.9
845 1000 768
845 768
49.9 49.9 49.9
0
54.9 49.9 49.9
240 795 380
470
51
49.9
1000
10
49.9
R
R
G (Ω)
O (Nominal) (Ω) 49.9
49.9
49.9
RS (Ω)
0
RT (Nominal) (Ω) 54.9
49.9
880
49.9
460
49.9
260
49.9
20
49.9
710
49.9
440
49.9
260
49.9
20
49.9
260
49.9
20
Small Signal
BW (MHz)
0.1 dB Flatness
(MHz)
340
105
70
105
130
100
120
110 300 145
REV. D
–14–
AD8001
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.005 (0.13) 0.055 (1.40)
MIN
MAX
8
5
8
1
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54) BSC
0.405 (10.29) MAX
0.100 (2.54)
BSC
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.060 (1.52)
0.015 (0.38)
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.200 (5.08)
MAX
0.150 (3.81)
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
15
0
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC]
(R-8)
5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
2.90 BSC
8
1
5
4
5
1
4
3
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
2.80 BSC
1.60 BSC
2
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
PIN 1
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.95 BSC
0.25 (0.0098)
0.10 (0.0040)
1.90
BSC
1.30
1.15
0.90
8؇
0.51 (0.0201)
0.31 (0.0122)
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
1.45 MAX
0.22
0.08
COMPLIANT TO JEDEC STANDARDS MS-012AA
10؇
5؇
0؇
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.15 MAX
0.60
0.45
0.30
0.50
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
–15–
REV. D
AD8001
Revision History
Location
Page
7/03—Data Sheet changed from REV. C to REV. D
Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. D
相关型号：
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