AD8003 [ADI]
Triple, 1.5 GHz Op Amp; 三重， 1.5 GHz的运算放大器
| 型号： | AD8003 |
| 厂家： | 
ADI |
| 描述： | Triple, 1.5 GHz Op Amp |
| 文件： | 总16页 (文件大小：688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Triple, 1.5 GHz Op Amp
AD8003
CONNECTION DIAGRAM
FEATURES
High speed
1650 MHz (G = +1)
730 MHz (G = +2, VO = 2 V p-p)
4300 V/μs (G = +2, 4 V step)
Settling time 12 ns to 0.1%, 2 V step
Excellent for QXGA resolution video
Gain flatness 0.1 dB to 190 MHz
0.05% differential gain error, RL = 150 Ω
0.01° differential phase error, RL = 150 Ω
Low voltage offset: 0.7 mV (typical)
Low input bias current: 7 μA (typical)
Low noise: 1.8 nV/√Hz
Low distortion over wide bandwidth: SFDR −73 dBc @ 20 MHz
High output drive: 100 mA output load drive
Supply operation: +5 V to 5 V voltage supply
Supply current: 9.5 mA/amplifier
24 23 22 21 20 19
+V
+V
1
18
17
16
15
14
13
S1
S3
FEEDBACK 1
–IN 1
FEEDBACK 3
–IN 3
2
3
4
+IN 1
+IN 3
POWER DOWN 1
POWER DOWN 3
5
6
–V
S1
–V
S3
7
8
9
10 11 12
Figure 1. 24-Lead, 4 mm × 4 mm LFCSP_VQ (CP-24)
APPLICATIONS
High resolution video graphics
Professional video
Consumer video
High speed instrumentation
The AD8003 operates on only 9.5 mA of supply current per
amplifier. The independent power-down function of the
AD8003 reduces the quiescent current even further to 1.6 mA.
GENERAL DESCRIPTION
The AD8003 is a triple ultrahigh speed current feedback
amplifier. Using ADI’s proprietary eXtra Fast Complementary
Bipolar (XFCB) process, the AD8003 achieves a bandwidth of
1.5 GHz and a slew rate of 4300 V/μs. Additionally, the
amplifier provides excellent dc precision with an input bias
current of 50 μA maximum and a dc input voltage of 0.7 mV.
The AD8003 amplifier is available in a compact 4 mm × 4 mm,
24-lead LFCSP_VQ. The AD8003 is rated to work over the
industrial temperature range of −40°C to +85°C.
3
V
= ±5V
S
G = +1, R = 432Ω
F
2
1
The AD8003 has excellent video specifications with a frequency
response that remains flat out to 190 MHz and 0.1% settling within
12 ns to ensure that even the most demanding video systems
maintain excellent fidelity. For applications that use NTSC video,
as well as high speed video, the amplifier provides a differential
gain of 0.05% and a differential gain of 0.01°.
G = +2, +5, R = 464Ω
G = +1
F
R
= 150Ω
G = +2
L
V
= 2V p-p
OUT
0
–1
–2
–3
–4
–5
–6
–7
G = +5
The AD8003 has very low spurious-free dynamic range (SFDR)
(−73 dBc @ 20 MHz) and noise (1.8 nV/√Hz). With a supply
range between 5 V and 11 V and ability to source 100 mA of
output current, the AD8003 is ideal for a variety of applications.
1
10
100
1000
FREQUENCY (MHz)
Figure 2. Large Signal Frequency Response for Various Gains
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8003
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Configurations .................................................................. 12
RGB Video Driver...................................................................... 12
Printed Circuit Board Layout ....................................................... 13
Low Distortion Pinout............................................................... 13
Signal Routing............................................................................. 13
Exposed Paddle........................................................................... 13
Power Supply Bypassing............................................................ 13
Grounding................................................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications with 5 V Supply..................................................... 3
Specifications with +5 V Supply..................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications..................................................................................... 12
REVISION HISTORY
2/06—Rev. 0 to Rev. A
Changes to Figure 34...................................................................... 11
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD8003
SPECIFICATIONS WITH 5 ꢀ SꢁPPLY
TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, V = 0.2 V p-p, RF = 432 Ω
1650
730
MHz
MHz
MHz
MHz
MHz
V/μs
ns
o
G = +2, V = 2 V p-p
o
G = +10, V = 0.2 V p-p
290
o
G = +5, V = 2 V p-p
330
o
Bandwidth for 0.1 dB Flatness
Slew Rate
V = 2 V p-p
o
190
G = +2, V = 2 V step, RL = 150 Ω
3800
12
o
Settling Time to 0.1%
G = +2, V = 2 V step
o
Overload Recovery Input/Output
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz
30/40
ns
G = +1, V = 2 V p-p
76/97
79/73
dBc
dBc
o
Second/Third Harmonic @ 20 MHz
G = +1, V = 2 V p-p
o
Input Voltage Noise
Input Current Noise (I−/I+)
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
f = 1 MHz
f = 1 MHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
1.8
nV/√Hz
pA/√Hz
%
36/3
0.05
0.01
Degree
Input Offset Voltage
−9.3
+0.7
1.08
7.4
+9.3
mV
mV
μV/°C
μA
μA
μA
kΩ
TMIN − TMAX
Input Offset Voltage Drift
Input Bias Current
+IB/−IB
TMIN − TMAX (+IB/−IB)
−19/−40 −7/−7
−3.8/+29.5
14.2
600
+4/+50
1100
Input Offset Current
Transimpedance
V = 2.5 V
o
400
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
1.6/3
3.6
−48
MΩ/pF
V
dB
VCM = 2.5 V
−51
−46
3.92
RL = 150 Ω
VO = 2 V p-p, second harmonic < −50 dBc
40% over shoot
3.85
3.9
100
27
V
mA
pF
Linear Output Current
Capacitive Load Drive
POWER DOWN PINS
Power-Down Input Voltage
Power down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
<VS − 2.5
>VS − 2.5
40
V
V
ns
Turn-Off Time
Turn-On Time
130
ns
Input Current
Enabled
Power-Down
0.1
−235
μA
μA
−365
−85
POWER SUPPLY
Operating Range
4.5
8.1
1.2
10
10.2
1.6
V
mA
mA
Quiescent Current per Amplifier
Quiescent Current per Amplifier
Power Supply Rejection Ratio (+PSRR/−PSRR)
Enabled
Power down
9.5
1.4
−59/−57 −57/−53
−55/−50 dB
Rev. A | Page 3 of 16
AD8003
SPECIFICATIONS WITH +5 ꢀ SꢁPPLY
TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, V = 0.2 V p-p, RF = 432 Ω
1050
590
290
310
83
MHz
MHz
MHz
MHz
MHz
V/μs
ns
o
G = +2, V = 2 V p-p
o
G = +10, V = 0.2 V p-p
o
G = +5, V = 2 V p-p
o
Bandwidth for 0.1 dB Flatness
Slew Rate
V = 2 V p-p
o
G = +2, V = 2 V step, RL = 150 Ω
2860
12
o
Settling Time to 0.1%
G = +2, V = 2 V step
o
Overload Recovery Input/Output
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz
40/60
ns
G = +1, V = 2 V p-p
75/78
66/61
dBc
dBc
o
Second/Third Harmonic @ 20 MHz
G = +1, V = 2 V p-p
o
Input Voltage Noise
Input Current Noise (I−/I+)
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
f = 1 MHz
f = 1 MHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
1.8
nV/√Hz
pA/√Hz
%
36/3
0.04
0.01
Degree
Input Offset Voltage
−6.5
+2.7
2.06
14.2
+11
mV
mV
μV/°C
μA
TMIN − TMAX
Input Offset Voltage Drift
Input Bias Current (+IB/−IB)
−21/−50 −7.7/−2.3 +5/+48
TMIN − TMAX (+IB/−IB)
−4/−27.8
5.4
μA
μA
Input Offset Current
Transimpedance
300
530
1500
kΩ
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
1.6/3
1.3 to 3.7
−48
MΩ/pF
V
dB
−50
−45
1.62
RL = 150 Ω
VO = 2 V p-p, second harmonic < −50 dBc
45% over shoot
1.52
1.57
70
27
V
mA
pF
Linear Output Current
Capacitive Load Drive
POWER DOWN PINS
Power-Down Input Voltage
Power down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
<VS − 2.5
>VS − 2.5
125
V
V
ns
Turn-Off Time
Turn-On Time
80
ns
Input Current
Enabled
Power-Down
0.1
−43
μA
μA
−160
+80
POWER SUPPLY
Operating Range
4.5
6.3
0.8
10
9.4
1.1
V
mA
mA
Quiescent Current per Amplifier
Quiescent Current per Amplifier
Power Supply Rejection Ratio (+PSRR/−PSRR)
Enabled
Power down
7.9
0.9
−59/−56 −57/−53
−55/−50 dB
Rev. A | Page 4 of 16
AD8003
ABSOLꢁTE MAXIMꢁM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the
Parameter
Rating
quiescent power dissipation and the power dissipated in the die
due to the AD8003 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Supply Voltage
11 V
Power Dissipation
See Figure 3
−VS − 0.7 V to +VS + 0.7 V
±VS
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
PD = Quiescent Power + (Total Drive Power – Load Power)
−VS
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VS VOUT
VOUT
RL
−65°C to +125°C
−40°C to +85°C
300°C
PD =
(
VS × IS
)
+
×
–
2
RL
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2
VS /4
RL
)
PD =
(
VS ×IS +
)
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
THERMAL RESISTANCE
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduce θJA.
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
Unit
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle,
4 mm × 4 mm LFCSP_VQ (70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
24-Lead LFCSP_VQ
70
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8003 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8003. Exceeding a junction temperature of 175°C for
an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
3.0
2.5
2.0
1.5
1.0
0.5
0
–55
–35
–15
5
25
45
65
85
105
125
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation and loss of functionality.
Rev. A | Page 5 of 16
AD8003
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
3
V
= ±5V
V
= ±5V
S
S
F
L
G = +1, R = 432Ω
G = +2, +10, R = 464Ω
R
R
R
= 464Ω
= 150Ω
F
2
1
F
G = +2
V
= 200mV p-p
OUT
= 150Ω
= 200mV p-p
L
1
V
OUT
G = +1
0
0
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
–7
G = +10
G = –1
G = –2
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 4. Small Signal Frequency Response for Various Gains
3
3
G = +2
G = +2
V = ±5V
R
= 150Ω
S
L
L
2
1
2
1
R
= 150Ω
= 200mV p-p
V
= 200mV p-p
OUT
V
OUT
T = +105°C
0
0
V
= ±5V
S
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
–7
T = +25°C
T = –40°C
V
= +5V
S
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response for Various Temperatures
Figure 5. Small Signal Frequency Response for Various Supplies
3
3
G = +2
G = +2
V
= ±5V
V
= ±5V
S
L
S
L
2
1
2
1
R
V
= 150Ω
= 2V p-p
R
V
= 150Ω
= 200mV p-p
R
= 392Ω
R = 357Ω
F
OUT
R
= 392Ω
R
= 357Ω
F
OUT
F
F
F
0
0
R
= 432Ω
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
R
= 432Ω
F
R
= 464Ω
F
R = 464Ω
F
–5
–6
–7
1
10
100
FREQUENCY (MHz)
1000
1
10
100
1000
FREQUENCY (MHz)
Figure 9. Large Signal Feedback Resistor (RF) Optimization
Figure 6. Small Signal Feedback Resistor (RF) Optimization
Rev. A | Page 6 of 16
AD8003
6
3
0.3
0.2
G = +1
G = +2
V
= ±5V
R
= 150Ω
R
= 0Ω
S
L
L
S
V
= +5V
S
R
V
= 150Ω
= 200mV p-p
V
= 2V p-p
OUT
0.1
OUT
R
= 25Ω
S
0
V
= ±5V
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
S
R
= 50Ω
S
–3
–6
–9
–12
1
10
100
FREQUENCY (MHz)
1000
10000
1
10
100
1000
FREQUENCY (MHz)
Figure 13. 0.1 dB Flatness Response
Figure 10. G = +1 Series Resistor (RS) Optimization
3
2
3
2
V
= ±5V
V
= ±5V
S
S
G = +1, R = 432Ω
G = +2, +5, R = 464Ω
R
G = +2
R
V
F
G = +1
= 150Ω
F
L
T = +105°C
T = –40°C
= 150Ω
= 2V p-p
G = +2
= 2V p-p
L
OUT
1
1
V
OUT
0
0
T = +25°C
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
G = +5
–7
1
1
10
100
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Gains
Figure 14. Large Signal Frequency Response for Various Temperatures
–30
–30
G = +1
G = +2
V
V
= ±5V
= +5V
V
V
= ±5V
= +5V
S
S
S
S
R
= 100Ω
R
= 150Ω
L
L
–40
–50
–40
–50
V
= 2V p-p
V
= 2V p-p
OUT
OUT
–60
–60
SECOND
THIRD
SECOND
–70
–70
–80
–80
–90
–90
THIRD
–100
–110
–120
–100
–110
–120
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Harmonic Distortion vs. Frequency for Various Supplies
Figure 15. Harmonic Distortion vs. Frequency for Various Supplies
Rev. A | Page 7 of 16
AD8003
–10
0.20
0.15
0.10
0.05
0
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
G = +2
= 150Ω
OUT
G = +2
= 2V p-p
fC = 5MHz
V
V
= ±5V
= +5V
S
S
R
V
L
V
OUT
= 200mV p-p
–20
–30
–40
–50
–60
–70
–80
–90
V
= +5V
= ±5V
S
V
SECOND
S
–0.05
–0.10
–0.15
–0.20
THIRD
10
12
14
16
18
20
(Ω)
22
24
26
28
30
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
TIME (ns)
L
Figure 16. Harmonic Distortion vs. RL
Figure 19. Small Signal Pulse Response for Various Supplies
4.5
2.0
1.5
G = +2
0.3
0.2
0.1
R
V
= 150Ω
L
= 2V p-p
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
OUT
V
= +5V
S
1.0
V
= ±5V
S
0.5
C
= 15pF
0
L
0
–0.1
–0.2
–0.3
C
= 0pF
L
–0.5
–1.0
–1.5
–2.0
G = +2
R
= 150Ω
= ±5V
L
S
C
= 27pF
L
V
V
= 200mV p-p
OUT
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TIME (ns)
0
5
10
15
20
25
30
35
TIME (ns)
Figure 17. Large Signal Pulse Response for Various Supplies
Figure 20. Small Signal Pulse Response for Various Capacitive Loads
2.8
2.7
2.6
1.5
1.0
0.3
0.2
0.1
0
G = +2
V
OUT
V
= ±5V
S
R
= 150Ω
L
V
IN
0.5
C
= 15pF
L
2.5
2.4
2.3
2.2
0
C
= 0pF
L
V
SETTLE
–0.5
–1.0
–1.5
–0.1
–0.2
–0.3
G = +2
C = 27pF
L
R
= 150Ω
= 5V
L
S
V
V
= 200mV p-p
OUT
0
5
10
15
20
25
30
35
TIME (ns)
–5
0
5
10
15
20
TIME (ns)
25
30
35
40
45
Figure 18. Small Signal Pulse Response for Various Capacitive Loads
Figure 21. Short-Term 0.1% Settling Time
Rev. A | Page 8 of 16
AD8003
5
4
6000
5000
4000
3000
2000
1000
0
G = +2
= 150Ω
G = +1
INPUT
RISE
FALL
R
V
= ±5V
L
S
V
= ±5V
S
R
= 150Ω
L
3
OUTPUT
2
1
0
–1
–2
–3
–4
–5
V
= +5V
S
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
1
2
3
4
(V)
5
6
7
TIME (µs)
V
OUT p-p
Figure 25. Input Overdrive Recovery
Figure 22. Slew Rate vs. Output Voltage
1000
100
10
5
4
G = +1/+2
= ±5V
G = +2
= ±5V
INPUT × 2
V
V
S
S
R
= 150Ω
L
3
OUTPUT
2
1
0
–1
–2
–3
–4
–5
1
0.1
0.1
1
10
100
1000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (MHz)
TIME (µs)
Figure 23. Output Overdrive Recovery
Figure 26. Output Impedance vs. Frequency
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
G = 0
= ±5V
L
G = +2
V
V
= ±5V
S
S
R
= 150Ω
R
= 150Ω
L
PSR–
PSR+
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 24. Common-Mode Rejection vs. Frequency
Figure 27. Power Supply Rejection vs. Frequency
Rev. A | Page 9 of 16
AD8003
80
20
15
60
V
= ±5V
S
V
= +5V
S
V
= ±5V
V
= +5V
S
S
10
40
5
20
0
0
–5
–20
–40
–10
–15
–20
–60
–5
–4
–3
–2
–1
0
1
2
3
4
5
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 28. Offset Voltage vs. Input Common-Mode Range
Figure 31. Noninverting Input Bias Current vs. Common-Mode Range
10
8
6
V
= +5V
G = +2
S
V
DIS (VS = ±5V)
R
= 150Ω
L
V
= 0.5V dc
IN
6
5
4
3
2
1
0
V
= ±5V
S
4
2
0
V
DIS (VS = +5V)
–2
–4
–6
–8
–10
V
OUT (VS = +5V)
V
OUT (VS = ±5V)
V
OUT (VS = +5V)
V
OUT (VS = ±5V)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
(V)
OUT
TIME (µs)
Figure 29. Inverting Input Bias Current Linearity
Figure 32. Disable Switching Time for Various Supplies
10
9
8
7
6
5
4
3
2
1
0
200
150
100
50
10
9
8
7
6
5
4
3
2
1
0
40
G = +2
G = +2
R
V
= 150Ω
R
V
= 150Ω
L
S
L
S
30
= ±5V
= 5V
20
10
I
DIS
I
CC
0
0
I
DIS
–50
–100
–150
–200
–250
–300
–10
–20
–30
–40
–50
–60
I
CC
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
POWER DOWN PIN VOLTAGE (V
(V))
POWER DOWN PIN VOLTAGE (V
(V))
DIS
DIS
Figure 30. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
Figure 33. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
Rev. A | Page 10 of 16
AD8003
10000
1000
100
10
1000
100
V
= ±5V
= 1kΩ
S
F
V
= ±5V
S
R
I–
I+
10
1
10
1
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. Input Voltage Noise vs. Frequency
Figure 36. Input Current Noise vs. Frequency
200
180
160
140
120
100
80
1M
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
G = +2
= 150Ω
DRIVING: CH1 AND CH3
RECEIVING: CH2
R
V = ±5V
S
L
100k
10k
1k
V
= +5V
S
60
40
20
100
1k
0
10k
100k
1M
10M
100M
1G
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 35. Worst-Case Crosstalk
Figure 37. Transimpedance
Rev. A | Page 11 of 16
AD8003
APPLICATIONS
GAIN CONFIGURATIONS
RGB VIDEO DRIVER
Unlike conventional voltage feedback amplifiers, the feedback
resistor has a direct impact on the closed-loop bandwidth and
stability of the current feedback op amp circuit. Reducing the
resistance below the recommended value can make the amplifier
response peak and can even become unstable. Increasing the
size of the feedback resistor reduces the closed-loop bandwidth.
Figure 40 shows a typical RGB driver application using
bipolar supplies. The gain of the amplifier is set at +2 , where
RF = RG = 464 Ω. The amplifier inputs are terminated with
shunt 75 Ω resistors, and the outputs have series 75 Ω resistors
for proper video matching. In Figure 40, the POWER DOWN
pins are not shown connected to any signal source for simplicity. If
the power-down function is not used, it is recommended that
the POWER DOWN pins be tied to the positive supply and not
be left floating (not connected).
Table 5 provides a convenient reference for quickly determining
the feedback and gain set resistor values, and the small and
large signal bandwidths for common gain configurations. The
feedback resistors in Table 5 have been optimized for 0.1 dB
flatness frequency response.
In applications that require a fixed gain of +2, as previously
mentioned, the designer may consider the ADA4862-3.
The ADA4862-3 is another high performance triple current
feedback amplifier. The ADA4862-3 has integrated feedback
and gain set resistors that reduce board area and simplify designs.
Table 5. Recommended Values and Frequency Response1
Large Large
−3 dB Signal Signal
SS BW −3 dB 0.1 dB
PD3
PD2
PD1
Gain RF (Ω) RG (Ω) RS (Ω) (MHz) BW
BW
−1
+1
+2
+5
+10
300
432
464
300
300
300
N/A
464
75
0
24.9
0
734
1650
761
567
446
668
822
730
558
422
--
--
190
165
170
+V
S
14
23
5
10µF
1
0.1µF
0
4
3
R
75Ω
IN
75Ω
R
33.2
0
R
OUT
G
–V
S
1Conditions: VS = 5 V, TA = 25°C, RL = 150 Ω.
10µF
464Ω
6
R
F
464Ω
0.1µF
Figure 38 and Figure 39 show the typical noninverting and inverting
configurations and recommended bypass capacitor values.
2
+V
S
+V
S
10µF
10µF
19
R
AD8003
F
0.1µF
0.1µF
22
21
FB
G
75Ω
IN
R
G
G
OUT
+V
–
75Ω
–V
S
AD8003
V
R
G
O
10µF
R
S
V
O
R
V
+
L
IN
464Ω
–V
0.1µF
0.1µF
10µF
R
F
464Ω
20
+V
S
10µF
18
13
–V
S
0.1µF
15
16
B
75Ω
IN
Figure 38. Noninverting Gain
B
OUT
75Ω
–V
S
R
G
+V
S
10µF
10µF
464Ω
0.1µF
R
F
R
F
464Ω
0.1µF
+V
17
FB
R
G
V
–
IN
Figure 40. RGB Video Driver
AD8003
+
V
O
V
O
R
L
–V
0.1µF
10µF
–V
S
Figure 39. Inverting Gain
Rev. A | Page 12 of 16
AD8003
PRINTED CIRCꢁIT BOARD LAYOꢁT
Printed circuit board (PCB) layout is usually one of the last
steps in the design process and often proves to be one of the
most critical. A high performance design can be rendered
mediocre due to poor or sloppy layout. Because the AD8003
can operate into the RF frequency spectrum, high frequency
board layout considerations must be taken into account. The
PCB layout, signal routing, power supply bypassing, and
grounding must all be addressed to ensure optimal
performance.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8003 power supply pins
need to be properly bypassed.
Each amplifier has its own supply pins brought out for the
utmost flexibility. Supply pins can be commoned together or
routed to a dedicated power plane. Commoned supply connections
can also reduce the need for bypass capacitors on each supply
line. The exact number and values of the bypass capacitors are
dictated by the design specifications of the actual circuit.
LOW DISTORTION PINOUT
The AD8003 LFCSP features ADI’s low distortion pinout. The
pinout lowers the second harmonic distortion and simplifies the
circuit layout. The close proximity of the noninverting input
and the negative supply pin creates a source of second harmonic
distortion. Physical separation of the noninverting input pin
and the negative power supply pin reduces this distortion.
A parallel combination of different value capacitors from each
of the power supply pins to ground tends to work the best.
Paralleling different values and sizes of capacitors helps to
ensure that the power supply pins see a low ac impedance across
a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier. Starting directly at the
power supply pins, the smallest value and physical-sized
component should be placed on the same side of the board as
the amplifier, and as close as possible to the amplifier, and
connected to the ground plane. This process should be repeated
for the next largest capacitor value. It is recommended that a
0.1 μF ceramic 0508 case be used for the AD8003. The 0508
offers low series inductance and excellent high frequency
performance. The 0.1 μF case provides low impedance at high
frequencies. A 10 μF electrolytic capacitor should be placed in
parallel with the 0.1 μF. The 10 μF capacitor provides low ac
impedance at low frequencies. Smaller values of electrolytic
capacitors can be used depending on the circuit requirements.
Additional smaller value capacitors help provide a low impedance
path for unwanted noise out to higher frequencies but are not
always necessary.
By providing an additional output pin, the feedback resistor
can be connected directly between the feedback pin and the
inverting input. This greatly simplifies the routing of the
feedback resistor and allows a more compact circuit layout,
which reduces its size and helps to minimize parasitics and
increase stability.
SIGNAL ROUTING
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which
degrades phase margin. Signals that are susceptible to noise
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding.
EXPOSED PADDLE
Placement of the capacitor returns (grounds), where the
capacitors enter into the ground plane, is also important.
Returning the capacitor grounds close to the amplifier load is
critical for distortion performance. Keeping the capacitors
distance short, but equal from the load, is optimal for
performance.
The AD8003 features an exposed paddle, which lowers the
thermal resistance by approximately 40% compared to a
standard SOIC plastic package. The paddle can be soldered
directly to the ground plane of the board. Thermal vias or heat
pipes can also be incorporated into the design of the mounting
pad for the exposed paddle. These additional vias improve the
thermal transfer from the package to the PCB. Using a heavier
weight copper also reduces the overall thermal resistance path
to ground.
In some cases, bypassing between the two supplies can help
improve PSRR and maintain distortion performance in
crowded or difficult layouts. Designers should note this as
another option for improving performance.
Rev. A | Page 13 of 16
AD8003
GROUNDING
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A
series inductance with the parallel capacitance can form a tank
circuit, which can introduce high frequency ringing at the
output. This additional inductance can also contribute to
increased distortion due to high frequency compression at the
output. The use of vias should be minimized in the direct path
to the amplifier power supply pins because vias can introduce
parasitic inductance, which can lead to instability. When
required, use multiple large diameter vias because this lowers
the equivalent parasitic inductance.
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce
stray trace inductance and provide a low thermal path for the
amplifier. Ground and power planes should not be used under
any of the pins of the AD8003. The mounting pads and the
ground or power planes can form a parasitic capacitance at the
amplifiers input. Stray capacitance on the inverting input and
the feedback resistor form a pole, which degrades the phase
margin, leading to instability. Excessive stray capacitance on the
output also forms a pole, which degrades phase margin.
Rev. A | Page 14 of 16
AD8003
OꢁTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
24
19
18
PIN 1
INDICATOR
0.50
BSC
2.25
TOP
VIEW
3.75
BSC SQ
EXPOSED
2.10 SQ
1.95
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
6
13
7
12
0.25 MIN
0.80 MAX
0.65TYP
2.50 REF
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8003ACPZ-R21
AD8003ACPZ-REEL1
AD8003ACPZ-REEL71
Temperature Range
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Package Option
Ordering Quantity
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
CP-24-1
CP-24-1
CP-24-1
250
5,000
1,500
1 Z = Pb-free part.
Rev. A | Page 15 of 16
AD8003
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05721-0-2/06(A)
Rev. A | Page 16 of 16
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