AD8007AKS-REEL [ADI]
Ultralow Distortion High Speed Amplifiers; 超低失真高速放大器
| 型号： | AD8007AKS-REEL |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion High Speed Amplifiers |
| 文件： | 总20页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion
High Speed Amplifiers
AD8007/AD8008
FEATURES
CONNECTION DIAGRAMS
Extremely Low Distortion
Second Harmonic
SOIC (R)
SC70 (KS-5)
–88 dBc @ 5 MHz
AD8007
AD8007
–83 dBc @ 20 MHz (AD8007)
–77 dBc @ 20 MHz (AD8008)
Third Harmonic
V
5
+V
S
1
2
3
OUT
1
2
3
4
8
7
6
5
(Top View)
NC
–IN
+IN
(Top View)
NC
+V
S
–V
S
V
–101 dBc @ 5 MHz
OUT
4
+IN
–IN
–92 dBc @ 20 MHz (AD8007)
–98 dBc @ 20 MHz (AD8008)
High Speed
–V
S
NC
NC = NO CONNECT
650 MHz, –3 dB Bandwidth (G = +1)
1000 V/s Slew Rate
Low Noise
SOIC (R) and MSOP (RM)
2.7 nV/ Hz Input Voltage Noise
AD8008
√
(Top View)
22.5 pA/ Hz Input Inverting Current Noise
V
1
2
3
4
8
7
6
5
+V
V
OUT1
S
√
Low Power
–IN1
+IN1
OUT2
9 mA/Amplifier Typ Supply Current
Wide Supply Voltage Range
5 V to 12 V
–IN2
+IN2
–V
S
0.5 mV Typical Input Offset Voltage
Small Packaging
SOIC-8, MSOP, and SC70 Packages Available
APPLICATIONS
Instrumentation
IF and Baseband Amplifiers
Filters
A/D Drivers
DAC Buffers
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both
8-lead SOIC and 8-lead MSOP packages. These amplifiers are
rated to work over the industrial temperature range of –40°C
to +85°C.
GENERAL DESCRIPTION
–30
The AD8007 (single) and AD8008 (dual) are high perfor-
mance current feedback amplifiers with ultralow distortion
and noise. Unlike other high performance amplifiers, the low
price and low quiescent current allow these amplifiers to be
used in a wide range of applications. ADI’s proprietary second
generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low
power consumption.
G = +2
R
V
= 150⍀
–40
–50
L
=
5V
S
V
= 2V p-p
OUT
–60
–70
SECOND
THIRD
–80
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/ Hz
√
voltage noise, –83 dB SFDR @ 20 MHz (AD8007), and –77 dBc
SFDR @ 20 MHz (AD8008).
–90
–100
–110
With the wide supply voltage range (5 V to 12 V) and wide band-
width, the AD8007/AD8008 are designed to work in a variety of
applications. The AD8007/AD8008 amplifiers have a low power
supply current of 9 mA/amplifier.
1
10
FREQUENCY – MHz
100
Figure 1. AD8007 Second and Third Harmonic
Distortion vs. Frequency
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8007/AD8008–SPECIFICATIONS
(@ TA = 25؇C, RS = 200 ⍀, RL = 150 ⍀, RF = 499 ⍀, Gain = +2, unless otherwise noted.)
VS = ؎5 V
AD8007/AD8008
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 2 V p-p, RL = 1 kΩ
VO = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V Input Step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V Step
540
250
180
200
50
650
500
230
235
90
30
1000
18
MHz
MHz
MHz
MHz
MHz
ns
V/µs
ns
ns
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
900
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
35
NOISE/HARMONIC PERFORMANCE
Second Harmonic
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 5 MHz, VO = 2 V p-p
fC = 20 MHz, VO = 2 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 2 V p-p
–88
–83/–77
–101
dBc
dBc
dBc
dBc
Third Harmonic
IMD
–92/–98
–77
dBc
Third Order Intercept
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
–Input, f = 100 kHz
+Input, f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
43.0/42.5
42.5
–68
2.7
22.5
2
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
%
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
0.015
0.010
Degree
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
0.5
3
4
0.4
16
9
1.5
0.8
4
mV
µV/°C
µA
µA
+Input
–Input
+Input
–Input
VO = 2.5 V, RL = 1 kΩ
RL = 150 Ω
8
6
Input Bias Current Drift
Transimpedance
nA/°C
nA/°C
MΩ
1.0
0.4
MΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
+Input
+Input
4
1
MΩ
pF
V
–3.9 to +3.9
59
VCM
=
2.5 V
56
dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short Circuit Current, Source
Short Circuit Current, Sink
Capacitive Load Drive
VCC – VOH, VOL – VEE, RL = 1 kΩ
1.1
130
90
8
1.2
V
mA
mA
pF
30% Overshoot
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
5
12
10.2
V
mA
9
59
59
64
65
dB
dB
–PSRR
–2–
REV. D
AD8007/AD8008
(@ TA = 25؇C, RS = 200 ⍀, RL = 150 ⍀, RF = 499 ⍀, Gain = +2, unless otherwise noted.)
VS = 5 V
AD8007/AD8008
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, VO = 0.2 V p-p, RL = 1 kΩ
G = +1, VO = 0.2 V p-p, RL = 150 Ω
G = +2, VO = 0.2 V p-p, RL = 150 Ω
G = +1, VO = 1 V p-p, RL = 1 kΩ
Vo = 0.2 V p-p, G = +2, RL = 150 Ω
2.5 V Input Step, G = +2, RL = 1 kΩ
G = +1, VO = 2 V Step
520
350
190
270
72
580
490
260
320
120
30
740
18
35
MHz
MHz
MHz
MHz
MHz
ns
V/µs
ns
ns
Bandwidth for 0.1 dB Flatness
Overdrive Recovery Time
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
665
G = +2, VO = 2 V Step
G = +2, VO = 2 V Step
NOISE/HARMONIC PERFORMANCE
Second Harmonic
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 5 MHz, VO = 1 V p-p
fC = 20 MHz, VO = 1 V p-p
fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 1 V p-p
–96/–95
–83/–80
–100
–85/–88
–89/–87
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
Third Order Intercept
fC = 5 MHz, RL = 1 kΩ
fC = 20 MHz, RL = 1 kΩ
Output to Output f = 5 MHz, G = +2
f = 100 kHz
–Input, f = 100 kHz
+Input, f = 100 kHz
43.0
42.5/41.5
–68
2.7
22.5
2
dBm
dBm
dB
nV/√Hz
pA/√Hz
pA/√Hz
Crosstalk (AD8008)
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
0.5
3
4
0.7
15
8
1.3
0.6
4
mV
µV/°C
+Input
–Input
+Input
–Input
8
6
µA
µA
Input Bias Current Drift
Transimpedance
nA/°C
nA/°C
MΩ
VO = 1.5 V to 3.5 V, RL = 1 kΩ
RL = 150 Ω
0.5
0.4
MΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
+Input
+Input
4
1
MΩ
pF
V
1.1 to 3.9
56
VCM = 1.75 V to 3.25 V
54
dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage
Short Circuit Current, Source
Short Circuit Current, Sink
Capacitive Load Drive
VCC – VOH, VOL – VEE, RL = 1 kΩ
1.05
70
50
8
1.15
V
mA
mA
pF
30% Overshoot
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
+PSRR
5
12
9
V
mA
8.1
59
59
62
63
dB
dB
–PSRR
REV. D
–3–
AD8007/AD8008
ABSOLUTE MAXIMUM RATINGS*
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, then the total drive power
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . VS
is VS ϫ IOUT
.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply:
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
1.0 V
Output Short Circuit Duration . . . . . . . . . . . . . . See Figure 2
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (soldering 10 sec) . . . . . . . . . 300°C
V 2
S
4
PD = V × I
+
(
)
S
S
RL
In single-supply operation, with RL referenced to VS, worst case is
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VS
2
VOUT
=
Airflow will increase heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will
reduce the θJA. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps as discussed in
the board layout section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its proper-
ties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, perma-
nently shifting the parametric performance of the AD8007/
AD8008. Exceeding a junction temperature of 175°C for an
extended period of time can result in changes in the silicon
devices, potentially causing failure.
Figure 2 shows the maximum safe power dissipation in the pack-
age versus ambient temperature for the SOIC-8 (125°C/W),
MSOP (150°C/W), and SC70 (210°C/W) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
2.0
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as follows:
1.5
MSOP-8
SOIC-8
1.0
T = T + P × θ
(
)
J
A
D
JA
SC70-5
The power dissipated in the package (PD) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current
(IS). Assuming the load (RL ) is referenced to midsupply, the
total drive power is VS/2 ϫ IOUT, some of which is dissipated in the
package and some in the load (VOUT ϫ IOUT). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
0.5
0
–60
–40
–20
0
20
40
60
80
100
AMBIENTTEMPERATURE – ؇C
Figure 2. Maximum Power Dissipation vs.
Temperature for a 4-Layer Board
PD = quiescent power + (total drive power – load power):
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
2
VS VOUT
VOUT
RL
PD = V × I
+
×
−
(
)
S
S
2
RL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8007/AD8008 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. D
AD8007/AD8008
ORDERING GUIDE
Package
Description
Model
Temperature Range
Package Outline
Branding
AD8007AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SC70
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
R-8
R-8
R-8
KS-5
KS-5
KS-5
R-8
R-8
R-8
AD8007AR-REEL
AD8007AR-REEL7
AD8007AKS-R2
AD8007AKS-REEL
AD8007AKS-REEL7
AD8008AR
AD8008AR-REEL7
AD8008AR-REEL
AD8008ARM
HTA
HTA
HTA
RM-8
RM-8
RM-8
H2B
H2B
H2B
AD8008ARM-REEL
AD8008ARM-REEL7
REV. D
–5–
AD8007/AD8008–Typical Performance Characteristics
(VS = ؎5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
3
2
6.4
6.3
G = +2
G = +1
1
0
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
G = +2
–1
–2
–3
–4
–5
–6
–7
V
= +5V
S
V
= ؎5V
S
G = +10
G = –1
5.4
1
10
100
1000
10
100
FREQUENCY – MHz
1000
FREQUENCY – MHz
TPC 1. Small Signal Frequency Response for Various Gains
TPC 4. 0.1 dB Gain Flatness; VS = +5, 5 V
3
9
G = +1
2
G = +2
8
7
1
R
= 1k⍀, V = ؎5V
S
L
R
= 1k⍀, V = +5V
S
L
0
–1
–2
–3
–4
–5
–6
–7
6
5
R
V
= 150⍀
= +5V
L
S
R
= 150⍀, V = ؎5V
S
L
4
3
R
= 150⍀, V = ؎5V
S
L
2
R
= 150⍀, V = +5V
R
= 1k⍀, V = ؎5V
L
S
1
L
S
0
–1
10
100
1000
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Small Signal Frequency Response for VS and RLOAD
TPC 5. Small Signal Frequency Response for VS and RLOAD
3
9
G = +2
G = +1
2
R
= R = 324⍀
G
8
7
F
R
= 1k⍀
L
1
0
R
= 200⍀
R
= R = 249⍀
G
S
F
6
5
4
–1
–2
–3
–4
–5
–6
R
= 301⍀
S
R
= R = 499⍀
G
F
3
R
= 249⍀
S
2
1
R
= R = 649⍀
F
G
0
–7
–1
10
100
FREQUENCY – MHz
1000
10
100
1000
FREQUENCY – MHz
TPC 3. Small Signal Frequency Response for
Various RS Values
TPC 6. Small Signal Frequency Response for Various
Feedback Resistors, RF = RG
–6–
REV. D
AD8007/AD8008
10
9
10M
1M
90
G = +2
20pF
20pF AND
10⍀ SNUB
30
20pF AND
20⍀ SNUB
TRANSIMPEDANCE
8
7
6
5
4
3
2
1
0
0
100k
10k
1k
–30
PHASE
–90
499⍀
–150
–180
499⍀
200⍀
0pF
R
SNUB
–210
–270
–330
100
C
LOAD
49.9⍀
10
1
1
10
100
1000
10k
100k
1M
10M
100M
1G 2G
FREQUENCY – MHz
FREQUENCY – Hz
TPC 7. Small Signal Frequency Response for Capacitive
Load and Snub Resistor
TPC 10. Transimpedance and Phase vs. Frequency
9
3
V
= +5V, +85؇C
= ؎5V, +85؇C
S
G = +2
G = +1
8
2
1
V
S
7
6
V = +5V, +85؇C
S
0
V
= ؎5V, +85؇C
S
5
–1
V
= +5V, –40؇C
V
= +5V, –40؇C
S
S
4
–2
V
= ؎5V, –40؇C
S
3
–3
–4
–5
V
= ؎5V, –40؇C
S
2
1
0
–6
–7
–1
10
100
1000
10
100
FREQUENCY – MHz
1000
FREQUENCY – MHz
TPC 11. Small Signal Frequency Response over
Temperature, VS = +5 V, 5 V
TPC 8. Small Signal Frequency Response over
Temperature, VS = +5 V, 5 V
9
3
V
= 2V p-p
G = +2
OUT
8
2
1
G = +2
G = +1
7
6
5
4
0
–1
–2
–3
–4
–5
–6
–7
G = +10
G = –1
R
= 150⍀, V = ؎5V,V = 2V p-p
S O
L
3
2
R
= 1k⍀, V = ؎5V,V = 2V p-p
S O
L
R
= 150⍀, V = +5V,V = 1V p-p
S O
L
1
R
= 1k⍀, V = +5V,V = 1V p-p
S O
L
0
–1
10
100
FREQUENCY – MHz
1000
1
10
100
1000
FREQUENCY – MHz
TPC 9. Large Signal Frequency Response for Various Gains
TPC 12. Large Signal Frequency Response for VS and RLOAD
REV. D
–7–
AD8007/AD8008
–40
–40
–50
G = ؉2
G = ؉1
V
V
= 5V
S
HD2, R = 150⍀
L
V
V
= 5V
S
= 1V p-p
–50
–60
O
= 1V p-p
O
HD3, R = 150⍀
L
HD2, R = 1k⍀
L
–60
HD2, R = 1k⍀
L
–70
–80
HD2, R = 150⍀
–70
L
HD3, R = 1k⍀
L
–80
–90
–90
HD3, R = 150⍀
L
–100
–110
–100
HD3, R = 1k⍀
L
–110
1
10
100
1
10
FREQUENCY – MHz
100
FREQUENCY – MHz
TPC 13. AD8007 Second and Third Harmonic Distortion
vs. Frequency and RL
TPC 16. AD8007 Second and Third Harmonic Distortion
vs. Frequency and RL
–40
–40
G = ؉1
G = ؉2
V
V
= ؎5V
V
V
= ؎5V
S
S
–50
–60
–50
–60
= 2V p-p
= 2V p-p
O
O
HD2, R = 1k⍀
L
HD2, R = 150⍀
L
–70
–70
HD2, R = 150⍀
L
–80
HD2, R = 1k⍀
L
–80
HD3, R = 150⍀
L
–90
–90
HD3, R = 150⍀
L
HD3, R = 1k⍀
L
–100
–100
HD3, R = 1k⍀
L
–110
–110
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
TPC 14. AD8007 Second and Third Harmonic Distortion
vs. Frequency and RL
TPC 17. AD8007 Second and Third Harmonic Distortion
vs. Frequency and RL
–30
–30
V
V
R
= ؎5V
= 2V p-p
= 150⍀
G = +2
S
V
=
5V
= 150⍀
L
S
O
–40
–50
–60
–70
–40
–50
R
L
HD2, G = ؉10
HD3, V = 4V p-p
O
HD2, V = 4V p-p
–60
–70
–80
O
HD3, G = ؉10
HD2, V = 2V p-p
O
–80
HD3, G = ؉1
HD2, G = ؉1
–90
–100
–110
–90
–100
–110
HD3, V = 2V p-p
O
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
TPC 15. AD8007 Second and Third Harmonic Distortion
vs. Frequency and Gain
TPC 18. AD8007 Second and Third Harmonic Distortion
vs. Frequency and VOUT
–8–
REV. D
AD8007/AD8008
(VS = ؎5 V, RS = 200 ⍀, RF = 499 ⍀, RL = 150 ⍀, @ 25°C, unless otherwise noted.)
–40
–50
–40
–50
G = 1
G = 2
V
V
= 5V
V
V
= 5V
S
S
= 1V p-p
= 1V p-p
O
O
–60
–60
–70
HD2, R = 150⍀
HD2, R = 150⍀
L
L
–70
HD2, R = 1k⍀
HD2, R = 1k⍀
L
L
–80
–80
–90
–90
HD3, R = 1k⍀
HD3, R = 1k⍀
L
L
–100
–110
–100
–110
HD3, R = 150⍀
HD3, R = 150⍀
L
L
1
1
10
100
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 19. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
TPC 22. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
–40
–40
G = 1
V
V
= 5V
S
=
5V
–50
–60
= 1V p-p
–50
–60
O
HD2, R = 1k⍀
L
–70
–70
HD2, R = 150⍀
L
HD2, R = 150⍀
L
–80
–80
HD2, R = 1k⍀
L
–90
–90
HD3, R = 1k⍀
L
–100
–110
–100
–110
HD3, R = 1k⍀
L
HD3, R = 150⍀
HD3, R = 150⍀
L
L
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
TPC 20. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
TPC 23. AD8008 Second and Third Harmonic
Distortion vs. Frequency and RL
–30
–30
V
V
R
= 5V
= 2V p-p
= 150⍀
S
G = 2
R
V
= 150⍀
–40
–50
O
L
–40
–50
=
5V
L
S
HD2, G = 10
–60
–60
HD2, V = 4V p-p
O
–70
–70
HD2, V = 2V p-p
O
–80
–80
HD2, G = 1
–90
–90
HD3, V = 4V p-p
O
–100
–110
–100
–110
HD3, G = 10
HD3, G = 1
HD3, V = 2V p-p
O
1
10
FREQUENCY – MHz
100
1
10
100
FREQUENCY – MHz
TPC 21. AD8008 Second and Third Harmonic
Distortion vs. Frequency and Gain
TPC 24. AD8008 Second and Third Harmonic
Distortion vs. Frequency and VOUT
REV. D
–9–
AD8007/AD8008
–60
–65
–70
–75
–80
G = ؉2
S
G = ؉2
S
HD3, R = 1k⍀
V
= 5V
HD3, R = 1k⍀
L
L
V
= ؎5V
F
= 20MHz
O
F
= 20MHz
O
–65
–70
–75
HD2, R = 150⍀
HD2, R = 1k⍀
L
L
–85
–90
HD3, R = 150⍀
L
HD2, R = 1k⍀
L
HD3, R = 150⍀
L
–80
–85
–90
–95
–100
–105
–110
HD2, R = 150⍀
L
1
1.5
2
2.5
1
2
3
4
5
6
V
–V p-p
V
–V p-p
OUT
OUT
TPC 28. AD8007 Second and Third Harmonic
Distortion vs. VOUT and RL
TPC 25. AD8007 Second and Third Harmonic
Distortion vs. VOUT and RL
44
44
G = ؉2
G = +2
43
42
41
40
V
V
= 5V
43
42
41
40
39
V
V
R
= ؎5V
S
S
= 2V p-p
= 2V p-p
= 1k⍀
O
O
R
= 1k⍀
L
L
39
38
38
37
37
36
35
36
35
5
10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY – MHz
5
10 15 20 25 30 35 40 45 50 55 60 65 70
FREQUENCY – MHz
TPC 29. AD8008 Third Order Intercept vs. Frequency
TPC 26. AD8007 Third Order Intercept vs. Frequency
–65
–65
G = ؉2
HD2, R = 1k⍀
L
V
F
= 5V
S
–70
–75
= 20MHz
HD2, R = 150⍀
O
L
HD2, R = 150⍀
L
–70
–75
–80
–85
–90
HD2, R = 1k⍀
L
–80
–85
HD3, R = 150⍀
L
HD3, R = 1k⍀
L
–90
HD3, R = 150⍀
L
–95
HD3, R = 1k⍀
L
–100
–105
G = ؉2
V
= 5V
S
F
= 20MHz
O
–110
1
2
3
4
5
6
1
1.5
2
2.5
V
–V p-p
V
–V p-p
OUT
OUT
TPC 30. AD8008 Second and Third Harmonic
Distortion vs. VOUT and RL
TPC 27. AD8008 Second and Third Harmonic
Distortion vs. VOUT and RL
–10–
REV. D
AD8007/AD8008
(VS = ؎5 V, RL = 150 ⍀, RS = 200 ⍀, RF = 499 ⍀, unless otherwise noted.)
100
1000
100
10
INVERTING CURRENT NOISE 22.5pA/ Hz
10
2.7nV/ Hz
NONINVERTING CURRENT NOISE 2.0pA/ Hz
100 1k 10k 100k
FREQUENCY – Hz
1
1
10
100
1k
10k
100k
1M
1G
1G
10
1M
10M
FREQUENCY – Hz
TPC 31. Input Voltage Noise vs. Frequency
TPC 34. Input Current Noise vs. Frequency
1000
–20
G = ؉2
–30
–40
–50
–60
–70
–80
–90
–100
G = ؉2
R = 150⍀
100
10
V
= ؎5V
S
V
= 1V p-p
M
SIDE B DRIVEN
1
SIDE A DRIVEN
0.1
0.01
100k
1M
10M
100M
100k
10M
100M
1G
1M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 35. AD8008 Crosstalk vs. Frequency (Output to Output)
TPC 32. Output Impedance vs. Frequency
20
10
0
V
= ؎5V, ؉5V
S
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
+PSRR
–40
–50
–60
–70
–80
–PSRR
10k
100k
1M
10M
100M
1G
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 36. PSRR vs. Frequency
TPC 33. CMRR vs. Frequency
REV. D
–11–
AD8007/AD8008
G = +2
R
= 150⍀, V = ؉5V AND ؎5V
S
R
= 150⍀, V = +5V AND 5V
S
G = ؉1
L
L
R
= 1k⍀, V = +5V AND 5V
S
L
R
= 1k⍀, V = ؉5V AND ؎5V
S
L
50mV/DIV
50mV/DIV
20
0
10
20
30
TIME – ns
40
50
30
TIME – ns
40
50
0
10
TPC 40. Small Signal Transient Response for
TPC 37. Small Signal Transient Response for
RL = 150 Ω, 1 kΩ and VS = +5 V, 5 V
RL = 150 Ω, 1 kΩ and VS = +5 V, 5 V
G = –1
G = +1
R
= 150⍀
L
INPUT
R
= 1k⍀
L
OUTPUT
1V/DIV
1V/DIV
0
10
20
30
40
50
0
10
20
30
40
50
TIME – ns
TIME – ns
TPC 41. Large Signal Transient Response, G = –1,
RL = 150 Ω
TPC 38. Large Signal Transient Response for
RL = 150 Ω, 1 kΩ
G = ؉2
C
= 0pF
C
= 0pF
L
G = ؉2
LOAD
C
= 20pF
L
C
= 10pF
= 20pF
C
= 20pF
LOAD
L
R
= 10⍀
SNUB
C
LOAD
499⍀
499⍀
200⍀
RSNUB
CLOAD
–
+
49.9⍀
50mV/DIV
10
1V/DIV
10
0
20
30
TIME – ns
40
50
0
20
30
40
50
TIME – ns
TPC 42. Small Signal Transient Response: Effect of
Series Snub Resistor when Driving Capacitive Load
TPC 39. Large Signal Transient Response
for Capacitive Load = 0 pF, 10 pF, and 20 pF
–12–
REV. D
AD8007/AD8008
4
3
G = +10
V
=
5V
G = ؉2
S
V
=
0.75V
IN
؉V
S
2
R
= 1k⍀
L
1
R
= 150⍀
L
0
–1
–2
OUTPUT (2V/DIV)
INPUT (1V/DIV)
؊V
S
–3
–4
0
100
200
300
400
500
0
200
400
600
800
1000
TIME – ns
R
–⍀
L
TPC 43. Output Overdrive Recovery, RL = 1 kΩ,
TPC 45. VOUT Swing vs. RLOAD, VS = 5 V, G = +10,
VIN 0.75 V
150 Ω, VIN
=
2.5 V
=
0.5
0.4
G = +2
0.3
0.2
0.1
0
؊0.1
18ns
؊0.2
؊0.3
؊0.4
؊0.5
0
5
10
15
20
25
30
35
40
45
TIME – ns
TPC 44. 0.1% Settling Time, 2 V Step
REV. D
–13–
AD8007/AD8008
THEORY OF OPERATION
USING THE AD8007/AD8008
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 3. It closely
resembles a classic current feedback amplifier comprised of a
complementary emitter-follower input stage, a pair of signal mir-
rors, and a diamond output stage. However, in the case of the
AD8007/AD8008, several modifications have been made to greatly
improve the distortion performance over that of a classic current
feedback topology.
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically sepa-
rate (and possibly distant) grounds can lead to degraded
even-order harmonic performance. This situation is shown in
Figure 4 using the AD8007 as an example. Note that for a sinu-
soidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
R
499⍀
F
+V
S
M1
GND 1
I
–
3
I
–
1
10F
0.1F
+V
C 1
+
Q5
J
S
R
499⍀
G
+V
S
Q1
IN–
Q3
D1
D2
I
HiZ
DO
IN+
I
DI
R
200⍀
S
OUT
OUT
AD8007
IN
Q2
Q4
–V
S
–V
S
C 2
Q6
J
10F
0.1F
+
I
–
2
–
I
4
GND 2
M2
–V
S
Figure 4. High Frequency Capacitors Returned
to Physically Separate Grounds (Not Recommended)
R
F
R
G
The decoupling scheme shown in Figure 5 is preferable. Here,
the two high frequency decoupling capacitors are first tied
together at a common node, and are then returned to the
ground plane through a single connection. By first adding the
two currents flowing through each high frequency decoupling
capacitor, one is ensuring that the current returned into the
ground plane is only at the fundamental frequency.
Figure 3. Simplified Schematic of AD8007
The signal mirrors have been replaced with low distortion, high
precision mirrors. They are shown as “M1” and “M2” in Figure 3.
Their primary function from a distortion standpoint is to greatly
reduce the effect of highly nonlinear distortion caused by capaci-
tances CJ1 and CJ2. These capacitors represent the collector-to-base
capacitances of the mirrors’ output devices.
R
F
499⍀
A voltage imbalance arises across the output stage, as measured
from the high impedance node “HiZ” to the output node
“Out.” This imbalance is a result of delivering high output
currents and is the primary cause of output distortion. Circuitry
is included to sense this output voltage imbalance and generate
a compensating current “IDO.” When injected into the circuit,
IDO reduces the distortion that would be generated at the output
stage. Similarly, the nonlinear voltage imbalance across the
input stage (measured from the noninverting to the inverting
input) is sensed, and a current “IDI” is injected to compensate
for input-generated distortion.
10F
+
+V
S
R
499⍀
G
0.1F
R
S
OUT
AD8007
200⍀
IN
0.1F
–V
S
10F
+
The design and layout are strictly top-to-bottom symmetric in
order to minimize the presence of even-order harmonics.
Figure 5. High Frequency Capacitors Returned
to Ground at a Single Point (Recommended)
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 5, the user can connect one of the high
frequency decoupling capacitors directly across the supplies and
connect the other high frequency decoupling capacitor to ground.
This is shown in Figure 6.
–14–
REV. D
AD8007/AD8008
R
499⍀
F
Output Capacitance
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. There are two methods to
effectively minimize its effect:
10F
+
+V
S
C1
0.1F
1. Put a small value resistor in series with the output to isolate
the load capacitance from the amplifier’s output stage.
(See TPC 7.)
R
G
499⍀
2. Increase the phase margin by (a) increasing the amplifier’s
gain or (b) adding a pole by placing a capacitor in parallel
with the feedback resistor.
R
200⍀
S
OUT
AD8007
C2
IN
0.1F
–V
S
Input-to-Output Coupling
10F
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted posi-
tive feedback.
+
Figure 6. High Frequency Capacitors Connected
across the Supplies (Recommended)
External Components and Stability
The AD8007 and AD8008 are current feedback amplifiers and,
to a first order, the feedback resistor determines the bandwidth
and stability. The gain, load impedance, supply voltage, and
input impedances also have an effect.
Layout Considerations
The standard noninverting configuration with recommended power
supply bypassing is shown in Figure 6. The 0.1 µF high fre-
quency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +VS pin to the –VS pin. Con-
nect C1 from the +VS pin to signal ground.
TPC 6 shows the effect of changing RF on bandwidth and peaking
for a gain of +2. Increasing RF will reduce peaking but also
reduce the bandwidth. TPC 1 shows that for a given RF, increasing
the gain will also reduce peaking and bandwidth. Table I shows
the recommended RF and RG values that optimize bandwidth with
minimal peaking.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads will work against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For the larger value capacitors, which
are intended to be effective at lower frequencies, the current
return path distance is less critical.
Table I. Recommended Component Values
Gain
RF(Ω)
RG(Ω)
RS (Ω)
–1
499
499
499
499
499
499
NA
499
124
54.9
200
200
200
200
200
LAYOUT AND GROUNDING CONSIDERATIONS
Grounding
+1
+2
+5
+10
A ground plane layer is important in densely packed PC boards
to minimize parasitic inductances. However, an understanding of
where the current flows in a circuit is critical to implementing
effective high speed circuit design. The length of the current path
is directly proportional to the magnitude of parasitic induc-
tances and thus the high frequency impedance of the path. High
speed currents in an inductive ground return will create an
unwanted voltage noise. Broad ground plane areas will reduce
the parasitic inductance.
The load resistor will also affect bandwidth as shown in TPCs 2
and 5. A comparison between TPCs 2 and 5 also demonstrates
the effect of gain and supply voltage.
When driving loads with a capacitive component, stability is
improved by using a series snub resistor RSNUB at the output.
The frequency and pulse responses for various capacitive loads
are illustrated in TPCs 7 and 42, respectively.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance will reduce the input imped-
ance at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations
if severe enough. It is recommended that the external passive com-
ponents that are connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
For noninverting configurations, a resistor in series with the input,
RS, is needed to optimize stability for Gain = +1, as illustrated
in TPC 3. For larger noninverting gains, the effect of a series
resistor is reduced.
REV. D
–15–
AD8007/AD8008
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8؇
0.51 (0.0201)
0.31 (0.0122)
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8؇
0؇
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
2.00 BSC
5
1
4
3
1.25 BSC
PIN 1
2.10 BSC
2
0.65 BSC
1.10 MAX
1.00
0.90
0.70
0.22
0.08
0.46
0.36
0.26
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AA
–16–
REV. D
AD8007/AD8008
Revision History
Location
Page
6/03—Data Sheet changed from REV. C to REV. D
Change to Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Deleted Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Deleted EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10/02—Data Sheet changed from REV. B to REV. C
CONNECTION DIAGRAMS captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9/02—Data Sheet changed from REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02—Data Sheet changed from REV. 0 to REV. A.
Added AD8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (RN) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to MAXIMUM POWER DISSIPATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
New TPCs 19–24 and TPCs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MSOP-8 (RM) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REV. D
–17–
–18–
–19–
–20–
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