AD8016AREZ [ADI]
Low Power, High Output; 低功耗，高输出
| 型号： | AD8016AREZ |
| 厂家： | 
ADI |
| 描述： | Low Power, High Output |
| 文件： | 总21页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, High Output
Current xDSL Line Driver
Data Sheet
AD8016
FEATURES
PIN CONFIGURATIONS
xDSL line driver that features full ADSL central office (CO)
Performance on ±12 V supplies
Low power operation
+V1
1
1
2
3
4
5
6
7
8
9
24 +V2
V
23
22
21
V
V
V
2
OUT
OUT
V
1
1
2
INN
INN
+
– + –
V
2
INP
INP
±± V to ±12 V voltage supply
AGND
AGND
AGND
AGND
PWDN0
20 AGND
19 AGND
18 AGND
17 AGND
16 PWDN1
15 BIAS
14 –V2
12.± mA/amp (typical) total supply current
Power reduced keep alive current of 4.± mA/amp
High output voltage and current drive
AD8016
TOP VIEW
(Not to Scale)
I
OUT = 600 mA
DGND 10
–V1 11
NC 12
40 V p-p differential output voltage RL = ±0 Ω, VS = ±12 V
Low single-tone distortion
13 NC
–7± dBc @ 1 MHz SFDR, RL = 100 Ω, VOUT = 2 V p-p
MTPR = –7± dBc, 26 kHz to 1.1 MHz, ZLINE = 100 Ω,
NC = NO CONNECT
PLINE = 20.4 dBm
Figure 1. 24-Lead SOIC_W_BAT (RB-24)
High Speed
1
2
28
NC
NC
NC
NC
78 MHz bandwidth (–3 dB), G = +±
40 MHz gain flatness
1000 V/μs slew rate
27 NC
3
26
25
24
23
22
21
20
19
18
17
16
15
NC
4
+V
–V
2
2
2
NC
IN
IN
5
PWDN1
BIAS
–V2
6
V
OUT
7
AD8016ARE
+V2
+V1
TOP VIEW
8
–V1
(Not to Scale)
9
V
1
1
1
DGND
NC
OUT
10
11
12
13
14
–V
+V
IN
PWDN0
NC
IN
NC
NC
NC
NC
NC
NOTES
1. THE EXPOSED PADDLE IS FLOATING,
NOT ELECTRICALLY CONNECTED
INTERNALLY.
2. NC = NO CONNECT.
Figure 2. 28-Lead TSSOP_EP (RE-28-1)
GENERAL DESCRIPTION
The AD8016 high output current dual amplifier is designed for
the line drive interface in Digital Subscriber Line systems such
as ADSL, HDSL2, and proprietary xDSL systems. The drivers
are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
the xDSL hybrid in Figure 35 and Figure 36. Two digital bits
(PWDN0, PWDN1) allow the driver to be capable of full
performance, an output keep-alive state, or two intermediate
bias states. The keep-alive state biases the output transistors
enough to provide a low impedance at the amplifier outputs
for back termination.
The AD8016 is available in a low cost 24-lead SOIC_W_BAT
and a 28-lead TSSOP_EP with an exposed lead frame (ePAD).
Operating from 12 ꢀ supplies, the AD8016 requires only 1.5 W
of total power dissipation (refer to the Power Dissipation section
for details) while driving 20.4 dBm of power downstream using
The low power dissipation, high output current, high output
voltage swing, flexible power-down, and robust thermal
packaging enable the AD8016 to be used as the central office
(CO) terminal driver in ADSL, HDSL2, ꢀDSL, and proprietary
xDSL systems.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
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Last content update 08/18/2013 06:42 pm
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AD8016
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Feedback Resistor Selection...................................................... 14
Bias Pin and PWDN Features................................................... 14
Thermal Shutdown .................................................................... 15
Applications Information .............................................................. 16
Multitone Power Ratio (MTPR)............................................... 16
Generating DMT........................................................................ 17
Power Dissipation....................................................................... 17
Thermal Enhancements and PCB Layout............................... 18
Thermal Testing.......................................................................... 18
Air Flow Test Conditions .......................................................... 18
Experimental Results ................................................................. 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Logic Inputs (CMOS Compatible Logic) .................................. 4
Absolute Maximum Ratings............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circuts...................................................................................... 13
Theory of Operation ...................................................................... 14
Power Supply and Decoupling.................................................. 14
REVISION HISTORY
3/12—Rev. B to Rev. C
Updated Format..................................................................Universal
Deleted PSOP Package and Evaluation Boards (Throughout)... 1
Added Pin Configurations and Function Descriptions Sections.. 7
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 19
11/03—Rev. A to Rev. B
Changes to Ordering Guide ............................................................ 4
Changes to TPC 21........................................................................... 8
Updated Outline Dimensions..................................................19-20
Rev. C | Page 2 of 20
Data Sheet
AD8016
SPECIFICATIONS
@ 25°C, VS = 12 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = −40°C, TMAX = +85°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 4 V p-p
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
380
78
38
MHz
MHz
MHz
MHz
dB
69
16
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
90
0.1
1000
2
V/μs
ns
VOUT = 2 V p-p
Settling Time
0.1%, VOUT = 2 V p-p
23
ns
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
VOUT = 12.5 V p-p
350
ns
VOUT = 2 V p-p, G = +5, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm
500 kHz, Δf = 10 kHz, RL = 100 Ω/25 Ω
500 kHz, RL = 100 Ω/25 Ω
f = 10 kHz
−75/−62
−88/−74
−77/−64
−93/−76
–75
−88/−85
43/41
2.6
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA√Hz
Third Harmonic
Multitone Power Ratio1
IMD
−84/−80
42/40
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
–Input Bias Current
Input Resistance
4.5
21
f = 10 kHz
18
−3.0
−45
−75
1.0
+3.0
+45
+75
mV
μA
μA
kΩ
pF
V
4
400
2
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
−10
58
+10
+11
64
dB
Single-ended, RL = 100 Ω
G = 5, RL = 10 Ω, f1 = 100 kHz, −60 dBc SFDR
−11
400
V
600
2000
80
mA
mA
pF
Operating Range
3
13
13.2
10
8
V
Quiescent Current
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
12.5
8
5
mA/Amp
mA/Amp
mA/Amp
mA/Amp
μs
4
6
Recovery Time
Shutdown Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
25
1.5
75
250 μA out of bias pin
ΔVS = 1 V
4.0
mA/Amp
dB
63
−40
+85
°C
1 See Figure 48, R20, R21 = 0 Ω, R1 = open.
Rev. C | Page 3 of 20
AD8016
Data Sheet
@ 25°C, VS = 6 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p
G = +5, RF = 499 Ω, VOUT = 0.2 V p-p
VOUT = 1 V rms
320
71
15
MHz
MHz
MHz
MHz
dB
70
10
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Peaking
Slew Rate
Rise and Fall Time
80
VOUT = 0.2 V p-p < 50 MHz
VOUT = 4 V p-p, G = +2
VOUT = 2 V p-p
0.7
300
2
1.0
V/μs
ns
Settling Time
0.1%, VOUT = 2 V p-p
39
ns
Input Overdrive Recovery Time
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
Second Harmonic
VOUT = 6.5 V p-p
350
ns
G = +5, VOUT = 2 V p-p, RF = 499 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
fC = 1 MHz, RL = 100 Ω/25 Ω
26 kHz to 138 kHz, ZLINE = 100 Ω, PLINE = 13 dBm
500 kHz, Δf = 110 kHz, RL = 100 Ω/25 Ω
500 kHz
−73/61
−80/−68
−75/−63
−82/−70
−68
−88/−83
42/39
4
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA√Hz
Third Harmonic
Multitone Power Ratio1
IMD
−87/−82
42/39
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
−Input Bias Current
Input Resistance
f = 10 kHz
f = 10 kHz
5
20
17
−3.0
−25
−30
0.2
10
10
400
2
+3.0
+25
+30
mV
μA
μA
kΩ
pF
V
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
−4
60
+4
+5
66
dB
Single-Ended, RL = 100 Ω
G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR
−5
300
V
420
830
50
mA
mA
pF
RS = 10 Ω
Quiescent Current
PWDN1, PWDN0 = (1, 1)
PWDN1, PWDN0 = (1, 0)
PWDN1, PWDN0 = (0, 1)
PWDN1, PWDN0 = (0, 0)
To 95% of IQ
8
6
4
3
23
1.0
80
9.7
6.9
5.0
4.1
mA/Amp
mA/Amp
mA/Amp
mA/Amp
μs
Recovery Time
Shutdown Current
250 μA out of bias pin
ΔVS = 1 V
2.0
mA/Amp
dB
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
63
−40
+85
°C
1See Figure 48, R20, R21 = 0 Ω, R1 = open.
LOGIC INPUTS (CMOS COMPATIBLE LOGIC)
PWDN0, PWDN1, VCC = 12 V or 6 V; full temperature range.
Table 3.
Parameter
Min
2.2
0
Typ
Max
VCC
0.8
Unit
V
V
Logic 1 Voltage
Logic 0 Voltage
Rev. C | Page 4 of 20
Data Sheet
AD8016
ABSOLUTE MAXIMUM RATINGS
Table 4.
The output stage of the AD8016 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8016 to source or sink 2000 mA. To ensure
proper operation, it is necessary to observe the maximum
power derating curves. Direct connection of the output to
either power supply rail can destroy the device.
8
Parameter
Rating
Supply Voltage
26.4 V
Internal Power Dissipation
SOIC_W_BAT Package1
TSSOP_EP Package2
1.4 W
1.4 W
VS
Input Voltage (Common-Mode)
Differential Input Voltage
Output Short-Circuit Duration
VS
7
6
5
Observe power derating
curves
Storage Temperature Range
−65°C to +125°C
−40°C to +85°C
300°C
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
4
SOIC_W_BAT
1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper
at 85°C 24-lead SOIC_W_BAT package: θJA = 28°C/W.
3
TSSOP-EP
2 Specification is for device on a 4-layer board with 9 inches2 of 1 oz copper at
85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W.
2
1
0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0
10
20
30
40
50
60
70
80
90
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for
TJ = 125 °C
ESD CAUTION
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8016 is limited by the associated rise in junction temper-
ature. The maximum safe junction temperature for a plastic
encapsulated device is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by
the package.
Rev. C | Page 5 of 20
AD8016
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
28
NC
NC
NC
NC
27 NC
3
26
25
24
23
22
21
20
19
18
17
16
15
NC
4
+V
–V
2
2
2
NC
IN
IN
5
PWDN1
BIAS
–V2
+V1
1
2
3
4
5
6
7
8
9
24 +V2
6
V
OUT
V
1
1
1
23
22
21
V
V
V
2
OUT
OUT
7
AD8016ARE
+V2
+V1
V
2
INN
INN
+
– + –
TOP VIEW
8
–V1
(Not to Scale)
V
2
INP
INP
9
V
1
1
1
DGND
NC
OUT
AGND
AGND
AGND
AGND
PWDN0
20 AGND
19 AGND
18 AGND
17 AGND
16 PWDN1
15 BIAS
14 –V2
10
11
12
13
14
–V
+V
IN
IN
AD8016
TOP VIEW
(Not to Scale)
PWDN0
NC
NC
NC
NC
NC
NC
DGND 10
–V1 11
NC 12
NOTES
1. THE EXPOSED PADDLE IS FLOATING,
NOT ELECTRICALLY CONNECTED
INTERNALLY.
13 NC
NC = NO CONNECT
2. NC = NO CONNECT.
Figure 4. 24-Lead SOIC_W_BAT (RB-24)
Figure 5. 28-Lead TSSOP_EP (RE-28-1)
Table 5. Pin Function Descriptions
Pin No.
SOIC_W_BAT
TSSOP_EP
Mnemonic
Description
1
2
3
4
8
9
+V1
Positive Power Supply, Amp 1.
Output Signal, Amp 1.
Negative Input Signal, Amp 1.
Positive Input Signal, Amp1.
Analog Ground.
Power-Down Input 0.
Digital Ground.
Negative Power Supply, Amp1.
VOUT
VINN
VINP
1
1
1
5 to 8, 17 to 20
9
10
11
AGND
PWDN0
DGND
−V1
18
20
21
12, 13
1 to 3, 12 to 17, 19,
25 to 28
NC
This pin is not connected internally (see Figure 4 and Figure 5).
14
15
16
21
22
23
24
22
23
24
−V2
BIAS
PWDN1
−V Power Supply, Amp 2.
Quiescent Current Adjust.
Power-Down Input 1.
Positive Input Signal, Amp 2.
Negative Input Signal, Amp 2.
Output Signal, Amp 2.
Positive Power Supply, Amp 2.
Positive Input Signal, Amp 2.
Negative Input Signal, Amp 2.
Negative Input Signal, Amp 1.
Positive Input Signal, Amp 1.
VINP
2
VINN
2
6
7
4
5
10
11
EP
VOUT
+V2
2
+VIN2
−VIN2
−VIN1
+VIN1
EPAD
Exposed Pad. The exposed paddle is floating, not electrically connected internally.
Rev. C | Page 6 of 20
Data Sheet
AD8016
TYPICAL PERFORMANCE CHARACTERISTICS
V
= 100mV
OUT
–75dBc
V
= 20mV
IN
TIME (100ns/DIV)
549.3
550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY (kHz)
Figure 9. 100 mV Step Response; G = +5, VS = 12 V, RL = 25 Ω, Single-Ended
Figure 6. Multitone Power Ratio; VS = 12 V, 20.4 dBm Output Power into
100 Ω, Downstream
V
= 100mV
V
= 4V
OUT
OUT
V
= 20mV
IN
V
= 800mV
IN
TIME (100ns/DIV)
TIME (100ns/DIV)
Figure 10. 4 V Step Response; G = +5, VS = 12 V, RL = 25 Ω, Single-Ended
Figure 7. 100 mV Step Response; G = +5, VS = 6 V, RL = 25 Ω, Single-Ended
–30
R
= 499Ω
F
V
= 5V
(0,0)
OUT
G = +10
= 4V p-p
V
–40
–50
OUT
(0,1)
(1,0)
–60
–70
V
= 800mV
IN
–80
PWDN1, PWDN0 = (1,1)
–90
–100
–110
TIME (100ns/DIV)
0.01
0.1
1
10
20
FREQUENCY (MHz)
Figure 11. Distortion vs. Frequency; Second Harmonic, VS = 12 V, RL = 50 Ω,
Differential
Figure 8. 4 V Step Response; G = +5, VS = 6 V, RL = 25 Ω, Single-Ended
Rev. C | Page 7 of 20
AD8016
Data Sheet
–30
–40
–30
(0,0)
(0,1)
R
= 499Ω
R = 499Ω
F
G = +10
V = 4V p-p
OUT
F
G = +10
= 4V p-p
V
–40
–50
OUT
(0,0)
(0,1)
–50
(1,0)
(1,0)
–60
–60
–70
–70
PWDN1, PWDN0 = (1,1)
–80
–80
PWDN1, PWDN0 = (1,1)
–90
–90
–100
–110
–100
–110
0.01
0.1
1
10
20
0.01
0.1
1
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Distortion vs. Frequency; Second Harmonic, VS = 6 V, RL = 50 Ω
Figure 15. Distortion vs. Frequency; Third Harmonic, VS = 6 V, RL = 50 Ω,
Differential
–30
–30
R
= 499Ω
R
= 499Ω
F
F
G = +5
G = +5
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–40
–50
–60
–70
–80
–90
(1,0)
(0,0)
(0,1)
(1,0)
(0,0)
(0,1)
PWDN1, PWDN0 = (1,1)
PWDN1,
PWDN0 = (1,1)
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600 700
PEAK OUTPUT CURRENT (mA)
PEAK OUTPUT CURRENT (mA)
Figure 13. Distortion vs. Peak Output Current; Second Harmonic, VS = 12 V,
RL = 10 Ω, f = 100 kHz, Single-Ended
Figure 16. Distortion vs. Peak Output Current, Third Harmonic; VS = 12 V,
RL = 10 Ω, G = +5, f = 100 kHz, Single-Ended
–30
–30
(0,0)
R
= 499Ω
R
= 499Ω
F
F
G = +5
G = +10
= 4V p-p
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
V
–40
–50
OUT
(0,1)
(0,0)
–60
(1,0)
(0,1)
–70
(1,0)
PWDN1, PWDN0 = (1,1)
–80
–90
–100
PWDN1, PWDN0 = (1,1)
–110
0.01
0
100
200
300
400
500
600
0.1
1
10
20
FREQUENCY (MHz)
PEAK OUTPUT CURRENT (mA)
Figure 14. Distortion vs. Frequency; Third Harmonic, VS = 12 V, RL = 50 Ω,
Differential
Figure 17. Distortion vs. Peak Output Current; Second Harmonic, VS = 6 V,
RL = 5 Ω, f = 100 kHz, Single-Ended
Rev. C | Page 8 of 20
Data Sheet
AD8016
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
(0,0)
(0,1)
(0,0)
(0,1)
(1,0)
(1,0)
PWDN1, PWDN0 = (1,1)
PWDN1, PWDN0 = (1,1)
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
DIFFERENTIAL OUTPUT (V p-p)
DIFFERENTIAL OUTPUT (V p-p)
Figure 18. Distortion vs. Output Voltage; Second Harmonic, VS = 12 V,
G = +10, f = 1 MHz, RL = 50 Ω, Differential
Figure 21. Distortion vs. Output Voltage; Third Harmonic, VS = 12 V,
G = +10, f = 1 MHz, RL = 50 Ω, Differential
–30
–30
–40
–50
–60
–40
(0,0)
–50
(0,1)
–60
(0,0)
(0,1)
(1,0)
–70
–70
(1,0)
PWDN1, PWDN0 = (1,1)
–80
–90
–80
PWDN1, PWDN0 = (1,1)
–90
0
5
10
15
20
0
5
10
15
20
DIFFERENTIAL OUTPUT (V p-p)
DIFFERENTIAL OUTPUT (V p-p)
Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = 6 V,
G = +10, f = 1 MHz, RL = 50 Ω, Differential
Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = 6 V, G = +10,
f = 1 MHz, RL = 50 Ω, Differential
–30
–35
–40
–45
3
0
–3
(1,1)
–6
(1,0)
–9
–12
–15
–18
–21
–24
–27
–50
(0,0)
–55
(0,1)
(0,1)
–60
(1,0)
–65
–70
–75
(0,0)
V
= 40mV p-p
IN
G = +5
= 100Ω
PWDN1, PWDN0 = (1,1)
400 500 600
R
L
–80
0
100
200
300
1
10
100
500
PEAK OUTPUT CURRENT (mA)
FREQUENCY (MHz)
Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = 6 V,
G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended
Figure 23. Frequency Response; VS = 12 V, @ PWDN1, PWDN0 Codes
Rev. C | Page 9 of 20
AD8016
Data Sheet
11
11
8
G = +5
L
F
G = +5
R
R
= 100Ω
= 499Ω
R
R
= 100Ω
L
F
8
5
= 499Ω
5
2
2
–1
–1
–4
–4
–7
–7
–10
–13
–16
–10
–13
–16
–19
–19
1
10
100
500
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. Output Voltage vs. Frequency; VS = 12 V
Figure 27. Output Voltage vs. Frequency; VS = 6 V
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
V
R
= 2V rms
= 602Ω
R
= 499Ω
IN
F
F
(1,1)
(1,0)
+PSRR
–10
–20
–30
–40
–50
–60
–70
–80
(0,1)
–PSRR
(0,0)
0.01
0.1
1
10
100
500
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. CMRR vs. Frequency; VS = 12 V @ PWDN1, PWDN0 Codes
Figure 28. PSRR vs. Frequency; VS = 12 V
180
160
140
120
100
80
6
3
0
90
80
70
60
50
40
30
20
10
0
(1,1)
–3
–6
(1,0)
(0,1)
–9
–12
–15
–18
–21
–24
60
+I
NOISE
40
V
(0,0)
IN NOISE
V
= 40mV p-p
20
IN
G = +5
= 100Ω
R
L
0
10
100
1k
10k
100k
1M
10M
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. Noise vs. Frequency
Figure 26. Frequency Response; VS = 6 V, @ PWDN1, PWDN0 Codes
Rev. C | Page 10 of 20
Data Sheet
AD8016
G = +2
G = +2
R
V
= 1kΩ
R
V
= 1kΩ
F
OUT
F
OUT
= 2V
= 2V
STEP
STEP
R
= 100Ω
R
= 100
Ω
L
L
+2mV
(–0.1%)
+2mV
(–0.1%)
0
0
–2mV
(–0.1%)
V
IN
–2mV
(–0.1%)
V
V
– V
IN
V
OUT
OUT
IN
V
OUT
V
– V
20
OUT
IN
–5
0
5
10
15
25
30
35
40
45
–5
0
5
10
15
20
TIME (ns)
25
30
35
40
45
TIME (ns)
Figure 30. Settling Time 0.1%; VS = 12 V
Figure 33. Settling Time 0.1%; VS = 6 V
1000
100
–20
–30
–40
–50
–60
–70
–80
–90
V
= 2V p-p
OUT
F
R
= 499Ω
G = +5
= 100Ω
R
L
(0,0)
(0,1)
10
1
(1,0)
(1,1)
0.1
0.01
0.03
0.1
1
10
100
500
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. Output Crosstalk vs. Frequency
Figure 34. Output Impedance vs. Frequency @ PWDN1, PWDN0 Codes
1M
360
320
280
240
200
160
120
80
V
V
= 2V/DIV
OUT
IN
= 5V/DIV
100k
10k
1k
V
OUT
PHASE
100
10
0V
0V
TRANSIMPEDANCE
V
IN
1
0.1
0.01
40
0.001
0.0001 0.001
0
10k
–100
0
100 200 300 400 500 600 700 800 900
TIME (ns)
0.01
0.1
1
10
100
1k
FREQUENCY (MHz)
Figure 32. Open-Loop Transimpedance and Phase vs. Frequency
Figure 35. Positive Overdrive Recovery; VS = 12 V, G = +5, RL = 100 Ω
Rev. C | Page 11 of 20
AD8016
Data Sheet
18
16
14
12
10
8
V
V
= 2V/DIV
OUT
IN
= 5V/DIV
PWDN1, PWDN0 = (1,1)
0V
V
OUT
(1,0)
(0,1)
0V
(0,0)
V
IN
6
4
2
–100
0
100 200 300 400 500 600 700 800 900
TIME (ns)
0
0
50
100
(µA)
150
200
I
BIAS
Figure 36. Negative Overdrive Recovery; VS = 12 V, G = +5, RL = 100 Ω
Figure 38. IQ vs. IBIAS Current; VS = 6 V
25
12
8
+V
, V = ±12V
S
OUT
PWDN1, PWDN0 = (1,1)
20
+V
, V = ±6V
S
OUT
4
0
(1,0)
(0,1)
15
10
5
–4
–8
(0,0)
–V
, V = ±6V
S
OUT
–V
, V = ±12V
S
OUT
–12
10
0
0
50
100
(µA)
150
200
100
1k
10k
I
BIAS
R
(Ω)
LOAD
Figure 37. IQ vs. IBIAS Current; VS = 12 V
Figure 39. Output Voltage vs. RLOAD
Rev. C | Page 12 of 20
Data Sheet
AD8016
TEST CIRCUTS
10µF
+V
S
+
0.1µF
124
Ω
499Ω
+V
IN
V
OUT
+V
–V
O
49.9Ω
R
+
L
499Ω
499Ω
V
111Ω
R
IN
L
49.9
Ω
+V
S
O
0.1µF
0.1µF
10µF
0.1µF
–V
IN
49.9Ω
10µF
+
+
10µF
–V
S
–V
S
Figure 40. Single-Ended Test Circuit; G = +5
Figure 41. Differential Test Circuit; G = +10
Rev. C | Page 13 of 20
AD8016
Data Sheet
THEORY OF OPERATION
The AD8016 is a current feedback amplifier with high
(500 mA) output current capability. With a current feedback
amplifier, the current into the inverting input is the feedback
signal and the open-loop behavior is that of a transimpedance,
dVOUT/dIIN or TZ. The open-loop transimpedance is analogous
to the open-loop voltage gain of a voltage feedback amplifier.
Figure 42 shows a simplified model of a current feedback ampli-
fier. Because RIN is proportional to 1/gm, the equivalent voltage
gain is just TZ × gm, where gm is the transconductance of the
input stage. Basic analysis of the follower with gain circuit yields
POWER SUPPLY AND DECOUPLING
The AD8016 should be powered with a good quality (that is,
low noise) dual supply of 12 V for the best distortion and
multitone power ratio (MTPR) performance. Careful attention
must be paid to decoupling the power supply pins. A 10 μF
capacitor located in near proximity to the AD8016 is required
to provide good decoupling for lower frequency signals. In
addition, 0.1 μF decoupling capacitors should be located as
close to each of the four power supply pins as is physically
possible. All ground pins should be connected to a common
low impedance ground plane.
TZ (S)
VOUT
= G ×
VIN
TZ (S) + G × RIN + RF
FEEDBACK RESISTOR SELECTION
where:
In current feedback amplifiers, selection of feedback and gain
resistors has an impact on the MTPR performance, bandwidth,
and gain flatness. Take care in selecting these resistors so that
optimum performance is achieved. Table 6 below shows the
recommended resistor values for use in a variety of gain
settings. These values are suggested as a good starting point
when designing for any application.
RF
RG
G = 1 +
1
RIN
=
≈ 25 Ω
gm
Recognizing that G × RIN << RF for low gains, the familiar result
of constant bandwidth with gain for current feedback amplifiers
is evident, the 3 dB point being set when |TZ| = RF. Of course,
for a real amplifier there are additional poles that contribute
excess phase and there is a value for RF below which the ampli-
fier is unstable. Tolerance for peaking and desired flatness
determines the optimum RF in each application.
Table 6. Resistor Selection Guide
Gain
RF (Ω)
1000
500
650
750
RG (Ω)
∞
500
650
187
111
+1
−1
+2
+5
+10
1000
R
F
R
G
–
BIAS PIN AND PWDN FEATURES
R
IN
+
I
T
IN
V
Z
The AD8016 is designed to cover both central office (CO)
and customer premise equipment (CPE) ends of an xDSL
application. It offers full versatility in setting quiescent bias
levels for the particular application from full on to reduced
bias (in three steps) to full off (via BIAS pin). This versatility
gives the modem designer the flexibility to maximize efficiency
while maintaining reasonable levels of MTPR performance.
Optimizing driver efficiency while delivering the required DMT
power is accomplished with the AD8016 through the use of on-
chip power management features. Two digitally programmable
logic pins, PWDN1 and PWDN0, may be used to select four
different bias levels: 100%, 60%, 40%, and 25% of full quiescent
power (see Table 7).
OUT
R
N
+
V
IN
Figure 42. Simplified Block Diagram
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power
saving. The AD8016 is also unique in that it has a power
management system included on-chip. It features four user
programmable power levels (all of which provide a low output
impedance of the driver), as well as the provision for complete
shutdown (high impedance state). Also featured is a thermal
shutdown with alarm signal.
Table 7. PWDN Code Selection Guide
PWDN1 PWDN0
Code
Code
Quiescent Bias Level
100% (full on)
60%
1
1
0
0
X
1
0
1
0
X
40%
25% (low ZOUT but not off)
Full off (high ZOUT via 250 μA pulled out of
BIAS pin)
Rev. C | Page 14 of 20
Data Sheet
AD8016
The bias level can be controlled with TTL logic levels (high = 1)
applied to the PWDN1 and PWDN0 pins alone or in combina-
tion with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where ±1ꢀ ꢁ or ±± ꢁ
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
THERMAL SHUTDOWN
The AD801± ARB is designed to incorporate shutdown
protection against accidental thermal overload. In the event
of thermal overload, the AD801± was designed to shut down
at a junction temperature of 1±5°C and return to normal
operation at a junction temperature 140°C. The AD801±
continues to operate, cycling on and off, as long as the thermal
overload condition remains. The frequency of the protection
cycle depends on the ambient environment, severity of the
thermal overload condition, the power being dissipated, and
the thermal mass of the PCB beneath the AD801±. When the
AD801± begins to cycle due to thermal stress, the internal
shutdown circuitry draws current out of the node connected
in common with the BIAS pin, while the voltage at the BIAS
pin goes to the negative rail. When the junction temperature
returns to 140°C, current is no longer drawn from this node,
and the BIAS pin voltage returns to the positive rail. Under
these circumstances, the BIAS pin can be used to trip an alarm
indicating the presence of a thermal overload condition.
The BIAS control pin by itself is a means to continuously adjust
the AD801± internal biasing and, thus, quiescent current IQ. By
pulling out a current of 0 μA (or open) to approximatelyꢀ00 μA,
the quiescent current can be adjusted from 100% (full on) to a
full off condition. The full off condition yields a high output
impedance. Because of an on-chip resistor variation of up to
±ꢀ0%, the actual amount of current required to fully shut down
the AD801± can vary. To institute a full chip shutdown, a pull-
down current of ꢀ50 μA is recommended. See Figure 43 for the
logic drive circuit for complete amplifier shutdown. Figure 37
and Figure 38 show the relationship between current pulled out
of the BIAS pin (IBIAS) and the supply current (IQ). A typical
shutdown IQ is less than 1 mA total. Alternatively, an external
pull-down resistor to ground or a current sink attached to the
BIAS pin can be used to set IQ to lower levels (see Figure 44).
The BIAS pin may be used in combination with the PWDN1
and PWDN0 pins; however, diminished MTPR performance
may result when IQ is lowered too much. Current pulled away
from the BIAS pin shunts away a portion of the internal bias
current. Setting PWDN1 or PWDN0 to Logic 0 also shunts
away a portion of the internal bias current. The reduction of
quiescent bias levels due to the use of PWDN1 and PWDN0 is
consistent with the percentages established in Table 7. When
PWDN0 alone is set to Logic 0, and no other means of reducing
the internal bias currents is used, full-rate ADSL signals may be
driven while maintaining reasonable levels of MTPR.
Figure 44 also shows three circuits for converting this signal to
a standard logic level.
V
CC
AD8016
10kΩ
200µA
V = V – 0.2V
CC
BIAS
SHUT-
DOWN
OR
0µA – 200µA
BIAS
V
EE
PWDN0
PWDN1
5V
10kΩ
V
CC
5V
ALARM
1MΩ
10kΩ
BIAS
ALARM
BIAS
OR
MIN β 350
100kΩ
1/4 HCF 40109B
SGS–THOMSON
3.3V LOGIC
R1*
Figure 44. Shutdown and Alarm Circuit
R2
50kΩ
BIAS
2N3904
*R1 = 47kΩ FOR ±12V OR +12V ,
S
.
S
R1 = 22kΩ FOR ±6V
S
Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown
Rev. C | Page 15 of 20
AD8016
Data Sheet
APPLICATIONS INFORMATION
The AD8016 dual amplifier forms an integrated single-channel
ADSL line driver. The AD8016 may be applied in driving mod-
ulated signals including discrete multitone (DMT) in either
direction; upstream from CPE to the CO and downstream
from CO to CPE. The most significant thermal management
challenge lies in driving downstream information from CO sites
to the CPE. Driving xDSL information downstream suggests
the need to locate many xDSL modems in a single CO site. The
implication is that several modems will be placed onto a single
printed circuit board residing in a card cage located in a variety
of ambient conditions. Environmental conditioners such as fans
or air conditioning may or may not be available, depending on
the density of modems and the facilities contained at the CO
site. To achieve long-term reliability and consistent modem
performance, designers of CO solutions must consider the wide
array of ambient conditions that exist within various CO sites.
See Figure 6 for a sample of the ADSL downstream spectrum
showing MTPR results while driving 20.4 dBm of power onto
a 100 Ω line. Measurements of MTPR are typically made at
the output (line side) of ADSL hybrid circuits. MTPR can be
affected by the components contained in the hybrid circuit,
including the quality of the capacitor dielectrics, voltage ratings,
and the turns ratio of the selected transformers. Other compo-
nents aside, an ADSL driver hybrid containing the AD8016 can
be optimized for the best MTPR performance by selecting the
turns ratio of the transformers. The voltage and current demands
from the differential driver changes, depending on the trans-
former turns ratio. The point on the curve indicating maximum
dynamic headroom is achieved when the differential driver
delivers both the maximum voltage and current while maintaining
the lowest possible distortion. Below this point, the driver has
reserve current-driving capability and experiences voltage
clipping. Above this point, the amplifier runs out of current
drive capability before the maximum voltage drive capability
is reached. Because a transformer reflects the secondary load
impedance back to the primary side by the square of the turns
ratio, varying the turns ratio changes the load across the
differential driver. The following equation may be used to
calculate the load impedance across the output of the differen-
tial driver, reflected by the transformers, from the line side of
the xDSL driver hybrid.
MULTITONE POWER RATIO (MTPR)
ADSL systems rely on discrete multitone modulation to carry
digital data over phone lines. DMT modulation appears in the
frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figure 6
for an example of downstream DMT signals used in evaluating
MTPR performance.) A uniquely encoded, quadrature ampli-
tude modulation (QAM) signal occurs at the center frequency
of each subband or tone. Difficulties arise when decoding these
subbands if a QAM signal from one subband is corrupted by the
QAM signal(s) from other subbands, regardless of whether the
corruption comes from an adjacent subband or harmonics of
other subbands. Conventional methods of expressing the output
signal integrity of line drivers, such as spurious-free dynamic
range (SFDR), single-tone harmonic distortion or THD, two-
tone intermodulation distortion (IMD), and third-order inter-
cept (IP3) become significantly less meaningful when amplifiers
are required to drive DMT and other heavily modulated
waveforms. A typical xDSL downstream DMT signal may
contain as many as 256 carriers (subbands or tones) of QAM
signals. MTPR is the relative difference between the measured
power in a typical subband (at one tone or carrier) vs. the power
at another subband specifically selected to contain no QAM
data. In other words, a selected subband (or tone) remains
open or void of intentional power (without a QAM signal),
yielding an empty frequency bin. MTPR, sometimes referred
to as the empty bin test, is typically expressed in dBc, similar
to expressing the relative difference between single-tone
fundamentals and second or third harmonic distortion
components.
Z2
2 × N
′
Z ≡
2
where:
Z' is the primary side impedance as seen by the differential
driver.
Z2 is the line impedance.
N is the transformer turns ratio.
Figure 45 shows the dynamic headroom in each subband of a
downstream DMT waveform vs. turns ratio running at 100%
and 60% of the quiescent power while maintaining −65 dBc
of MTPR at VS = 12 V.
4
V
= ±12V
S
PWDN1, PWDN0 = (1,1)
3
2
V
= ±11.4V
S
PWDN1, PWDN0 = (1,1)
V
= ±12V
S
PWDN1, PWDN0 = (1,0)
1
0
V
= ±11.4V
S
PWDN1, PWDN0 = (1,0)
–1
–2
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
DOWNSTREAM TURNS RATIO
Figure 45. Dynamic Headroom vs. XFMR Turns Ratio, VS = 12 V
Rev. C | Page 16 of 20
Data Sheet
AD8016
Once an optimum turns ratio is determined, the amplifier has
an MTPR performance for each setting of the power-down
pins. Table 8 demonstrates the effects of reducing the total
power dissipated by using the PWDN pins on MTPR perfor-
mance when driving 20.4 dBm downstream onto the line with
a transformer turns ratio of 1:1.4.
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by ~23%. For
example:
POUT = 23.4 dBm = 220 mW
VOUT @ 50 Ω = 3.31 V rms
VOUT = 2.354 V
Table 8. Dynamic Power Dissipation of Downstream
Transmission
at each amplifier output, which yields a PD of 1.81 W.
PWDN1
PWDN0
PD (W)
1.454
1.262
1.142
0.120
MTPR
Through measurement, a DMT signal of 23.4 dBm requires
1.47 W of power to be dissipated by the AD8016. Figure 46
shows the results of calculation and actual measurements
detailing the relationship between the power dissipated by
the AD8016 vs. the total output power delivered to the back
termination resistors and the load combined. A 1:2 transformer
turns ratio was used in the calculations and measurements.
2.5
1
1
0
01
1
0
1
0
−78 dBc
−75.3 dBc
−57.2 dBc
N/A
1 This mode is quiescent power dissipation.
GENERATING DMT
At this time, DMT modulated waveforms are not typically
menu selectable items contained within arbitrary waveform
generators. Even using AWG software to generate DMT signals,
AWGs that are available today may not deliver DMT signals
sufficient in performance with regard to MTPR due to limita-
tions in the DAC and output drivers used by AWG manufacturers.
Similar to evaluating single-tone distortion performance of an
amplifier, MTPR evaluation requires a DMT signal generator
capable of delivering MTPR performance better than that of
the driver under evaluation.
2.0
CALCULATED
1.5
MEASURED
SINE
MEASURED
DMT
1.0
0.5
POWER DISSIPATION
To properly size the heat sinking area for the user’s application,
it is important to consider the total power dissipation of the
0
0
100
200
300
OUTPUT POWER (mW)
AD8016. The dc power dissipation for VIN = 0 V is IQ (VCC
VEE), or 2 × IQ × VS.
−
Figure 46. Power Dissipation vs. Output Power (Including Back
Terminations), See Figure 9 for Test Circuit
For the AD8016 powered on +12 V and −12 V supplies ( VS),
the number is 0.6 W. In a differential driver circuit (Figure 41),
one can use symmetry to simplify the computation for a dc
input signal.
VOUT
RL
PD = 2× IQ ×VS + 4 ×(VS −VOUT
)
where:
OUT is the peak output voltage of an amplifier.
V
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current is commutated during sourcing or
sinking current into the load. For a sine wave source, integra-
tion over a half cycle yields
2
4VOUTVS VOUT
PD = 2 × IQ ×VS + 2
−
π RL
RL
Rev. C | Page 17 of 20
AD8016
Data Sheet
THERMAL ENHANCEMENTS AND PCB LAYOUT
AIR FLOW TEST CONDITIONS
DUT Power
There are several ways to enhance the thermal capacity of the
CO solution. Additional thermal capacity can be created using
enhanced PCB layout techniques such as interlacing (some-
times referred to as stitching or interconnection) of the layers
immediately beneath the line driver. This technique serves to
increase the thermal mass or capacity of the PCB immediately
beneath the driver. The AD8016 in a TSSOP_EP (ARE model)
package can be designed to operate in the CO solution using
prudent measures to manage the power dissipation through
careful PCB design. The ARE package is available for use in
designing the highest density CO solutions. Maximum heat
transfer to the PCB can be accomplished using the ARE
package when the thermal slug is soldered to an exposed
copper pad directly beneath the AD8016. Optimum thermal
performance can be achieved in the ARE package only when
the back of the package is soldered to a PCB designed for
maximum thermal capacity (see Figure 48). Thermal experi-
ments with the ARE package were conducted without soldering
the heat slug to the PCB. Heat transfer was through physical
contact only. The following offers some insight into the AD8016
power dissipation and relative junction temperature, as well as
the effects of PCB size and composition on the junction-to-air
thermal resistance or θJA.
A typical DSL DMT signal produces about 1.5 W of power
dissipation in the AD8016 package. The fully biased (PWDN0
and PWDN1 = Logic 1) quiescent current of the AD8016 is
~25 mA. A 1 MHz differential sine wave at an amplitude of
8 V p-p/amplifier into an RLOAD of 100 Ω differential (50 Ω
per side) produces the 1.5 W of power typical in the AD8016
device. (See the Power Dissipation section for details.)
Thermal Resistance
The junction-to-case thermal resistance (θJC) of the AD8016
ARB or SOIC_W_BAT package is 8.6°C/W and for the AD8016
ARE or TSSOP_EP it is 5.6°C/W. These package specifications
were used in this study to determine junction temperature
based on the measured case temperature.
PCB Dimensions of a Differential Driver Circuit
Several components are required to support the AD8016 in a
differential driver circuit. The PCB area necessary for these
components (that is, feedback and gain resistors, ac-coupling
and decoupling capacitors, termination and load resistors)
dictated the area of the smallest PCB in this study, 4.7 square
inches. Further reduction in PCB area, although possible, has
consequences in terms of the maximum operating junction
temperature method of thermal enhancement.) A cooling fan
that draws moving air over the PCB and xDSL drivers, while
not always required, may be useful in reducing the operating
temperature.
THERMAL TESTING
A wind tunnel study was conducted to determine the relation-
ship between thermal capacity (that is, printed circuit board
copper area), air flow, and junction temperature. Junction-to-
ambient thermal resistance, θJA, was also calculated for the
AD8016 ARE and AD8016 ARB packages. The AD8016 was
operated in a noninverting differential driver configuration,
typical of an xDSL application yet isolated from any other
modem components. Testing was conducted using a 1 oz.
copper board in an ambient temperature of ~24°C over air
flows of 200, 150, 100, and 50 linear feet per minute (LFM)
(0.200 and 400 for AD8016 ARE) and for the ARB packages as
well as in still air. The 4-layer PCB was designed to maximize
the area of copper on the outer two layers of the board, while
the inner layers were used to configure the AD8016 in a
differential driver circuit. The PCB measured 3 inches ×
4 inches in the beginning of the study and was progressively
reduced in size to approximately 2 inches × 2 inches. The
testing was performed in a wind tunnel to control airflow
in units of LFM. The tunnel is approximately 11 inches in
diameter.
Rev. C | Page 18 of 20
Data Sheet
AD8016
35
30
25
20
EXPERIMENTAL RESULTS
ARB 0 LFM
The experimental data suggests that for both packages, and
a PCB as small as 4.7 square inches, reasonable junction
temperatures can be maintained even in the absence of air
flow. The graph in Figure 47 shows junction temperature vs.
airflow for various dimensions of 1 oz. copper PCBs at an
ambient temperature of 24°C in the ARB package. For the
worst-case package, the AD8016 ARB and the worst-case
PCB at 4.7 square inches, the extrapolated junction temperature
for an ambient environment of 85°C would be approximately
132°C with 0 LFM of airflow. If the target maximum junction
temperature of the AD8016 ARB is 125°C, a 4-layer PCB with
1 oz. copper covering the outer layers and measuring 9 square
inches is required with 0 LFM of air flow.
ARB 50 LFM
ARB 100 LFM
ARB 150 LFM
ARB 200 LFM
15
10
4
7
10
PCB AREA (SQ-IN)
Figure 48. Junction-to-Ambient Thermal Resistance vs. PCB Area
Note that the AD8016 ARE is targeted at xDSL applications
other than full-rate CO ADSL. The AD8016 ARE is targeted
at g.lite and other xDSL applications where reduced power
dissipation can be achieved through a reduction in output
power. Extreme temperatures associated with full-rate ADSL
using the AD8016 ARE should be avoided whenever possible.
75
50
45
40
35
30
25
ARE 0 LFM
ARE 200 LFM
+24°C AMBIENT
ARB 4.7 SQ-IN
ARB 6 SQ-IN
70
65
60
55
50
45
40
ARE 400 LFM
20
15
ARB 7.125 SQ-IN
ARB 9 SQ-IN
10
0
1
2
3
4
5
6
7
8
9
10
PCB AREA (SQ-IN)
Figure 49. Junction-to-Ambient Thermal Resistance vs. PCB Area
0
50
100
150
200
AIR FLOW (LFM)
Figure 47. Junction Temperature vs. Air Flow
Rev. C | Page 19 of 20
AD8016
Data Sheet
OUTLINE DIMENSIONS
15.60
15.20
24
1
13
12
7.60
7.40
10.65
10.00
PIN 1
0.75
0.25
45°
2.65
2.35
8°
0°
0.30
0.10
0.32
0.23
1.27
BSC
0.51
0.33
1.27
0.40
SEATING
PLANE
COMPLIANT WITH JEDEC STANDARDS MS-013-AD
Figure 50. 24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC_W_BAT]
(RB-24)
Dimensions shown in millimeters
9.80
9.70
9.60
3.55
3.50
3.45
15
14
28
3.05
3.00
2.95
4.50
4.40
4.30
EXPOSED
PAD
(Pins Up)
6.40
BSC
1
TOP VIEW
BOTTOM VIEW
1.05
1.00
0.80
1.20 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
8°
0°
0.20
0.09
0.15
0.05
0.65 BSC
0.30
0.19
0.75
0.60
0.45
SEATING
PLANE
COPLANARITY
0.10
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-153-AET
Figure 51. 28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-28-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8016ARBZ
AD8016ARBZ-REEL
AD8016AREZ
AD8016AREZ-REEL
AD8016AREZ-REEL7
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead SOIC_W_BAT
24-Lead SOIC_W_BAT
28-Lead TSSOP_EP
28-Lead TSSOP_EP
28-Lead TSSOP_EP
Package Option
RB-24
RB-24
RE-28-1
RE-28-1
RE-28-1
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01019-0-3/12(C)
Rev. C | Page 20 of 20
相关型号：
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IC DUAL OP-AMP, 3000 uV OFFSET-MAX, PDSO20, PLASTIC, SOP3-20, Operational Amplifier
ADI
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