AD8021ARM-REEL7 [ADI]
Low Noise, High Speed Amplifier for 16-Bit Systems; 低噪声，高速放大器，用于16位系统
| 型号： | AD8021ARM-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Noise, High Speed Amplifier for 16-Bit Systems |
| 文件： | 总20页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, High Speed Amplifier
for 16-Bit Systems
AD8021
FEATURES
CONNECTION DIAGRAM
Low Noise
SOIC-8 (R-8)
MSOP-8 (RM-8)
2.1 nV/√Hz Input Voltage Noise
2.1 pA/√Hz Input Current Noise
Custom Compensation
Constant Bandwidth from G = –1 to G = –10
High Speed
200 MHz (G = –1)
190 MHz (G = –10)
Low Power
AD8021
LOGIC
1
2
3
4
8
7
6
5
DISABLE
REFERENCE
+V
S
–IN
V
+IN
OUT
–V
S
C
COMP
34 mW or 6.7 mA Typ for 5 V Supply
Output Disable Feature, 1.3 mA
Low Distortion
–93 dB Second Harmonic, fC = 1 MHz
–108 dB Third Harmonic, fC = 1 MHz
DC Precision
1 mV Max Input Offset Voltage
0.5 ꢀV/ꢁC Input Offset Voltage Drift
Wide Supply Range, 5 V to 24 V
Low Price
The AD8021 allows the user to choose the gain bandwidth
product that best suits the application. With a single capacitor,
the user can compensate the AD8021 for the desired gain with
little trade-off in bandwidth. The AD8021 is a very well behaved
amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast
overload recovery of 50 ns.
Small Packaging
Available in SOIC-8 and MSOP-8
The AD8021 is stable over temperature with low input offset
voltage drift and input bias current drift, 0.5 µV/°C and 10 nA/°C,
respectively. The AD8021 is also capable of driving a 75 Ω line
with 3 V video signals.
APPLICATIONS
ADC Preamp and Driver
Instrumentation Preamp
Active Filters
Portable Instrumentation
Line Receivers
Precision Instruments
Ultrasound Signal Processing
High Gain Circuits
The AD8021 is not only technically superior, but also priced
considerably less than comparable amps drawing much higher
quiescent current. The AD8021 is a high speed, general-purpose
amplifier, ideal for a wide variety of gain configurations, and can
be used throughout a signal processing chain and in control loops.
The AD8021 is available in both standard 8-lead SOIC and MSOP
packages in the industrial temperature range of –40°C to +85°C.
24
V
= 50mV p-p
OUT
21
18
15
12
9
PRODUCT DESCRIPTION
G = –10, R = 1kꢂ, R = 100ꢂ,
F
G
The AD8021 is a very high performance, high speed voltage
feedback amplifier that can be used in 16-bit resolution systems.
It is designed to have low voltage and current noise (2.1 nV/√Hz
typ and 2.1 pA/√Hz typ) while operating at the lowest quiescent
supply current (7 mA @ 5 V) among today’s high speed, low
noise op amps. The AD8021 operates over a wide range of
supply voltages from 2.5 V to 12 V, as well as from single
5 V supplies, making it ideal for high speed, low power instru-
ments. An output disable pin allows further reduction of the
quiescent supply current to 1.3 mA.
R
= 100ꢂ, C = 0pF
IN
C
G = –5, R = 1kꢂ, R = 200ꢂ,
F
G
R
= 66.5ꢂ, C = 1.5pF
IN
C
6
G = –2, R = 499ꢂ, R = 249ꢂ,
F
G
R
= 63.4ꢂ, C = 4pF
3
IN
C
0
G = –1, R = 499ꢂ, R = 499ꢂ,
F
G
R
= 56.2ꢂ, C = 7pF
–3
–6
IN
C
0.1M
1M
10M
FREQUENCY – Hz
100M
1G
Figure 1. Small Signal Frequency Response
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8021–SPECIFICATIONS
(@ TA = 25ꢁC, VS = 5 V, RL = 1 kꢂ, Gain = +2, unless otherwise noted.)
VS = ꢃ5 V
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
355
160
150
110
95
120
250
380
490
205
185
150
120
150
300
420
23
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
VO = 1 V Step, RL = 500 Ω
2.5 V Input Step, G = +2
50
ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
–93
–108
dBc
dBc
f = 5 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
–70
–80
2.1
2.1
0.03
dBc
dBc
nV/√Hz
pA/√Hz
%
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
2.6
0.04
Degrees
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
0.4
0.5
7.5
10
0.1
86
1.0
mV
TMIN to TMAX
+Input or –Input
µV/°C
10.5
0.5
µA
nA/°C
µA
82
dB
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
1
MΩ
pF
V
–4.1 to +4.6
–98
VCM
=
4 V
–86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
–3.5 to +3.2 –3.8 to +3.4
V
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p
60
75
15/120
mA
mA
pF
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
f = 10 MHz
–40
45
50
1.75/1.90
70
2
30
33
dB
ns
ns
VO = 0 V to 2 V, 50% Logic to 50% Output
VO = 0 V to 2 V, 50% Logic to 50% Output
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
V
µA
µA
µA
µA
Disabled Leakage Current
DISABLE = 0.4 V
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
12.0
7.7
1.6
V
Output Enabled
Output Disabled
VCC = +4 V to +6 V, VEE = –5 V
VCC = +5 V, VEE = –6 V to –4 V
7.0
1.3
–95
–95
mA
mA
dB
dB
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
–86
–86
Specifications subject to change without notice.
–2–
REV. D
AD8021
(@ T = 25؇C, R = 1 k⍀, Gain = +2, unless otherwise noted.)
VS = ؎12 V
A
L
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
520
175
170
125
105
140
265
400
560
220
200
165
130
170
340
460
21
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
Slew Rate, 1 V Step
Settling Time to 0.01%
Overload Recovery (50%)
VO = 1 V Step, RL = 500 Ω
6 V Input Step, G = +2
90
ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
–95
–116
dBc
dBc
f = 5 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
f = 50 kHz
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
–71
–83
2.1
2.1
0.03
0.04
dBc
dBc
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
2.6
nV/√Hz
pA/√Hz
%
Degrees
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
0.4
0.2
8
10
0.1
88
1.0
mV
TMIN to TMAX
+Input or –Input
µV/°C
11.3
0.5
µA
nA/°C
µA
84
dB
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
1
MΩ
pF
V
–11.1 to +11.6
–96
VCM
=
10 V
–86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
–10.2 to +9.8 –10.6 to +10.2
V
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p
70
115
15/120
mA
mA
pF
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
f = 10 MHz
–40
45
50
1.80/1.95
70
2
30
33
dB
ns
ns
VO = 0 V to 2 V, 50% Logic to 50% Output
VO = 0 V to 2 V, 50% Logic to 50% Output
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
V
µA
µA
µA
µA
Disabled Leakage Current
DISABLE= 0.4 V
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
7.8
1.7
–96
12.0
8.6
2.0
V
Output Enabled
Output Disabled
VCC = +11 V to +13 V, VEE = –12 V
VCC = +12 V, VEE = –13 V to –11 V
mA
mA
dB
dB
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
–86
–86
–100
Specifications subject to change without notice.
REV. D
–3–
AD8021
(@ TA = 25ꢁC, RL = 1 kꢂ, Gain = +2, unless otherwise noted.)
VS = 5 V
AD8021AR/AD8021ARM
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, CC = 10 pF, VO = 0.05 V p-p
G = +2, CC = 7 pF, VO = 0.05 V p-p
G = +5, CC = 2 pF, VO = 0.05 V p-p
G = +10, CC = 0 pF, VO = 0.05 V p-p
G = +1, CC = 10 pF
G = +2, CC = 7 pF
G = +5, CC = 2 pF
G = +10, CC = 0 pF
270
155
135
95
305
190
165
130
110
140
280
390
28
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ns
Slew Rate, 1 V Step
80
110
210
290
Settling Time to 0.01%
Overload Recovery (50%)
VO = 1 V Step, RL = 500 Ω
0 V to 2.5 V Input Step, G = +2
40
ns
DISTORTION/NOISE PERFORMANCE
f = 1 MHz
HD2
HD3
VO = 2 V p-p
VO = 2 V p-p
–84
–91
dBc
dBc
f = 5 MHz
HD2
HD3
Input Voltage Noise
Input Current Noise
VO = 2 V p-p
VO = 2 V p-p
f = 50 kHz
–68
–81
2.1
2.1
dBc
dBc
nV/√Hz
pA/√Hz
2.6
f = 50 kHz
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
0.4
0.8
7.5
10
0.1
76
1.0
mV
TMIN to TMAX
+Input or –Input
µV/°C
10.3
0.5
µA
nA/°C
µA
72
dB
INPUT CHARACTERISTICS
Input Resistance
Common-Mode Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
10
1
0.9 to 4.6
–98
MΩ
pF
V
1.5 V to 3.5 V
–84
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
1.25 to 3.38
1.10 to 3.60
V
Linear Output Current
Short-Circuit Current
Capacitive Load Drive for 30% Overshoot VO = 50 mV p-p/1 V p-p
30
50
10/120
mA
mA
pF
DISABLE CHARACTERISTICS
Off Isolation
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off/On
Enabled Leakage Current
f = 10 MHz
–40
45
50
1.55/1.70
70
2
30
33
dB
ns
ns
VO = 0 V to 1 V, 50% Logic to 50% Output
VO = 0 V to 1 V, 50% Logic to 50% Output
VDISABLE – VLOGIC REFERENCE
Logic Ref = 0.4 V
DISABLE = 4.0 V
Logic Ref = 0.4 V
V
µA
µA
µA
µA
Disabled Leakage Current
DISABLE = 0.4 V
POWER SUPPLY
Operating Range
Quiescent Current
2.25
5
12.0
7.5
1.5
V
Output Enabled
Output Disabled
VCC = 4.5 V to 5.5 V, VEE = 0 V
VCC = +5 V, VEE = –0.5 V to +0.5 V
6.7
1.2
–82
–84
mA
mA
dB
dB
+Power Supply Rejection Ratio
–Power Supply Rejection Ratio
–74
–76
Specifications subject to change without notice.
–4–
REV. 0
AD8021
ABSOLUTE MAXIMUM RATINGS1
2.0
1.5
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . Observed Power Derating Curves
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . ±VS ± 1 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±0.8 V
Differential Input Current . . . . . . . . . . . . . . . . . . . . . ±10 mA
Output Short-Circuit Duration
8-LEAD SOIC
1.0
. . . . . . . . . . . . . . . . . . . . . . Observed Power Derating Curves
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +125∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300∞C
8-LEAD MSOP
0.5
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 The AD8021 inputs are protected by diodes. Current-limiting resistors are not
used in order to preserve the low noise. If a differential input exceeds ±0.8 V, the
input current should be limited to ±10 mA.
0.01
–55 –45 –35 –25 –15 –5
5 15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (؇C)
Figure 2. Maximum Power Dissipation vs. Temperature*
*Specification is for device in free air:
8-Lead SOIC: JA = 125∞C/W
8-Lead MSOP: JA = 145∞C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8021
is limited by the associated rise in junction temperature. The maxi-
mum safe junction temperature for plastic encapsulated devices
is determined by the glass transition temperature of the plastic,
approximately 150∞C. Temporarily exceeding this limit may cause
a shift in parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding a junction tempera-
ture of 175∞C for an extended period can result in device failure.
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1
LOGIC REFERENCE Reference for Pin 8* Voltage
Level. Connect to logic low
supply.
2
3
4
5
–IN
+IN
–VS
Inverting Input
Noninverting Input
Negative Supply Voltage
Compensation Capacitor. Tie
to –VS. (See the Applications
section for value.)
While the AD8021 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (150∞C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves.
CCOMP
6
7
8
VOUT
Output
Positive Supply Voltage
Disable, Active Low*
+VS
DISABLE
PIN CONFIGURATION
*When Pin 8 (DISABLE) is about 2 V or more higher than Pin 1 (LOGIC
REFERENCE), the part is enabled. When Pin 8 is brought down to within about
1.5 V of Pin 1, the part is disabled. (See the Specification tables for exact disable and
enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied
to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alterna-
tively, if Pin 1 and Pin 8 are not connected, the part will be in an enabled state.
AD8021
LOGIC
1
2
3
4
8
7
6
5
DISABLE
REFERENCE
+V
S
–IN
V
+IN
OUT
C
–V
S
COMP
ORDERING GUIDE
Model
AD8021AR
AD8021AR-REEL
AD8021AR-REEL7
AD8021ARM
AD8021ARM-REEL
AD8021ARM-REEL7
AD8021ARZ*
AD8021ARZ-REEL*
AD8021ARZ-REEL7*
Temperature Range
Package Description
Package Outline
Branding
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
HNA
HNA
HNA
R-8
R-8
*Z = Lead Free
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8021 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. D
–5–
AD8021–Typical Performance Characteristics
(TA = 25ЊC, VS = ꢃ5 V, RL = 1 kꢂ, G = +2, RF = RG = 499 ꢂ, RS = 49.9 ꢂ, RO = 976 ꢂ, RD = 53.6 ꢂ, CC = 7 pF, CL = 0, CF = 0, VOUT = 2 V p-p,
Freq = 1 MHz, unless otherwise noted.)
24
21
18
15
12
9
9
8
G = 2
G = 10, R = 1kꢂ, R = 110ꢂ, C = 0pF
V
= ꢃ2.5V
F
G
C
S
ꢃ5V
7
G = 5, R = 1kꢂ, R = 249ꢂ, C = 2pF
F
G
C
6
5
4
G = 2, R = R = 499ꢂ, C = 7pF
F
G
C
ꢃ12V
6
3
3
2
V
= ꢃ2.5V
G = 1, R = 75ꢂ, C = 10pF
S
F
C
0
1
–3
0
–6
0.1M
–1
1M
10M
100M
1G
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
TPC 4. Small Signal Frequency Response vs.
Frequency and Supply, VOUT = 50 mV p-p,
Noninverting. See Test Circuit 1.
TPC 1. Small Signal Frequency Response vs.
Frequency and Gain, VOUT = 50 mV p-p,
Noninverting. See Test Circuit 1.
24
3
G = –1
V
= ꢃ2.5V
S
21
2
1
G = –10, R = 1kꢂ, R = 100ꢂ,
ꢃ5V
F
G
18
15
12
9
R
= 100ꢂ, C = 0pF
IN
C
0
V
= ꢃ12V
G = –5, R = 1kꢂ, R = 200ꢂ,
S
F
G
–1
–2
–3
–4
–5
–6
–7
R
= 66.5ꢂ, C = 1.5pF
IN
C
6
G = –2, R = 499ꢂ, R = 249ꢂ,
F
G
R
= 63.4ꢂ, C = 4pF
3
IN
C
0
G = –1, R = 499ꢂ, R = 499ꢂ,
V
= ꢃ2.5V
F
G
S
R
= 56.2ꢂ, C = 7pF
–3
–6
IN
C
1M
10M
100M
1G
0.1M
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
TPC 5. Small Signal Frequency Response vs.
Frequency and Supply, VOUT = 50 mV p-p,
Inverting. See Test Circuit 3.
TPC 2. Small Signal Frequency Response
vs. Frequency and Gain, VOUT = 50 mV p-p,
Inverting. See Test Circuit 1.
9
9
G = 2
8
C
= 5pF
G = 2
C
8
7
6
5
4
3
2
1
0
7
V
= 0.1V AND 50mV p-p
7pF
OUT
6
5
9pF
4
V
= 4V p-p
1V p-p
OUT
3
2
7pF
9pF
1
0
–1
–1
1M
10M
100M
1G
0.1M
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 6. Frequency Response vs. Frequency
and VOUT, Noninverting. See Test Circuit 1.
TPC 3. Small Signal Frequency Response vs.
Frequency and Compensation Capacitor,
VOUT = 50 mV p-p. See Test Circuit 1.
–6–
REV. D
AD8021
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
= 1kꢂ
G = 2
= R
G = 2
F
R
F
G
R
= 499ꢂ
F
R
= 250ꢂ
F
1kꢂ
R
= 150ꢂ
F
R
= 100ꢂ
L
R
= 75ꢂ
F
R
= 1kꢂ AND C = 2.2pF
F
F
0.1M
1M
10M
100M
1G
1M
10M
FREQUENCY – Hz
100M
1G
0.1M
FREQUENCY – Hz
TPC 7. Large Signal Frequency Response vs.
Frequency and Load, Noninverting. See Test
Circuit 2.
TPC 10. Small Signal Frequency Response vs.
Frequency and RF, Noninverting, VOUT = 50 mV p-p.
See Test Circuit 1.
9
15
+85ꢁC
G = 2
G = 2
12
8
+25ꢁC
7
9
6
3
6
–40ꢁC
5
4
3
2
1
0
V
=
OUT
R
= 49.9ꢂ
+85ꢁC
50mV p-p
S
0
–3
V
=
OUT
2V p-p
R
= 100ꢂ
–6
S
+25ꢁC
–40ꢁC
–9
R
= 249ꢂ
S
–12
–1
–15
0.1M
1M
10M
100M
1G
1M
10M
FREQUENCY – Hz
100M
1G
FREQUENCY – Hz
TPC 8. Frequency Response vs. Frequency,
Temperature and VOUT, Noninverting.
See Test Circuit 1.
TPC 11. Small Signal Frequency Response vs.
Frequency and RS, Noninverting, VOUT = 50 mV p-p.
See Test Circuit 1.
100
90
18
50pF
G = 2
15
12
9
30pF
80
20pF
10pF
70
60
50
40
30
20
10
0
180
135
90
6
3
0pF
45
0
0
–3
–6
–9
–12
–45
–90
–135
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 9. Small Signal Frequency Response vs.
Frequency and Capacitive Load, Noninverting,
VOUT = 50 mV p-p. See Test Circuit 2 and Figure 16.
TPC 12. Open-Loop Gain and Phase vs.
Frequency, RG =100 Ω, RF = 1 kΩ, RO = 976 Ω,
RD = 53.6 Ω, CC = 0 pF. See Test Circuit 3.
REV. D
–7–
AD8021
–20
–30
6.4
G = 2
–40
6.2
6.0
5.8
5.6
5.4
V
= ꢃ2.5V
f1
f2
S
–50
ꢄf = 0.2MHz
P
OUT
–60
976ꢂ
–70
ꢃ5V
53.6ꢂ
50ꢂ
–80
ꢃ12V
–90
–100
–110
–120
1M
10M
FREQUENCY – Hz
100M
9.5
9.7
10.0
FREQUENCY – MHz
10.3
10.5
TPC 13. 0.1 dB Flatness vs. Frequency and
TPC 16. Intermodulation Distortion vs. Frequency
Supply, VOUT = 1 V p-p, RL = 150 Ω, Noninverting.
See Test Circuit 2.
–20
–30
–40
50
45
40
SECOND
–50
–60
–70
V
= ꢃ5V
S
35
30
25
20
R
= 100ꢂ
L
–80
V
= ꢃ2.5V
S
R
= 1kꢂ
L
–90
–100
–110
–120
–130
THIRD
0.1M
1M
FREQUENCY – Hz
10M
20M
0
5
10
FREQUENCY – MHz
15
20
TPC 14. Second and Third Harmonic Distortion
vs. Frequency and RL
TPC 17. Third-Order Intercept vs. Frequency and
Supply Voltage
–30
–40
–50
–60
–50
–60
–70
SECOND
–70
–80
THIRD
–80
–90
R
= 100ꢂ
L
SECOND
V
= ꢃ2.5V
S
THIRD
–90
SECOND
SECOND
–100
–110
–120
–130
–100
–110
–120
V
= ꢃ5V
R
= 1kꢂ
S
L
V
= ꢃ12V
S
SECOND
THIRD
THIRD
100k
1M
FREQUENCY – Hz
10M
20M
1
2
3
V
4
5
6
–V p-p
OUT
TPC 15. Second and Third Harmonic Distortion
vs. Frequency and VS
TPC 18. Second and Third Harmonic Distortion
vs. VOUT and RL
REV. D
–8–
AD8021
–50
–60
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
–3.1
–3.2
–3.3
–3.4
–3.5
–3.6
–3.7
–3.8
POSITIVE OUTPUT
SECOND
fC = 5MHz
–70
–80
THIRD
–90
SECOND
fC = 1MHz
–100
–110
–120
NEGATIVE OUTPUT
THIRD
2
1
3
4
5
6
0
400
800
1200
1600
2000
V
–V p-p
LOAD –ꢂ
OUT
TPC 22. DC Output Voltage vs. Load. See Test
Circuit 1.
TPC 19. Second and Third Harmonic Distortion
vs. VOUT and Fundamental Frequency (fC), G = +2
120
–40
V
= ꢃ12
–50
S
100
80
fC = 5MHz
–60
SECOND
V
= ꢃ5.0
= ꢃ2.5
S
–70
60
THIRD
V
S
–80
SECOND
40
20
0
–90
fC = 1MHz
THIRD
–100
–110
–50
–30
–10
10
30
50
70
90
110
1
2
3
4
5
6
TEMPERATURE – ꢁC
V
–V p-p
OUT
TPC 23. Short-Circuit Current to Ground vs.
Temperature
TPC 20. Second and Third Harmonic Distortion
vs. VOUT and Fundamental Frequency (fC), G = +10
50
–70
G = 2
40
fC = 1MHz
R
= 1kꢂ
L
R
= 1kꢂ, 150ꢂ
L
30
20
10
–80
–90
SECOND
THIRD
600
–10
–20
–30
–40
–50
–100
–110
–120
0
200
400
800
1000
0
40
80
120
TIME – ns
160
200
FEEDBACK RESISTANCE –ꢂ
TPC 21. Second and Third Harmonic Distortion
vs. Feedback Resistor (RF)
TPC 24. Small Signal Transient Response vs. RL,
VO = 50 mV p-p. See Test Circuit 2, Noninverting.
REV. D
–9–
AD8021
V
G = 2
= 4V p-p
V
G = 2
= 2V p-p
O
O
2.0
2.0
1.0
R
= 1kꢂ
L
1.0
R
= 150ꢂ
V
= ꢃ2.5V
L
S
–1.0
–1.0
–2.0
V
= ꢃ5V
S
–2.0
0
0
40
80
120
TIME – ns
160
200
40
80
120
TIME – ns
160
200
TPC 28. Large Signal Transient Response vs. VS.
See Test Circuit 1.
TPC 25. Large Signal Transient Response vs. RL.
See Test Circuit 2, Noninverting.
5
V
= ꢃ3V
IN
G = +2
V
= 4V p-p
O
G = –1
4
3
2
1
V
R = 1kꢂ
L
V
V
= 1V/DIV
= 2V/DIV
OUT,
IN
OUT
V
IN
R
= 150ꢂ
L
–1
–2
–3
–4
–5
V
OUT
V
IN
0
100
200
300
400
500
0
50
100
150
200
250
TIME – ns
TIME – ns
TPC 29. Overdrive Recovery vs. RL. See Test Circuit 2.
TPC 26. Large Signal Transient Response.
See Test Circuit 3, Inverting.
C
G = 2
= 50pF
V
= 4V p-p
L
O
G = 2
2.0
1.0
C
= 10pF, 0pF
L
+0.01%
–0.01%
25ns
–1.0
–2.0
VERT = 0.2mV/DIV
HOR = 5ns/DIV
0
40
80
120
TIME – ns
160
200
TPC 30. 0.01% Settling Time, 2 V Step
TPC 27. Large Signal Transient Response vs. CL.
See Test Circuit 1.
REV. D
–10–
AD8021
100
80
100
60
40
PULSEWIDTH = 120ns
20
0
10
–20
–40
–60
–80
–100
PULSEWIDTH = 300ꢀs
5V
0V
t1
1
10
0
4
8
12
16
20
24
28
32
100
1k
10k
100k
1M
10M
TIME – ꢀs
FREQUENCY – Hz
TPC 31. Long-Term Settling, 0 V to 5 V, VS = 12 V, G = +13
TPC 34. Input Current Noise vs. Frequency
50
0.48
G = ꢅ1
40
0.44
0.40
0.36
0.32
0.28
0.24
30
20
10
–10
–20
–30
–40
–50
–50
–25
0
25
50
75
100
0
40
80
120
TIME – ns
160
200
TEMPERATURE – ꢁC
TPC 32. Small Signal Transient Response,
VO = 50 mV p-p. G = +1. See Test Circuit 1.
TPC 35. VOS vs. Temperature
100
8.4
8.0
7.6
7.2
6.8
6.4
6.0
10
2.1nV/ Hz
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
–50
–25
0
25
50
75
100
TEMPERATURE – ꢁC
TPC 33. Input Voltage Noise vs. Frequency
TPC 36. Input Bias Current vs. Temperature
REV. D
–11–
AD8021
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–120
10k
–100
0.1M
100k
1M
10M
100M
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 37. CMRR vs. Frequency. See Test Circuit 4.
TPC 40. Input to Output Isolation, Chip Disabled.
See Test Circuit 7.
300
100
30
300k
100k
30k
10k
3k
10
3
1k
1
300
100
30
0.3
0.1
0.03
0.01
0.003
10
3
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 38. Output Impedance vs. Frequency, Chip
Enabled. See Test Circuit 5.
TPC 41. Output Impedance vs. Frequency, Chip
Disabled. See Test Circuit 8.
0
DISABLE
4V
–10
2V
–PSRR
–20
–30
–40
V
OUTPUT
V
= ꢃ2.5V
+PSRR
= ꢃ12V
S
2V
–50
–60
V
S
tEN = 45ns
1V
–70
tDIS = 50ns
V
= ꢃ5V
S
–80
–90
–100
0
100
200
300
400
500
10k
100k
1M
10M
100M
500M
TIME – ns
FREQUENCY – Hz
TPC 39. Enable (tEN)/Disable (tDIS) Time vs. VOUT
See Test Circuit 6.
.
TPC 42. PSRR vs. Frequency and Supply Voltage.
See Test Circuits 9 and 10.
REV. D
–12–
AD8021
8.5
8.0
7.5
7.0
6.5
6.0
5.5
–50
–25
0
25
50
75
100
TEMPERATURE – ꢁC
TPC 43. Quiescent Supply Current vs. Temperature
HP8753D
Test Circuits
NETWORK
ANALYZER
50ꢂ
50ꢂ
AD8021
+V
C
S
49.9ꢂ
50ꢂ CABLE
50ꢂ
+V
R
S
S
499ꢂ
50ꢂ CABLE
R
O
499ꢂ
5
5
R
C
IN
C
C
R
49.9ꢂ
D
–V
S
7pF
–V
S
R
C
F
R
G
499ꢂ
499ꢂ
55.6ꢂ
F
Test Circuit 1. Noninverting Gain
Test Circuit 4. CMRR
FET
PROBE
AD8021
HP8753D
+V
S
+V
S
NETWORK
ANALYZER
50ꢂ CABLE
R
S
50ꢂ
100ꢂ
5
50ꢂ
5
C
L
C
C
R
49.9ꢂ
IN
R
L
7pF
C
–V
C
S
–V
S
R
R
F
G
R
499ꢂ
R
499ꢂ
G
F
C
F
Test Circuit 2. Noninverting Gain with FET Probe
Test Circuit 5. Output Impedance, Chip Enabled
AD8021
+V
S
+V
S
49.9ꢂ
50ꢂ CABLE
R
O
1
976ꢂ
49.9ꢂ
1.0V
LOGIC REF
49.9ꢂ
5
C
C
DISABLE
8
53.6ꢂ
5
R
D
C
C
–V
S
4V
49.9ꢂ
50ꢂ CABLE
–V
S
7pF
50ꢂ
R
R
F
G
R
49.9ꢂ
IN
499ꢂ
499ꢂ
Test Circuit 3. Inverting Gain
Test Circuit 6. Enable/Disable
REV. D
–13–
AD8021
BIAS
BNC
HP8753D
NETWORK
ANALYZER
HP8753D
NETWORK
ANALYZER
50ꢂ
50ꢂ
+V
S
50ꢂ
+V
50ꢂ
50ꢂ CABLE
50ꢂ CABLE
S
49.9ꢂ, 5W
49.9ꢂ
+V
AD8021
5
S
FET
PROBE
1
8
976ꢂ
49.9ꢂ
LOGIC REF
249ꢂ
5
DISABLE
53.6ꢂ
1kꢂ
C
7pF
C
–V
C
7pF
S
C
–V
S
499ꢂ
499ꢂ
499ꢂ
499ꢂ
Test Circuit 7. Input to Output Isolation, Chip Disabled
Test Circuit 9. Positive PSRR
BIAS
BNC
HP8753D
NETWORK
ANALYZER
50ꢂ
50ꢂ
–V
S
50ꢂ CABLE
+V
S
976ꢂ
249ꢂ
5
53.6ꢂ
HP8753D
AD8021
1
NETWORK
ANALYZER
+V
C
7pF
S
C
8
–V
S
49.9ꢂ
5W
100ꢂ
50ꢂ
5
C
7pF
C
499ꢂ
499ꢂ
–V
S
Test Circuit 8. Output Impedance, Chip Disabled
Test Circuit 10. Negative PSRR
REV. D
–14–
AD8021
APPLICATIONS
bandwidth is degraded to about 20 MHz and the phase margin
increases to 90° (Arrow B). However, by reducing CC to zero,
the bandwidth and phase margin return to about 200 MHz and
60° (Arrow C), respectively. In addition, the slew rate is dra-
matically increased, as it roughly varies with the inverse of CC.
The typical voltage feedback op amp is frequency stabilized with
a fixed internal capacitor, CINTERNAL, using dominant pole compen-
sation. To a first-order approximation, voltage feedback op amps
have a fixed gain bandwidth product. For example, if its –3 dB
bandwidth for G = +1 is 200 MHz, at a gain of G = +10 its
bandwidth will be only about 20 MHz. The AD8021 is a voltage
feedback op amp with a minimal CINTERNAL of about 1.5 pF. By
adding an external compensation capacitor, CC, the user can
circumvent the fixed gain bandwidth limitation of other voltage
feedback op amps.
10
9
8
7
6
5
4
3
2
1
0
Unlike the typical op amp with fixed compensation, the AD8021
allows the user to
1. Maximize the amplifier bandwidth for closed-loop gains
between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.
2. Optimize the trade-off between bandwidth and phase
margin for a particular application.
1
2
3
4
5
6
7
8
9
10
11
3. Match bandwidth in gain blocks with different noise gains,
such as when designing differential amplifiers (as shown in
Figure 10).
NOISE GAIN –V/V
Figure 4. Suggested Compensation Capacitance
vs. Gain for Maintaining 1 dB Peaking
110
100
180
135
90
Table I and Figure 4 provide recommended values of compensa-
tion capacitance at various gains and the corresponding slew rate,
bandwidth, and noise. Note that the value of the compensation
capacitor depends on the circuit noise gain, not the voltage gain.
As shown in Figure 5, the noise gain, GN, of an op amp gain block
is equal to its noninverting voltage gain, regardless of whether
it is actually used for inverting or noninverting gain. Thus,
90
86
80
(A)
(C)
45
(B)
= 0pF
C
C
70
60
50
40
30
20
10
0
0
C
= 10pF
C
(C)
Noninverting GN = RF / RG +1
Inverting GN = RF / RG +1
(B)
(A)
R
200ꢂ
R
F
800ꢂ
G
–10
1k
3
R
S
10k
100k
1M
10M
100M
1G
10G
+
–
1
FREQUENCY – Hz
2
3
6
–
+
AD8021
Figure 3. Simplified Diagram of Open-Loop Gain
and Phase Response
6
5
AD8021
2
R
800ꢂ
5
F
–V
S
Figure 3 is the AD8021 gain and phase plot that has been sim-
plified for instructional purposes. If the desired closed-loop gain
is G = +1 and CC = 10 pF is chosen, Arrow A of the figure
shows that the bandwidth is about 200 MHz and the phase
margin is about 60°. If the gain is changed to G = +10 and CC
is fixed at 10 pF, then (as expected for a typical op amp) the
G = –4
= 5
–V
S
G
C
N
COMP
C
G = G = 5
R
G
200ꢂ
COMP
N
NONINVERTING
INVERTING
Figure 5. The Noise Gain of Both Is 5
Table I. Recommended Component Values. See Test Circuit 2. CF = CL = 0, RL = 1 kꢂ, RIN = 49.9 ꢂ
Noise Gain
(Noninverting
Gain)
Slew
CCOMP Rate
–3 dB
SS BW
(MHz)
Output Noise
(AD8021 Only)
Output Noise
(AD8021 with Resistors)
(nV/√Hz)
RS
(ꢂ)
RF
(ꢂ)
RG
(ꢂ)
(pF)
(V/ꢀs)
(nV/
√Hz)
1
75
75
NA
499
249
110
52.3
10
10
7
2
0
0
120
150
300
420
200
34
490
205
185
150
42
2.1
4.3
10.7
21.2
42.2
2.8
8.2
15.5
27.9
52.7
2
49.9
49.9
49.9
49.9
49.9
499
1 k
1 k
1 k
1 k
5
10
20
100
0
6
211.1
264.1
REV. D
–15–
AD8021
With the AD8021, a variety of trade-offs can be made to fine-tune
its dynamic performance. Sometimes more bandwidth or slew
rate is needed at a particular gain. Reducing the compensation
capacitance, as illustrated in TPC 3, will increase the bandwidth
and peaking due to a decrease in phase margin. On the other hand,
if more stability is needed, increasing the compensation cap will
decrease the bandwidth while increasing the phase margin.
this high impedance with a current gain of 5,000, so that the
AD8021 can maintain a high open-loop gain even when driving
heavy loads.
Two internal diode clamps across the inputs (Pins 2 and 3) protect
the input transistors from large voltages that could otherwise cause
emitter-base breakdown, which would result in degradation of
offset voltage and input bias current.
As with all high speed amplifiers, parasitic capacitance and induc-
tance around the amplifier can affect its dynamic response.
Often, the input capacitance (due to the op amp itself, as well
as the PC board) could have a significant effect. The feedback
resistance, together with the input capacitance, may contribute to
a loss of phase margin, thereby affecting the high frequency response,
as shown in TPC 10. Furthermore, a capacitor (CF) in parallel
with the feedback resistor can compensate for this phase loss.
+V
S
OUTPUT
+IN
Additionally, any resistance in series with the source will create
a pole with the input capacitance (as well as dampen high fre-
quency resonance due to package and board inductance and
capacitance), the effect of which is shown in TPC 11.
C
INTERNAL
1.5pF
–IN
–V
S
It must also be noted that increasing resistor values will increase
the overall noise of the amplifier, and that reducing the feedback
resistor value will increase the load on the output stage, thus
increasing distortion (TPC 18).
C
COMP
C
C
Figure 6. Simplified Schematic
Using the Disable Feature
When Pin 8 (DISABLE) is approximately 2 V or more higher than
Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8
is brought down to within about 1.5 V of Pin 1, the part is dis-
abled. See the Specification tables for exact disable and enable
voltage levels. If the disable feature is not going to be used, Pin 8
can be tied to VS or a logic high source, and Pin 1 can be tied to
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part will be in an enabled state.
PCB LAYOUT CONSIDERATIONS
As with all high speed op amps, achieving optimum performance
from the AD8021 requires careful attention to PC board layout.
Particular care must be exercised to minimize lead lengths
between the ground leads of the bypass capacitors and between
the compensation capacitor and the negative supply. Otherwise,
lead inductance can influence the frequency response and even
cause high frequency oscillations. Use of a multilayer printed
circuit board, with an internal ground plane, will reduce ground
noise and enable a compact component arrangement.
THEORY OF OPERATION
The AD8021 is fabricated on the second generation of Analog
Devices’ proprietary High Voltage eXtra-Fast Complementary
Bipolar (XFCB) process, which enables the construction of PNP
and NPN transistors with similar fTs in the 3 GHz region. The
transistors are dielectrically isolated from the substrate (and each
other), eliminating the parasitic and latch-up problems caused
by junction isolation. It also reduces nonlinear capacitance
(a source of distortion) and allows a higher transistor fT for a
given quiescent current. The supply current is trimmed, which
results in less part-to-part variation of bandwidth, slew rate,
distortion, and settling time.
Due to the relatively high impedance of Pin 5 and low values of
the compensation capacitor, a guard ring is recommended. The
guard ring is simply a PC trace that encircles Pin 5 and is
connected to the output, Pin 6, which is at the same potential as
Pin 5. This serves two functions. It shields Pin 5 from any local
circuit noise generated by surrounding circuitry. It also mini-
mizes stray capacitance, which would tend to otherwise reduce
the bandwidth. An example of a guard ring layout may be seen
in Figure 7.
Also shown in Figure 7, the compensation capacitor is located
immediately adjacent to the edge of the AD8021 package, spanning
Pin 4 and Pin 5. This capacitor must be a high quality surface-
mount COG or NPO ceramic. The use of leaded capacitors is not
recommended. The high frequency bypass capacitor(s) should
be located immediately adjacent to the supplies, Pins 4 and 7.
As shown in Figure 6, the AD8021 input stage consists of an NPN
differential pair in which each transistor operates at 0.8 mA collec-
tor current. This allows the input devices a high transconductance;
thus, the AD8021 has a low input noise of 2.1 nV/√Hz @ 50 kHz.
The input stage drives a folded cascode that consists of a pair of
PNP transistors. The folded cascode and current mirror provide
a differential to single-ended conversion of signal current. This
current then drives the high impedance node (Pin 5), where the
CC external capacitor is connected. The output stage preserves
To achieve the shortest possible lead length at the inverting
input, the feedback resistor RF is located beneath the board and
just spans the distance from the output, Pin 6, to inverting input
Pin 2. The return node of resistor RG should be situated as
closely as possible to the return node of the negative supply
bypass capacitor connected to Pin 4.
REV. D
–16–
AD8021
(TOPVIEW)
Table II. Summary of ADC Driver Performance,
fC = 65 kHz, VOUT = 10 V p-p
BYPASS
LOGIC REFERENCE
1
2
3
4
8
7
6
5
DISABLE
CAPACITOR
Parameter
Measurement Unit
+V
–IN
+IN
S
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
–101.3
–109.5
–100.0
100.3
dB
dB
dB
dB
V
OUT
GROUND
PLANE
–V
S
C
COMP
METAL
+12V
5V
BYPASS
CAPACITOR
50ꢂ
3
+
50ꢂ
COMPENSATION
CAPACITOR
6
IN
HI
AD8021
50ꢂ
5
2
–
C
GROUND
PLANE
C
AD7665
570kSPS
R
750ꢂ
F
–12V
Figure 7. Recommended Location of Critical
Components and Guard Ring
ADC
R
82.5ꢂ
G
OPTIONAL C
F
IN
LO
DRIVING 16-BIT ADCS
Low noise and adjustable compensation make the AD8021
especially suitable as a buffer/driver for high resolution analog-
to-digital converters.
Figure 9. Noninverting ADC Driver, Gain = 10, fC = 100 kHz
As seen in TPC 15, the harmonic distortion is better than 90 dB at
frequencies between 100 kHz and 1 MHz. This is a real advantage
for complex waveforms that contain high frequency information,
as the phase and gain integrity of the sampled waveform can be
preserved throughout the conversion process. The increase in
loop gain results in improved output regulation and lower noise
when the converter input changes state during a sample. This
advantage is particularly apparent when using 16-bit high resolu-
tion ADCs with high sampling rates.
Table III. Summary of ADC Driver Performance,
fC = 100 kHz, VOUT = 20 V p-p
Parameter
Measurement Unit
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
–92.6
–86.4
–84.4
5.4
dB
dB
dB
dB
Figure 8 shows a typical ADC driver configuration. The AD8021
is in an inverting gain of –7.5, fC is 65 kHz, and its output voltage
is 10 V p-p. The results are listed in Table II.
Figure 9 shows another ADC driver connection. The circuit was
tested with a noninverting gain of 10.1 and an output voltage of
approximately 20 V p-p for optimum resolution and noise per-
formance. No filtering was used. An FFT was performed using
Analog Devices’ evaluation software for the AD7665 16-bit
converter. The results are listed in Table III.
+12V
5V
3
+
6
IN
HI
AD8021
590ꢂ
DIFFERENTIAL DRIVER
5
2
–
C
C
The AD8021 is uniquely suited as a low noise differential driver
for many ADCs, balanced lines, and other applications requiring
differential drive. If pairs of internally compensated op amps are
configured as inverter and follower, the noise gain of the inverter
will be higher than that of the follower section, resulting in an
imbalance in the frequency response (see Figure 11).
10pF
AD7665
570kSPS
R
200ꢂ
G
–12V
50ꢂ
R
F
65kHz
1.5kꢂ
56pF
IN
LO
A better solution takes advantage of the external compensation
feature of the AD8021. By reducing the CCOMP value of the inverter,
its bandwidth may be increased to match that of the follower,
avoiding compromises in gain bandwidth and phase delay. The
inverting and noninverting bandwidths can be closely matched
using the compensation feature, thus minimizing distortion.
Figure 8. Inverting ADC Driver, Gain = –7.5, fC = 65 kHz
REV. D
–17–
AD8021
Figure 10 illustrates an inverter-follower driver circuit operating
at a gain of 2, using individually compensated AD8021s. The
values of feedback and load resistors were selected to provide a
total load of less than 1 kΩ, and the equivalent resistances seen
at each op amp’s inputs were matched to minimize offset volt-
age and drift. Figure 12 is a plot of the resulting ac responses of
driver halves.
USING THE AD8021 IN ACTIVE FILTERS
The low noise and high gain bandwidth of the AD8021 make it an
excellent choice in active filter circuits. Most active filter litera-
ture provides resistor and capacitor values for various filters but
neglects the effect of the op amp’s finite bandwidth on filter
performance; ideal filter response with infinite loop gain is implied.
Unfortunately, real filters do not behave in this manner. Instead,
they exhibit finite limits of attenuation, depending on the gain
bandwidth of the active device. Good low-pass filter performance
requires an op amp with high gain bandwidth for attenuation at
high frequencies, and low noise and high dc gain for low frequency,
pass-band performance.
249ꢂ
G = +2
3
+
V
IN
6
AD8021
–
49.9ꢂ
5
2
–V
S
7pF
Figure 13 shows the schematic of a 2-pole, low-pass active filter,
and Table IV lists typical component values for filters having a
Bessel-type response with gains of 2 and 5. Figure 14 is a network
analyzer plot of this filter’s performance.
499ꢂ
499ꢂ
V
OUT1
1kꢂ
232ꢂ
G = –2
3
2
+
6
V
AD8021
–
OUT2
5
C1
1kꢂ
+V
S
–V
S
5pF
AD8021
R1
R2
C2
3
2
V
IN
6
332ꢂ
664ꢂ
V
OUT
5
Figure 10. Differential Amplifier
C
C
–V
S
12
R
F
R
G
9
6
Figure 13. Schematic of a Second-Order Low-Pass
Active Filter
3
G = –2
G = +2
0
–3
–6
–9
–12
–15
–18
Table IV. Typical Component Values for Second-Order
Low-Pass Filter of Figure 13
Gain R1 (ꢂ) R2 (ꢂ) RF (ꢂ) RS (ꢂ) C1
C2
CC
2
5
71.5
44.2
215
365
499
90.9
499
365
10 nF 10 nF 7 pF
10 nF 10 nF 2 pF
100k
1M
10M
100M
1G
50
40
FREQUENCY – Hz
Figure 11. AC Response of Two Identically
Compensated High Speed Op Amps Configured
for Gains of +2 and –2
30
20
G = 5
10
12
9
0
G = 2
–10
–20
–30
–40
6
3
G = ꢃ2
0
–3
–50
1k
–6
10k
100k
FREQUENCY – Hz
1M
10M
–9
–12
–15
–18
Figure 14. Frequency Response of the Filter Circuit
of Figure 13 for Two Different Gains
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure12. AC Response of Two Dissimilarly
Compensated AD8021 Op Amps (Figure 11) Configured
for Gains of +2 and –2. Note the Close Gain Match.
REV. D
–18–
AD8021
20
18
16
14
12
10
8
Driving Capacitive Loads
When the AD8021 drives a capacitive load, the high frequency
response may show excessive peaking before it rolls off. Two
techniques can be used to improve stability at high frequency and
reduce peaking. The first technique is to increase the compensa-
tion capacitor, CC, which reduces the peaking while maintaining
gain flatness at low frequencies. The second technique is to add a
resistor, RSNUB, in series between the output pin of the AD8021
and the capacitive load, CL. Figure 15 shows the response of the
AD8021 when both CC and RSNUB are used to reduce peaking.
For a given CL, Figure 16 can be used to determine the value of
RSNUB that maintains 2 dB of peaking in the frequency response.
Note, however, that using RSNUB attenuates the low frequency
output by a factor of RLOAD/(RSNUB + RLOAD).
6
4
2
0
0
5
10
15
20
25
30
35
40
45
50
CAPACITIVE LOAD – pF
18
FET
PROBE
+V
S
Figure 16. Relationship of RSNUB vs. CL for 2 dB
Peaking at a Gain of +2
16
C
R
= 7pF;
= 0
R
C
SNUB
SNUB
5
6
49.9ꢂ
14
12
10
8
49.9ꢂ
R
1kꢂ
L
33pF
C
R
= 8pF;
C
–V
S
= 0
C
SNUB
C
499ꢂ
499ꢂ
6
4
2
C
R
= 8pF;
C
0
= 17.4ꢂ
SNUB
0.1
1.0
10
FREQUENCY – MHz
100
1000
Figure 15. Peaking vs. RSNUB and CC for CL = 33 pF
REV. D
–19–
AD8021
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢆ 45ꢁ
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8ꢁ
0.51 (0.0201)
0.31 (0.0122)
0ꢁ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8ꢁ
0ꢁ
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
Revision History
Location
Page
10/03—Data Sheet changed from REV. C to REV. D.
Edits to SPECIFICATIONS heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7/03—Data Sheet changed from REV. B to REV. C.
Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Replaced Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/03—Data Sheet changed from REV. A to REV. B.
Edits to Evaluation Board Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Edits to Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6/02—Data Sheet changed from REV. 0 to REV. A.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
–20–
REV. D
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