AD8044_04 [ADI]
Quad 150 MHz Rail-to-Rail Amplifier; 四核150 MHz轨到轨放大器
| 型号： | AD8044_04 |
| 厂家： | 
ADI |
| 描述： | Quad 150 MHz Rail-to-Rail Amplifier |
| 文件： | 总16页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 150 MHz
Rail-to-Rail Amplifier
a
AD8044
CONNECTION DIAGRAM
FEATURES
14-Lead Plastic DIP and SOIC
Single AD8041 and Dual AD8042 Also Available
Fully Specified at +3 V, +5 V, and ؎5 V Supplies
Output Swings to Within 25 mV of Either Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 1 V Beyond Supplies
Low Power of 2.75 mA/Amplifier
High Speed and Fast Settling on +5 V
150 MHz –3 dB Bandwidth (G = +1)
170 V/s Slew Rate
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
+IN D
12
V–
11
10
9
AD8044
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
8
40 ns Settling Time to 0.1%
TOP VIEW
Good Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness of 0.1 dB to 12 MHz
0.06% Differential Gain Error
0.15؇ Differential Phase Error
Low Distortion
–68 dBc Total Harmonic @ 5 MHz
Outstanding Load Drive Capability
Drives 30 mA 0.5 V from Supply Rails
The output voltage swing extends to within 25 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 12 MHz, while offering differ-
ential gain and phase error of 0.04% and 0.22∞ on a single +5 V
supply. This makes the AD8044 useful for video electronics,
such as cameras, video switchers, or any high speed portable
equipment. The AD8044’s low distortion and fast settling make
it ideal for active filter applications.
APPLICATIONS
Active Filters
Video Switchers
Distribution Amplifiers
A/D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)
The AD8044 offers low power supply current of 13.1 mA max
and can run on a single +3.3 V power supply. These features are
ideally suited for portable and battery-powered applications
where size and power are critical.
The wide bandwidth of 150 MHz, along with 170 V/ms of slew
rate on a single +5 V supply, make the AD8044 useful in many
general-purpose, high speed applications where dual power
supplies of up to ±6 V and single supplies from +3 V to +12 V
are needed. The AD8044 is available in 14-lead PDIP and
SOIC.
PRODUCT DESCRIPTION
The AD8044 is a quad, low power, voltage feedback, high
speed amplifier designed to operate on +3 V, +5 V, or ±5 V
supplies. It has true single-supply capability with an input volt-
age range extending 200 mV below the negative rail and within
1 V of the positive rail.
18
V
= +5V
S
15
12
9
G = +1
V
= +5V
S
6
5V
3
0
2.5V
–3
–6
–9
0V
1V
2s
–12
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 1. Output Swing: Gain = –1, RL = 2 kW
REV. B
Figure 2. Frequency Response: Gain = +1, VS = +5 V
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8044–SPECIFICATIONS(@ TA = +25؇C, VS = +5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted.)
AD8044A
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
G = +1
80
150
12
170
26
MHz
MHz
V/ms
MHz
ns
G = +2, RL = 150 W
G = –1, VO = 4 V Step
VO = 2 V p-p
140
G = –1, VO = 2 V Step
30
Settling Time to 0.1%
40
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
f
C = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kW
–68
16
850
0.04
0.22
–60
dB
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 W to 2.5 V
G = +2, RL = 150 W to 2.5 V
f = 5 MHz, RL = 1 kW, G = +2
nV/÷Hz
fA/÷Hz
%
Degrees
dB
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.0
6
8
mV
mV
mV/∞C
mA
mA
mA
T
MIN–TMAX
Offset Drift
Input Bias Current
8
2
4.5
4.5
1.2
T
R
MIN–TMAX
Input Offset Current
Open-Loop Gain
0.2
94
88
L = 1 kW
82
80
dB
dB
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
225
1.6
–0.2 to 4
90
kW
pF
V
VCM = 0 V to 3.5 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
R
R
R
T
L = 10 kW to 2.5 V
L = 1 kW to 2.5 V
L = 150 W to 2.5 V
MIN–TMAX, VOUT = 0.5 V to 4.5 V
0.03 to 4.975
0.25 to 4.75 0.075 to 4.91
V
V
V
mA
mA
mA
pF
0.55 to 4.4
0.25 to 4.65
30
45
85
40
Short Circuit Current
Sourcing
Sinking
G = +2
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current
Power Supply Rejection Ratio
11
80
13.1
mA
dB
VS = 0, +5 V, ±1 V
70
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
–40
+85
∞C
REV. B
–2–
AD8044
SPECIFICATIONS
(@ TA = +25؇C, VS = +3 V, RL = 2 k⍀ to 1.5 V, unless otherwise noted.)
AD8044A
Typ
Parameter
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 1%
G = +1
G = +2, RL = 150 W
G = –1, VO = 2 V Step
80
135
10
150
22
MHz
MHz
V/ms
MHz
ns
110
V
O = 2 V p-p
G = –1, VO = 2 V Step
35
Settling Time to 0.1%
55
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
f
C = 5 MHz, VO = 2 V p-p, G = –1, RL = 100 W
–48
16
600
0.13
0.3
dB
f = 10 kHz
f = 10 kHz
nV/÷Hz
fA/÷Hz
%
Degrees
dB
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
G = +2, RL = 150 W to 1.5 V, Input VCM = 0.5 V
G = +2, RL = 150 W to 1.5 V, Input VCM = 0.5 V
f = 5 MHz, RL = 1 kW, G = +2
–60
DC PERFORMANCE
Input Offset Voltage
1.5
5.5
7.5
mV
mV
mV/∞C
mA
mA
mA
T
MIN–TMAX
Offset Drift
Input Bias Current
8
2
4.5
4.5
1.2
T
R
MIN–TMAX
Input Offset Current
Open-Loop Gain
0.2
92
88
L = 1 kW
80
76
dB
dB
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
225
1.6
–0.2 to 2
90
kW
pF
V
VCM = 0 V to 1.5 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
R
R
R
T
L = 10 kW to 1.5 V
L = 1 kW to 1.5 V
L = 150 W to 1.5 V
MIN–TMAX, VOUT = 0.5 V to 2.5 V
0.025 to 2.98
0.17 to 2.82 0.06 to 2.93
0.35 to 2.55 0.15 to 2.75
V
V
V
mA
mA
mA
pF
25
30
50
35
Short Circuit Current
Sourcing
Sinking
G = +2
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current
Power Supply Rejection Ratio
10.5
80
12.5
mA
dB
VS = 0, +3 V, +0.5 V
70
0
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
+70
∞C
REV. B
–3–
(@ T = +25؇C, V = ؎5 V, R = 2 k⍀ to 0 V, unless otherwise noted.)
AD8044–SPECIFICATIONS
A
S
L
AD8044A
Typ
Parameter
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
G = +1
G = +2, RL = 150 W
G = –1, VO = 8 V Step
85
160
15
190
29
MHz
MHz
V/ms
MHz
ns
150
V
O = 2 V p-p
G = –1, VO = 2 V Step
30
Settling Time to 0.01%
40
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
f
C = 5 MHz, VO = 2 V p-p, G = +2
–72
16
900
0.06
0.15
–60
dB
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 W
G = +2, RL = 150 W
f = 5 MHz, RL = 1 kW, G = +2
nV/÷Hz
fA/÷Hz
%
Degrees
dB
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
1.4
6.5
9
mV
mV
mV/∞C
mA
mA
mA
T
MIN–TMAX
Offset Drift
Input Bias Current
10
2
4.5
4.5
1.2
T
R
MIN–TMAX
Input Offset Current
Open-Loop Gain
0.2
96
92
L = 1 kW
82
76
dB
dB
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
225
1.6
–5.2 to 4
90
kW
pF
V
VCM = –5 V to 3.5 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing:
Output Voltage Swing:
Output Current
R
R
R
T
L = 10 kW
L = 1 kW
L = 150 W
MIN–TMAX, VOUT = –4.5 V to +4.5 V
–4.97 to +4.97
–4.85 to +4.85
–4.5 to +4.5
30
60
100
40
V
V
V
mA
mA
mA
pF
–4.6 to +4.6
–4.0 to +3.8
Short Circuit Current
Sourcing
Sinking
G = +2
Capacitive Load Drive
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current
Power Supply Rejection Ratio
11.5
80
13.6
mA
dB
VS = –5, +5 V, ±1 V
70
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
–40
+85
∞C
–4–
REV. B
AD8044
ABSOLUTE MAXIMUM RATINGS1
While the AD8044 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (+150∞C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V
Internal Power Dissipation2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.6 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage (Common-Mode) . . . . . . . . . . . . . . ±VS ± 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V
Output Short Circuit Duration
2.5
T
= +150 C
J
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65∞C to +125∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300∞C
2.0
14-LEAD PLASTIC DIP PACKAGE
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for the device in free air:
1.5
1.0
0.5
14-LEAD SOIC
14-Lead Plastic Package: qJA = 75∞C/W
14-Lead SOIC Package: qJA = 120∞C/W
MAXIMUM POWER DISSIPATION
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (؇C)
The maximum power that can be safely dissipated by the
AD8044 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic encap-
sulated devices is determined by the glass transition temperature
of the plastic, approximately +150∞C. Exceeding this limit
temporarily may cause a shift in parametric performance due to
a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175∞C for an extended
period can result in device failure.
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8044AN
AD8044AR-14
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
14-Lead PDIP
14-Lead SOIC
14-Lead SOIC 13" REEL R-14
14-Lead SOIC 7" REEL
14-Lead Plastic SOIC
14-Lead SOIC 13" REEL R-14
N-14
R-14
AD8044AR-14-REEL
AD8044AR-14-REEL7
AD8044ARZ-14*
AD8044ARZ-14-REEL*
AD8044ARZ-14-REEL7*
R-14
R-14
14-Lead SOIC 7" REEL
R-14
*Z = Pb free part
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–5–
REV. B
AD8044–Typical Performance Characteristics
100
95
11
V
= +5V
S
A
10
9
T
= +25؇C
62 PARTS
MEAN = 350V
8
7
STD DEVIATION = 560V
90
6
5
4
3
2
1
85
V
= +5V
S
T = +25؇C
80
75
70
0
0
250
500
750
1000
1250
1500
1750 2000
–3 –2.5 –2 –1.5 –1 –0.5
V
0
0.5
1
1.5
2
2.5
3
LOAD RESISTANCE (⍀)
(mV)
Figure 4. Typical Distribution of VOS
Figure 7. Open-Loop Gain vs. RL to +2.5 V
100
97
15
V
= +5V
= 1k⍀ TO +2.5V
S
L
MEAN = 7.9V/؇C
STD DEV = 2.3V/؇C
SAMPLE SIZE = 62
R
12
9
V
= +5
S
94
6
3
0
91
88
85
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0
DRIFT (V/؇C)
–40
–20
0
20
40
60
80
100
V
OS
TEMPERATURE (؇C)
Figure 5. VOS Drift Over –40∞C to +85∞C
Figure 8. Open-Loop Gain vs. Temperature
2.4
2.2
100
V
= +5V
S
V
= +5V
90
80
70
60
50
40
30
R = 500⍀
L
S
R
= 50⍀
L
2.0
1.8
0
20
10
0
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85
TEMPERATURE (؇C)
0
0.15 0.35 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.45 4.65 4.85
OUTPUT VOLTAGE (V)
5
Figure 6. IB vs. Temperature
Figure 9. Open-Loop Gain vs. Output Voltage
REV. B
–6–
AD8044
300
100
30
0.03
0.02
V
= +5V
S
G = +2
= 150⍀
0.01
0.00
R
L
–0.01
–0.02
–0.03
–0.04
0
10
10
20
20
30
30
40
40
50
50
60 70
80
90 100
10
0.20
V
= +5V
0.15
0.10
0.05
0.00
S
G = +2
= 150⍀
R
L
3
1
–0.05
–0.10
–0.15
–0.20
10
100
1M
10M
1k
10k
100k
0
60 70
80
90 100
FREQUENCY (Hz)
Figure 10. Input Voltage Noise vs. Frequency
Figure 13. Differential Gain and Phase Errors
–30
V
R
A
= +5V,
= 100⍀
= +1
S
L
V
V
= 2V p-p
O
0.3
0.2
0.1
V
R
A
= +5V,
= 100⍀
= +2
S
L
V
–40
–50
–60
–70
–80
V
= +3V,
= 100⍀
= –1
S
R
A
L
V
11.6MHz
0.0
–0.1
–0.2
V
R
R
= +5V
S
F
L
= 200⍀
–0.3
–0.4
–0.5
–0.6
= 150⍀ TO 2.5V
V
R
A
= +5V,
= 1k⍀
= +2
V
R
A
= +5V,
= 1k⍀
= +1
S
L
V
S
L
V
–90
G = +2
V = 0.2V p-p
i
–100
1
2
3
4
5
6
7
8 9 10
FUNDAMENTAL FREQUENCY (MHz)
1M
10M
FREQUENCY (Hz)
100M
Figure 11. Total Harmonic Distortion
Figure 14. 0.1 dB Gain Flatness
–30
80
–40
–50
–60
–70
V
= +5V
= 2k⍀
= 5pF
10MHz
S
L
L
70
60
R
C
50
40
–80
–90
5MHz
1MHz
GAIN
30
20
10
180
–100
–110
135
90
V
= +5V
PHASE
S
L
R
= 2k⍀ TO 2.5V
–120
–130
G = +2
0
45
0
–10
–140
80MHz
100M
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
–20
OUTPUT VOLTAGE (V p-p)
10M
1M
FREQUENCY (Hz)
30k
100k
Figure 12. Worst Harmonic vs. Output Voltage
Figure 15. Open-Loop Gain and Phase Margin
vs. Frequency
–7–
REV. B
AD8044
4
3
2
70
+85؇C
+25؇C
–40؇C
G = –1
= 2k⍀
V
= +5V
R
S
L
L
L
R
C
= 2k⍀ TO 2.5V
= 5pF
60
50
40
30
20
V
= +3V, 0.1%
S
G = +1
V
V
= +5V, 0.1% AND
S
S
V
= 0.2V p-p
O
= ؎5V, 0.1%
1
0
–1
–2
–3
–4
V
= +3V, 1%
S
V
V
= +5V, 1% AND
= ؎5V, 1%
S
S
10
0
–5
1M
10M
0.5
1
1.5
2
100M
INPUT STEPS (V p-p)
FREQUENCY (Hz)
Figure 19. Settling Time vs. Input Step
Figure 16. Closed-Loop Frequency Response
vs. Temperature
6
0
G = +1
5
4
+3V
+5V
؎5V
–10
–20
–30
R
C
= 2k⍀
L
L
O
V
= ؎5V
= 5pF
= 0.2V p-p
S
V
3
2
V
= +3V
S
1
0
–40
–50
–60
؎5V
–1
–2
–3
+3V
+5V
–70
–80
–4
100k
1M
10M
100M
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency
Figure 17. Closed-Loop Frequency Response vs. Supply
1.00
0.875
0.750
0.625
0.500
R
= 50⍀
BT
100
10
1
V
= +5V
+5V –V
(+125؇C)
S
OH
G = +1
= +5V
V
S
+5V –V
(+25؇C)
OH
R
BT
V
OUT
+5V –V
(–55؇C)
OH
0.375
0.250
0.125
R
= 0⍀
0.1
BT
V
(+125؇C)
OL
V
(+25؇C)
OL
0.01
V
(–55؇C)
OL
0.00
0
3
6
9
12
15
18
21
24
27
30
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
LOAD CURRENT (mA)
Figure 21. Output Saturation Voltage vs. Load Current
Figure 18. Output Resistance vs. Frequency
–8–
REV. B
AD8044
60
50
40
12.0
11.5
11.0
G = +2, R = 0⍀,
S
G = +3, R = 0⍀,
O
S
V
= ؎5V
S
V
= 100mV STEP
O
V
= 150mV STEP
R
= R = 750⍀
F
G
G = +1, R = 20⍀,
S
V
= +5V
= +3V
S
V
= 100mV STEP
O
R
R
= 750⍀
= 375⍀
F
G
R
= 0, R =
G
F
G = +1, R = 40⍀,
O
S
V
S
V
= 100mV STEP
R
R
F
30
20
10
0
G
10.5
10.0
9.5
R
= 0, R =
G
F
+2.5V
V
OUT
V
IN
R
S
–2.5V
50⍀
0
50
100
150
200
250
9.0
LOAD CAPACITANCE (pF)
–40
–20
0
20
40
60
80
100
TEMPERATURE (؇C)
Figure 25. % Overshoot vs. Capacitive Load
Figure 22. Supply Current vs. Temperature
3
20
10
G = +2
2
1
R
= 150⍀ TO 2.5V
G = +2
L
V
= +5V
S
R
= 200⍀
F
0
–10
–20
–30
–40
–50
–60
–70
–80
0
G = +5
–PSRR
+PSRR
–1
–2
–3
–4
V
R
R
= +5V
= 5k⍀ TO 2.5V
= 2k⍀
S
L
F
–5
–6
G = +10
–7
10M
FREQUENCY (Hz)
100M
500M
100k
1M
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 23. PSRR vs. Frequency
Figure 26. Frequency Response vs. Closed-Loop Gain
10
9
–10
V
V
= ؎5V
S
IN
V
= ؎5V
= 2k⍀
S
L
–20
–30
= 1V p-p
R
G = +2
8
R
= 1k⍀
F
–40
–50
7
R
= 100⍀
6
L
–60
–70
–80
5
4
R
= 1k⍀
L
3
–90
2
1
0
–100
–110
0.1
1
10
FREQUENCY (MHz)
100
400
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 24. Output Voltage Swing vs. Frequency
Figure 27. Crosstalk (Output to Output) vs. Frequency
–9–
REV. B
AD8044
5V
4.656V
2.6V
V
= +5V
S
G = +1
V
R
C
= +5V
= 150⍀ TO +2.5V
= 5pF
S
R
C
= 2k⍀
= 5pF
L
L
L
2.55V
L
G = –1
2.5V
2.5V
2.45V
2.4V
0.211V
50mV
40ns
100s
500mV
0V
Figure 28a. Output Swing vs. Load Reference Voltage,
VS = +5 V, G = –1
Figure 30. 100 mV Step Response, VS = +5 V, G = +1
5V
3V
4.309V
+2.920V
V
= 3V p-p
= 2k⍀
= 5pF
IN
V
R
C
= +5V
= 150⍀ TO GND
= 5pF
S
L
L
2.5V
2V
R
C
V
L
L
= +3V
S
G = –1
G = –1
2.5V
1.5V
1V
0.5V
0V
+10mV
+22mV
500mV
100s
500mV
200s
Figure 28b. Output Swing vs. Load Reference Voltage,
VS = +5 V, G = –1
Figure 31. Output Swing, VS = +3 V
1.60V
4.5V
V
= 0.1V p-p
I
N
L
L
1.58V
1.56V
V
= +5V
R
C
V
=
2k⍀
S
G = +2
=
5pF
R
= 2k⍀
= 1V p-p
= 5pF
L
= +3V
3.5V
2.5V
1.5V
S
1.54V
1.52V
1.50V
V
IN
G = +1
C
L
1.48V
1.46V
1.44V
1.42V
1.40V
20mV
20ns
500mV
20ns
0.5V
Figure 29. One Volt Step Response, VS = +5 V, G = +2
Figure 32. Step Response, G = +1, VIN = 100 mV
–10–
REV. B
AD8044
Overdrive Recovery
Driving Capacitance Loads
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 33, the AD8044 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
The capacitive load drive of the AD8044 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for vary-
ing voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less over-
shoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.
V
= +5V
= +2
= 2k⍀
= 2k⍀
S
A
R
R
V
F
L
V
OUT
1V/DIV
V
CC
I1
I10
I2
I3
I9
Q50
Q39
V
Q25
Q51
IN
R26
Q4
R39
Q5
2V/DIV
Q36
V
I5
Q23
Q40
V
EE
R15 R2
Q22
R27
R23
Q21
V
EE
C3
Q31
Q7
V
P
Q17
Q13
IN
OUT
Q27
V
N
IN
C9
SIN
SIP
2V
1V
50ns
Q2
Q11
R3
Q8
Q3
Q24
I7
Q47
I8
CC
Figure 33. Overdrive Recovery, VS + 5 V, VIN = 4 V Step
I11
V
C7
R5
R21
Circuit Description
V
EE
The AD8044 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar fTs in the 2 GHz–4 GHz region. The process is dielectri-
cally isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construc-
tion of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –85 dB
@ 1 MHz into 100 W with VOUT = 2 V p-p (Gain = +2) on a
single 5 volt supply is achieved.
Figure 34. AD8044 Simplified Schematic
The AD8044’s rail-to-rail output range is provided by a comple-
mentary common-emitter output stage. High output drive capa-
bility is provided by injecting all output stage predriver currents
directly into the bases of the output devices Q8 and Q36. Bias-
ing of Q8 and Q36 is accomplished by I8 and I5, along with a
common-mode feedback loop (not shown). This circuit topol-
ogy allows the AD8044 to drive 50 mA of output current with
the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Ex-
ceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
–11–
REV. B
AD8044
+5V
1000
GRAPHICS
IC
V
= +5V
S
R
< 30% OVERSHOOT
⍀
= 10
⍀
= 0
S
R
75⍀
S
R
G
75⍀
100
B
75⍀
75⍀
75⍀
R
R
F
G
R
S
V
RGB
IN
+3V OR +5V
75⍀
V
OUT
MONITOR #1
C
100mV STEP
L
AD8044
10
1
10F
0.1F
75⍀
2
3
4
5
6
A
(V/V)
CL
V+
A
B
C
Figure 35. Capacitive Load Drive vs. Closed-Loop Gain
1k⍀
APPLICATIONS
RGB Buffer
The AD8044 can provide buffering of RGB signals that include
ground while operating from a single +3 V or +5 V supply.
1k⍀
1k⍀
75⍀
75⍀
AD8044
75⍀
When driving two monitors from the same RGB video source it
is necessary to provide an additional driver for one of the moni-
tors to prevent the double termination situation that the second
monitor presents. This has usually required a dual-supply op
amp because the level of the input signal from the video driver
goes all the way to ground during horizontal blanking. In single-
supply systems it can be a major inconvenience and expense to
add an additional negative supply.
1k⍀
75⍀
AD8044
V–
75⍀
RGB
MONITOR #2
1k⍀
A single AD8044 can provide the necessary drive capability and
yet does not require a negative supply in this application. Fig-
ure 36 is a schematic that uses three amplifiers out of a single
AD8044 to provide buffering for a second monitor.
1k⍀
Figure 36. Single Supply RGB Video Driver
The source of the RGB signals is shown to be from a set of three
current output DACs that are within a single-supply graphics
IC. This is typically the situation in most PCs and workstations
that may use either a standalone triple DAC or DACs that are
integrated into a larger graphics chip.
Figure 37 is an oscilloscope photo of the circuit in Figure 36
operating from a +3 V supply and driven by the Blue signal of a
color bar pattern. Note that the input and output are at ground
during the horizontal blanking interval. The RGB signals are
specified to output a maximum of 700 mV peak. The output of
the AD8044 is 1.4 V with the termination resistors providing a
divide-by-two.
During horizontal blanking, the current output from the DACs
is turned off and the RGB outputs are pulled to ground by the
termination resistors. If voltage sources were used for the RGB
signals, then the termination resistors near the graphics IC
would be in series and the rest of the circuit would remain the
same. This is because a voltage source is an ac short circuit, so a
series resistor is required to make the drive end of the line see
75 W to ac ground. On the other hand, a current source has a
very high output impedance, so a shunt resistor is required to
make the drive end of the line see 75 W to ground. In either
case, the monitor terminates its end of the line with 75 W.
500mV
5s
100
90
V
IN
GND
GND
V
OUT
10
0%
The circuit in Figure 36 shows minimum signal degradation
when using a single-supply for the AD8044. The circuit per-
forms equally well on either a +3 V or +5 V supply.
500mV
Figure 37. +3 V, RGB Buffer
–12–
REV. B
AD8044
Active Filters
Layout Considerations
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
The specified high speed performance of the AD8044 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
Figure 38 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8044 package. Such
circuits are sometimes used in medical ultrasound systems to
lower the noise bandwidth of the analog signal before A/D
conversion.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large (0.47 mF
– 10 mF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
R6
1k⍀
C1
50pF
R2
2k⍀
R4
2k⍀
C2
R1
50pF
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
3k⍀
R3
2
3
V
2k⍀
IN
R5
1
6
5
2k⍀
7
9
8
V
OUT
AD8044
10
AD8044
AD8044
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and properly termi-
nated at each end.
Figure 38. 2 MHz Biquad Band-pass Filter Using AD8044
The frequency response of the circuit is shown in Figure 39.
0
–10
–20
–30
–40
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 39. Frequency Response of 2 MHz Band-pass
Biquad Filter
–13–
REV. B
AD8044
OUTLINE DIMENSIONS
14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
Dimensions shown in inches and (millimeters)
0.685 (17.40)
0.665 (16.89)
0.645 (16.38)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
14
1
8
7
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
MIN
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.180 (4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
PLANE
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.022 (0.56) 0.060 (1.52)
0.018 (0.46) 0.050 (1.27)
0.014 (0.36) 0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
؋
45؇ 0.25 (0.0098)
0.10 (0.0039)
8؇
0؇
0.51 (0.0201)
0.31 (0.0122)
SEATING
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–14–
REV. B
AD8044
Revision History
Location
Page
8/04—Data Sheet changed from Rev. A to Rev. B
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
–15–
REV. B
–16–
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