AD8051ART-R [ADI]
IC OP-AMP, 27000 uV OFFSET-MAX, PDSO5, MO-178AA, SOT-23, 5 PIN, Operational Amplifier;
| 型号： | AD8051ART-R |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 27000 uV OFFSET-MAX, PDSO5, MO-178AA, SOT-23, 5 PIN, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, High Speed
Rail-to-Rail Amplifiers
a
AD8051/AD8052/AD8054
FEATURES
PIN CONNECTIONS
(Top Views)
Low Cost Single (AD8051), Dual (AD8052), and Quad
(AD8054)
Voltage Feedback Architecture
R-8 (SOIC)
Fully Specified at +3 V, +5 V, and ؎5 V Supplies
Single-Supply Operation
AD8051
1
2
3
4
8
7
6
5
NC
+V
NC
–IN
+IN
S
Output Swings to Within 25 mV of Either Rail
Input Voltage Range: –0.2 V to +4 V; VS = +5 V
High Speed and Fast Settling on 5 V:
110 MHz –3 dB Bandwidth (G = +1) (AD8051/AD8052)
150 MHz –3 dB Bandwidth (G = +1) (AD8054)
145 V/s Slew Rate
50 ns Settling Time to 0.1%
Small Packaging
AD8051 Available in SOT-23-5
AD8052 Available in MSOP-8
V
OUT
–V
NC
S
NC = NO CONNECT
SOT-23-5 (RT)
AD8051
V
1
2
5 +V
S
OUT
–V
S
+ –
AD8054 Available in TSSOP-14
+IN
3
4 –IN
Good Video Specifications (G = +2)
Gain Flatness of 0.1 dB to 20 MHz; RL = 150 ⍀
0.03% Differential Gain Error; RL = 1 k⍀
0.03؇ Differential Phase Error; RL = 1 k⍀
Low Distortion
–80 dBc Total Harmonic @ 1 MHz, RL = 100 ⍀
Outstanding Load Drive Capability
Drives 45 mA, 0.5 V from Supply Rails (AD8051/AD8052)
Drives 50 pF Capacitive Load (G = +1) (AD8051/AD8052)
Low Power of 2.75 mA/Amplifier (AD8054)
Low Power of 4.4 mA/Amplifier (AD8051/AD8052)
R-8, MSOP (RM)
AD8052
1
2
3
4
8
7
6
5
+V
S
OUT1
–IN1
+IN1
–
+
OUT
–IN2
+IN2
–
+
–V
S
R-14, TSSOP-14 (RU-14)
APPLICATIONS
Coax Cable Drivers
Active Filters
Video Switchers
A/D Driver
Professional Cameras
CCD Imaging Systems
CD/DVD ROMs
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
OUT A
؊IN A
+IN A
V+
؊IN D
+IN D
AD8054
V؊
+IN C
+IN B
؊IN B
OUT B
؊IN C
8
OUT C
GENERAL DESCRIPTION
The AD8051 (single), AD8052 (dual), and AD8054 (quad) are
low cost, voltage feedback, high speed amplifiers designed to
operate on +3 V, +5 V, or 5 V supplies. They have true single-
supply capability with an input voltage range extending 200 mV
below the negative rail and within 1 V of the positive rail.
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage
swing extends to within 25 mV of each rail, providing the maxi-
mum output dynamic range with excellent overdrive recovery.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8051/AD8052/AD8054
This makes the AD8051/AD8052/AD8054 useful for video
electronics, such as cameras, video switchers, or any high speed
portable equipment. Low distortion and fast settling make them
ideal for active filter applications.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
V
= +5V
S
G = –1
R
R
= 2k⍀
= 2k⍀
F
L
The AD8051/AD8052/AD8054 offer low power supply current
and can operate on a single 3 V power supply. These features
are ideally suited for portable and battery-powered applications
where size and power are critical.
1.5
1.0
The wide bandwidth and fast slew rate on a single +5 V supply
make these amplifiers useful in many general-purpose, high
speed applications where dual power supplies of up to 6 V and
single supplies from +3 V to +12 V are needed.
0.5
0
0.1
1
10
50
All of this low cost performance is offered in an 8-lead SOIC, as
well as a tiny SOT-23-5 package (AD8051), an MSOP package
(AD8052), and a TSSOP-14 (AD8054). The AD8051 and
AD8052 in the SOIC-8 and RM packages, and the AD8054 in
the RN-14 and RU packages are available in the extended tem-
perature range of –40°C to +125°C.
FREQUENCY – MHz
Figure 1. Low Distortion Rail-to-Rail Output Swing
–2–
REV. F
AD8051/AD8052/AD8054
(@ TA = 25؇C, VS = 5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted.)
SPECIFICATIONS
AD8051A/AD8052A
Typ
AD8054A
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V,
RF = 806 Ω for AD8051A/
AD8052A
RF = 200 Ω for AD8054A
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
70
110
50
80
150
60
MHz
MHz
Bandwidth for 0.1 dB Flatness
20
MHz
MHz
V/µs
MHz
ns
12
170
45
Slew Rate
Full Power Response
Settling Time to 0.1%
100
145
35
50
140
40
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion*
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
–67
16
–68
16
dB
nV/√Hz
fA/√Hz
%
850
0.09
0.03
0.19
0.03
–60
850
0.07
0.02
0.26
0.05
–60
%
Differential Phase Error (NTSC)
Crosstalk
Degrees
Degrees
dB
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
1.7
10
25
1.7
12
30
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
TMIN–TMAX
Offset Drift
Input Bias Current
10
1.4
15
2
2.5
3.25
0.75
4.5
4.5
1.2
TMIN–TMAX
Input Offset Current
Open-Loop Gain
0.1
98
96
82
78
0.2
98
96
82
78
RL = 2 kΩ to 2.5 V
TMIN–TMAX
RL = 150 Ω to 2.5 V
TMIN–TMAX
86
76
82
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
290
1.4
–0.2 to +4
88
300
1.5
–0.2 to +4
kΩ
pF
V
VCM = 0 V to 3.5 V
72
70
86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ to 2.5 V
RL = 2 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
VOUT = 0.5 V to 4.5 V
TMIN–TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
0.015 to 4.985
0.025 to 4.975
0.2 to 4.8
45
45
80
130
50
0.03 to 4.975
0.125 to 4.875 0.05 to 4.95
V
V
V
mA
mA
mA
mA
pF
pF
0.1 to 4.9
0.3 to 4.625
0.55 to 4.4
0.25 to 4.65
Output Current
30
30
45
85
Short-Circuit Current
Capacitive Load Drive
40
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
3
12
5
3
12
V
4.4
80
2.75
80
3.275 mA
dB
⌬VS
=
1 V
70
68
OPERATING TEMPERATURE RANGE
RT
–40
–40
+85
°C
RM, R-8, RU, R-14
+125 –40
+125 °C
*Refer to TPC 13.
Specifications subject to change without notice.
REV. F
–3–
AD8051/AD8052/AD8054
(@ TA = 25؇C, VS = 3 V, RL = 2 k⍀ to 1.5 V, unless otherwise noted.)
SPECIFICATIONS
AD8051A/AD8052A
Typ
AD8054A
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
70
110
50
80
135
65
MHz
MHz
Bandwidth for 0.1 dB Flatness
R
R
R
L = 150 Ω to 2.5 V,
F = 402 Ω for AD8051A/AD8052A
F = 200 Ω for AD8054A
17
MHz
MHz
V/µs
MHz
ns
10
150
85
Slew Rate
Full Power Response
Settling Time to 0.1%
G = –1, VO = 2 V Step
G = +1, VO = 1 V p-p
G = –1, VO = 2 V Step
90
135
65
55
110
55
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion*
fC = 5 MHz, VO = 2 V p-p,
G = –1, RL = 100 Ω to 1.5 V
f = 10 kHz
–47
16
600
–48
16
600
dB
nV/√Hz
fA/√Hz
Input Voltage Noise
Input Current Noise
f = 10 kHz
Differential Gain Error (NTSC)
G = +2, VCM = 1 V
R
R
L = 150 Ω to 1.5 V,
L = 1 kΩ to 1.5 V
0.11
0.09
0.13
0.09
%
%
Differential Phase Error (NTSC)
Crosstalk
G = +2, VCM = 1 V
R
R
L = 150 Ω to 1.5 V
L = 1 kΩ to 1.5 V
0.24
0.10
–60
0.3
0.1
–60
Degrees
Degrees
dB
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
1.6
10
25
1.6
12
30
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
TMIN–TMAX
Offset Drift
Input Bias Current
10
1.3
15
2
2.6
3.25
0.8
4.5
4.5
1.2
T
MIN–TMAX
Input Offset Current
Open-Loop Gain
0.15
96
94
82
76
0.2
96
94
80
76
R
T
R
L = 2 kΩ
MIN–TMAX
L = 150 Ω
80
74
80
72
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
290
1.4
–0.2 to +2
88
300
1.5
–0.2 to +2
kΩ
pF
V
VCM = 0 V to 1.5 V
72
70
86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ to 1.5 V
0.01 to 2.99
0.025 to 2.98
V
R
R
V
T
L = 2 kΩ to 1.5 V
L = 150 Ω to 1.5 V
OUT = 0.5 V to 2.5 V
MIN–TMAX
0.075 to 2.9 0.02 to 2.98
0.1 to 2.9
0.35 to 2.55
0.35 to 2.965
0.15 to 2.75
25
25
30
50
V
V
0.2 to 2.75
0.125 to 2.875
Output Current
45
45
60
90
45
mA
mA
mA
mA
pF
pF
Short-Circuit Current
Capacitive Load Drive
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
35
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
4.2
80
4.8
2.625
80
3.125 mA
dB
⌬VS = 0.5 V
68
68
OPERATING TEMPERATURE RANGE
RT
–40
–40
+85
°C
+125 °C
RM, R-8, RU, R-14
+125 –40
*Refer to TPC 13.
Specifications subject to change without notice.
–4–
REV. F
AD8051/AD8052/AD8054
(@ TA = 25؇C, VS = ؎5 V, RL = 2 k⍀ to Ground, unless otherwise noted.)
SPECIFICATIONS
AD8051A/AD8052A
Typ
AD8054A
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω,
70
110
50
85
160
65
MHz
MHz
Bandwidth for 0.1 dB Flatness
RF = 1.1 kΩ for
AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
20
MHz
MHz
V/µs
MHz
ns
15
190
50
Slew Rate
Full Power Response
Settling Time to 0.1%
105
170
40
50
150
40
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
–71
16
–72
16
dB
nV/√Hz
fA/√Hz
%
900
0.02
0.02
0.11
0.02
–60
900
0.06
0.02
0.15
0.03
–60
%
Differential Phase Error (NTSC)
Crosstalk
Degrees
Degrees
dB
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
1.8
11
27
1.8
13
32
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
TMIN–TMAX
Offset Drift
Input Bias Current
10
1.4
15
2
2.6
3.5
0.75
4.5
4.5
1.2
TMIN–TMAX
Input Offset Current
Open-Loop Gain
0.1
96
96
82
80
0.2
96
96
82
80
RL = 2 kΩ
88
78
84
76
TMIN–TMAX
RL = 150 Ω
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
290
1.4
–5.2 to +4
88
300
1.5
–5.2 to +4
kΩ
pF
V
VCM = –5 V to +3.5 V
72
70
86
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ
–4.98 to +4.98
–4.97 to +4.97
V
RL = 2 kΩ
RL = 150 Ω
–4.85 to +4.85 –4.97 to +4.97
–4.45 to +4.3 –4.6 to +4.6
–4.8 to +4.8
–4.0 to +3.8
–4.9 to +4.9
–4.5 to +4.5
V
V
Output Current
VOUT = –4.5 V to +4.5 V
TMIN–TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
45
45
100
160
50
30
30
60
100
mA
mA
mA
mA
pF
pF
Short-Circuit Current
Capacitive Load Drive
40
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
4.8
80
5.5
2.875
80
3.4
mA
dB
⌬VS
=
1 V
68
68
OPERATING TEMPERATURE RANGE
RT
–40
–40
+85
°C
RM, RN-8, RU, R-14
+125 –40
+125 °C
Specifications subject to change without notice.
REV. F
–5–
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS1
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Small Outline Package (RN) Observe Power Derating Curves
SOT-23-5 Package . . . . . . . Observe Power Derating Curves
MSOP Package . . . . . . . . . Observe Power Derating Curves
TSSOP-14 Package . . . . . . Observe Power Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (RN) . . . . . . . . –65°C to +150°C
Operating Temperature Range (A Grade) . . –40°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
While the AD8051/AD8052/AD8054 are internally short-circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves.
2.5
NOTES
SOIC-14
SOIC-8
2.0
1.5
1.0
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Specification is for device in free air:
TSSOP-14
8-Lead SOIC: JA = 125°C/W
5-Lead SOT-23-5: JA = 180°C/W
MSOP-8
8-Lead MSOP: JA = 150°C/W
0.5
0
14-Lead SOIC: JA = 90°C/W
SOT-23-5
14-Lead TSSOP: JA = 120°C/W
MAXIMUM POWER DISSIPATION
–35 –15
15
35
55
75
95
115
–55
5
AMBIENT TEMPERATURE – ؇C
The maximum power that can be safely dissipated by the
AD8051/AD8052/AD8054 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8051/AD8052/AD8054 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–6–
REV. F
AD8051/AD8052/AD8054
ORDERING GUIDE
Temperature
Range
Package
Descriptions
Package
Model
Options1
Branding
AD8051AR
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
R-8
R-8
R-8
R-8
R-8
R-8
RT-5
RT-5
RT-5
RT-5
RT-5
RT-5
AD8051AR-REEL
AD8051AR-REEL7
AD8051ARZ2
13" Tape and Reel
7" Tape and Reel
8-Lead SOIC
AD8051ARZ-REEL2
AD8051ARZ-REEL72
AD8051ART-REEL
AD8051ART-REEL7
AD8051ART-R2
13" Tape and Reel
7" Tape and Reel
13" Tape and Reel
7" Tape and Reel
7" Tape and Reel
7" Tape and Reel
13" Tape and Reel
7" Tape and Reel
H2A
H2A
H2A
H2A
H2A
H2A
AD8051ARTZ-R22
AD8051ARTZ-REEL2
AD8051ARTZ-REEL72 –40°C to +85°C
AD8052AR
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
8-Lead SOIC
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
AD8052AR-REEL
AD8052AR-REEL7
AD8052ARZ2
13" Tape and Reel
7" Tape and Reel
8-Lead SOIC
13" Tape and Reel
7" Tape and Reel
8-Lead MSOP
13" Tape and Reel
7" Tape and Reel
7" Tape and Reel
AD8052ARZ-REEL2
AD8052ARZ-REEL72
AD8052ARM
H4A
H4A
H4A
H4A
AD8052ARM-REEL
AD8052ARM-REEL7
AD8052ARMZ-REEL72 –40°C to +125°C
AD8054AR
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
14-Lead SOIC
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
AD8054AR-REEL
AD8054AR-REEL7
AD8054ARZ2
13" Tape and Reel
7" Tape and Reel
14-Lead SOIC
AD8054ARZ-REEL2
AD8054ARZ-REEL72
AD8054ARU
13" Tape and Reel
7" Tape and Reel
14-Lead TSSOP
13" Tape and Reel
7" Tape and Reel
14-Lead TSSOP
13" Tape and Reel
7" Tape and Reel
AD8054ARU-REEL
AD8054ARU-REEL7
AD8054ARUZ2
AD8054ARUZ-REEL2
AD8054ARUZ-REEL72 –40°C to +125°C
NOTES
1R = Small Outline; RM = MSOP; RT = SOT-23; RU = TSSOP.
2Z = Pb-free part.
REV. F
–7–
AD8051/AD8052/AD8054
–Typical Performance Characteristics
3
5
V
= +5V
G = +1
= 0
S
4
3
2
1
G = +2
= 2k⍀
2
1
G = +2
= 2k⍀
R
GAIN AS SHOWN
R
R
F
R
F
R
AS SHOWN
= 5k⍀
= 0.2V p-p
F
F
L
V
O
0
–1
–2
G = +5
= 2k⍀
R
F
0
–1
–2
–3
G = +1
= 0
G = +10
= 2k⍀
R
F
R
F
G = +10
= 2k⍀
–3
–4
–5
R
F
V
= +5V
S
GAIN AS SHOWN
R
R
–4
–5
–6
–7
AS SHOWN
= 2k⍀
F
L
G = +5
= 2k⍀
V
= 0.2V p-p
–6
–7
O
R
F
0.1
1
10
FREQUENCY – MHz
100
500
1M
500M
100k
10M
FREQUENCY – Hz
100M
TPC 1. AD8051/AD8052 Normalized Gain vs.
Frequency; VS = +5 V
TPC 4. AD8054 Normalized Gain vs. Frequency;
VS = +5 V
3
2
6
5
4
+3V
+5V
؎5V
V
= +3V
V
= +5V
G = +1
S
S
1
0
R
C
= 2k⍀
= 5pF
L
L
3
2
V
= 0.2V p-p
O
–1
V
= ؎5V
S
–2
–3
–4
–5
1
0
V
AS SHOWN
S
G = +1
R
= 2k⍀
= 0.2V p-p
L
V
O
؎5V
–1
–2
–3
–4
+3V
+5V
–6
–7
0.1
1
10
FREQUENCY – MHz
100
500
100k
1M
10M
100M
500M
FREQUENCY – Hz
TPC 2. AD8051/AD8052 Gain vs. Frequency
vs. Supply
TPC 5. AD8054 Gain vs. Frequency vs. Supply
3
2
4
+85؇C
3
+25؇C
–40؇C
1
2
–40؇C
0
1
0
+85؇C
–1
+25؇C
–2
V
R
C
= +5V
= 2k⍀ TO 2.5V
= 5pF
–1
–2
S
–3
–4
–5
L
V
= +5V
S
L
G = +1
R
G = +1
= 0.2V p-p
= 2k⍀
= 0.2V p-p
L
–3
–4
–5
V
O
V
O
–6 TEMPERATURE AS SHOWN
–7
0.1
1
10
FREQUENCY – MHz
100
500
1
10
100
500
FREQUENCY – MHz
TPC 3. AD8051/AD8052 Gain vs. Frequency vs.
Temperature
TPC 6. AD8054 Gain vs. Frequency vs.
Temperature
–8–
REV. F
AD8051/AD8052/AD8054
6.3
6.2
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
6.1
6.0
5.9
5.8
V
= +5V
S
R
R
= 200⍀
= 150⍀
V
= +5V
F
S
5.7
5.6
G = +2
L
R
R
V
= 150⍀
= 806⍀
= 0.2V p-p
L
F
G = +2
= 0.2V p-p
V
O
5.5
O
5.4
5.3
0.1
1
10
100
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 7. AD8051/AD8052 0.1 dB Gain Flatness vs.
Frequency; G = +2
TPC 10. AD8054 0.1 dB Gain Flatness vs.
Frequency; G = +2
9
9
8
V
V
= +5V
= 2V p-p
8
7
6
V
V
= +5V
= 2V p-p
S
S
O
O
7
6
5
4
3
5
V
V
= ؎5V
= 4V p-p
S
4
O
V
V
= ؎5V
= 4V p-p
S
3
O
V
AS SHOWN
V
AS SHOWN
S
S
2
2
1
G = +2
G = +2
R
R
V
= 2k⍀
= 2k⍀
AS SHOWN
R
R
V
= 2k⍀
= 2k⍀
AS SHOWN
L
F
L
F
1
0
O
0
O
–1
0.1
–1
0.1
1
10
FREQUENCY – MHz
100
500
1
10
100
500
FREQUENCY – MHz
TPC 8. AD8051/AD8052 Large Signal Frequency
Response; G = +2
TPC 11. AD8054 Large Signal Frequency
Response; G = +2
80
80
70
V
R
= +5V
= 2k⍀
V
R
C
= +5V
= 2k⍀
= 5pF
S
70
60
50
40
30
20
S
L
L
L
60
50
40
30
20
GAIN
GAIN
0
180
50؇ PHASE
MARGIN
–45
–90
–135
–180
135
90
PHASE
45؇ PHASE
MARGIN
PHASE
10
0
10
0
45
0
–10
–20
–10
–20
0.01
0.1
1
10
100
500
30k 100k
1M
10M
100M
500M
FREQUENCY – MHz
FREQUENCY – Hz
TPC 9. AD8051/AD8052 Open-Loop Gain and
Phase vs. Frequency
TPC 12. AD8054 Open-Loop Gain and Phase
Margin vs. Frequency
REV. F
–9–
AD8051/AD8052/AD8054
1000
100
10
؊20
V
= 2V p-p
V = +3V, G = ؊1
S
O
V
= +5V
S
R
= 2k⍀, R = 100⍀
F
L
؊30
؊40
V
R
= +5V, G = +2
S
= 2k⍀, R = 100⍀
F
L
V
R
= +5V, G = +1
= 100⍀
S
؊50
؊60
L
؊70
V
= +5V, G = +1
S
؊80
R
= 2k⍀
L
V
R
= +5V, G = +2
S
؊90
= 2k⍀, R = 2k⍀
F
L
؊100
؊110
1
10
1
2
3
4
5
6
7
8
9 10
100
1k
10k
100k
1M
10M
FUNDAMENTAL FREQUENCY – MHz
FREQUENCY – Hz
TPC 13. Total Harmonic Distortion
TPC 16. Input Voltage Noise vs. Frequency
؊30
؊40
100
V
= +5V
S
10MHz
؊50
؊60
10
؊70
؊80
5MHz
؊90
؊100
؊110
؊120
؊130
؊140
V
R
= +5V
= 2k⍀
S
1MHz
1
L
G = +2
0.1
10
0
0.5 1.0 1.5
2.0 2.5
3.0 3.5
OUTPUT VOLTAGE – V p-p
4.0
5.0
4.5
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 14. Worst Harmonic vs. Output Voltage
TPC 17. Input Current Noise vs. Frequency
0.10
0.10
R
= 150⍀
NTSC SUBSCRIBER (3.58MHz)
NTSC SUBSCRIBER (3.58MHz)
L
0.08
0.06
0.04
0.02
R
= 1k⍀
0.05
L
0.00
0.00
؊0.02
R
= 1k⍀
L
–0.05
V
= +5, G = +2
V
= +5, G = +2
S
S
R
= 2k⍀, R AS SHOWN
؊0.04
؊0.06
R = 150⍀
L
R
= 2k⍀, R AS SHOWN
F
L
F
L
–0.10
0
50
10
20
30
40
60
70
80
90 100
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
0.3
0.2
0.1
0.10
0.05
R
= 1k⍀
L
0.00
R
= 1k⍀
L
؊0.05
؊0.10
؊0.15
؊0.20
؊0.25
0.0
–0.1
–0.2
R
= 150⍀
L
V
R
R
= +5, G = +2
= 2k⍀,
AS SHOWN
S
V
R
= +5, G = +2
S
F
L
= 2k⍀, R AS SHOWN
R = 150⍀
L
F
L
–0.3
20
30
40
50
60
70
80
90 100
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
MODULATING RAMP LEVEL – IRE
0
10
MODULATING RAMP LEVEL – IRE
TPC 15. AD8051/AD8052 Differential Gain and
Phase Errors
TPC 18. AD8054 Differential Gain and
Phase Errors
–10–
REV. F
AD8051/AD8052/AD8054
–10
–20
–10
–20
V
R
R
= +5V
S
= 2k⍀
= 2k⍀
= 2V p-p
F
L
–30
–40
–30
–40
–50
–60
–70
–80
V
O
R
= 100⍀
L
–50
–60
–70
–80
–90
V
= ؎5V
R
= 1k⍀
S
L
R
R
= 1k⍀
= AS SHOWN
= 2V p-p
F
L
V
O
–90
–100
–110
–100
0.1
1
10
FREQUENCY – MHz
1
10
100
500
0.1
100
500
FREQUENCY – MHz
TPC 19. AD8052 Crosstalk (Output-to-Output) vs.
Frequency
TPC 22. AD8054 Crosstalk (Output-to-Output) vs.
Frequency
20
0
V
= +5V
V
= +5V
S
S
–10
–20
–30
–40
–50
–60
10
0
–10
–PSRR
+PSRR
–20
–30
–40
–50
–70
–80
–60
–70
–90
–100
0.03
–80
0.01
500
0.1
1
10
100
500
0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 20. CMRR vs. Frequency
TPC 23. PSRR vs. Frequency
70
100
31
V
= ؉5V
S
AD8051/AD8052
60
50
G = ؉1
10
AD8054
3.1
40
1
0.31
0.1
30
20
V
= ؉5V
S
10
0
0.031
0.01
G = ؊1
= 2k⍀
R
L
0.5
1
1.5
2
0.1
1
10
100
500
INPUT STEP – V p-p
FREQUENCY – MHz
TPC 21. Closed-Loop Output Resistance vs.
Frequency
TPC 24. Settling Time vs. Input Step
REV. F
–11–
AD8051/AD8052/AD8054
1.00
1.000
V
= +5V
S
V
= +85؇C
V
= +5V
OH
S
0.90
0.80
+5V – V
(+125؇C)
OH
0.875
0.750
0.625
0.500
V
= +25؇C
OH
0.70
0.60
0.50
0.40
+5V – V
(+25؇C)
OH
V
= –40؇C
OH
V
= +85؇C
OL
+5V – V
(–40؇C)
OH
0.375
0.250
0.125
0.00
0.30
0.20
V
= +25؇C
OL
V
(+125؇C)
V
= –40؇C
OL
OL
V
(+25؇C)
0.10
0
OL
V
(–40؇C)
OL
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT – mA
0
3
6
9
12
15
18
21
24
27
30
LOAD CURRENT – mA
TPC 25. AD8051/AD8052 Output Saturation
Voltage vs. Load Current
TPC 27. AD8054 Output Saturation Voltage vs.
Load Current
100
R
= 2k⍀
L
90
R
= 150⍀
L
80
70
V
= +5V
S
60
0
5.0
0.5
1.0 1.5
2.0 2.5
3.0 3.5
4.0 4.5
OUTPUT VOLTAGE – V
TPC 26. Open-Loop Gain vs. Output Voltage
–12–
REV. F
AD8051/AD8052/AD8054
5
2.5
1.50
Figure 3. 100 mV Step Response, G = +1
Figure 6. Output Swing; G = –1, RL = 2 kΩ
2.55
2.50
2.45
2.60
2.50
2.40
20ns
Figure 4. AD8051/AD8052 200 mV Step
Response; VS = +5 V, G = +1
Figure 7. AD8054 100 mV Step Response;
VS = +5 V, G = +1
4.5
3.5
2.5
1.5
0.5
4
3
2
1
؊1
؊2
؊3
؊4
20ns
500mV
Figure 5. Large Signal Step Response; VS = +5 V, G = +2
Figure 8. Large Signal Step Response;
VS = 5 V, G = +1
REV. F
–13–
AD8051/AD8052/AD8054
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this overdrive
condition. As shown in Figure 9, the AD8051/AD8052/AD8054
recovers within 60 ns from negative overdrive and within 45 ns
from positive overdrive.
2.60
2.55
2.50
2.45
2.40
Figure 11. AD8051/AD8052 200 mV Step
Response: CL = 50 pF
10000
1000
100
10
V
= +5V
S
Յ 30%
OVERSHOOT
R
= 3⍀
S
Figure 9. Overdrive Recovery
R
= 0⍀
S
Driving Capacitive Loads
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figures 10
and 11 show its frequency and time domain responses, respec-
tively, to a small-signal excitation. The capacitive load drive of
the AD8051/AD8052/AD8054 can be increased by adding a
low value resistor in series with the load. Figures 12 and 13
show the effect of a series resistor on the capacitive drive for
varying voltage gains. As the closed-loop gain is increased, the
larger phase margin allows for larger capacitive loads with less
peaking. Adding a series resistor with lower closed-loop gains
accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and the load capacitance.
R
R
G
F
R
S
V
IN
100mV STEP
50⍀
V
OUT
C
L
1
1
2
3
A
4
5
6
– V/V
CL
Figure 12. AD8051/AD8052 Capacitive Load Drive
vs. Closed-Loop Gain
1000
V
= +5V
S
Յ 30%
OVERSHOOT
8
6
R
= 10⍀
S
4
2
R
= 0⍀
S
100
0
؊2
؊4
R
R
G
F
R
S
V
IN
100mV STEP
50⍀
V
= +5V
V
OUT
S
؊6
؊8
C
G = +1
R
C
V
L
= 2k⍀
= 50pF
= 200mV p-p
L
L
10
O
1
2
3
A
4
5
6
؊10
– V/V
CL
500
0.1
1
10
100
Figure 13. AD8054 Capacitive Load Drive vs.
Closed-Loop Gain
FREQUENCY – MHz
Figure 10. AD8051/AD8052 Closed-Loop
Frequency Response: CL = 50 pF
Circuit Description
The AD8051/AD8052/AD8054 is fabricated on the Analog Devices
proprietary eXtra-Fast Complementary Bipolar (XFCB) process,
which enables the construction of PNP and NPN transistors
with similar fTs in the 2 GHz to 4 GHz region. The process is
dielectrically isolated to eliminate the parasitic and latch-up
–14–
REV. F
AD8051/AD8052/AD8054
problems caused by junction isolation. These features allow the
construction of high frequency, low distortion amplifiers with
low supply currents. This design uses a differential output input
stage to maximize bandwidth and headroom (see Figure 14).
The smaller signal swings required on the first stage outputs (nodes
SIP, SIN) reduce the effect of nonlinear currents due to junction
capacitances and improve the distortion performance. This
design achieves harmonic distortion of –80 dBc @ 1 MHz into
100 Ω with VOUT = 2 V p-p (Gain = +1) on a single 5 V supply.
minimum. Parasitic capacitance of less than 1 pF at the inverting
input can significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end.
Active Filters
Active filters at higher frequencies require wider bandwidth
op amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
The inputs of the device can handle voltages from –0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.
Figure 15 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not shown).
This circuit topology allows the AD8051/AD8052 to drive 45 mA
of output current and allows the AD8054 to drive 30 mA of
output current with the outputs within 0.5 V of the supply rails.
Note that the unused amplifier’s inputs should be tied to
ground.
R6
1k⍀
C1
50pF
13
12
R2
2k⍀
R4
2k⍀
14
C2
50pF
R1
3k⍀
R3
2k⍀
2
3
V
IN
R5
2k⍀
V
1
6
5
CC
7
9
I9
Q25
Q50
Q39
R26
Q4
R39
Q5
8
I10
I2
I3
Q36
I5
10
AD8054
Q51
AD8054
AD8054
Q23
V
Q40
EE
BAND-PASS
FILTER OUTPUT
R2
R15
Q13
Q22
R27
R23
Q21
V
EE
C3
C9
Q31
Q7
V
V
P
N
IN
Q1
V
OUT
Figure 15. 2 MHz Biquad Band-Pass Filter Using AD8054
Q27
IN
The frequency response of the circuit is shown in Figure 16.
SIP
SIN
0
؊10
؊20
؊30
؊40
Q2
Q8
Q11
R3
Q3
Q24
I7
Q47
I8
I11
V
C7
R21
R5
CC
V
EE
Figure 14. AD8051/AD8052 Simplified Schematic
APPLICATIONS
Layout Considerations
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low parasitic
component selection are necessary.
10k
100k
1M
10M
100M
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce parasitic capacitance.
FREQUENCY – Hz
Figure 16. Frequency Response of 2 MHz Band-
Pass Biquad Filter
Chip capacitors should be used for supply bypassing. One end
should be connected to the ground plane and the other within
3 mm of each power pin. An additional large (4.7 µF to 10 µF)
tantalum electrolytic capacitor should be connected in parallel,
but not necessarily so close, to supply current for fast, large
signal changes at the output.
A/D and D/A Applications
Figure 17 is a schematic showing the AD8051 used as a driver for
an AD9201, a 10-bit 20 MSPS dual A/D converter. This converter
is designed to convert I and Q signals in communications systems.
In this application, only the I channel is being driven. The I chan-
nel is enabled by applying a logic HIGH to SELECT, Pin 13.
The feedback resistor should be located close to the inverting
input pin to keep the parasitic capacitance at this node to a
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
REV. F
–15–
AD8051/AD8052/AD8054
CLK
SLEEP
INA-I
0.33F
0.01F
22⍀
؉V
DD
SELECT
+5V
10pF
1k⍀
22⍀
INB-I
10pF
10F
0.1F
AD9201
DATA OUT
REFT-I
D9
D8
D7
D6
22⍀
10F
0.1F
0.1F
0.1F
10F
REFB-I
AVSS
50⍀
AD8051
REFSENSE
VREF
1k⍀
1k⍀
D5
D4
0.1F
10F
0.1F
؊5V
AVDD
؉5V
D3
10F
0.1F
D2
REFB-Q
REFT-Q
0.1F
10F
0.1F
D1
0.1F
22⍀
D0
؉5V
DVDD
DVSS
INB-Q
10pF
0.1F
10F
22⍀
INA-Q
10pF
CHIP–SELECT
Figure 17. AD8051 Driving an AD9201, a 10-Bit 20 MSPS A/D Converter
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the A/D.
With the sampling clock running at 20 MSPS, the A/D output
was analyzed with a digital analyzer. Two input frequencies
were used, 1 MHz and 9.5 MHz, which is just short of the
Nyquist frequency. These signals were well filtered to minimize
any harmonics.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
Figure 18 shows the FFT response of the A/D for the case of
a 1 MHz analog input. The SFDR is –71.66 dB and the A/D is
producing 8.8 ENOB (effective number of bits). When the analog
frequency was raised to 9.5 MHz, the SFDR was reduced to
–60.18 dB and the A/D operated with 8.46 ENOBs as shown in
Figure 19. The inclusion of the AD8051 in the circuit did not
worsen the distortion performance of the AD9201.
The output of the op amp is ac-coupled into INA-I (Pin 16)
via two parallel capacitors to provide good high frequency and
low frequency coupling. The 1 kΩ resistor references the signal
to VREF that is applied to INB-I. Thus, INA-I swings both
positive and negative with respect to the bias voltage applied
to INB-I.
10
10
PART#
0
PART#
FFTSIZE 8192
0
FUND
FUND
FFTSIZE 8192
0
؊10
؊20
؊30
0
؊10
؊20
؊30
FCLK
FUND
20.0MHz
FCLK
FUND
VIN
20.0MHz
998.5kHz
؊0.51dB
؊68.13
54.97
9.5MHz
VIN
؊0.44dB
THD
THD
؊57.08
54.65
52.69
8.46
SNR
SNR
SINAD
ENOB
SFDR
54.76
SINAD
ENOB
SFDR
2ND
8.80
؊40
؊50
؊40
؊50
71.66
60.18
؊60.18
؊74.53
؊76.06
؊76.35
؊79.05
؊80.36
2ND
3RD
3RD
؊60.23
؊82.01
؊78.83
؊81.28
؊77.28
؊84.54
2ND
3RD
؊60
؊70
؊60
؊70
؊80
4TH
5TH
4TH
5TH
7TH
2ND
9TH
3RD
4TH
6TH
7TH
8TH
9TH
6TH
7TH
7TH
8TH
5TH
6TH
6TH
؊75.08
؊88.12
؊77.87
4TH
؊80
8TH
8TH
9TH
؊90
؊90
؊92.78
؊100
؊110
؊120
؊100
؊110
؊120
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
6
7
8
9
10
5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 18. FFT Plot for AD8051 Driving the AD9201
at 1 MHz
Figure 19. FFT Plot for AD8051 Driving the AD9201
at 9.5 MHz
–16–
REV. F
AD8051/AD8052/AD8054
Sync Stripper
duty cycle that is a small fraction of a percent, and the other
extreme defined by the opposite condition.
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as A/D conversion,
it is not desirable to have the sync pulses on the video signal.
These pulses reduce the dynamic range of the video signal and
do not provide any useful information for such a function.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video specifications.
The combination of horizontal and vertical blanking intervals
limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 20
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.
As a result of the duty cycles between the two extremes presented
above, a 1 V p-p composite video signal that is multiplied by a
gain of +2 requires about 3.2 V p-p of dynamic voltage swing at
the output for an op amp to pass a composite video signal of
arbitrarily varying duty cycle without distortion.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
V
GROUND
+0.4V
BLANK
Some circuits use a sync tip clamp to hold the sync tips at a relatively
constant level to lower the amount of dynamic signal swing
required. However, these circuits can have artifacts such as sync
tip compression unless they are driven by a source with a very
low output impedance. The AD8051/AD8052/AD8054 have
adequate signal swing when running on a single 5 V supply to handle
an ac-coupled composite video signal.
GROUND
+3V OR +5V
+
0.1F
10F
100⍀
V
IN
TO A/D
AD8051
R2
1k⍀
The input to the circuit in Figure 21 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
R1
1k⍀
+0.8V
(OR 2
؋
V )
BLANK
Figure 20. Sync Stripper
The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync pulses
stripped at the proper level.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values and
the cost of the capacitors can be reduced by as much as a factor
of five with minimum visible degradation in the picture.
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by 2 by
the amplifier. This level must be at ground at the output for the
sync stripping action to take place. Since the gain of the ampli-
fier from the input of R1 to the output is –1, a voltage equal to
2 × VBLANK must be applied to make the blanking level come
out at ground.
+5V
4.99k⍀
Single-Supply Composite Video Line Driver
+
10F
4.99k⍀
+
0.1F
10F
Many composite video signals have their blanking level at ground
and have video information that is both positive and negative.
Such signals require dual-supply amplifiers to pass them. However,
by ac level shifting, a single-supply amplifier can be used to
pass these signals. The following complications may arise from
such techniques.
COMPOSITE
47F
+
VIDEO
R
75⍀
BT
IN
1000F
R
+
T
V
OUT
10k⍀
AD8051
75⍀
R
L
75⍀
0.1F
R
F
1k⍀
R
1k⍀
G
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst case,
the dynamic signal swing will approach twice the peak-to-peak
value. The two conditions that define the maximum dynamic swing
requirements are a signal that is mostly low but goes high with a
220F
Figure 21. Single-Supply Composite Video Line Driver
REV. F
–17–
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
14-Lead Standard Small Outline Package [SOIC]
5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Narrow Body
(R-14)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
2.90 BSC
8.75 (0.3445)
8.55 (0.3366)
5
1
4
3
2.80 BSC
1.60 BSC
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
2
PIN 1
0.95 BSC
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
؋
45؇ 1.90
BSC
0.25 (0.0098)
0.10 (0.0039)
1.30
1.15
0.90
8؇
0؇
0.51 (0.0201)
0.31 (0.0122)
SEATING
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
1.45 MAX
0.22
0.08
PLANE
10؇
5؇
0؇
COMPLIANT TO JEDEC STANDARDS MS-012AB
0.15 MAX
0.60
0.45
0.30
0.50
0.30
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-178AA
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
3.00
BSC
5.00 (0.1968)
4.80 (0.1890)
8
5
4
4.90
BSC
3.00
BSC
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1
PIN 1
0.65 BSC
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
1.10 MAX
0.15
0.00
0.25 (0.0098)
0.10 (0.0040)
0.80
0.60
0.40
8؇
0؇
8؇
0.38
0.22
0.51 (0.0201)
0.31 (0.0122)
0.23
0.08
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012AA
COMPLIANT TO JEDEC STANDARDS MO-187AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–18–
REV. F
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.05
1.00
0.80
0.65
BSC
0.20
0.09
1.20
0.75
0.60
0.45
MAX
8؇
0؇
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
REV. F
–19–
AD8051/AD8052/AD8054
Revision History
Location
Page
9/04—Data Sheet changed from REV. E to REV. F.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/04—Data Sheet changed from REV. D to REV. E.
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2/03—Data Sheet changed from REV. C to REV. D.
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1/03—Data Sheet changed from REV. B to REV. C.
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
–20–
REV. F
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