AD8054ARU-REEL [ADI]
Low Cost, High Speed Rail-to-Rail Amplifiers; 低成本，高速轨到轨放大器
| 型号： | AD8054ARU-REEL |
| 厂家： | 
ADI |
| 描述： | Low Cost, High Speed Rail-to-Rail Amplifiers |
| 文件： | 总16页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, High Speed
Rail-to-Rail Amplifiers
a
AD8051/AD8052/AD8054
CONNECTION DIAGRAMS
(Top Views)
FEATURES
Low Cost Single (AD8051), Dual (AD8052) and Quad
(AD8054)
Voltage Feedback Architecture
Fully Specified at +3 V, +5 V and ؎5 V Supplies
Single Supply Operation
Output Swings to Within 25 mV of Either Rail
Input Voltage Range: –0.2 V to +4 V; VS = +5 V
High Speed and Fast Settling on +5 V:
110 MHz –3 dB Bandwidth (G = +1) (AD8051/AD8052)
150 MHz –3 dB Bandwidth (G = +1) (AD8054)
145 V/s Slew Rate
SO-8
SOT-23-5 (RT)
AD8051
AD8051
1
2
3
4
V
OUT
8
7
6
5
NC
+V
1
2
5 +V
S
NC
–IN
+IN
S
–V
S
+ –
V
OUT
+IN
3
4 –IN
–V
NC
S
NC = NO CONNECT
R-8, SOIC (RM)
R-14, TSSOP-14 (RU-14)
50 ns Settling Time to 0.1%
Small Packaging
AD8051 Available in SOT-23-5
AD8052 Available in SOIC-8
AD8052
1
2
3
4
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7
6
5
+V
S
OUT1
–IN1
+IN1
OUT D
OUT A
؊IN A
+IN A
V+
–
+
OUT
–IN2
+IN2
؊IN D
+IN D
–
+
AD8054 Available in TSSOP-14
AD8054
V؊
–V
S
Good Video Specifications (G = +2)
Gain Flatness of 0.1 dB to 20 MHz; RL = 150 ⍀
0.03% Differential Gain Error; RL = 1K
0.03؇ Differential Phase Error; RL = 1K
Low Distortion
–80 dBc Total Harmonic @ 1 MHz, RL = 100 ⍀
Outstanding Load Drive Capability
Drives 45 mA, 0.5 V from Supply Rails (AD8051/AD8052)
Drives 50 pF Capacitive Load (G = +1) (AD8051/AD8052)
Low Power of 2.75 mA/Amplifier (AD8054)
Low Power of 4.4 mA/Amplifier (AD8051/AD8052)
+IN C
+IN B
؊IN B
OUT B
؊IN C
8
OUT C
portable equipment. Low distortion and fast settling make them
ideal for active filter applications.
The AD8051/AD8052/AD8054 offer low power supply cur-
rent and can operate on a single +3 V power supply. These
features are ideally suited for portable and battery powered
applications where size and power are critical.
APPLICATIONS
Coax Cable Driver
Active Filters
Video Switchers
A/D Driver
The wide bandwidth and fast slew rate on a single +5 V supply
make these amplifiers useful in many general purpose, high speed
applications where dual power supplies of up to ±6 V and single
supplies from +3 V to +12 V are needed.
All of this low cost performance is offered in an 8-lead SOIC,
along with a tiny SOT-23-5 package (AD8051), a µSOIC
package (AD8052) and a TSSOP-14 (AD8054).
Professional Cameras
CCD Imaging Systems
CD/DVD ROM
5.0
4.5
PRODUCT DESCRIPTION
The AD8051 (single), AD8052 (dual) and AD8054 (quad) are
low cost, voltage feedback, high speed amplifiers designed to
operate on +3 V, +5 V or ±5 V supplies. They have true single
supply capability with an input voltage range extending 200 mV
below the negative rail and within 1 V of the positive rail.
V
= +5V
S
G = –1
R
4.0
3.5
3.0
2.5
2.0
= 2k⍀
F
L
R
= 2k⍀
Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output volt-
age swing extends to within 25 mV of each rail, providing the
maximum output dynamic range with excellent overdrive recov-
ery. This makes the AD8051/AD8052/AD8054 useful for video
electronics such as cameras, video switchers or any high speed
1.5
1.0
0.5
0
0.1
1
10
50
FREQUENCY – MHz
REV. B
Figure 1. Low Distortion Rail-to-Rail Output Swing
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD8051/AD8052/AD8054–SPECIFICATIONS (@ T = +25؇C, V = +5 V, R = 2 k⍀ to +2.5 V,
unless otherwise noted)
A
S
L
AD8051A/AD8052A
Typ
AD8054A
Parameter
Conditions
Min
Max Min
Typ
Max Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to +2.5 V,
70
110
50
80
150
60
MHz
MHz
Bandwidth for 0.1 dB Flatness
RF = 806 Ω for AD8051A/AD8052A
RF = 200 Ω for AD8054A
G = –1, VO = 2 V Step
20
MHz
MHz
V/µs
MHz
ns
12
Slew Rate
100
145
35
140
170
45
Full Power Response
Settling Time to 0.1%
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
50
40
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
Input Voltage Noise
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
–67
16
–68
16
dB
nV/√Hz
fA/√Hz
%
Input Current Noise
f = 10 kHz
850
0.09
0.03
0.19
0.03
–60
850
0.07
0.02
0.26
0.05
–60
Differential Gain Error (NTSC)
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
f = 5 MHz, G = +2
%
Differential Phase Error (NTSC)
Crosstalk
Degrees
Degrees
dB
DC PERFORMANCE
Input Offset Voltage
1.7
10
25
1.7
12
30
mV
mV
µV/°C
µA
TMIN –TMAX
Offset Drift
10
15
2
Input Bias Current
1.4
2.5
4.5
4.5
1.2
TMIN –TMAX
3.25
0.75
82
µA
Input Offset Current
Open-Loop Gain
0.1
98
96
82
78
0.2
98
96
82
78
µA
RL = 2 kΩ to +2.5 V
TMIN –TMAX
86
76
dB
dB
RL = 150 Ω to +2.5 V
TMIN –TMAX
74
dB
dB
INPUT CHARACTERISTICS
Input Resistance
290
300
1.5
kΩ
pF
V
Input Capacitance
1.4
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
–0.2 to 4
88
–0.2 to 4
86
VCM = 0 V to +3.5 V
72
70
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L = 10 kΩ to +2.5 V
0.015 to 4.985
0.03 to 4.975
V
RL = 2 kΩ to +2.5 V
RL = 150 Ω to +2.5 V
VOUT = 0.5 V to +4.5 V
TMIN –TMAX
0.1 to 4.9
0.025 to 4.975
0.125 to 4.875 0.05 to 4.95
V
0.3 to 4.625 0.2 to 4.8
0.55 to 4.4
0.25 to 4.65
V
Output Current
45
30
30
45
85
mA
mA
mA
mA
pF
pF
45
80
Short Circuit Current
Capacitive Load Drive
Sourcing
Sinking
130
50
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
40
POWER SUPPLY
Operating Range
3
12
5
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
4.4
2.75
80
3.275 mA
dB
∆VS = ±1 V
70
80
68
OPERATING TEMPERATURE RANGE
–40
+85 –40
+85 °C
NOTES
1Refer to Figure 15.
Specifications subject to change without notice.
–2–
REV. B
AD8051/AD8052/AD8054
(@ TA = +25؇C, VS = +3 V, RL = 2 k⍀ to +1.5 V, unless otherwise noted)
SPECIFICATIONS
AD8051A/AD8052A
Typ
AD8054A
Typ
Parameter
Conditions
Min
Max Min
Max Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
70
110
50
80
135
65
MHz
MHz
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V,
Bandwidth for 0.1 dB Flatness
RF = 402 Ω for AD8051A/AD8052A
17
MHz
MHz
V/µs
MHz
ns
R
F = 200 Ω for AD8054A
10
150
85
Slew Rate
Full Power Response
Settling Time to 0.1%
G = –1, VO = 2 V Step
G = +1, VO = 1 V p-p
G = –1, VO = 2 V Step
90
135
65
55
110
55
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion1
fC = 5 MHz, VO = 2 V p-p,
G = –1, RL = 100 Ω to +1.5 V
f = 10 kHz
–47
16
600
–48
16
600
dB
nV/√Hz
fA/√Hz
Input Voltage Noise
Input Current Noise
f = 10 kHz
Differential Gain Error (NTSC)
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V,
0.11
0.09
0.13
0.09
%
%
R
L = 1 kΩ to +1.5 V
Differential Phase Error (NTSC)
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V
0.24
0.10
–60
0.3
0.1
–60
Degrees
Degrees
dB
R
L = 1 k Ω to +1.5 V
Crosstalk
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
1.6
10
25
1.6
12
30
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
T
MIN –TMAX
Offset Drift
Input Bias Current
10
1.3
15
2
2.6
3.25
0.8
80
4.5
4.5
1.2
TMIN –TMAX
Input Offset Current
Open-Loop Gain
0.15
96
94
82
76
0.2
96
94
80
76
RL = 2 kΩ
T
RL = 150 Ω
TMIN –TMAX
80
74
MIN –TMAX
72
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
290
1.4
–0.2 to 2
88
300
1.5
–0.2 to 2
86
kΩ
pF
V
VCM = 0 V to 1.5 V
72
70
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L = 10 kΩ to +1.5 V
0.01 to 2.99
0.075 to 2.9 0.02 to 2.98
0.025 to 2.98
0.35 to 2.965
V
V
RL = 2 kΩ to +1.5 V
0.1 to 2.9
R
V
L = 150 Ω to +1.5 V
OUT = 0.5 V to +2.5 V
0.2 to 2.75 0.125 to 2.875
0.35 to 2.55 0.15 to 2.75
V
Output Current
45
45
60
90
45
25
25
30
50
mA
mA
mA
mA
pF
pF
TMIN –TMAX
Sourcing
Sinking
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
Short Circuit Current
Capacitive Load Drive
35
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
4.2
80
4.8
2.625
80
3.125 mA
dB
∆VS = +0.5 V
68
68
OPERATING TEMPERATURE RANGE
–40
+85 –40
+85 °C
NOTES
1Refer to Figure 15.
Specifications subject to change without notice.
REV. B
–3–
(@ TA = +25؇C, VS = ؎5 V, RL = 2 k⍀ to Ground,
unless otherwise noted)
AD8051/AD8052/AD8054–SPECIFICATIONS
AD8051A/AD8052A
AD8054A
Typ
Parameter
Conditions
Min
Typ
Max Min
Max Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω,
70
110
50
85
160
65
MHz
MHz
Bandwidth for 0.1 dB Flatness
R
F = 1.1 kΩ for AD8051A/AD8052A
20
MHz
MHz
V/µs
MHz
ns
RF = 200 Ω for AD8054A
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
15
Slew Rate
105
170
40
150
190
50
Full Power Response
Settling Time to 0.1%
50
40
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
–71
16
–72
16
dB
nV/√Hz
fA/√Hz
%
Input Current Noise
f = 10 kHz
900
0.02
0.02
0.11
0.02
–60
900
0.06
0.02
0.15
0.03
–60
Differential Gain Error (NTSC)
G = +2, RL = 150 Ω
R
L = 1 kΩ
%
Differential Phase Error (NTSC)
Crosstalk
G = +2, RL = 150 Ω
RL = 1 kΩ
Degrees
Degrees
dB
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
1.8
11
27
1.8
13
32
mV
mV
µV/°C
µA
TMIN –TMAX
Offset Drift
10
15
2
Input Bias Current
1.4
2.6
3.5
0.75
84
4.5
4.5
1.2
TMIN –TMAX
µA
Input Offset Current
Open-Loop Gain
0.1
96
96
82
80
0.2
96
96
82
80
µA
RL = 2 kΩ
88
78
dB
TMIN –TMAX
RL = 150 Ω
TMIN –TMAX
dB
76
dB
dB
INPUT CHARACTERISTICS
Input Resistance
290
300
kΩ
pF
V
Input Capacitance
1.4
1.5
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
–5.2 to 4
88
–5.2 to 4
86
VCM = –5 V to +3.5 V
72
70
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 10 kΩ
RL = 2 kΩ
–4.98 to +4.98
–4.97 to +4.97
V
–4.85 to +4.85 –4.97 to +4.97
–4.8 to +4.8 –4.9 to +4.9
V
R
L = 150 Ω
–4.45 to +4.3 –4.6 to +4.6
–4.0 to +3.8 –4.5 to +4.5
V
Output Current
VOUT = –4.5 V to +4.5 V
TMIN –TMAX
45
30
mA
mA
mA
mA
pF
pF
45
30
Short Circuit Current
Capacitive Load Drive
Sourcing
100
160
50
60
Sinking
100
G = +1 (AD8051/AD8052)
G = +2 (AD8054)
40
POWER SUPPLY
Operating Range
3
12
3
12
V
Quiescent Current/Amplifier
Power Supply Rejection Ratio
4.8
5.5
2.875
3.4
mA
dB
∆VS = ±1 V
68
80
68
80
OPERATING TEMPERATURE RANGE
–40
+85 –40
+85 °C
Specifications subject to change without notice.
–4–
REV. B
AD8051/AD8052/AD8054
ABSOLUTE MAXIMUM RATINGS1
plastic encapsulated devices is determined by the glass transi-
tion temperature of the plastic, approximately +150°C. Tempo-
rarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die by
the package. Exceeding a junction temperature of +175°C for an
extended period can result in device failure.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Small Outline Package (R) . . . Observe Power Derating Curves
SOT-23-5 Package . . . . . . . . Observe Power Derating Curves
µSOIC Package . . . . . . . . . . Observe Power Derating Curves
TSSOP-14 Package . . . . . . . Observe Power Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±2.5 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
While the AD8051/AD8052/AD8054 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to ob-
serve the maximum power derating curves.
2.0
14-LEAD SOIC
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
8-Lead SOIC: θJA = 155°C/W
5-Lead SOT-23-5: θJA = 240°C/W
8-Lead µSOIC: θJA = 200°C/W
14-Lead SOIC: θJA = 120°C/W
1.5
8-LEAD SOIC
PACKAGE
T
= +150؇C
J
14-LEAD TSSOP-14
1.0
0.5
0
SOIC
SOT-23-5
14-Lead TSSOP: θJA = 180°C/W
MAXIMUM POWER DISSIPATION
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
The maximum power that can be safely dissipated by the AD8051/
AD8052/AD8054 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054
ORDERING GUIDE
Temperature
Range
Package
Descriptions
Package
Options* Code
Brand
Model
AD8051AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
SO-8
AD8051AR-REEL
AD8051AR-REEL7
AD8051ART-REEL
13" Tape and Reel SO-8
7" Tape and Reel SO-8
13" Tape and Reel RT-5
H2A
H2A
AD8051ART-REEL7 –40°C to +85°C
7" Tape and Reel
RT-5
AD8052AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
13" Tape and Reel SO-8
7" Tape and Reel
8-Lead µSOIC
SO-8
AD8052AR-REEL
AD8052AR-REEL7
AD8052ARM
SO-8
RM-8
H4A
H4A
H4A
AD8052ARM-REEL
13" Tape and Reel RM-8
AD8052ARM-REEL7 –40°C to +85°C
7" Tape and Reel
RM-8
AD8054AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
14-Lead SOIC
13" Tape and Reel R-14
7" Tape and Reel
14-Lead µSOIC
R-14
AD8054AR-REEL
AD8054AR-REEL7
AD8054ARU
R-14
RU-14
AD8054ARU-REEL
13" Tape and Reel RU-14
AD8054ARU-REEL7 –40°C to +85°C
7" Tape and Reel RU-14
*R = Small Outline; RM = Micro Small Outline; RT = Surface Mount; RU = TSSOP .
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8051/AD8052/AD8054 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD8051/AD8052/AD8054
3
5
4
3
2
1
V
= +5V
G = +1
= 0
S
2
1
G = +2
= 2k⍀
G = +2
R
GAIN AS SHOWN
F
R
F
R
= 2k⍀
F
R
R
V
AS SHOWN
= 5k⍀
F
L
= 0.2V p-p
0
–1
–2
O
G = +5
R
= 2k⍀
F
0
–1
–2
–3
G = +1
= 0
G = +10
= 2k⍀
R
F
R
F
G = +10
= 2k⍀
–3
–4
–5
R
F
V
= +5V
S
GAIN AS SHOWN
R
–4
–5
–6
–7
AS SHOWN
F
R
= 2k⍀
L
G = +5
= 2k⍀
V
= 0.2V p-p
–6
–7
O
R
F
0.1
1
10
FREQUENCY – MHz
100
500
1M
500M
100k
10M
FREQUENCY – Hz
100M
Figure 3. AD8051/AD8052 Normalized Gain vs.
Frequency; VS = +5 V
Figure 6. AD8054 Normalized Gain vs. Frequency;
VS = +5 V
3
2
6
5
4
+3V
+5V
؎5V
V
= +3V
V
= +5V
S
S
G = +1
1
0
R
C
= 2k⍀
= 5pF
L
L
3
2
V
= 0.2V p-p
O
–1
V
= ؎5V
S
–2
–3
–4
–5
1
0
V
AS SHOWN
S
G = +1
R
= 2k⍀
= 0.2V p-p
L
V
O
؎5V
–1
–2
–3
–4
+3V
+5V
–6
–7
0.1
1
10
FREQUENCY – MHz
100
500
100k
1M
10M
100M
500M
FREQUENCY – Hz
Figure 7. AD8054 Gain vs. Frequency vs. Supply
Figure 4. AD8051/AD8052 Gain vs. Frequency
vs. Supply
3
2
4
+85؇C
3
+25؇C
–40؇C
1
2
–40؇C
0
1
0
+85؇C
–1
+25؇C
–2
–3
V
= +5V
–1
–2
S
R
C
= 2k⍀ TO 2.5V
= 5pF
L
V
= +5V
S
L
–4
–5
G = +1
R
G = +1
= 0.2V p-p
= 2k⍀
= 0.2V p-p
–3
–4
–5
V
L
O
V
O
–6 TEMPERATURE AS SHOWN
–7
0.1
1
10
100
500
1
10
100
500
FREQUENCY – MHz
FREQUENCY – MHz
Figure 5. AD8051/AD8052 Gain vs. Frequency vs.
Temperature
Figure 8. AD8054 Gain vs. Frequency vs. Temperature
–6–
REV. B
AD8051/AD8052/AD8054
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
6.3
6.2
6.1
6.0
5.9
5.8
V
= +5V
S
R
R
= 200⍀
= 150⍀
F
V
= +5V
S
5.7
5.6
G = +2
R
R
L
= 150⍀
= 806⍀
= 0.2V p-p
G = +2
V = 0.2V p-p
O
L
F
5.5
V
O
5.4
5.3
1
10
100
0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. AD8051/AD8052 0.1 dB Gain Flatness vs.
Frequency; G = +2
Figure 12. AD8054 0.1 dB Gain Flatness vs. Frequency;
G = +2
9
9
V
V
= +5V
= 2V p-p
V
V
= +5V
= 2V p-p
8
7
6
8
7
S
S
O
O
6
5
5
4
3
V
V
= ؎5V
= 4V p-p
S
4
O
V
V
= ؎5V
= 4V p-p
S
3
O
V
AS SHOWN
V AS SHOWN
S
G = +2
S
2
2
1
G = +2
R
R
V
= 2k⍀
= 2k⍀
AS SHOWN
R
R
V
= 2k⍀
= 2k⍀
AS SHOWN
O
L
F
L
1
F
0
0
O
–1
0.1
–1
0.1
1
10
100
500
1
10
FREQUENCY – MHz
100
500
FREQUENCY – MHz
Figure 10. AD8051/AD8052 Large Signal Frequency
Response; G = +2
Figure 13. AD8054 Large Signal Frequency Response;
G = +2
80
80
V
= +5V
V
= +5V
= 2k⍀
= 5pF
S
70
60
50
40
30
20
S
70
R
= 2k⍀
R
C
L
L
L
60
50
40
30
20
GAIN
GAIN
0
180
50؇ PHASE
MARGIN
–45
–90
–135
–180
135
90
PHASE
45؇ PHASE
MARGIN
PHASE
10
0
10
0
45
0
–10
–20
–10
–20
0.01
0.1
1
10
100
500
30k 100k
1M
10M
100M
500M
FREQUENCY – MHz
FREQUENCY – Hz
Figure 11. AD8051/AD8052 Open-Loop Gain and
Phase vs. Frequency
Figure 14. AD8054 Open-Loop Gain and Phase
Margin vs. Frequency
REV. B
–7–
AD8051/AD8052/AD8054
1000
100
10
؊20
V
= 2V p-p
V = +3V, G = ؊1
S
V
= +5V
O
S
R
= 2k⍀, R = 100⍀
L
F
؊30
؊40
V
R
= +5V, G = +2
S
= 2k⍀, R = 100⍀
F
L
V
= +5V, G = +1
S
؊50
؊60
R
= 100⍀
L
؊70
V
= +5V, G = +1
S
؊80
R
= 2k⍀
L
V
R
= +5V, G = +2
= 2k⍀, R = 2k⍀
L
S
؊90
F
؊100
؊110
1
10
1
2
3
4
5
6
7
8
9 10
100
1k
10k
100k
1M
10M
FUNDAMENTAL FREQUENCY – MHz
FREQUENCY – Hz
Figure 18. Input Voltage Noise vs. Frequency
Figure 15. Total Harmonic Distortion
؊30
100
V
= +5V
S
؊40
؊50
10MHz
؊60
10
؊70
؊80
5MHz
؊90
؊100
؊110
؊120
؊130
؊140
V
R
= +5V
= 2k⍀
S
1MHz
1
L
G = +2
0.1
10
0
0.5 1.0 1.5
2.0 2.5
3.0 3.5
OUTPUT VOLTAGE – V p-p
4.0
5.0
4.5
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 16. Worst Harmonic vs. Output Voltage
Figure 19. Input Current Noise vs. Frequency
0.10
0.10
R
= 150⍀
NTSC SUBSCRIBER (3.58MHz)
NTSC SUBSCRIBER (3.58MHz)
L
0.08
0.06
0.04
0.02
R
= 1k⍀
0.05
L
0.00
0.00
؊0.02
؊0.04
؊0.06
R
= 1k⍀
L
–0.05
V
R
= +5, G = +2
V
= +5, G = +2
S
S
= 2k⍀, R AS SHOWN
R
= 150⍀
F
L
R
= 2k⍀, R AS SHOWN
L
F
L
–0.10
0
50
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
10
20
30
40
60
70
80
90 100
0.3
0.2
0.1
0.10
0.05
R
= 1k⍀
L
0.00
R
= 1k⍀
L
؊0.05
؊0.10
؊0.15
؊0.20
؊0.25
0.0
–0.1
–0.2
R
= 150⍀
L
V
R
R
= +5, G = +2
= 2k⍀,
AS SHOWN
S
V
= +5, G = +2
S
F
L
R
= 150⍀
R
= 2k⍀, R AS SHOWN
L
L
F
–0.3
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
MODULATING RAMP LEVEL – IRE
20
30
40
50
60
70
80
90 100
0
10
MODULATING RAMP LEVEL – IRE
Figure 17. AD8051/AD8052 Differential Gain and Phase
Errors
Figure 20. AD8054 Differential Gain and Phase Errors
–8–
REV. B
AD8051/AD8052/AD8054
–10
–20
–10
–20
V
= +5V
S
R
R
= 2k⍀
= 2k⍀
= 2V p-p
F
L
–30
–40
–30
–40
–50
–60
–70
–80
V
O
R
= 100⍀
L
–50
–60
–70
–80
–90
V
= ؎5V
R
= 1k⍀
S
L
R
R
= 1k⍀
= AS SHOWN
= 2V p-p
F
L
V
O
–90
–100
–110
–100
0.1
1
10
100
500
1
10
FREQUENCY – MHz
0.1
100
500
FREQUENCY – MHz
Figure 24. AD8054 Crosstalk (Output-to-Output) vs.
Frequency
Figure 21. AD8052 Crosstalk (Output-to-Output) vs.
Frequency
20
0
V
= +5V
V
= +5V
S
S
–10
–20
–30
–40
–50
–60
10
0
–10
–PSRR
+PSRR
–20
–30
–40
–50
–70
–80
–60
–70
–90
–100
–80
0.03
500
0.01
0.1
1
10
100
500
0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
Figure 25. PSRR vs. Frequency
Figure 22. CMRR vs. Frequency
100
31
70
V
= ؉5V
S
AD8051/AD8052
60
50
G = ؉1
10
AD8054
3.1
40
1
0.31
0.1
30
20
V
= ؉5V
S
10
0
0.031
0.01
G = ؊1
= 2k⍀
R
L
0.1
1
10
100
500
0.5
1
1.5
2
INPUT STEPS – Volts p-p
FREQUENCY – MHz
Figure 23. Closed Loop Output Resistance vs. Frequency
Figure 26. Settling Time vs. Input Step
REV. B
–9–
AD8051/AD8052/AD8054
1.00
1.00
V
= +5V
V = +5V
S
S
V
= +85؇C
OH
0.90
0.80
+5V –V
(+125؇C)
0.875
0.750
0.625
0.500
OH
V
= +25؇C
OH
+5V –V
(+25؇C)
0.70
0.60
0.50
0.40
OH
V
= –40؇C
OH
V
= +85؇C
OL
+5V –V
(–55؇C)
OH
0.375
0.250
0.125
0.00
0.30
0.20
V
= +25؇C
OL
V
(+125؇C)
OL
V
= –40؇C
OL
V
(+25؇C)
0.10
0
OL
V
(–55؇C)
OL
0
3
6
9
12
15
18
21
24
27
30
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT – mA
LOAD CURRENT – mA
Figure 27. AD8051/AD8052 Output Saturation Voltage vs.
Load Current
Figure 29. AD8054 Output Saturation Voltage vs. Load
Current
100
R
= 2k⍀
L
90
R
= 150⍀
L
80
70
V
= +5V
S
60
0
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
OUTPUT VOLTAGE – Volts
Figure 28. Open-Loop Gain vs. Output Voltage
–10–
REV. B
AD8051/AD8052/AD8054
5
2.5
1.50V
Figure 33. Output Swing; G = –1, RL = +2 kΩ
Figure 30. 100 mV Step Response, G = +1
2.55
2.50
2.45
2.60
2.50
2.40
20ns
Figure 34. AD8054 100 mV Step Response; VS = +5 V,
G = +1
Figure 31. AD8051/AD8052 200 mV Step Response;
VS = +5 V, G = +1
4
3
2
3.5
2.5
1.5
1
؊1
؊2
؊3
؊4
Figure 32. Large Signal Step Response; VS = +5 V, G = +2
Figure 35. Large Signal Step Response; VS = ±5 V, G = +1
REV. B
–11–
AD8051/AD8052/AD8054
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 36, the AD8051/AD8052/
AD8054 recovers within 60 ns from negative overdrive and
within 45 ns from positive overdrive.
2.60
2.55
2.50
2.45
2.40
Figure 38. AD8051/AD8052 200 mV Step Response:
CL = 50 pF
10000
V
= +5V
S
Յ 30%
OVERSHOOT
R
= 3⍀
S
Figure 36. Overdrive Recovery
1000
100
10
R
= 0⍀
Driving Capacitive Loads
S
Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figures 37
and 38 show its frequency and time domain responses, respec-
tively, to a small-signal excitation. The capacitive load drive of
the AD8051/AD8052/AD8054 can be increased by adding a
low valued resistor in series with the load. Figures 39 and 40
show the effect of a series resistor on capacitive drive for varying
voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less peak-
ing. Adding a series resistor with lower closed-loop gains ac-
complishes the same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and the load capacitance.
R
R
G
F
R
S
V
IN
V
OUT
100mV STEP
50⍀
C
L
1
1
2
3
4
5
6
A
– V/V
CL
Figure 39. AD8051/AD8052 Capacitive Load Drive vs.
Closed-Loop Gain
8
6
1000
V
= +5V
S
4
Յ 30%
OVERSHOOT
2
R
= 10⍀
S
0
؊2
؊4
R
= 0⍀
S
100
V
= +5V
S
؊6
؊8
G = +1
R
R
G
F
R
C
V
= 2k⍀
= 50pF
= 200mV p-p
L
L
R
S
V
IN
100mV STEP
50⍀
V
O
OUT
؊10
C
L
500
0.1
1
10
100
10
FREQUENCY – MHz
1
2
3
4
5
6
A
– V/V
CL
Figure 37. AD8051/AD8052 Closed-Loop Frequency
Response: CL = 50 pF
Figure 40. AD8054 Capacitive Load Drive vs. Closed-Loop
Gain
Circuit Description
The AD8051/AD8052/AD8054 is fabricated on Analog Devices’
proprietary eXtra-Fast Complementary Bipolar (XFCB) pro-
cess, which enables the construction of PNP and NPN transis-
tors with similar fTs in the 2 GHz–4 GHz region. The process is
dielectrically isolated to eliminate the parasitic and latch-up
–12–
REV. B
AD8051/AD8052/AD8054
problems caused by junction isolation. These features allow the
construction of high frequency, low distortion amplifiers with low
supply currents. This design uses a differential output input stage
to maximize bandwidth and headroom (see Figure 1). The smaller
signal swings required on the first stage outputs (nodes S1P, S1N)
reduce the effect of nonlinear currents due to junction capacitances
and improve the distortion performance. With this design har-
to a minimum. Parasitic capacitance of less than 1 pF at the
inverting input can significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Active Filters
monic distortion of –80 dBc @ 1 MHz into 100 Ω with VOUT
=
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
2 V p-p (Gain = +1) on a single 5 V supply is achieved.
The inputs of the device can handle voltages from –0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.
Figure 42 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.
Please note that the unused amplifiers’ inputs should be tied to
ground.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all out-
put stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to drive
45 mA of output current and the AD8054 to drive 30 mA of out-
put current with the outputs within 0.5 V of the supply rails.
R6
1k⍀
C1
50pF
13
12
R2
R4
2k⍀
14
C2
2k⍀
R1
3k⍀
50pF
R3
2k⍀
2
3
V
IN
R5
2k⍀
1
6
5
7
9
V
CC
8
V
I9
OUT
Q25
AD8054
10
Q50
Q39
R26
Q4
R39
Q5
I10
I2
I3
AD8054
Q36
I5
AD8054
Q51
Q23
V
Q40
EE
Figure 42. 2 MHz Biquad Bandpass Filter Using AD8054
R2
R15
Q13
Q22
R27
R23
Q21
V
EE
The frequency response of the circuit is shown in Figure 43.
C3
C9
Q31
Q7
V
V
P
N
IN
Q1
V
OUT
Q27
IN
SIP
SIN
0
؊10
؊20
؊30
؊40
Q2
Q8
Q11
R3
Q3
Q24
I7
Q47
I8
I11
V
C7
R21
R5
CC
V
EE
Figure 41. AD8051/AD8052 Simplified Schematic
APPLICATIONS
Layout Considerations
The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low-parasitic
component selection are necessary.
10k
100k
1M
10M
100M
FREQUENCY – Hz
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the parasitic capacitance.
Figure 43. Frequency Response of 2 MHz Bandpass
Biquad Filter
A/D and D/A Applications
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 3 mm of each power pin. An additional large (4.7 µF to
10 µF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
Figure 44 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit 20 MSPS dual A/D converter. This
converter is designed to convert I and Q signals in communica-
tion systems. In this application, only the I channel is being
driven. The I channel is enabled by applying a logic HIGH to
SELECT, Pin 27.
The feedback resistor should be located close to the inverting
input pin in order to keep the parasitic capacitance at this node
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and
REV. B
–13–
AD8051/AD8052/AD8054
CLK
SLEEP
INA-I
0.33F
0.01F
22⍀
؉V
SELECT
DD
+5V
10pF
1k⍀
22⍀
INB-I
10pF
10F
0.1F
AD9201
DATA OUT
REFT-I
D9
D8
D7
D6
D5
D4
D3
D2
22⍀
10F
0.1F
0.1F
0.1F
10F
REFB-I
50⍀
AD8051
AVSS
REFSENSE
1k⍀
1k⍀
V
REF
0.1F
10F
0.1F
؊5V
AVDD
؉5V
10F
0.1F
REFB-Q
REFT-Q
0.1F
10F
0.1F
D1
D0
0.1F
22⍀
؉5V
DVDD
DVSS
INB-Q
10pF
0.1F
10F
22⍀
INA-Q
10pF
THREE–STATE
Figure 44. AD8051 Driving an AD9201, a 10-Bit 20 MSPS A/D Converter
applied to the noninverting input of the AD8051. The amplifier
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the A/D.
positive and negative with respect to the bias voltage applied to
INB-I.
With the sampling clock running at 20 MSPS, the A/D output
was analyzed with a digital analyzer. Two input frequencies
were used, 1 MHz and 9.5 MHz, which is just short of the
Nyquist frequency. These signals were well filtered to minimize
any harmonics.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 8) which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low pass filter that
also helps to reduce distortion.
Figure 45 shows the FFT response of the A/D for the case of
1 MHz analog input. The SFDR is 71.66 dB and the A/D is
producing 8.8 ENOB (effective number of bits). When the
analog frequency was raised to 9.5 MHz, the SFDR was re-
duced to 60.18 dB and the A/D operated with 8.46 ENOBs as
shown in Figure 46. The inclusion of the AD8051 in the circuit
had no worsening of the distortion performance of the AD9201.
The output of the op amp is ac coupled into INA-I (Pin 2) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I will swing both
10.0
10.0
PART#
FFTSIZE 8192
0
PART#
0
5.0
0.0
5.0
0.0
FUND
FUND
FFTSIZE 8192
FCLK
FUND
VIN
20.0E؉6
؊5.0
؊10.0
؊15.0
FCLK
FUND
20.0E؉6
؊5.0
9.5E؉6
؊10.0
؊15.0
؊20.0
؊25.0
؊30.0
؊35.0
؊40.0
؊45.0
؊50.0
؊55.0
؊60.0
؊65.0
؊70.0
؊75.0
؊80.0
؊85.0
؊90.0
؊95.0
؊100.0
؊105.0
؊110.0
؊115.0
؊120.0
998.5E؉3
؊0.51dB
؊68.13
54.97
؊0.44dB
VIN
؊20.0
؊25.0
؊30.0
THD
؊57.08
54.65
THD
SNR
SNR
SINAD
ENOB
SFDR
2ND
52.69
SINAD
ENOB
SFDR
54.76
؊35.0
؊40.0
؊45.0
؊50.0
8.46
8.80
؊60.18
؊60.18
؊71.66
؊74.53
؊76.06
؊76.35
؊79.05
؊80.36
2ND
3RD
؊55.0
؊60.0
؊65.0
3RD
؊60.23
؊82.01
؊78.83
؊81.28
؊77.28
؊84.54
2ND
3RD
4TH
5TH
4TH
5TH
؊70.0
؊75.0
؊80.0
؊85.0
7TH
6TH
7TH
8TH
9TH
2ND
9TH
7TH
4TH
6TH
7TH
3RD
8TH
6TH
6TH
4TH
5TH
؊75.08
؊88.12
؊77.87
8TH
8TH
9TH
؊90.0
؊95.0
؊92.78
؊100.0
؊105.0
؊110.0
؊115.0
؊120.0
0.0E؉0
2.0E؉6
4.0E؉6
6.0E؉6
8.0E؉6
10.0E؉6
9.0E؉6
0.0E؉0
2.0E؉6
4.0E؉6
6.0E؉6
8.0E؉6
10.0E؉6
9.0E؉6
1.0E؉6
3.0E؉6
5.0E؉6
7.0E؉6
1.0E؉6
3.0E؉6
5.0E؉6
7.0E؉6
Figure 46. FFT Plot for AD8051 Driving the AD9201 at
9.5 MHz
Figure 45. FFT Plot for AD8051 Driving the AD9201 at
1 MHz
–14–
REV. B
AD8051/AD8052/AD8054
Sync Stripper
goes high with a duty cycle that is a small fraction of a percent.
The opposite condition defines the other extreme.
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, like A/D conversion,
it is not desirable to have the sync pulses on the video signal.
These pulses will reduce the dynamic range of the video signal
and do not provide any useful information for such a function.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame, but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal will have negative-going
excursions is compliance with the composite video specifica-
tions. The combination of horizontal and vertical blanking inter-
vals limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.
A sync stripper will remove the synchronizing pulses from a
video signal while passing all the useful video information. Fig-
ure 47 shows a practical single supply circuit that uses only a
single AD8051. It is capable of directly driving a reverse termi-
nated video line.
As a result of the duty cycles between the two extremes pre-
sented above, a 1 V p-p composite video signal that is multiplied
by a gain of two requires about 3.2 V p-p of dynamic voltage
swing at the output for an op amp to pass a composite video
signal of arbitrary varying duty cycle without distortion.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
V
GROUND
+0.4V
BLANK
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level in order to lower the amount of dynamic
signal swing required. However, these circuits can have artifacts
like sync tip compression unless they are driven by a source with
a very low output impedance. The AD8051/AD8052/AD8054
have adequate signal swing when running on a single +5 V
supply to handle an ac coupled composite video signal.
GROUND
+3V OR +5V
+
0.1F
10F
100⍀
V
IN
TO A/D
AD8051
R2
1k⍀
The input to the circuit in Figure 48 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac cou-
pling. The noninverting input of the op amp is biased to half of
the supply voltage.
R1
1k⍀
+0.8V
(OR 2
؋
V )
BLANK
Figure 47. Sync Stripper
The feedback circuit provides unity gain for the dc biasing of the
input, and provides a gain of two for any signals that are in the
video bandwidth. The output is ac coupled and terminated to
drive the line.
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to
two via the two 1 kΩ resistors in the feedback circuit. A bias
voltage must be applied to R1 in order that the input signal has
the sync pulses stripped at the proper level.
The capacitor values were selected for providing minimum “tilt”
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broad-
cast quality. However, if a lower consumer grade of video,
sometimes referred to as “consumer video” is all that is desired,
the values and the cost of the capacitors can be reduced by as
much as a factor of five with minimum visible degradation in the
picture.
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by two
by the amplifier. This level must be at ground at the output in
order for the sync stripping action to take place. Since the gain
of the amplifier from the input of R1 to the output is –1, a volt-
age equal to 2 × VBLANK must be applied to make the blanking
level come out at ground.
+5V
4.99k⍀
Single Supply Composite Video Line Driver
+
10F
4.99k⍀
+
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual supply amplifiers to pass
them. However, by ac level shifting a single supply amplifier can
be used to pass these signals. The following complications may
arise from such techniques.
0.1F
10F
COMPOSITE
VIDEO
47F
+
R
BT
IN
1000F
75⍀
R
+
T
V
OUT
10F
AD8051
75⍀
R
L
75⍀
0.1F
R
F
1k⍀
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak to peak amplitude after they are ac coupled. As a worst
case, the dynamic signal swing will approach twice the peak-
to-peak value. The two conditions that define the maximum
dynamic wing requirements are a signal that is mostly low, but
R
1k⍀
G
220F
Figure 48. Single Supply Composite Video Line Driver
REV. B
–15–
AD8051/AD8052/AD8054
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
14-Lead SOIC
(R-14)
0.1968 (5.00)
0.1890 (4.80)
0.3444 (8.75)
0.3367 (8.55)
8
1
5
4
14
1
8
7
0.1574 (4.00)
0.1497 (3.80)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0196 (0.50)
0.0099 (0.25)
x 45°
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0075 (0.19)
8-Lead SOIC
14-Lead TSSOP
(RU-14)
(RM-8)
0.122 (3.10)
0.114 (2.90)
0.201 (5.10)
0.193 (4.90)
14
8
7
5
4
8
1
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
0.177 (4.50)
0.256 (6.50)
0.246 (6.25)
0.169 (4.30)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
PIN 1
0.006 (0.15)
0.002 (0.05)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
33°
27°
0.018 (0.46)
0.028 (0.70)
0.020 (0.50)
8°
0°
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.008 (0.20)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
5-Lead Plastic Surface Mount
(RT-5)
0.1220 (3.100)
0.1063 (2.700)
5
1
4
0.1181 (3.000)
0.0709 (1.800)
0.0590 (1.500)
0.0984 (2.500)
2
3
PIN 1
0.0374 (0.950) REF
0.0748 (1.900)
REF
0.0079 (0.200)
0.0035 (0.090)
0.0512 (1.300)
0.0354 (0.900)
0.0571 (1.450)
0.0354 (0.900)
10°
0°
SEATING
PLANE
0.0197 (0.500)
0.0118 (0.300)
0.0590 (0.150)
0.0000 (0.000)
0.0236 (0.600)
0.0039 (0.100)
REV. B
–16–
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