AD8055AN [ADI]

Low Cost, 300 MHz Voltage Feedback Amplifiers; 低成本， 300 MHz电压反馈放大器


型号：	AD8055AN
厂家：	ADI
描述：	Low Cost, 300 MHz Voltage Feedback Amplifiers 低成本， 300 MHz电压反馈放大器放大器
文件：	总11页 (文件大小：208K)
中文：	中文翻译
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Low Cost, 300 MHz

Voltage Feedback Amplifiers

AD8055/AD8056

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Low Cost Single (AD8055) and Dual (AD8056)

Easy to Use Voltage Feedback Architecture

High Speed

300 MHz, –3 dB Bandwidth (G = +1)

1400 V/␮s Slew Rate

20 ns Settling to 0.1%

Low Distortion: –72 dBc @ 10 MHz

Low Noise: 6 nV/√Hz

N-8 and SO-8

SOT-23-5 (RT)

AD8055

–IN

+IN

OUT

–V

OUT

–V

–IN

+IN

(Not to Scale)

NC = NO CONNECT

Low DC Errors: 5 mV Max V_OS, 1.2 ␮A Max I_B

Small Packaging

N-8, SO-8, microSOIC (RM)

AD8055 Available in SOT-23-5

AD8056 Available in 8-Lead microSOIC

Excellent Video Specifications (R_L= 150 ⍀, G = +2)

Gain Flatness 0.1 dB to 40 MHz

0.01% Differential Gain Error

AD8056

OUT1

–IN1

+IN1

OUT

–IN2

+IN2

–V

0.02؇ Differential Phase Error

(Not to Scale)

Drives Four Video Loads (37.5 ⍀) with 0.02% and

0.1؇ Differential Gain and Differential Phase

Low Power, ؎5 V Supplies

5 mA Typ/Amplifier Power Supply Current

High Output Drive Current: Over 60 mA

The AD8055 and AD8056 require only 5 mA typ/amplifier of

supply current and operate on dual 5 V or single +12 V power

supply, while being capable of delivering over 60 mA of load

current. All this is offered in a small 8-lead plastic DIP, 8-lead

SOIC packages, 5-lead SOT-23-5 package (AD8055) and an

8-lead microSOIC package (AD8056). These features make

the AD8055/AD8056 ideal for portable and battery powered

applications where size and power are critical. These amplifiers are

available in the industrial temperature range of –40°C to +85°C.

APPLICATIONS

Imaging

Photodiode Preamp

Video Line Driver

Differential Line Driver

Professional Cameras

Video Switchers

Special Effects

= 100mV p-p

= 100⍀

OUT

A-to-D Driver

Active Filters

OUT

50⍀

G = +1

= 0⍀

= 100⍀

G = +2

= 402⍀

PRODUCT DESCRIPTION

The AD8055 (single) and AD8056 (dual) voltage feedback

amplifiers offer bandwidth and slew rate typically found in cur-

rent feedback amplifiers. Additionally, these amplifiers are easy

to use and available at a very low cost.

–1

–2

–3

–4

G = +10

= 909⍀

Despite their low cost, the AD8055 and AD8056 provide excel-

lent overall performance. For video applications, their differen-

tial gain and phase error are 0.01% and 0.02° into a 150 Ω load,

and 0.02% and 0.1° while driving four video loads (37.5 Ω).

Their 0.1 dB flatness out to 40 MHz, wide bandwidth out to

300 MHz, along with 1400 V/µs slew rate and 20 ns settling

time, make them useful for a variety of high speed applications.

G = +5

= 1000⍀

–5

0.3M

10M

100M

FREQUENCY – Hz

Figure 1. Frequency Response

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(@ T_A= +25؇C, V_S= 65 V, R_F= 402 ⍀, R_L= 100 ⍀, Gain = +2,

AD8055/AD8056–SPECIFICATIONS _{unless otherwise noted)}

Model

AD8055A/AD8056A

Conditions

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth

G = +1, V_O= 0.1 V p-p

G = +1, V_O= 2 V p-p

G = +2, V_O= 0.1 V p-p

G = +2, V_O= 2 V p-p

V_O= 100 mV p-p

G = +1, V_O= 4 V Step

G = +2, V_O= 4 V Step

G = +2, V_O= 2 V Step

G = +1, V_O= 0.5 V Step

G = +1, V_O= 4 V Step

G = +2, V_O= 0.5 V Step

G = +2, V_O= 4 V Step

220

125

120

125

1000

750

300

150

160

150

1400

840

MHz

V/µs

Bandwidth for 0.1 dB Flatness

Slew Rate

Settling Time to 0.1%

Rise and Fall Time, 10% to 90%

2.7

2.8

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion

f_C= 10 MHz, V_O= 2 V p-p, R_L= 1 kΩ

f_C= 20 MHz, V_O= 2 V p-p, R_L= 1 kΩ

f = 5 MHz, G = +2

f = 100 kHz

NTSC, G = +2, R_L= 150 Ω

NTSC, G = +2, R_L= 37.5 Ω

NTSC, G = +2, R_L= 150 Ω

NTSC, G = +2, R_L= 37.5 Ω

–72

–57

–60

dBc

nV/√Hz

pA/√Hz

Degree

Crosstalk, Output to Output (AD8056)

Input Voltage Noise

Input Current Noise

Differential Gain Error

0.01

0.02

0.1

Differential Phase Error

Degree

DC PERFORMANCE

Input Offset Voltage

µV/°C

µA

_MIN–T_MAX

Offset Drift

Input Bias Current

0.4

1.2

T_MIN–T_MAX

V_O= 2.5 V

T_MIN–T_MAX

µA

Open Loop Gain

INPUT CHARACTERISTICS

Input Resistance

Input Capacitance

Input Common-Mode Voltage Range

Common-Mode Rejection Ratio

3.2

MΩ

V_CM

2.5 V

OUTPUT CHARACTERISTICS

Output Voltage Swing

Output Current¹

R_L= 150 Ω

V_O= 2.0 V

2.9

3.1

110

Short Circuit Current¹

POWER SUPPLY

Operating Range

Quiescent Current

4.0

5.0

5.4

6.0

6.5

7.3

13.3

AD8055

T_MIN–T_MAX

AD8056

_MIN–T_MAX

Power Supply Rejection Ratio

+V_S= +5 V to +6 V, –V_S= –5 V

–V_S= –5 V to –6 V, +V_S= +5 V

OPERATING TEMPERATURE RANGE

–40

+85

°C

NOTES

¹Output current is limited by the maximum power dissipation in the package. See the power derating curves.

Specifications subject to change without notice.

REV. B

–2–

AD8055/AD8056

ABSOLUTE MAXIMUM RATINGS¹

of the plastic, approximately +150°C. Exceeding this limit tem-

porarily may cause a shift in parametric performance due to a

change in the stresses exerted on the die by the package. Exceeding

a junction temperature of +175°C for an extended period can

result in device failure.

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V

Internal Power Dissipation²

Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . 1.3 W

Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W

SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . 0.5 W

microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 0.6 W

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . V_S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 2.5 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range N, R . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C

While the AD8055/AD8056 are internally short circuit protected,

this may not be sufficient to guarantee that the maximum junc-

tion temperature (+150°C) is not exceeded under all conditions.

To ensure proper operation, it is necessary to observe the maxi-

mum power derating curves.

2.0

8-LEAD PLASTIC DIP PACKAGE

NOTES

1.5

8-LEAD SOIC

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²Specification is for device in free air:

T = +150؇C

PACKAGE

1.0

0.5

8-Lead Plastic DIP Package: θ_JA= 90°C/W

␮SOIC

8-Lead SOIC Package: θ_JA= 155°C/W

SOT-23-5

5-Lead SOT-23-5 Package: θ_JA= 240°C/W

8-Lead microSOIC Package: θ_JA= 200°C/W

–50 –40 –30 –20 –10

10 20 30 40 50 60 70 80 90

MAXIMUM POWER DISSIPATION

AMBIENT TEMPERATURE – ؇C

The maximum power that can be safely dissipated by the AD8055/

AD8056 is limited by the associated rise in junction temperature.

The maximum safe junction temperature for plastic encapsu-

lated devices is determined by the glass transition temperature

Figure 2. Plot of Maximum Power Dissipation vs.

Temperature for AD8055/AD8056

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

Brand Code

AD8055AN

AD8055AR

AD8055AR-REEL

AD8055AR-REEL7

AD8055ART-REEL

AD8055ART-REEL7

–40°C to +85°C

Plastic DIP

N-8

Small Outline Package (SOIC)

13" Tape and Reel

7" Tape and Reel

13" Tape and Reel

7" Tape and Reel

SO-8

RT-5

H3A

AD8056AN

AD8056AR

–40°C to +85°C

Plastic DIP

N-8

Small Outline Package (SOIC)

13" Tape and Reel

7" Tape and Reel

microSOIC

13" Tape and Reel

7" Tape and Reel

SO-8

RM-8

AD8056AR-REEL

AD8056AR-REEL7

AD8056ARM

AD8056ARM-REEL

AD8056ARM-REEL7

H5A

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8055/AD8056 features proprietary ESD protection circuitry, permanent dam-

age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–3–

–Typical Performance Characteristics

AD8055/AD8056

402⍀

4.7␮F

0.01␮F

0.001␮F

0.01␮F

0.001␮F

HP8130A

PULSE

HP8130A

PULSE

100⍀

50⍀

402⍀

GENERATOR

OUT

/T = 0.67ns

/T = 1ns

AD8055

57⍀

AD8055

OUT

100⍀

4.7␮F

0.01␮F

4.7␮F

0.01␮F

0.001␮F

–V

Figure 6. Test Circuit, G = –1, R_L= 100 Ω

Figure 7. Small Step Response, G = –1

Figure 8. Large Step Response, G = –1

Figure 3. Test Circuit, G = +1, R_L= 100 Ω

Figure 4. Small Step Response, G = +1

Figure 5. Large Step Response, G = +1

REV. B

–4–

AD8055/AD8056

–50

–60

= 100mV p-p

OUT

R = 100⍀

R_C

V_IN

V_OUT

= 2V p-p

50⍀

OUT

G = +2

= 402⍀

G = +2

= 100⍀

R_F

R_S

R_L

G = +1

= 0⍀

2ND

–70

= 100⍀

–80

–1

–2

–3

3RD

G = +10

= 909⍀

–90

G = +5

= 1000⍀

–4

–5

–100

0.3M

10M

100M

10k

100M

100k

10M

FREQUENCY – Hz

Figure 9. Small Signal Frequency Response,

G = +1, G = +2, G = +5, G = +10

Figure 12. Distortion vs. Frequency

–50

–60

–70

–80

= 2V p-p

= 100⍀

OUT

G = +2

= 1k⍀

G = +1

= 0⍀

G = +2

= 402⍀

–1

–2

–3

2ND

G = +10

= 909⍀

–90

3RD

G = +5

= 1000⍀

–4

–5

–100

0.3M

10M

FREQUENCY – Hz

100M

10k

100k

FREQUENCY – Hz

10M

100M

Figure 10. Large Signal Frequency Response,

G = +1, G = +2, G = +5, G = +10

Figure 13. Distortion vs. Frequency

–40

0.5

= 100mV

OUT

G = +2

0.4

0.3

G = +2

= 100⍀

= 402⍀

–50

–60

= 1k⍀

0.2

0.1

2ND

–0.1

–0.2

–0.3

–0.4

–0.5

–70

–80

–90

3RD

0.4 0.8

1.2

1.6

2.0 2.4

– V p-p

2.8 3.2 3.6 4.0

0.3M

10M

100M

FREQUENCY – Hz

OUT

Figure 11. 0.1 dB Flatness

Figure 14. Distortion vs. V_OUT@ 20 MHz

REV. B

–5–

AD8055/AD8056

G = +1

G = +2

= 100⍀

= 0⍀

= 100⍀

= 402⍀

FALLTIME

RISETIME

FALLTIME

0.2

0.4

0.6

0.8

– V p-p

1.0

1.2

1.4

1.6

0.5 1.0

1.5 2.0

2.5 3.0 3.5 4.0

4.5 5.0

– V p-p

Figure 15. Risetime and Falltime vs. V_IN

Figure 18. Risetime and Falltime vs. V_IN

5.0

G = +1

G = +2

= 1k⍀

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

= 1k⍀

= 0⍀

= 402⍀

RISETIME

FALLTIME

RISETIME

0.5 1.0

1.5 2.0

2.5

3.0 3.5 4.0

4.5 5.0

0.2

0.4

0.6

0.8

– V p-p

1.0

1.2

1.4

1.6

– V p-p

Figure 19. Risetime and Falltime vs. V_IN

Figure 16. Risetime and Falltime vs. V_IN

0.7

0.6

= 0V TO 2V OR

0V TO –2V

OUT

G = +2

= 402⍀

G = +2

0.5

= 100⍀

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.4

0.3

0.2

–PSRR

0.1

+PSRR

–0.1

–0.2

–0.3

–0.4

–0.5

0.1

TIME – ns

100

500

FREQUENCY – MHz

Figure 20. PSRR vs. Frequency

Figure 17. Settling Time

REV. B

–6–

AD8055/AD8056

Figure 21. Overload Recovery

Figure 24. Overload Recovery

–20

–30

= 0dBm

G = +2

= 100⍀

= 402⍀

–40

–50

–60

SIDE 2 DRIVEN

–70

–80

SIDE 1 DRIVEN

–90

–100

–110

–120

–10

0.01

0.1

100

500

FREQUENCY – MHz

100 200

FREQUENCY – MHz

Figure 22. Crosstalk (Output-to-Output) vs. Frequency

Figure 25. Open Loop Gain vs. Frequency

402⍀

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

= 100⍀

50⍀

–45

402⍀

58⍀

402⍀

–90

–135

–180

0.1

FREQUENCY – MHz

100

500

0.01

0.1

100

500

FREQUENCY – MHz

Figure 23. CMRR vs. Frequency

Figure 26. Phase vs. Frequency

REV. B

–7–

AD8055/AD8056

1000

100

0.04

1 BACK TERMINATED LOAD (150⍀)

0.02

0.00

–0.02

–0.04

G = +2

= 402⍀

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

IRE

0.04

0.02

6nV/ Hz

1 BACK TERMINATED LOAD (150⍀)

0.00

G = +2

–0.02

= 402⍀

–0.04

100

10k

100k

10M 15M

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

IRE

FREQUENCY – Hz

Figure 27. Differential Gain and Differential Phase

Figure 30. Voltage Noise vs. Frequency

100

0.04

4 VIDEO LOADS (37.5⍀)

0.02

0.00

G = +2

–0.02

= 402⍀

–0.04

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

IRE

0.15

0.10

0.05

4 VIDEO LOADS (37.5⍀)

0.00

–0.05

–0.10

–0.15

G = +2

= 402⍀

0.1

100

10k

100k

10M 15M

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

IRE

FREQUENCY – Hz

Figure 28. Differential Gain and Differential Phase

Figure 31. Current Noise vs. Frequency

5.0

= ؎5V

G = +2

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

= 402⍀

= 1k⍀

= 150⍀

= 50⍀

–5

0.01

–55 –35

–15

105

125

0.1

100

500

TEMPERATURE – ؇C

FREQUENCY – MHz

Figure 32. Output Impedance vs. Frequency

Figure 29. Output Swing vs. Temperature

REV. B

–8–

AD8055/AD8056

APPLICATIONS

Four-Line Video Driver

The gain of this circuit from the input to Amp 1 output is R_F/R_I,

while the gain to the output of Amp 2 is –R_F/R_I. The circuit

thus creates a balanced differential output signal from a single-

ended input. The advantage of this circuit is that the gain can be

changed by changing a single resistor and still maintain the

balanced differential outputs.

The AD8055 is a useful low cost circuit for driving up to four

video lines. For such an application, the amplifier is configured

for a noninverting gain of 2 as shown in Figure 33. The input

video source is terminated in 75 Ω and applied to the high

impedance noninverting input.

Each output cable is connected to the op amp output via a 75 Ω

series back termination resistor for proper cable termination.

The terminating resistors at the other ends of the lines will

divide the output signal by two, which is compensated for by

the gain-of-two of the op amp stage.

402⍀

+5V

10␮F

0.1␮F

402⍀

49.9⍀

OUT

AMP1

For a single load, the differential gain error of this circuit was

measured to be 0.01%, with a differential phase error of

0.02 degrees. The two load measurements were 0.02% and

0.03 degrees, respectively. For four loads, the differential gain

error is 0.02%, while the differential phase increases to 0.1

degrees.

402⍀

AD8056

402⍀

75⍀

OUT1

+5V

75⍀

402⍀

49.9⍀

–V

OUT

AMP2

75⍀

10␮F

0.1␮F

402⍀

75⍀

OUT2

75⍀

10␮F

0.1␮F

AD8055

–5V

75⍀

OUT3

Figure 34. Single-Ended to Differential Line Driver

0.1␮F

75⍀

Low Noise, Low Power Preamp

–5V

The AD8055 makes a good low cost, low noise, low power

preamp. A gain of 10 preamp can be made with a feedback

resistor of 909 ohms and a gain resistor of 100 ohms as shown

in Figure 35. The circuit has a –3 dB bandwidth of 20 MHz.

OUT4

Figure 33. Four-Line Video Driver

Single-Ended to Differential Line Driver

909⍀

Creating differential signals from single-ended signals is

required for driving balanced, twisted pair cables, differential

input A/D converters and other applications that require differen-

tial signals. This is sometimes accomplished by using an inverting

and a noninverting amplifier stage to create the complementary

signals.

+5V

0.1␮F

10␮F

100⍀

OUT

AD8055

The circuit shown in Figure 34 shows how an AD8056 can be

used to make a single-ended to differential converter that offers

some advantages over the architecture mentioned above. Each

op amp is configured for unity gain by the feedback resistors

from the outputs to the inverting inputs. In addition, each out-

put drives the opposite op amp with a gain of –1 by means of the

crossed resistors. The result of this is that the outputs are comple-

mentary and there is high gain in the overall configuration.

10␮F

0.1␮F

–5V

Figure 35. Low Noise, Low Power Preamp with G = 10

and BW = 20 MHz

With a low source resistance (<approximately 100 Ω), the major

contributors to the input referred noise of this circuit are the

input voltage noise of the amplifier and the noise of the 100 Ω

resistor. These are 6 nV/√Hz and 1.2 nV/√Hz, respectively.

These values yield a total input referred noise of 6.1 nV/√Hz.

Feedback techniques similar to a conventional op amp are used

to control the gain of the circuit. From the noninverting input

of Amp 1 to the output of Amp 2, is an inverting gain. Between

these points a feedback resistor can be used to close the loop.

As in the case of a conventional op amp inverting gain stage, an

input resistor is added to vary the gain.

REV. B

–9–

AD8055/AD8056

Power Dissipation Limits

402⍀

With a 10 V supply (total V_CC– V_EE), the quiescent power dissi-

pation of the AD8055 in the SOT-23-5 package is 65 mW,

while the quiescent power dissipation of the AD8056 in the

microSOIC is 120 mW. This translates into a 15.6°C rise above

the ambient for the SOT-23-5 package and a 24°C rise for the

microSOIC package.

402⍀

= 30pF

C_L

100⍀

V_IN= 0dBm

50⍀

The power dissipated under heavy load conditions is approxi-

mately equal to the supply voltage minus the output voltage,

times the load current, plus the quiescent power computed above.

This total power dissipation is then multiplied by the thermal

resistance of the package to find the temperature rise, above

ambient, of the part. The junction temperature should be kept

below 150°C.

= 20pF

= 10pF

–1

–2

–3

–4

–5

= 0pF

0.3

FREQUENCY – MHz

100

500

The AD8055 in the SOT-23-5 package can dissipate 270 mW

while the AD8056 in the microSOIC package can dissipate

325 mW (at 85°C ambient) without exceeding the maximum

die temperature. In the case of the AD8056, this is greater than

1.5 V rms into 50 Ω, enough to accommodate a 4 V p-p sine-wave

signal on both outputs simultaneously. But since each output of

the AD8055 or AD8056 is capable of supplying as much as

110 mA into a short circuit, a continuous short circuit condition

will exceed the maximum safe junction temperature.

Figure 36. Capacitive Load Drive

In general, to minimize peaking or to ensure the stability for

larger values of capacitive loads, a small series resistor, R_S,can

be added between the op amp output and the capacitor, C_L. For

the setup depicted in Figure 37, the relationship between R_Sand

C_Lwas empirically derived and is shown in Figure 38. R_Swas

chosen to produce less than 1 dB of peaking in the frequency

response. Note also that after a sharp rise R_Squickly settles to

about 25 Ω.

Resistor Selection

The following table is provided as a guide to resistor selection

for maintaining gain flatness vs. frequency for various values of

gain.

402⍀

+5V

0.1␮F

10␮F

–3 dB

Bandwidth

(MHz)

402⍀

FET PROBE

AD8055

Gain

R_F(⍀)

R_I(⍀)

OUT

= 0dBm

+10

402

—

300

160

50⍀

10␮F

402

249

100

0.1␮F

–5V

909

Figure 37. Setup for R_Svs. C_L

Driving Capacitive Loads

When driving a capacitive load, most op amps will exhibit peak-

ing in the frequency response just before the frequency rolls off.

Figure 36 shows the responses for an AD8056 running at a gain

of +2, with a 100 Ω load that is shunted by various values of

capacitance. It can be seen that under these conditions, the part

is still stable with capacitive loads of up to 30 pF.

– pF

270

Figure 38. R_Svs. C_L

REV. B

–10–

AD8055/AD8056

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

8-Lead microSOIC Package

(RM-8)

0.430 (10.92)

0.348 (8.84)

0.122 (3.10)

0.114 (2.90)

0.280 (7.11)

0.240 (6.10)

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

0.325 (8.25)

0.300 (7.62)

PIN 1

0.100 (2.54)

BSC

0.060 (1.52)

0.015 (0.38)

PIN 1

0.0256 (0.65) BSC

0.210

(5.33)

MAX

0.195 (4.95)

0.115 (2.93)

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

0.015 (0.381)

0.008 (0.204)

33؇

SEATING

PLANE

0.022 (0.558) 0.070 (1.77)

0.014 (0.356) 0.045 (1.15)

0.018 (0.46)

0.008 (0.20)

27؇

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

8-Lead Small Outline SOIC

(SO-8)

5-Lead Plastic Surface Mount

(RT-5)

0.1220 (3.100)

0.1063 (2.700)

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

0.1181 (3.000)

0.0984 (2.500)

0.0709 (1.800)

0.0590 (1.500)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

BSC

0.0374 (0.950) REF

45؇

0.0688 (1.75)

0.0532 (1.35)

0.0748 (1.900)

REF

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.0079 (0.200)

0.0035 (0.090)

8؇

0؇

0.0500 (1.27)

0.0160 (0.41)

0.0192 (0.49)

0.0138 (0.35)

0.0512 (1.300)

0.0354 (0.900)

0.0571 (1.450)

0.0354 (0.900)

0.0098 (0.25)

0.0075 (0.19)

10؇

0؇

SEATING

PLANE

0.0197 (0.500)

0.0118 (0.300)

0.0059 (0.150)

0.0000 (0.000)

0.0236 (0.600)

0.0039 (0.100)

REV. B

–11–

AD8055AN [ADI]

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