AD8062ARMZ-REEL_技术文档

Dual, Current-Output,

Serial-Input, 16-/14-Bit DACs

Data Sheet

AD5545/AD5555

FEATURES

FUNCTIONAL BLOCK DIAGRAM

B

REF

V

A

V

REF

16-bit resolution AD5545

14-bit resolution AD5555

1 LSB DNL monotonic

16 OR 14

V

DD

R

I

A

FB

D0..DX

INPUT

REGISTER

DAC A

REGISTER

SDI

A

DAC A

DAC B

OUT

1 LSB INL

R

A

GND

2 mA full-scale current 20%, with V_REF= 10 V

0.5 µs settling time

2Q multiplying reference-input 6.9 MHz BW

Zero or midscale power-up preset

Zero or midscale dynamic reset

3-wire interface

R

I

B

FB

CS

INPUT

REGISTER

DAC B

REGISTER

B

OUT

EN

CLK

A

B

GND

DAC A

B

POWER-

ON

RESET

ADDR

DECODE

AD5545/

AD5555

Compact 16-lead TSSOP package

02918-0-001

DGND

RS MSB

LDAC

Figure 1.

APPLICATIONS

Automatic test equipment

Instrumentation

Digitally controlled calibration

Industrial control PLCs

Programmable attenuator

PRODUCT OVERVIEW

The AD5545/AD5555 are 16-bit/14-bit, current-output, digital-

to-analog converters designed to operate from a 4.5 V to 5.5 V

supply range.

An external reference is needed to establish the full-scale

output-current. An internal feedback resistor (R_FB) enhances

the resistance and temperature tracking when combined

with an external op amp to complete the I-to-V conversion.

A serial data interface offers high speed, 3-wire microcontroller

compatible inputs using serial data in (SDI), clock (CLK), and

CS

LDAC

chip select ( ). Additional

function allows

simultaneous update operation. The internal reset logic allows

power-on preset and dynamic reset at either zero or midscale,

depending on the state of the MSB pin.

The AD5545/AD5555 are packaged in the compact TSSOP-16

package and can be operated from −40°C to +85°C.

Rev. G

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5545/AD5555

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Grounding................................................................................... 11

Applications Information .............................................................. 12

Stability ........................................................................................ 12

Positive Voltage Output............................................................. 12

Bipolar Output............................................................................ 12

Programmable Current Source ................................................ 13

DAC with Programmable Input Reference Range................ 14

Reference Selection .................................................................... 15

Amplifier Selection .................................................................... 15

Evaluation Board for the AD5545................................................ 17

System Demonstration Platform.............................................. 17

Operating the Evaluation Board .............................................. 17

Evaluation Board Schematics ................................................... 18

Evaluation Board Layout........................................................... 21

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

Product Overview............................................................................. 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Diagrams.......................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Digital-to-Analog Converter ...................................................... 9

Serial Data Interface................................................................... 10

Power-Up Sequence ................................................................... 11

Layout and Power Supply Bypassing ....................................... 11

REVISION HISTORY

4/13—Rev. F to Rev. G

3/11—Rev. B to Rev. C

Changes to Product Overview Section.......................................... 1

Changes to Ordering Guide .......................................................... 23

Change to Equation 4, Bipolar Output Section.......................... 12

4/10—Rev. A to Rev. B

2/13—Rev. E to Rev. F

Changes to 2Q Multiplying Reference Input .................................1

Changes to AC Characteristics and Endnote 3 in Table 1 ...........4

Changes to Figure 13 and Figure 15 ...............................................8

Added Reference Selection Section, Amplifier Selection Section,

and Table 10 .................................................................................... 15

Added Table 11 and Table 12........................................................ 16

Changes to Ordering Guide.......................................................... 17

Change to V_DDPin Description, Table 3........................................ 6

Changed ADA4899 to ADA4899-1, Table 12............................. 16

Changes to Ordering Guide .......................................................... 23

12/11—Rev. D to Rev. E

Added Figure 13; Renumbered Sequentially ................................ 8

5/11—Rev. C to Rev. D

9/09—Rev. 0 to Rev. A

Added Evaluation Board for the AD5545 Section, System

Demonstration Platform Section, and Operating the Evaluation

Board Section .................................................................................. 17

Added Figure 25 and Figure 26; Renumbered Sequentially ..... 17

Added Evaluation Board Schematics Section, Figure 27 .......... 18

Added Figure 28.............................................................................. 19

Added Figure 29.............................................................................. 20

Added Evaluation Board Layout Section, Figure 30, and

Changes to Features Section ............................................................1

Changes to Static Performance, Relative Accuracy, AD5545C

Parameter, Table 1 .............................................................................3

Moved ESD Caution..........................................................................5

Changes to Ordering Guide.......................................................... 16

7/03—Revision 0: Initial Version

Figure 31, ......................................................................................... 21

Added Figure 32.............................................................................. 22

Changes to Ordering Guide .......................................................... 23

Rev. G | Page 2 of 24

Data Sheet

AD5545/AD5555

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 5 V 10%, I_OUT= virtual GND, GND = 0 V, V_REF= 10 V, T_A= full operating temperature range, unless otherwise noted.

Table 1.

Parameter

Symbol

N

Conditions

Min Typ

Max

Unit

STATIC PERFORMANCE¹

Resolution

AD5545, 1 LSB = V_REF/2¹⁶= 153 µV when V_REF= 10 V

AD5555, 1 LSB = V_REF/2¹⁴= 610 µV when V_REF= 10 V

AD5545B

AD5555C

AD5545C

Monotonic

Data = 0x0000, T_A= 25°C

Data = 0x0000, T_A= T_AMax

Data = full scale

16

14

2

1

Bits

LSB

nA

mV

ppm/°C

Relative Accuracy

INL

Differential Nonlinearity

Output Leakage Current

DNL

I_OUT

1

10

20

4

Full-Scale Gain Error

Full-Scale Temperature Coefficient²

REFERENCE INPUT

G_FSE

TCV_FS

1

V_REFRange

Input Resistance

Input Capacitance²

V_REF

R_REF

C_REF

–12

5

+12

V

kΩ³

5

pF

ANALOG OUTPUT

Output Current

I_OUT

C_OUT

Data = full scale

Code dependent

2

200

mA

pF

Output Capacitance²

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance²

INTERFACE TIMING^{2, 4}

Clock Input Frequency

Clock Width High

V_IL

V_IH

I_IL

0.8

V

2.4

10

50

µA

pF

MHz

ns

C_IL

10

0

f_CLK

t_CH

t_CL

Clock Width Low

CS to Clock Setup

t_CSS

t_CSH

t_DS

10

5

ns

Clock to CS Hold

Data Setup

Data Hold

ns

10

5

ns

t_DH

ns

LDAC Setup

Hold

LDAC Width

10

t_LDS

t_LDH

t_LDAC

ns

50

MHz

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Power Dissipation

V_DDrange

I_DD

P_DISS

4.5

5.5

10

0.055

0.006

V

µA

mW

%/%

Logic inputs = 0 V

∆V_DD= 5%

Power Supply Sensitivity

PSS

Rev. G | Page 3 of 24

AD5545/AD5555

Data Sheet

Parameter

Symbol

Conditions

Min Typ

Max

Unit

AC CHARACTERISTICS

Output Voltage Setting Time

t_S

To ±±.ꢀ1 full scale, data = zero scale to

full scale to zero scale

±.5

μs

Reference Multiplying BW

DAC Glitch Impulse

Feedthrough Error

BW

Q

V_OUT/V_REF

V_REF= ꢀ±± mV rms, data = full scale, Cꢀ = 5.6 pF

V_REF= ± V, data = midscale minus ꢀ to midscale

Data = zero scale, V_REF= ꢀ±± mV rms,

f = ꢀ kHz, same channel

6.9

–2

–8ꢀ

MHz

nV-s

dB

Digital Feedthrough

Total Harmonic Distortion

Analog Crosstalk

Q

CS

nV-s

dB

= logic high and f_CLK= ꢀ MHz

7

THD

C_TA

V_REF= 5 V p-p, data = full scale, f = ꢀ kHz to ꢀ± kHz

V_REFB= ± V, measure V_OUTBwith V_REFA= 5 V p-p

sine wave, data = full scale, f = ꢀ kHz to ꢀ± kHz

–ꢀ±4

–95

Output Spot Noise Voltage

e_N

f = ꢀ kHz, BW = ꢀ Hz

ꢀ2

nV/√Hz

^ꢀAll static performance tests (except I_OUT) are performed in a closed-loop system using an external precision OPꢀꢀ77 I-to-V converter amplifier. The AD5545 R_FBterminal

is tied to the amplifier output. Typical values represent average readings measured at 25°C.

²These parameters are guaranteed by design and not subject to production testing.

³All ac characteristic tests are performed in a closed-loop system using an AD8±38 I-to-V converter amplifier and the AD8±65 for the THD specification.

⁴All input control signals are specified with t_R= t_F= 2.5 ns (ꢀ±1 to 9±1 of 3 V) and timed from a voltage level of ꢀ.5 V.

TIMING DIAGRAMS

SDI

A1

A0

D15

D14

D13

D12

D11

D10

D1

D0

INPUT REG LD

CLK

t_DS

t_DH

t_CH

t_CL

CS

t_CSS

t_CSH

LDAC

t_LDH

t_LDS

t_LDAC

02918-0-003

Figure 2. AD5545 18-Bit Data Word Timing Diagram

SDI

A1

A0

D13

D12

D11

D10

D09

D08

D1

D0

INPUT REG LD

CLK

t_DS

t_DH

t_CH

t_CL

CS

t_CSS

t_CSH

LDAC

t_LDH

t_LDS

t_LDAC

02918-0-004

Figure 3. AD5555 16-Bit Data Word Timing Diagram

Rev. G | Page 4 of 24

Data Sheet

AD5545/AD5555

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_REFto GND

Logic Inputs to GND

V(I_OUT) to GND

Input Current to Any Pin except

Supplies

–0.3 V to +8 V

–18 V to +18 V

–0.3 V to +8 V

–0.3 V to V_DD+ 0.3 V

50 mA

ESD CAUTION

Package Power Dissipation

Thermal Resistance θ_JA

16-Lead TSSOP

Maximum Junction Temperature

(T_Jmax)

(T_Jmax – T_A)/θ_JA

150°C/W

150°C

Operating Temperature Range

Storage Temperature Range

Lead Temperature

–40°C to +85°C

–65°C to +150°C

RU-16 (Vapor Phase, 60 sec)

RU-16 (Infrared, 15 sec)

215°C

220°C

Rev. G | Page 5 of 24

AD5545/AD5555

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

R

A

B

16 CLK

15 LDAC

14 MSB

1

2

3

4

5

6

7

8

FB

V

REF

OUT

I

AD5545/

A

V

DD

13

12

11

10

9

GND

AD5555

DGND

CS

TOP VIEW

(Not to Scale)

I

OUT

V

RS

REF

R

SDI

FB

02918-0-002

Figure 4. 16-Lead TSSOP

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

R_FBA

Establish voltage output for DAC A by connecting this pin to an external amplifier output.

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can

be tied to the V_DDpin.

V_REFA

3

4

5

6

7

I_OUT

A_GND

I_OUT

V_REF

A

B

DAC A Current Output.

DAC A Analog Ground.

DAC B Analog Ground.

DAC B Current Output.

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.

This pin can be tied to the V_DDpin.

8

9

10

R_FBB

SDI

RS

Establish voltage output for DAC B by the R_FBB pin connecting to an external amplifier output.

Serial Data Input. Input data loads directly into the shift register.

Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register

Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when

MSB = 1.

11

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register

data to the input register when CS/LDAC returns high. This does not affect LDAC operation.

12

13

14

DGND

V_DD

MSB

Digital Ground Pin.

Positive Power Supply Input. Specified range of operation 5 V 10%.

MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.

Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied

permanently to ground or V_DD

.

15

16

LDAC

CLK

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC

registers. Asynchronous active low input. See Table 7 and Table 8 for operation.

Clock Input. Positive edge clocks data into shift register.

Rev. G | Page 6 of 24

Data Sheet

AD5545/AD5555

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

8192 16384 24576 32768 40960 49152 57344 65536

0

0248 4096

6144

8192 10240 12288 14336 16384

CODE (Decimal)

02918-0-009

02918-0-012

Figure 5. AD5545 Integral Nonlinearity Error

Figure 8. AD5555 Differential Nonlinearity Error

1.0

0.8

1.5

V

= 2.5V

REF

= 25°C

T

A

1.0

0.5

0.6

0.4

0.2

INL

0

DNL

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

GE

0

8192 16384 24576 32768 40960 49152 57344 65536

2

4

6

8

10

CODE (Decimal)

SUPPLY VOLTAGE V (V)

DD

02918-0-010

02918-0-013

Figure 6. AD5545 Differential Nonlinearity Error

Figure 9. Linearity Errors vs. V_DD

1.0

0.8

5

4

3

2

V

= 5V

DD

= 25°C

T

A

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

1

0

2048 4096

6144

8192 10240 12288 14336 16384

0

0.5

1.0 1.5

2.0

2.5 3.0

3.5

IH

4.0

4.5 5.0

CODE (Decimal)

LOGIC INPUT VOLTAGE V (V)

02918-0-014

02918-0-011

Figure 10. Supply Current vs. Logic Input Voltage

Figure 7. AD5555 Integral Nonlinearity Error

Rev. G | Page 7 of 24

AD5545/AD5555

Data Sheet

2

0

3.0

2.5

2.0

–2

–4

0x5555

0x8000

–6

1.5

–8

1.0

0.5

0xFFFF

0x0000

–10

–12

–14

0

10k

100k

1M

CLOCK FREQUENCY (Hz)

10M

100M

10k

100k

1M

10M

100M

FREQUENCY (Hz)

02918-0-117

02918-0-015

Figure 11. Supply Current vs. Clock Frequency

Figure 14. Reference Multiplying Bandwidth

90

V

= 5V ± 10%

DD

80

70

= 10V

REF

CS

60

50

40

30

20

10

0

V

OUT

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

02918-0-016

02918-0-018

Figure 12. Power Supply Rejection Ration vs. Frequency

Figure 15. Settling Time

–3.70

–3.75

–3.80

–3.85

–3.90

–3.95

–4.00

–4.05

20

0

–20

–40

–60

–80

–100

–120

–140

–160

–200

–100

0

100

200

300

400

0

5

10

15

20

25

TIME (ns)

02918-0-119

FREQUENCY (Hz)

02918-0-113

Figure 13. AD5545/AD5555 Analog THD

Figure 16. Midscale Transition and Digital Feedthrough

Rev. G | Page 8 of 24

Data Sheet

AD5545/AD5555

THEORY OF OPERATION

The AD5545/AD5555 contain a 16-/14-bit, current-output,

digital-to-analog converter, a serial-input register, and a DAC

register. Both parts require a minimum of a 3-wire serial data

These DACs are also designed to accommodate ac reference input

signals. The AD5545/AD5555 accommodate input reference

voltages in the range of –12 V to +12 V. The reference voltage

inputs exhibit a constant nominal input-resistance value of

5 kΩ, 30%. The DAC output (I_OUT) is code dependent, pro-

ducing various output resistances and capacitances. When

choosing an external amplifier, the user should take into

account the variation in impedance generated by the AD5545/

AD5555 on the amplifiers inverting input node. The feedback

resistance in parallel with the DAC ladder resistance dominates

output voltage noise.

LDAC

interface with an additional

update.

for dual channel simultaneous

DIGITAL-TO-ANALOG CONVERTER

The DAC architecture uses a current-steering R-2R ladder

design. Figure 17 shows the typical equivalent DAC. The DAC

contains a matching feedback resistor for use with an external

I-to-V converter amplifier. The R_FBpin is connected to the

output of the external amplifier. The I_OUTterminal is connected

to the inverting input of the external amplifier. These DACs are

designed to operate with either negative or positive reference

voltages. The V_DDpower pin is used only by the logic to drive

the DAC switches on and off. Note that a matching switch is

used in series with the internal 5 kΩ feedback resistor. If users

attempt to measure the R_FBvalue, power must be applied to V_DD

to achieve continuity. The V_REFinput voltage and the digital data

(D) loaded into the corresponding DAC register, according to

Equation 1 and Equation 2, determine the DAC output voltage.

5V

V

IN

V

2.500V

OUT

ADR03

GND

V

DD

R

A

FB

V

A

REF

2R

R

5kΩ

+3V

S2

S1

I

A

OUT

V

CC

V

OUT

AD8628

V

EE

AD5545/AD5555

V_OUT= –V_REF× D/65,536

(1)

(2)

LOAD

–3V

A

GND

V_OUT= –V_REF× D/16,384

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:

SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED

02918-0-006

DD

Note that the output full-scale polarity is the opposite of the

Figure 18. Recommended System Connections

V

_REFpolarity for dc reference voltages.

V

DD

R

V

R

REF

FB

2R

R

5kΩ

S2

S1

I

OUT

GND

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:

SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED

DD

02918-0-005

Figure 17. Equivalent R-2R DAC Circuit

Rev. G | Page 9 of 24

AD5545/AD5555

Data Sheet

to the DAC A register. At this time, the output is not updated. To

SERIAL DATA INTERFACE

CS

load DAC B data, pull

DAC B with the proper address and data, then pull

LDAC

low for an 18-bit duration and program

CS

The AD5545/AD5555 use a minimum 3-wire ( , SDI, CLK)

serial data interface for single channel update operation. With

Table 7 as an example (AD5545), users can tie

CS

high to

latch data to the DAC B register. Finally, pull

low and then

LDAC

low

high to update both the DAC A and DAC B outputs

simultaneously.

RS CS

and

high, and then pull

low for an 18-bit duration. New

serial data is then clocked into the serial-input register in an 18-

bit data-word format with the MSB bit loaded first. Table 8

defines the truth table for the AD5555. Data is placed on the

SDI pin and clocked into the register on the positive clock edge

of CLK. For the AD5545, only the last 18-bits clocked into the

Table 6 shows that each DAC A and DAC B can be individually

loaded with a new data value. In addition, a common new data

value can be loaded into both DACs simultaneously by setting Bit

A1 = A0 = high. This command enables the parallel combination

of both DACs, with I_OUTA and I_OUTB tied together, to act as one

DAC with significant improved noise performance.

CS

serial register are interrogated when the

pin is strobed high,

transferring the serial register data to the DAC register and

updating the output. If the applied microcontroller outputs

serial data in different lengths than the AD5545, such as 8-bit

bytes, three right justified data bytes can be written to the

AD5545. The AD5545 ignores the six MSB and recognizes the

18 LSB as valid data. After loading the serial register, the rising

ESD Protection Circuits

All logic input pins contain back-biased ESD protection Zeners

connected to digital ground (DGND) and V_DDas shown in

Figure 19.

V

DD

CS

edge of

transfers the serial register data to the DAC register

DIGITAL

INPUTS

CS

and updates the output; during the

not be toggled.

strobe, the CLK should

5kΩ

If users want to program each channel separately but update them

LDAC RS

DGND

simultaneously, program

and high initially, then

low for an 18-bit duration and program DAC A with the

CS

02918-0-007

CS

pull

proper address and data bits.

Figure 19. Equivalent ESD Protection Circuits

is then pulled high to latch data

Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format¹

MSB

LSB

Bit Position

Data Word

B17

A1

B16 B15

A0 D15

B14

D14

B13

D13

B12

D12 D11

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

CS

Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the line’s positive edge

returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the

decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in

LDAC

are used. If double-buffered data is not needed, the

pin can be tied logic low to disable the DAC registers.

Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format¹

MSB

LSB

B0

D0

Bit Position

Data Word

B15

A1

B14

A0

B13

D13

B12

D12

B11

D11

B10

D10

B9

D9

B8

D8

B7

D7

B6

D6

B5

D5

B4

D4

B3

D3

B2

D2

B1

D1

1

CS

Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the line’s positive edge

returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the

decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in

LDAC

are used. If double-buffered data is not needed, the

pin can be tied logic low to disable the DAC registers.

Table 6. Address Decode

A1

A0

DAC Decoded

None

0

1

DAC A

1

0

DAC B

1

DAC A and DAC B

Rev. G | Page 10 of 24

Data Sheet

AD5545/AD5555

Table 7. AD5545 Control Logic Truth Table^{1, 2}

CS

LDAC

RS

CLK

X

L

MSB

Serial Shift Register Function

Input Register Function

Latched

DAC Register

Latched

H

L

H

X

No effect

Shift register data advanced one bit

Latched

+

H

L

No effect

Latched

Selected DAC updated

with current SR current

Latched

+

H

X

L

H

L

X

0

No effect

Latched

Transparent

Latched

+

H

Latched data = 0x0000

Latched data = 0x8000

Latched data = 0x0000

Latched data = 0x8000

L

H

¹SR = shift register, + = positive logic transition, and X = don’t care.

²At power-on, both the input register and the DAC register are loaded with all 0s.

Table 8. AD5555 Control Logic Truth Table^{1, 2}

CS

CLK

LDAC

RS MSB

Serial Shift Register Function

Input Register Function

DAC Register

H

L

X

L

H

X

No effect

Shift register data advanced one bit

Latched

Selected DAC updated

with current SR current

Latched

+

H

L

No effect

+

H

X

L

H

L

X

0

No effect

Latched

Transparent

Latched

+

H

Latched data = 0x0000

Latched data = 0x2000

Latched data = 0x0000

Latched data = 0x2000

L

H

¹SR = shift register, + = positive logic transition, and X = don’t care.

²At power-on, both the input register and the DAC register are loaded with all 0s.

(see Figure 20). Users should not apply switching regulators for

_DDdue to the power supply rejection ratio degradation over

frequency.

POWER-UP SEQUENCE

V

It is recommended to power-up V_DDand ground prior to any

reference voltages. The ideal power-up sequence is A_GNDx,

DGND, V_DD, V_REFx, and digital inputs. A noncompliance

power-up sequence can elevate reference current, but the device

will resume normal operation once V_DDis powered.

AD5545/

AD5555

V

DD

C2

+

C1

10F 0.1F

A

X

GND

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. The input leads should be as direct as possible

with a minimum conductor length. Ground paths should have

low resistance and low inductance.

DGND

02918-0-008

Figure 20. Power Supply Bypassing and Grounding Connection

Similarly, it is also good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to

the device should be bypassed with 0.01 μF to 0.1 μF disc or

chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or

electrolytic capacitors should also be applied at V_DDto minimize

any transient disturbance and to filter any low frequency ripple

GROUNDING

The DGND and A_GNDx pins of the AD5545/AD5555 refer to the

digital and analog ground references. To minimize the digital

ground bounce, the DGND terminal should be joined remotely

at a single point to the analog ground plane (see Figure 20).

Rev. G | Page 11 of 24

AD5545/AD5555

Data Sheet

APPLICATIONS INFORMATION

STABILITY

BIPOLAR OUTPUT

V

DD

The AD5545/AD5555 is inherently a 2-quadrant multiplying

DAC. It can easily be set up for unipolar output operation. The

full-scale output polarity is the inverse of the reference input

voltage.

U1

C1

V

R

DD

FB

V

I

OUT

REF

V

O

AD8628

In some applications, it may be necessary to generate the full

4-quadrant multiplying capability or a bipolar output swing. This

is easily accomplished by using an additional external amplifier,

U4, configured as a summing amplifier (see Figure 23). In this

circuit, the second amplifier, U4, provides a gain of 2, which

increases the output span magnitude to 5 V. Biasing the external

amplifier with a 2.5 V offset from the reference voltage results in a

full 4-quadrant multiplying circuit. The transfer equation of this

circuit shows that both negative and positive output voltages are

created because the input data (D) is incremented from code zero

GND

AD5545/AD5555

U2

02918-0-020

Figure 21. Operational Compensation Capacitor for Gain Peaking

Prevention

In the I-to-V configuration, the I_OUTof the DAC and the

inverting node of the op amp must be connected as close as

possible, and proper PCB layout techniques must be employed.

Because every code change corresponds to a step function, gain

peaking may occur if the op amp has limited GBP, and if there

is excessive parasitic capacitance at the inverting node.

(V_OUT= −2.5 V) to midscale (V_OUT= 0 V) to full scale (V_OUT

+2.5 V).

=

An optional compensation capacitor, C1, can be added for

stability as shown in Figure 21. C1 should be found empirically,

but 6 pF is generally more than adequate for the compensation.

V

_OUT= (D/32,768 − 1) × V_REF(AD5545)

_OUT= (D/8192 − 1) × V_REF(AD5555)

(3)

(4)

V

For the AD5545, the external resistance tolerance becomes the

dominant error that users should be aware of.

POSITIVE VOLTAGE OUTPUT

To achieve the positive voltage output, an applied negative

reference to the input of the DAC is preferred over the output

inversion through an inverting amplifier because of the

resistors’ tolerance errors. To generate a negative reference, the

reference can be level shifted by an op amp such that the V_OUT

and GND pins of the reference become the virtual ground and

−2.5 V, respectively (see Figure 22).

R1

R2

10kΩ±0.01% 10kΩ±0.01%

C2

U4

+5V

U1

5kΩ±0.01%

V

V+

1/2

AD8620

O

R3

ADR03

C1

OUT

V

R

FB

V–

DD

5V

V

I

OUT IN

V

+5V

REF

GND

–5V

1/2

AD8620

ADR03

GND

–2.5 < V < +2.5

O

U3

V

OUT IN

U4

+5V

U1

AD5545/AD5555

Figure 23. Four-Quadrant Multiplying Application Circuit

U2

02918-0-022

GND

U3

C1

OUT

V

R

DD

FB

V+

1/2

AD8620

V–

I

V

REF

V

O

–2.5V

1/2

AD8628

GND

–5V

0 < V < +2.5

AD5545/AD5555

U2

O

02918-0-021

Figure 22. Positive Voltage Output Configuration

Rev. G | Page 12 of 24

Data Sheet

AD5545/AD5555

If the resistors are perfectly matched, Z_Ois infinite, which is

desirable, and the resistors behave as an ideal current source.

On the other hand, if they are not matched, Z_Ocan be either

positive or negative. The latter can cause oscillation. As a result,

C1 is needed to prevent the oscillation. For critical applications,

C1 could be found empirically but typically falls in the range of

a few picofarads.

PROGRAMMABLE CURRENT SOURCE

Figure 24 shows a versatile V-to-I conversion circuit using

improved Howland Current Pump. In addition to the precision

current conversion it provides, this circuit enables a bidirec-

tional current flow and high voltage compliance. This circuit

can be used in a 4 mA to 20 mA current transmitter with up to

a 500 Ω of load. In Figure 24, it shows that if the resistor

network is matched, the load current is

V

DD

U1

(

R2 + R3)

R1

R3

V

R

FB

DD

I_L=

×V_REF×D

(5)

I

V

R1'

R2'

OUT

REF

GND

150kΩ 15kΩ

AD8628

R3, in theory, can be made small to achieve the current needed

within the U3 output current driving capability. This circuit is

versatile such that the AD8510 can deliver 20 mA in both

directions, and the voltage compliance approaches 15 V, which

is mainly limited by the supply voltages of U3. However, users

must pay attention to the compensation. Without C1, it can be

shown that the output impedance becomes

C1

10pF

AD5545/AD5555

U2

V

DD

U3

R3'

50Ω

V+

AD8510

V–

R3

50Ω

V

SS

V

L

′

R1 R3

(

R1+ R2)

Z_O=

(6)

R1

150kΩ

R2

15kΩ

′

R1

(

R2 + R3

)

– R1

(

R2 + R3

)

I

LOAD

L

02918-0-023

Figure 24. Programmable Current Source with Bidirectional

Current Control and High Voltage Compliance Capabilities

Rev. G | Page 13 of 24

AD5545/AD5555

Data Sheet

By putting Equations 7 through 10 together, the following

results:

DAC WITH PROGRAMMABLE INPUT

REFERENCE RANGE

Because high voltage references can be costly, users may

consider using one of the DACs, a digital potentiometer, and a

low voltage reference to form a single-channel DAC with a

programmable input reference range. This approach optimizes

the programmable range as well as facilitates future system

upgrades with just software changes. Figure 25 shows this

implementation. V_REFAB is in the feedback network, therefore,













D_C

128  D_C

1

V_REFAB V_REF

(11)

D_A

2^N

D_C

1



128  D_C

Table 9 shows a few examples of V_REFAB of the 14-bit AD5555.

Table 9. V_REFABvs. D_Band D_Cof the AD5555

















D_C

D_A

V_REFAB

R_WB

R_WA

D_AR_WB



V_REFAB V_REF 1

– –V_{REF_AB}



(7)

2^N



0

X

0

8192

0

8192

0

V_REF

R_WA



32

64

96

1.33 V_REF

1.6 V_REF

2 V_REF

4 V_REF

where:

V_REFAB = reference voltage of V_REFA and V_REF

_REF= external reference voltage

D_A= DAC A digital code in decimal

N = number of bits of DAC

B

V

8192

–8 V_REF

R

_WBand R_WAare digital potentiometer 128-step programmable

The output of DAC B is, therefore,

resistances and are given by

D_B

V_OB V_REFAB

(12)

D_C

128

R_WB

_WA

R_WB



R_AB

(8)

(9)

2^N

where D_Bis the DAC B digital code in decimal.

128  D_C

R

R_AB

The accuracy of V_REFAB is affected by the matching of the input

and feedback resistors and, therefore, a digital potentiometer is

used for U4 because of its inherent resistance matching. The

AD7376 is a 30 V or 15 V, 128-step digital potentiometer. If

15 V or 7.5 V is adequate for the application, a 256-step

AD5260 digital potentiometer can be used instead.

128

D_C



(10)

R_WA128  D_C

where D_C= digital potentiometer digital code in decimal

(0 ≤ D_C≤ 127).

+5V

C1

+15V

R

A

V

FB

DD

I

A

OUT

V+

OP4177

V–

U4

A

B

V

A

REF

U1A

A

AD7376

A

W

C2

GND

+15V

2

2.2p

–15V

U2A

U3

V

IN

3

5

6

OP4177

TEMP TRIM

AD5555

V

REF_AB

REF

V

OUT

GND

U2C

4

ADR03

C3

R

B

FB

POT

I

B

OUT

V

B

O

V

REF

B

OP4177

U1B

A

B

GND

U2B

02918-0-024

Figure 25. DAC with Programmable Input Reference Range

Rev. G | Page 14 of 24

Data Sheet

AD5545/AD5555

The input bias current of an op amp also generates an offset at

the voltage output because of the bias current flowing in the

feedback resistor, R_FB.

REFERENCE SELECTION

When selecting a reference for use with the AD55xx series

of current output DACs, pay attention to the output voltage,

temperature coefficient specification of the reference. Choosing

a precision reference with a low output temperature coefficient

minimizes error sources. Table 10 lists some of the references

available from Analog Devices, Inc., that are suitable for use

with this range of current output DACs.

Common-mode rejection of the op amp is important in voltage-

switching circuits because it produces a code-dependent error

at the voltage output of the circuit.

Provided that the DAC switches are driven from true wideband

low impedance sources (V_INand AGND), they settle quickly.

Consequently, the slew rate and settling time of a voltage-switching

DAC circuit is determined largely by the output op amp. To obtain

minimum settling time in this configuration, minimize capacitance

at the V_REFnode (the voltage output node in this application) of

the DAC. This is done by using low input capacitance buffer

amplifiers and careful board design.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an

amplifier with low input bias currents and low input offset voltage.

Because of the code-dependent output resistance of the DAC,

the input offset voltage of an op amp is multiplied by the variable

gain of the circuit. A change in this noise gain between two

adjacent digital fractions produces a step change in the output

voltage due to the amplifier’s input offset voltage. This output

voltage change is superimposed upon the desired change in

output between the two codes and gives rise to a differential

linearity error, which, if large enough, can cause the DAC to be

nonmonotonic.

Analog Devices offers a wide range of amplifiers for both precision

dc and ac applications, as listed in Table 11 and Table 12.

Table 10. Suitable Analog Devices Precision References

Maximum Temperature

Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C)

I_SS(mA) Output Noise (µV p-p) Package(s)

ADR01

ADR02

ADR03

ADR06

ADR420 2.048

ADR421 2.50

ADR423 3.00

ADR425 5.00

ADR431 2.500

ADR435 5.000

ADR391 2.5

ADR395 5.0

10

0.05

0.06

0.1

0.05

0.04

0.16

0.10

3

9

3

9

3

9

3

9

3

9

1

0.5

0.8

0.12

20

10

6

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8, MSOP-8

TSOT-5

5.0

2.5

3.0

6

10

1.75

2

3.4

3.5

8

5

8

TSOT-5

Rev. G | Page 15 of 24

AD5545/AD5555

Data Sheet

Table 11. Suitable Analog Devices Precision Op Amps

V

_OSMaximum I_BMaximum 0.1 Hz to 10 Hz

Part No.

OP97

OP1177

AD8675

AD8671

Supply Voltage (V) (μV)

(nA)

Noise (μV p-p)

Supply Current (μA)

Package(s)

±2 ꢀo ±2±

±2.5 ꢀo ±15

±5 ꢀo ±18

±5 ꢀo ±15

25

6±

75

125

5±

65

±.1

2

12

±.5

±.4

±.1

±.±77

±.1

2.3

2.4

6±±

5±±

23±±

3±±±

2±±±

4±

SOIC-8 , PDIP-8

MSOP-8, SOIC-8

SOIC-8, SOT-23-5

TSOT-5

ADA4±±4-1 ±5 ꢀo ±15

9±

AD86±3

AD86±7

AD86±5

AD8615

AD8616

1.8 ꢀo 5

2.7 ꢀo 5

±.±±1

4±

MSOP-8, SOIC-8

WLCSP-5, SOT-23-5

TSOT-5

1±±±

2±±±

MSOP-8, SOIC-8

Table 12. Suitable Analog Devices High Speed Op Amps

Part No.

AD8±65

AD8±66

AD8±21

AD8±38

Supply Voltage (V) BW @ ACL (MHz)

Slew Rate (V/μs)

V_OS(Max) (μV)

I_B(Max) (nA)

±.±±6

1±,5±±

75±

1±±

5±±

35±

Package(s)

5 ꢀo 24

3 ꢀo 12

145

49±

35±

6±±

325

32±

18±

12±

425

31±

1±±±

85±

65±

13±±

15±±

1±±±

3±±±

35

5±±±

6±±±

1±,±±±

SOIC-8, SOT-23-5

SOIC-8, MSOP-8

SOIC-8, SC7±-5

LFCSP-8, SOIC-8

SOT-23-5, SOIC-8

SOIC-8, MSOP-8

SOT-23-5, SOIC-8

SOIC-8, MSOP-8

SOIC-8, PDIP-8

ADA4899-1 5 ꢀo 12

AD8±57

AD8±58

AD8±61

AD8±62

AD9631

3 ꢀo 12

2.7 ꢀo 8

±3 ꢀo ±6

35±

7±±±

Rev. G | Page 16 of 24

Data Sheet

AD5545/AD5555

EVALUATION BOARD FOR THE AD5545

The EVAL-AD5545SDZ is used in conjunction with an SDP1Z

system demonstration platform board available from Analog

Devices, which is purchased separately from the evaluation

board. The USB-to-SPI communication to the AD5545 is

completed using this Blackfin®-based demonstration board.

SYSTEM DEMONSTRATION PLATFORM

The system demonstration platform (SDP) is a hardware and

software evaluation tool for use in conjunction with product

evaluation boards. The SDP board is based on the Blackfin

ADSP-BF527 processor with USB connectivity to the PC

through a USB 2.0 high speed port. For more information about

this device, see the system demonstration platform web page.

OPERATING THE EVALUATION BOARD

The evaluation board requires 12 V and +5 V supplies.

The +12 V V_DDand −12 V V_SSare used to power the output

amplifier, and the +5 V is used to power the DAC (DVDD).

Figure 27. Evaluation Board Software—AD5545 Dual DAC

Figure 26. Evaluation Board Software – Device Selection Window

Rev. G | Page 17 of 24

AD5545/AD5555

Data Sheet

EVALUATION BOARD SCHEMATICS

0 2 0 8 -

0

Figure 28. EVAL-AD5545SDZ Schematic Part A

Rev. G | Page 18 of 24

Data Sheet

AD5545/AD5555

0 2 0 9 -

0

Figure 29. EVAL-AD5545SDZ Schematic Part B

Rev. G | Page 19 of 24

AD5545/AD5555

Data Sheet

0 3 0 0 -

0

Figure 30. EVAL-AD5545SDZ Schematic Part B

Rev. G | Page 20 of 24

Data Sheet

AD5545/AD5555

EVALUATION BOARD LAYOUT

Figure 31. Silkscreen

Figure 32. Component Side

Rev. G | Page 21 of 24

AD5545/AD5555

Data Sheet

Figure 33. Solder Side

Rev. G | Page 22 of 24

Data Sheet

AD5545/AD5555

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

INL

LSB

DNL

LSB

Resolution Temperature

Package

Description

Package

Ordering

Qty

Model^{1, 2}

(Bits)

Range

Option

RU-16

AD5545BRUZ

AD5545BRUZ-REEL7

AD5545CRUZ

AD5545CRUZ-REEL7

AD5555CRU

AD5555CRU-REEL7

AD5555CRUZ

2

1

16

−40°C to +85°C

Evaluation Board

16-Lead TSSOP

96

1000

96

1000

96

1000

96

1

14

AD5555CRUZ-REEL7

EV-AD5544/45SDZ

1000

¹The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.

²Z = RoHS Compliant Part.

Rev. G | Page 23 of 24

AD5545/AD5555

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02918-0-4/13(G)

Rev. G | Page 24 of 24


型号：	AD8062ARMZ-REEL
厂家：	ADI
描述：	IC DUAL OP-AMP, 6000 uV OFFSET-MAX, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8, Operational Amplifier
文件：	总24页 (文件大小：924K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8062ARMZ-REEL [ADI]

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