AD8065AR-EBZ [ADI]
High Performance, 145 MHz FastFET Op Amps; 高性能， 145 MHz的FastFET运算放大器
| 型号： | AD8065AR-EBZ |
| 厂家： | 
ADI |
| 描述： | High Performance, 145 MHz FastFET Op Amps |
| 文件： | 总29页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance, 145 MHz
FastFET Op Amps
AD8065/AD8066
FEATURES
APPLICATIONS
Automotive driver assistance systems
Photodiode preamps
Filters
A/D drivers
Level shifting
Qualified for automotive applications
FET input amplifier
1 pA input bias current
Low cost
High speed: 145 MHz, −3 dB bandwidth (G = +1)
180 V/μs slew rate (G = +2)
Low noise
Buffering
CONNECTION DIAGRAMS
AD8065
AD8065
7 nV/√Hz (f = 10 kHz)
0.6 fA/√Hz (f = 10 kHz)
V
+V
1
2
3
5
OUT
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
S
–V
S
+V
V
S
Wide supply voltage range: 5 V to 24 V
Single-supply and rail-to-rail output
Low offset voltage 1.5 mV maximum
High common-mode rejection ratio: −100 dB
Excellent distortion specifications
SFDR −88 dBc @ 1 MHz
Low power: 6.4 mA/amplifier typical supply current
No phase reversal
Small packaging: SOIC-8, SOT-23-5, and MSOP-8
4
+IN
–IN
OUT
TOP VIEW
(Not to Scale)
–V
S
NC
TOP VIEW
(Not to Scale)
AD8066
1
2
3
4
8
7
6
5
+V
S
V
OUT1
V
–IN1
+IN1
OUT2
–IN2
+IN2
–V
S
TOP VIEW
(Not to Scale)
Figure 1.
The AD8065/AD8066 are high performance, high speed, FET
input amplifiers available in small packages: SOIC-8, MSOP-8,
and SOT-23-5. They are rated to work over the industrial
temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
The AD8065/AD80661 FastFET™ amplifiers are voltage feedback
amplifiers with FET inputs offering high performance and ease
of use. The AD8065 is a single amplifier, and the AD8066 is a
dual amplifier. These amplifiers are developed in the Analog
Devices, Inc. proprietary XFCB process and allow exceptionally
low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as
very high input impedance.
The AD8065WARTZ-REEL7 is fully qualified for automotive
applications. It is rated to operate over the extended temperature
range (−40°C to +105°C), up to a maximum supply voltage
range of +5V only.
24
With a wide supply voltage range from 5 V to 24 V, the ability to
operate on single supplies, and a bandwidth of 145 MHz, the
AD8065/AD8066 are designed to work in a variety of applications.
For added versatility, the amplifiers also contain rail-to-rail outputs.
21
18
15
12
9
G = +10
G = +5
V
= 200mV p-p
O
Despite the low cost, the amplifiers provide excellent overall
performance. The differential gain and phase errors of 0.02%
and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz,
make these amplifiers ideal for video applications. Additionally,
they offer a high slew rate of 180 V/μs, excellent distortion (SFDR
of −88 dBc @ 1 MHz), extremely high common-mode rejection
of −100 dB, and a low input offset voltage of 1.5 mV maximum
under warmed up conditions. The AD8065/AD8066 operate
using only a 6.4 mA/amplifier typical supply current and are
capable of delivering up to 30 mA of load current.
G = +2
G = +1
6
3
0
–3
–6
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 2. Small Signal Frequency Response
1 Protected by U. S. Patent No. 6,262,633.
Rev. J
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD8065_8066*
Last content update 08/20/2013 06:24 pm
DOCUMENTATION
PARAMETRIC SELECTION TABLES
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
AN-649: Using the Analog Devices Active Filter Design Tool
AN-581: Biasing and Decoupling Op Amps in Single Supply
Applications
AN-402: Replacing Output Clamping Op Amps with Input Clamping
Amps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
dBm/dBu/dBv Calculator
Constraints in Low Voltage High Speed Systems
MT-060: Choosing Between Voltage Feedback and Current Feedback
Op Amps
Analog Filter Wizard 2.0
MT-059: Compensating for the Effects of Input Capacitance on VFB
Power Dissipation vs Die Temp
ADIsimOpAmp™
and CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
OpAmp Stability
AD8065 SPICE Macro-Model
AD8066 SPICE Macro-Model
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don’t Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-Order
System
MT-049: Op Amp Total Output Noise Calculations for Single-Pole
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the AD8065
View the Evaluation Boards and Kits page for the AD8066
Symbols and Footprints for AD8065
System
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and
Equivalent Noise Bandwidth
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
FOR THE AD8065
Symbols and Footprints for AD8066
DESIGN SUPPORT
AN-108: JFET-Input Amps are Unrivaled for Speed and Accuracy
Submit your support request here:
Linear and Data Converters
AN-356: User's Guide to Applying and Measuring Operational
Amplifier Specifications
Embedded Processing and DSP
CN-0272: 2 MHz Bandwidth PIN Photodiode Preamp with Dark
Current Compensation
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
1-800-262-5643
00800-266-822-82
4006-100-006
1800-419-0108
8-800-555-45-90
CN-0055: Programmable Gain Element Using the
AD5450/AD5451/AD5452/AD5453 Current Output DAC Family
CN-0034: Unipolar, Precision DC Digital-to-Analog Conversion Using
the AD5426/AD5432/AD5443 8-Bit to12-Bit DACs
India:
Russia:
UG-127: Universal Evaluation Board for High Speed Op Amps in
Quality and Reliability
Lead(Pb)-Free Data
SOT-23-5/SOT-23-6 Packages
UG-101: Evaluation Board User Guide
FOR THE AD8066
CN-0053: Precision, Bipolar, Configuration for the AD5450/1/2/3
8-14bit Multiplying DACs
SAMPLE & BUY
AD8065
CN-0036: Precision, Bipolar Configuration for the
AD5426/AD5432/AD5443 8-Bit to12-Bit DACs
AD8066
MT-047: Op Amp Noise
View Price & Packaging
Request Evaluation Board and Samples
Check Inventory & Purchase
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
UG-129: Evaluation Board User Guide
Find Local Distributors
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD8065/AD8066
TABLE OF CONTENTS
Features .............................................................................................. 1
Wideband Operation................................................................. 21
Input Protection ......................................................................... 21
Thermal Considerations............................................................ 22
Input and Output Overload Behavior ..................................... 22
Layout, Grounding, and Bypassing Considerations .................. 23
Power Supply Bypassing............................................................ 23
Grounding................................................................................... 23
Leakage Currents........................................................................ 23
Input Capacitance ...................................................................... 23
Output Capacitance ................................................................... 23
Input-to-Output Coupling........................................................ 24
Wideband Photodiode Preamp................................................ 24
High Speed JFET Input Instrumentation Amplifier.............. 25
Video Buffer................................................................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 28
Automotive Products................................................................. 28
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications 5 V........................................................................... 4
Specifications 12 V......................................................................... 6
Specifications +5 V........................................................................... 7
Absolute Maximum Ratings............................................................ 9
Maximum Power Dissipation ..................................................... 9
Output Short Circuit.................................................................... 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 17
Theory of Operation ...................................................................... 20
Closed-Loop Frequency Response........................................... 20
Noninverting Closed-Loop Frequency Response.................. 20
Inverting Closed-Loop Frequency Response ......................... 20
Rev. J | Page 2 of 28
AD8065/AD8066
REVISION HISTORY
8/10—Rev. I to Rev. J
12/05—Rev. E to Rev. F
Changes to Features Section, Applications Section, and General
Description Section...........................................................................1
Change to Table 1..............................................................................4
Change to Table 3..............................................................................7
Changes to Table 4 ............................................................................9
Changes to Figure 9.........................................................................10
Changes to Inverting Closed-Loop Frequency Response
Section ..............................................................................................20
Moved Leakage Currents Section, Input Capacitance Section,
and Output Capacitance Section...................................................23
Moved Input-to-Input Coupling Section, Wideband
Photodiode Preamp Section, and Figure 59 ................................24
Changes to Table 5 ..........................................................................25
Moved Figure 60 and High Speed JFET Input Instrumentation
Amplifier Section ............................................................................25
Updated Outline Dimensions........................................................27
Changes to Ordering Guide...........................................................28
Added Automotive Products Section ...........................................28
Updated Format ................................................................. Universal
Changes to Features..........................................................................1
Changes to General Description.....................................................1
Changes to Figure 22 through Figure 27......................................11
Updated Outline Dimensions........................................................25
Changes to Ordering Guide...........................................................26
2/04—Rev. D to Rev. E.
Updated Format ................................................................Universal
Updated Figure 56......................................................................... 21
Updated Outline Dimensions...................................................... 25
Updated Ordering Guide ............................................................. 26
11/03—Rev. C to Rev. D.
Changes to Features.........................................................................1
Changes to Connection Diagrams.................................................1
Updated Ordering Guide ................................................................5
Updated Outline Dimensions...................................................... 22
4/03—Rev. B to Rev. C.
Added SOIC-8 (R) for the AD8065...............................................4
3/09—Rev. H to Rev. I
Changes to High Speed JFET Input Instrumentation Amplifier
Section ..............................................................................................23
Updated Outline Dimensions........................................................24
2/03—Rev. A to Rev. B.
Changes to Absolute Maximum Ratings.......................................4
Changes to Test Circuit 10 ........................................................... 14
Changes to Test Circuit 11 ........................................................... 15
Changes to Noninverting Closed-Loop Frequency Response 16
Changes to Inverting Closed-Loop Frequency Response ....... 16
Updated Figure 6 .......................................................................... 18
Changes to Figure 7 ...................................................................... 19
Changes to Figure 10 .................................................................... 21
Changes to Figure 11 .................................................................... 22
Changes to High Speed JFET Instrumentation Amplifier ...... 22
Changes to Video Buffer .............................................................. 22
9/08—Rev. G to Rev. H
Deleted Usable Range Parameter, Table 1......................................3
Deleted Usable Range Parameter, Table 2......................................4
Deleted Usable Range Parameter, Table 3......................................5
Changes to Layout.............................................................................6
Changes to Input and Output Overload Behavior Section........19
Changes to Table 5 Expressions Column.....................................22
1/06—Rev. F to Rev. G
Changes to Ordering Guide...........................................................26
8/02—Rev. 0 to Rev. A.
Added AD8066..................................................................Universal
Added SOIC-8 (R) and MSOP-8 (RM).........................................1
Edits to General Description..........................................................1
Edits to Specifications......................................................................2
New Figure 2.....................................................................................5
Changes to Ordering Guide............................................................5
Edits to TPCs 18, 25, and 28...........................................................8
New TPC 36................................................................................... 11
Added Test Circuits 10 and 11 .................................................... 14
MSOP (RM-8) Added .................................................................. 23
Rev. J | Page 3 of 28
AD8065/AD8066
SPECIFICATIONS 5 ꢀ
@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
AD8065WARTZ only: TMIN − TMAX
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −5.5 V to +5.5 V
G = −1, −5.5 V to +5.5 V
G = +2, VO = 4 V step
AD8065WARTZ only: TMIN − TMAX
G = +2, VO = 2 V step
100
88
100
145
MHz
MHz
MHz
MHz
MHz
MHz
ns
120
50
42
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
7
175
170
180
ns
130
155
V/μs
V/μs
ns
Settling Time to 0.1%
55
G = +2, VO = 8 V step
205
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 1 MHz, G = +2, VO = 8 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−88
−67
−73
24
7
0.6
dBc
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.02
0.02
Degrees
Input Offset Voltage
VCM = 0 V, SOIC package
AD8065WARTZ only: TMIN − TMAX
0.4
1
1.5
2.6
17
17
6
mV
mV
μV/°C
μV/°C
pA
Input Offset Voltage Drift
Input Bias Current
AD8065WARTZ only: TMIN − TMAX
SOIC package
2
TMIN to TMAX
25
1
125
10
pA
pA
Input Offset Current
Open-Loop Gain
TMIN to TMAX
VO = 3 V, RL = 1 kΩ
AD8065WARTZ only: TMIN − TMAX
1
113
125
pA
dB
dB
100
100
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
−5 to +1.7
−5 to +1.7
−85
−82
−82
−5.0 to +2.4
V
V
dB
dB
dB
AD8065WARTZ only: TMIN − TMAX
VCM = −1 V to +1 V
VCM = −1 V to +1 V (SOT-23)
AD8065WARTZ only: TMIN − TMAX
Common-Mode Rejection Ratio
−100
−91
Rev. J | Page 4 of 28
AD8065/AD8066
Parameter
Conditions
Min
Typ
Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
AD8065WARTZ only: TMIN − TMAX
RL = 150 Ω
−4.88 to +4.90
−4.88 to +4.90
−4.94 to +4.95
V
V
V
−4.8 to +4.7
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
35
90
20
mA
mA
pF
30% overshoot G = +1
Operating Range
5
5
24
10
V
V
AD8065WARTZ only: TMIN − TMAX
Quiescent Current per Amplifier
Power Supply Rejection Ratio
6.4
7.2
7.2
mA
mA
dB
dB
AD8065WARTZ only: TMIN − TMAX
PSRR
AD8065WARTZ only: TMIN − TMAX
−85
−85
−100
Rev. J | Page 5 of 28
AD8065/AD8066
SPECIFICATIONS 1ꢁ ꢀ
@ TA = 25°C, VS = 12 V, RL = 1 kΩ, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −12.5 V to +12.5 V
G = −1, −12.5 V to +12.5 V
G = +2, VO = 4 V step
100
100
145
115
50
40
7
175
170
180
55
MHz
MHz
MHz
MHz
MHz
ns
ns
V/μs
ns
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery
Output Overdrive Recovery
Slew Rate
130
Settling Time to 0.1%
G = +2, VO = 2 V step
G = +2, VO = 10 V step
250
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 1 MHz, G = +2, VO = 10 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−100
−67
−85
24
7
1
dBc
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.04
0.03
Degrees
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
VCM = 0 V, SOIC package
0.4
1
3
25
2
1.5
17
7
mV
μV/°C
pA
pA
pA
SOIC package
TMIN to TMAX
Input Offset Current
10
TMIN to TMAX
2
pA
Open-Loop Gain
VO = 10 V, RL = 1 kΩ
103
114
dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
−12 to +8.5
−85
−82
−12.0 to +9.5
−100
−91
V
dB
dB
Common-Mode Rejection Ratio
VCM = −1 V to +1 V
VCM = −1 V to +1 V (SOT-23)
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
−11.8 to +11.8 −11.9 to +11.9
V
RL = 350 Ω
−11.25 to +11.5
V
Output Current
VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
30
120
25
mA
mA
pF
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
30% overshoot G = +1
Operating Range
5
24
V
Quiescent Current per Amplifier
Power Supply Rejection Ratio
6.6
−93
7.4
mA
dB
PSRR
−84
Rev. J | Page 6 of 28
AD8065/AD8066
SPECIFICATIONS +5 ꢀ
@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
G = +1, VO = 0.2 V p-p (AD8065)
AD8065WARTZ only: TMIN − TMAX
G = +1, VO = 0.2 V p-p (AD8066)
G = +2, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +2, VO = 0.2 V p-p
G = +1, −0.5 V to +5.5 V
G = −1, −0.5 V to +5.5 V
G = +2, VO = 2 V step
AD8065WARTZ only: TMIN − TMAX
G = +2, VO = 2 V step
125
90
110
155
MHz
MHz
MHz
MHz
MHz
MHz
ns
130
50
43
Bandwidth for 0.1 dB Flatness
Input Overdrive Recovery Time
Output Recovery Time
Slew Rate
6
175
170
160
ns
105
123
V/μs
V/μs
ns
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
60
fC = 1 MHz, G = +2, VO = 2 V p-p
fC = 5 MHz, G = +2, VO = 2 V p-p
fC = 10 MHz, RL = 100 Ω
f = 10 kHz
f = 10 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
−65
−50
22
7
0.6
dBc
dBc
dBm
nV/√Hz
fA/√Hz
%
Third-Order Intercept
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
0.13
0.16
Degrees
Input Offset Voltage
VCM = 1.0 V, SOIC package
AD8065WARTZ only: TMIN − TMAX
0.4
1
1.5
2.6
17
17
5
mV
mV
μV/ºC
μV/ºC
pA
Input Offset Voltage Drift
Input Bias Current
AD8065WARTZ only: TMIN − TMAX
SOIC package
1
TMIN to TMAX
25
1
125
5
pA
pA
Input Offset Current
Open-Loop Gain
TMIN to TMAX
1
113
125
pA
dB
dB
dB
VO = 1 V to 4 V (AD8065)
AD8065WARTZ only: TMIN − TMAX
VO = 1 V to 4 V (AD8066)
100
100
90
103
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
1000 || 2.1
1000 || 4.5
GΩ || pF
GΩ || pF
0 to 1.7
0 to 1.7
−74
−78
−76
0 to 2.4
V
V
dB
dB
dB
AD8065WARTZ only: TMIN − TMAX
VCM = 0.5 V to 1.5 V
VCM = 1 V to 2 V (SOT-23)
AD8065WARTZ only: TMIN-TMAX
Common-Mode Rejection Ratio
−100
−91
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
AD8065WARTZ only: TMIN − TMAX
RL = 150 Ω
0.1 to 4.85
0.1 to 4.85
0.03 to 4.95
V
V
V
0.07 to 4.83
Output Current
Short-Circuit Current
Capacitive Load Drive
VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz
35
75
5
mA
mA
pF
30% overshoot G = +1
Rev. J | Page 7 of 28
AD8065/AD8066
Parameter
Conditions
Min
Typ
Max Unit
POWER SUPPLY
Operating Range
5
5
24
10
V
V
AD8065WARTZ only: TMIN − TMAX
Quiescent Current per Amplifier
Power Supply Rejection Ratio
5.8
6.4
7.0
7.0
mA
mA
dB
dB
AD8065WARTZ only: TMIN − TMAX
PSRR
AD8065WARTZ only: TMIN − TMAX
−78
−78
−100
Rev. J | Page 8 of 28
AD8065/AD8066
ABSOLUTE MAXIMUM RATINGS
RMS output voltages should be considered. If RL is referenced to
VS−, as in single-supply operation, then the total drive power is
Table 4.
Parameter
Rating
VS × IOUT
.
Supply Voltage
26.4 V
Power Dissipation
See Figure 3
VEE − 0.5 V to VCC + 0.5 V
1.8 V
−65°C to +125°C
−40°C to +85°C
−40°C to +105°C
300°C
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply.
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
AD8065WARTZ Only
2
(
VS/4
RL
)
PD =
(
VS × IS
)
+
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
Lead Temperature
(Soldering, 10 sec)
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1.5
MSOP-8
SOIC-8
1.0
SOT-23-5
MAXIMUM POWER DISSIPATION
0.5
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8065/AD8066.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
0
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduce
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.
The still air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated by
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC (125°C/W),
SOT-23 (180°C/W), and MSOP (150°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
TJ = TA + (PD × θJA)
OUTPUT SHORT CIRCUIT
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS /2 × IOUT, some of
Shorting the output to ground or drawing excessive current for
the AD8065/AD8066 will likely cause catastrophic failure.
ESD CAUTION
which is dissipated in the package and some in the load (VOUT
OUT). The difference between the total drive power and the load
power is the drive power dissipated in the package.
×
I
PD = Quiescent Power +
Total Drive Power − Load Power
2
V
VOUT
RL
VOUT
RL
⎛
⎜
⎞
⎟
S
PD =
(
VS × IS
)
+
×
−
2
⎝
⎠
Rev. J | Page 9 of 28
AD8065/AD8066
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: 5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C.
24
21
18
15
12
9
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
R
= 150Ω
L
G = +10
G = +5
G = +2
V
V
= 0.2V p-p
= 0.7V p-p
V
= 200mV p-p
OUT
O
OUT
V
= 1.4V p-p
OUT
G = +2
G = +1
6
3
0
–3
–6
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 4. Small Signal Frequency Response for Various Gains
Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)
6
4
9
8
7
6
5
4
3
V
= 200mV p-p
V = 200mV p-p
O
O
G = +1
G = +2
V
= +5V
S
V
= +5V
S
2
V
= ±5V
S
V
= ±5V
S
0
V
= ±12V
S
V
= ±12V
S
–2
–4
–6
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Supplies
(See Figure 42)
Figure 8. Small Signal Frequency Response for Various Supplies
(See Figure 43)
8
2
V
= 2V p-p
O
V
= 2V p-p
O
G = +2
G = +1
7
6
5
4
3
2
1
0
V
= +5V
1
0
S
V
= ±5V
S
V
= ±12V
S
V
= ±5V
S
–1
–2
–3
–4
–5
V
= ±12V
S
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response for Various Supplies
(See Figure 43)
Figure 6. Large Signal Frequency Response for Various Supplies
(See Figure 42)
Rev. J | Page 10 of 28
AD8065/AD8066
9
6
8
6
V
= 200mV p-p
O
C
R
= 25pF
L
G = +1
= 20Ω
SNUB
C
C
= 25pF
= 20pF
C
= 55pF
= 25pF
L
L
L
C
= 5pF
L
4
C
L
3
2
0
0
C
= 5pF
L
–2
–4
–6
–8
–3
–6
–9
V
= 200mV p-p
O
G = +2
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42)
Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43)
8
8
V
= 0.2V p-p
OUT
R
= 100Ω
6
4
7
6
5
4
3
2
1
0
L
V
= 2V p-p
= 4V p-p
G = +2
OUT
R
= 1kΩ
L
2
V
OUT
0
–2
–4
–6
–8
V
= 200mV p-p
O
G = +2
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Frequency Response for Various Output Amplitudes
(See Figure 43)
Figure 14. Small Signal Frequency Response for Various RLOAD (See Figure 43)
80
60
40
20
0
120
60
14
12
10
8
V
= 200mV p-p
O
G = +2
PHASE
R
R
= R = 1kΩ,
F
S
G
= 500Ω
R
R
= R = 500Ω,
F
S
G
0
= 250Ω
6
GAIN
R
R
C
= R = 500Ω,
F
S
F
G
4
= 250Ω,
–60
–120
–180
R
= R = 1kΩ,
G
F
= 2.2pF
R
= 500Ω,
S
2
C
= 3.3pF
F
0
–2
–4
–20
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Small Signal Frequency Response for Various RF/CF (See Figure 43)
Figure 15. Open-Loop Response
Rev. J | Page 11 of 28
AD8065/AD8066
–40
–50
–30
–40
–50
G = +2
–60
HD2 G = +2
–60
HD3 G = +2
–70
–70
HD2 R = 150Ω
L
HD2 R = 1kΩ
HD2 G = +1
L
–80
–80
HD3 R = 1kΩ
L
–90
–90
HD3 R = 150Ω
L
HD3 G = +1
–100
–110
–120
–100
–110
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 19. Harmonic Distortion vs. Frequency for Various Gains
(See Figure 42 and Figure 43)
Figure 16. Harmonic Distortion vs. Frequency for Various Loads
(See Figure 43)
–20
–30
–30
V
= ±12V
S
–40
–50
G = +2
= ±12V
F = 1MHz
G = +2
HD2 V = 20V p-p
V
O
S
–40
HD3 V = 20V p-p
–50
O
–60
–60
HD2 V = 10V p-p
O
HD2 R = 150Ω
–70
L
–70
HD3 R = 150Ω
L
–80
HD3 V = 10V p-p
–80
O
–90
HD2 R = 300Ω
–90
L
–100
–110
–120
HD2 V = 2V p-p
–100
–110
–120
O
HD3 R = 300Ω
L
HD3 V = 2V p-p
O
0.1
1.0
10.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
OUTPUT AMPLITUDE (V p-p)
FREQUENCY (MHz)
Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = 12 V
(See Figure 43)
Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 43)
50
100
10
1
R
= 100Ω
L
V
= ±12V
S
45
40
35
30
25
20
15
V
= ±5V
S
V
= +5V
S
10
100
1k
10k
100k
1M
10M
100M
1G
1
10
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 21. Voltage Noise
Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage
Rev. J | Page 12 of 28
AD8065/AD8066
G = +1
C
= 20pF
G = +1
L
C
= 5pF
L
25ns/DIV
50mV/DIV
25ns/DIV
50mV/DIV
Figure 22. Small Signal Transient Response 5 V Supply (See Figure 42)
Figure 25. Small Signal Transient Response 5 V (See Figure 42)
G = +1
G = +2
5µs
V
= 10V p-p
= 4V p-p
OUT
V
= ±12V
S
V
= ±12V
S
V
= 10V p-p
= 2V p-p
OUT
V
OUT
V
OUT
V
= 2V p-p
OUT
50ns/DIV
2V/DIV
50ns/DIV
2V/DIV
Figure 23. Large Signal Transient Response (See Figure 42)
Figure 26. Large Signal Transient Response (See Figure 43)
G = –1
G = +1
V
= ±5V
S
V
= ±5V
S
2.0V/DIV
100ns/DIV
2.0V/DIV
100ns/DIV
Figure 24. Output Overdrive Recovery (See Figure 44)
Figure 27. Input Overdrive Recovery (See Figure 42)
Rev. J | Page 13 of 28
AD8065/AD8066
V
= 140mV/DIV
IN
V
= 500mV/DIV
IN
V
– 2V
IN
OUT
+0.1%
+0.1%
–0.1%
–0.1%
t = 0
t = 0
V
– 2V
IN
OUT
2mV/DIV
10ns/DIV
2mV/DIV
64μs/DIV
Figure 28. Long-Term Settling Time (See Figure 49)
Figure 31. 0.1% Short-Term Settling Time (See Figure 49)
0
–5
42
36
30
24
18
12
6
+I
b
–I
b
–I
b
–10
–15
–20
–25
–30
0
10
5
–I
b
+I
0
b
–5
+I
b
–10
–15
–20
–25
–30
25
35
45
55
65
75
85
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12
COMMON-MODEVOLTAGE (V)
TEMPERATURE (°C)
Figure 32. Input Bias Current vs. Common-Mode Voltage Range
(See the Input and Output Overload Behavior Section)
Figure 29. Input Bias Current vs. Temperature
0.3
0.2
40
N = 299
SD = 0.388
MEAN = –0.069
35
30
0.1
25
20
15
10
5
V
= +5V
S
V
= ±5V
S
0
–0.1
–0.2
–0.3
V
= ±12V
S
0
–2.0
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (mV)
Figure 30. Input Offset Voltage vs. Common-Mode Voltage
Figure 33. Input Offset Voltage
Rev. J | Page 14 of 28
AD8065/AD8066
–30
–40
–50
–60
–70
–80
–90
–100
100
10
1
G = +1
G = +2
V
= ±12V
S
0.1
0.01
0
V
= ±5V
S
100
1k
10k
100k
1M
10M
100M
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (Hz)
Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)
Figure 34. CMRR vs. Frequency (See Figure 46)
80
0.30
0.25
0.20
0.15
0.10
0.05
0
70
V
– V
OH
CC
V
– V
OH
CC
60
50
40
30
V
– V
EE
OL
V
– V
EE
OL
25
35
45
55
65
75
85
0
10
20
30
40
TEMPERATURE (°C)
I
(mA)
LOAD
Figure 38. Output Saturation Voltage vs. Temperature
Figure 35. Output Saturation Voltage vs. Output Load Current
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
V
= 2V p-p
IN
G = +1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–PSRR
+PSRR
B TO A
A TO B
0.1
1
10
FREQUENCY (MHz)
100
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)
Figure 39. Crosstalk vs. Frequency (See Figure 51)
Rev. J | Page 15 of 28
AD8065/AD8066
6.60
125
120
115
110
105
100
95
V
= ±12V
S
6.55
6.50
6.45
6.40
6.35
6.30
6.25
V
= ±5V
S
V
= ±12V
S
V
= +5V
S
V
= +5V
S
V
= ±5V
S
90
85
80
–40
–20
0
20
40
60
80
0
10
20
(mA)
30
40
TEMPERATURE (°C)
I
LOAD
Figure 40. Quiescent Supply Current vs. Temperature for Various
Supply Voltages
Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages
Rev. J | Page 16 of 28
AD8065/AD8066
TEST CIRCUITS
SOIC-8 Pinout
+V
CC
+V
CC
4.7μF
0.1μF
4.7μF
0.1μF
2.2pF
24.9Ω
499Ω
499Ω
V
IN
49.9Ω
FET PROBE
FET PROBE
R
SNUB
AD8065
AD8065
V
IN
249Ω
C
LOAD
1kΩ
1kΩ
49.9Ω
0.1μF
4.7μF
0.1μF
4.7μF
–V
EE
–V
EE
Figure 44. G = −1
Figure 42. G = +1
+V
CC
+V
CC
4.7μF
0.1μF
4.7μF
0.1μF
2.2pF
24.9Ω
499Ω
499Ω
FET PROBE
R
SNUB
AD8065
AD8065
V
NETWORK ANALYZER S22
IN
249Ω
C
1kΩ
LOAD
0.1μF
4.7μF
49.9Ω
0.1μF
4.7μF
–V
EE
–V
EE
Figure 43. G = +2
Figure 45. Output Impedance G = +1
Rev. J | Page 17 of 28
AD8065/AD8066
+V
CC
V
IN
1V p-p
4.7μF
0.1μF
+V
CC
49.9Ω
24.9Ω
499Ω
499Ω
V
IN
FET PROBE
FET PROBE
AD8065
AD8065
49.9Ω
499Ω
1kΩ
1kΩ
0.1μF
4.7μF
0.1μF
4.7μF
499Ω
–V
EE
–V
EE
Figure 46. CMRR
Figure 48. Positive PSRR
+V
CC
+V
CC
4.7μF
4.7μF
0.1μF
0.1μF
2.2pF
499Ω
499Ω
499Ω
499Ω
AD8065
249Ω
NETWORK ANALYZER
S22
976Ω
TO SCOPE
AD8065
249Ω
V
0.1μF
IN
49.9Ω
0.1μF
49.9Ω
4.7μF
4.7μF
–V
EE
–V
EE
Figure 49. Settling Time
Figure 47. Output Impedance G = +2
Rev. J | Page 18 of 28
AD8065/AD8066
2.2pF
+V
CC
4.7μF
0.1μF
499Ω
499Ω
5V
4.7μF
1.5V
24.9Ω
0.1μF
FET PROBE
AD8065
249Ω
FET PROBE
V
IN
AD8065
1kΩ
49.9Ω
1kΩ
49.9Ω
1.5V
1.5V
V
IN
1V p-p
–V
EE
Figure 50. Negative PSRR
Figure 52. Single Supply
24.9Ω
FET PROBE
24.9Ω
AD8066
+5V
1kΩ
4.7μF
0.1μF
RECEIVE SIDE
AD8066
V
IN
0.1μF
1kΩ
49.9Ω
4.7μF
–5V
DRIVE SIDE
Figure 51. Crosstalk—AD8066
Rev. J | Page 19 of 28
AD8065/AD8066
THEORY OF OPERATION
The AD8065/AD8066 are voltage feedback operational amplifiers
that combine a laser-trimmed JFET input stage with the Analog
Devices eXtra Fast Complementary Bipolar (XFCB) process,
resulting in an outstanding combination of precision and speed.
The supply voltage range is from 5 V to 24 V. The amplifiers feature
a patented rail-to-rail output stage capable of driving within 0.5 V
of either power supply while sourcing or sinking up to 30 mA.
Also featured is a single-supply input stage that handles common-
mode signals from below the negative supply to within 3 V of the
positive rail. Operation beyond the JFET input range is possible
because of an auxiliary bipolar input stage that functions with
input voltages up to the positive supply. The amplifiers operate as
if they have a rail-to-rail input and exhibit no phase reversal
behavior for common-mode voltages within the power supply.
NONINVERTING CLOSED-LOOP FREQUENCY
RESPONSE
Solving for the transfer function
2π× fcrossover
(
RG + RF
)
VO
VI
=
(
RF + RG s +2π× fcrossover × RG
)
where fcrossover is the frequency where the amplifier’s open-loop
gain equals 0 db
VO RF + RG
At dc
=
VI
RG
Closed-loop −3 dB frequency
RG
RF + RG
f−3dB = fcrossover
×
With voltage noise of 7 nV/√Hz and −88 dBc distortion for
1 MHz, 2 V p-p signals, the AD8065/AD8066 are a great choice
for high resolution data acquisition systems. Their low noise,
sub-pA input current, precision offset, and high speed make
them superb preamps for fast photodiode applications. The
speed and output drive capability of the AD8065/AD8066 also
make them useful in video applications.
INVERTING CLOSED-LOOP FREQUENCY
RESPONSE
−2π× fcrossover × RF
RF + RG +2π× fcrossover × RG
VO
VI
=
s
(
)
VO
VI
RF
RG
At dc
= −
CLOSED-LOOP FREQUENCY RESPONSE
Closed-loop −3 dB frequency
The AD8065/AD8066 are classic voltage feedback amplifiers
with an open-loop frequency response that can be approximated as
the integrator response shown in Figure 53. Basic closed-loop
frequency response for inverting and noninverting configurations
can be derived from the schematics shown.
RG
f−3dB = fcrossover
×
RF + RG
R
F
R
F
R
G
R
G
V
I
V
V
O
O
V
E
A
A
V
E
V
I
80
A = (2π × fcrossover)/s
60
40
20
0
fcrossover = 65MHz
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 53. Open-Loop Gain vs. Frequency and Basic Connections
Rev. J | Page 20 of 28
AD8065/AD8066
The closed-loop bandwidth is inversely proportional to the noise
gain of the op amp circuit, (RF + RG )/RG. This simple model is
accurate for noise gains above 2. The actual bandwidth of circuits
with noise gains at or below 2 is higher than those predicted
with this model due to the influence of other poles in the
frequency response of the real op amp.
Actual distortion performance depends on a number of
variables:
•
•
•
•
•
The closed-loop gain of the application
Whether it is inverting or noninverting
Amplifier loading
Signal frequency and amplitude
Board layout
R
F
+V
–
Also see Figure 16 to Figure 20. The lowest distortion is obtained
with the AD8065 used in low gain inverting applications,
because this eliminates common-mode effects. Higher closed-
loop gains result in worse distortion performance.
OS
R
G
V
O
I
I
A
b
–
R
S
V
I
b+
INPUT PROTECTION
The inputs of the AD8065/AD8066 are protected with back-to-
back diodes between the input terminals as well as ESD diodes
to either power supply. This results in an input stage with picoamps
of input current that can withstand up to 1500 V ESD events
(human body model) with no degradation.
Figure 54. Voltage Feedback Amplifier DC Errors
Figure 54 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
R + R
RG
R + R
RG
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
G
F
G
F
VO
(
error
)
= Ib+ × RS
− I × RF +VOS
b−
Excessive power dissipation through the protection devices
destroys or degrades the performance of the amplifier. Differ-
ential voltages greater than 0.7 V result in an input current of
approximately (|V+ − V−| 0.7 V)/RI, where RI is the resistance in
series with the inputs.
⎝
⎠
⎝
⎠
The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG
(though with the AD8065 input currents at typically less than
20 pA over temperature, this is likely not a concern). To include
common-mode and power supply rejection effects, total VOS can be
modeled
For input voltages beyond the positive supply, the input current
is approximately (VI − VCC − 0.7)/RI. Beyond the negative supply,
the input current is about (VI − VEE + 0.7)/RI. If the inputs of the
amplifier are to be subjected to sustained differential voltages
greater than 0.7 V, or to input voltages beyond the amplifier
power supply, input current should be limited to 30 mA by an
appropriately sized input resistor (RI), as shown in Figure 55.
ΔVS ΔVCM
PSR CMR
VOS =VOS
+
+
nom
VOS
is the offset voltage specified at nominal conditions,
nom
ΔVS is the change in power supply from nominal conditions,
PSR is the power supply rejection, ΔVCM is the change in common-
mode voltage from nominal conditions, and CMR is the common-
mode rejection.
(V – V – 0.7V)
(| V – V | – 0.7V)
I
EE
+
–
R >
I
R >
I
30mA
30mA
(V – V + 0.7V)
I
EE
FOR LARGE | V – V
+
|
R >
I
–
WIDEBAND OPERATION
30mA
FOR V BEYOND
SUPPLY VOLTAGES
AD8065
I
R
Figure 42 through Figure 44 show the circuits used for wideband
characterization for gains of +1, +2, and −1. Source impedance at
the summing junction (RF || RG) forms a pole in the amplifier’s loop
response with the amplifier’s input capacitance of 6.6 pF. This
can cause peaking and ringing if the time constant formed is too
low. Feedback resistances of 300 Ω to 1 kΩ are recommended,
because they do not unduly load down the amplifier, and the
time constant formed will not be too low. Peaking in the
frequency response can be compensated for with a small
capacitor (CF) in parallel with the feedback resistor, as
illustrated in Figure 12. This shows the effect of different
feedback capacitances on the peaking and bandwidth for a
noninverting G = +2 amplifier.
I
V
I
V
O
Figure 55. Current-Limiting Resistor
For the best settling times and the best distortion, the impedances
at the AD8065/AD8066 input terminals should be matched. This
minimizes nonlinear common-mode capacitive effects that can
degrade ac performance.
Rev. J | Page 21 of 28
AD8065/AD8066
THERMAL CONSIDERATIONS
INPUT AND OUTPUT OVERLOAD BEHAVIOR
With 24 V power supplies and 6.5 mA quiescent current, the
AD8065 dissipates 156 mW with no load. The AD8066 dissipates
312 mW. This can lead to noticeable thermal effects, especially
in the small SOT-23-5 (thermal resistance of 160°C/W). VOS
temperature drift is trimmed to guarantee a maximum drift of
17 μV/°C, so it can change up to 0.425 mV due to warm-up
effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.
A simplified schematic of the AD8065/AD8066 input stage is
shown in Figure 56. This shows the cascoded N-channel JFET
input pair, the ESD and other protection diodes, and the
auxiliary NPN input stage that eliminates any phase inversion
behavior. When the common-mode input voltage to the amplifier
is driven to within approximately 3 V of the positive power supply,
the input JFET’s bias current turns off and the bias of the NPN
pair turns on, taking over control of the amplifier. The NPN
differential pair now sets the amplifier’s offset, and the input
bias current is now in the range of several tens of microamps.
This behavior is shown in Figure 32. Normal operation resumes
when the common-mode voltage goes below the 3 V from the
positive supply threshold.
Ib increases by a factor of 1.7 for every 10°C rise in temperature.
Ib is close to five times higher at 24 V supplies as opposed to a
single 5 V supply.
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Maximum Power
Dissipation section. Care should be taken not to exceed the
rated power dissipation of the package.
The output transistors of the rail-to-rail output stage have
circuitry to limit the extent of their saturation when the output
is overdriven. This helps output recovery time. Output recovery
from a 0.5 V output overdrive on a 5 V supply is shown in
Figure 24.
V
CC
R1
R5
TO REST OF AMP
Q2
Q5
V
THRESHOLD
VBIAS
D1
D2
R6
R3
Q1
Q6
V
V
N
P
D3
D4
Q3
Q4
S
S
R4
R7
R2
R8
Q7
I
I
T2
T1
–V
EE
Figure 56. Simplified Input Stage
Rev. J | Page 22 of 28
AD8065/AD8066
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
inputs and surrounding area to set up any leakage currents.
For the guard ring to be completely effective, it must be driven
by a relatively low impedance source and should completely
surround the input leads on all sides, above and below, using
a multilayer board.
POWER SUPPLY BYPASSING
Power supply pins are actually inputs and care must be taken so
that a noise-free stable dc voltage is applied. The purpose of bypass
capacitors is to create low impedances from the supply to ground at
all frequencies, thereby shunting or filtering most of the noise.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard ring
helps to reduce the absorption. Also, low absorption materials,
such as Teflon® or ceramic, could be necessary in some instances.
Decoupling schemes are designed to minimize the bypassing
impedance at all frequencies with a parallel combination of
capacitors. 0.1 μF (X7R or NPO) chip capacitors are critical
and should be as close as possible to the amplifier package.
The 4.7 μF tantalum capacitor is less critical for high frequency
bypassing, and, in most cases, only one is needed per board at
the supply inputs.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance reduces the input impedance at high
frequencies, in turn increasing the amplifier’s gain, causing peaking
of the frequency response or even oscillations, if severe enough.
It is recommended that the external passive components connected
to the input pins be placed as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a small distance from the input pins on all layers of
the board.
GROUNDING
A ground plane layer is important in densely packed PC boards
to spread the current minimizing parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and, therefore, the high frequency impedance
of the path. High speed currents in an inductive ground return
create unwanted voltage noise.
OUTPUT CAPACITANCE
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor. Place
the ground leads of the bypass capacitors at the same physical
location. Because load currents flow from the supplies as well,
the ground for the load impedance should be at the same physical
location as the bypass capacitor grounds. For the larger value
capacitors, which are effective at lower frequencies, the current
return path distance is less critical.
To a lesser extent, parasitic capacitances on the output can cause
peaking and ringing of the frequency response. There are two
methods to effectively minimize their effect:
•
As shown in Figure 57, put a small value resistor (RS) in
series with the output to isolate the load capacitor from the
amp’s output stage. A good value to choose is 20 Ω (see
Figure 10).
•
Increase the phase margin with higher noise gains or add
a pole with a parallel resistor and capacitor from −IN to
the output.
LEAKAGE CURRENTS
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8065/AD8066. Any voltage
differential between the inputs and nearby runs sets up leakage
currents through the PC board insulator, for example, 1 V/100 GΩ
= 10 pA. Similarly, any contaminants on the board can create
significant leakage (skin oils are a common problem). To reduce
leakage significantly, put a guard ring (shield) around the inputs
and input leads that are driven to the same voltage potential as
the inputs. This way there is no voltage potential between the
R
= 20Ω
S
V
AD8065
O
C
V
L
I
Figure 57. Output Isolation Resistor
Rev. J | Page 23 of 28
AD8065/AD8066
C
F
R
F
11
= 10 Ω
SH
C
C
I
R
M
PHOTO
C
S
C
D
V
M
O
V
B
C
+ C
S
F
R
F
Figure 58. Wideband Photodiode Preamp
The frequency response in this case shows about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half results in a flat frequency response with
about 5% transient overshoot.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling between the inputs and output,
the output signal traces should not be parallel with the inputs.
WIDEBAND PHOTODIODE PREAMP
The preamp’s output noise over frequency is shown in Figure 59.
Figure 58 shows an I/V converter with an electrical model of a
photodiode. The basic transfer function is
1
f1
=
2πR (C + C + C + 2C
)
F
F
S
M
D
IPHOTO × RF
1+ sCF RF
VOUT
=
1
f2
f3
=
=
2πR C
F
F
fCR
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth.
(C + C + 2C + C )/C
F
S
M
D
F
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the amplifier’s summing junction, including CS
and the amplifier input capacitance. RF and the total capacitance
produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding CF creates a 0 in the
loop transmission that compensates for the pole’s effect and
reduces the signal bandwidth. It can be shown that the signal
bandwidth resulting in a 45° phase margin (f(45)) is defined by
R
NOISE
F
f3
f2
VEN (C + C + C + 2C )/C
F
F
S
M
D
f1
VEN
NOISE DUE TO AMPLIFIER
FREQUENCY (Hz)
Figure 59. Photodiode Voltage Noise Contributions
fCR
The pole in the loop transmission translates to a 0 in the
amplifier’s noise gain, leading to an amplification of the input
voltage noise over frequency. The loop transmission 0
introduced by CF limits the amplification. The noise gain
bandwidth extends past the preamp signal bandwidth and is
eventually rolled off by the decreasing loop gain of the
amplifier. Keeping the input terminal impedances matched is
recommended to eliminate common-mode noise peaking
effects, which adds to the output noise.
f(
=
)
45
2π× RF ×CS
where fCR is the amplifier crossover frequency, RF is the feedback
resistor, and CS is the total capacitance at the amplifier summing
junction (amplifier + photodiode + board parasitics).
The value of CF that produces f(45) can be shown to be
CS
CF =
2π× RF × fCR
Integrating the square of the output voltage noise spectral
density over frequency and then taking the square root allows
users to obtain the total rms output noise of the preamp. Table 5
summarizes approximations for the amplifier and feedback and
source resistances. Noise components for an example preamp
with RF = 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about
1.6 MHz) are also listed.
Rev. J | Page 24 of 28
AD8065/AD8066
Table 5. RMS Noise Contributions of Photodiode Preamp
Contributor
Expression
RMS Noise with RF = 50 kΩ, CS = 15 pF, CF = 2 pF
RF (×2)
64.5 μV
2.4 μV
31 μV
2 × 4 kT × RF × f2 ×1.57
Amp to f1
VEN × f1
Amp (f2 – f1)
CS +CM +CF +2CD
VEN ×
×
×
f2 − f1
CF
Amp to (past f2)
260 μV
CS + CM + 2CD + CF
VEN ×
f3 ×1.57
CF
270 μV (Total)
V
CC
4.7μF
0.1μF
R
S1
1
/
2
V
2.2pF
N
AD8066
4.7μF
R2
0.1μF
500Ω
V
V
CC
EE
4.7μF
0.1μF
R1
500Ω
R
= 500Ω
F
V
O
AD8065
R
G
4.7μF
0.1μF
R3
V
R
= 500Ω
500Ω
EE
F
V
CC
4.7μF
0.1μF
R4
500Ω
2.2pF
1
/
2
AD8066
R
S2
V
4.7μF
P
0.1μF
V
EE
Figure 60. High Speed Instrumentation Amplifier
Common-mode rejection of the in-amp is primarily
determined by the match of the resistor ratios R1:R2 to R3:R4.
It can be estimated
HIGH SPEED JFET INPUT INSTRUMENTATION
AMPLIFIER
Figure 60 shows an example of a high speed instrumentation
amplifier with high input impedance using the
AD8065/AD8066. The dc transfer function is
VO
VCM
(
δ1−δ2
)
=
(
1+ δ1
)
δ2
The summing junction impedance for the preamps is equal to
RF || 0.5(RG). This is the value to be used for matching purposes.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1000
RG
VOUT
=
(
VN −VP
)
1+
For G = +1, it is recommended that the feedback resistors for
the two preamps be set to a low value (for instance 50 Ω for
50 Ω source impedance). The bandwidth for G = +1 is 50 MHz.
For higher gains, the bandwidth is set by the preamp, equaling
Inamp−3dB
=
fCR × RG
/
2 × RF
Rev. J | Page 25 of 28
AD8065/AD8066
+V
S
VIDEO BUFFER
The output current capability and speed of the AD8065 make it
useful as a video buffer, shown in Figure 61.
4.7μF
4.7μF
0.1μF
249Ω
75Ω
+
AD8065
V
–
The G = +2 configuration compensates for the voltage division
of the signal due to the signal termination. This buffer maintains
0.1 dB flatness for signals up to 7 MHz, from low amplitudes up
to 2 V p-p (see Figure 7). Differential gain and phase have been
measured to be 0.02% and 0.028°, respectively, at 5 V supplies.
I
+
V
–
75Ω
O
0.1μF
–V
S
2.2pF
499Ω
499Ω
Figure 61. Video Buffer
Rev. J | Page 26 of 28
AD8065/AD8066
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 62. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.20
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 63. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 64. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. J | Page 27 of 28
AD8065/AD8066
ORDERING GUIDE
Model1, 2
AD8065AR
AD8065AR-REEL
AD8065AR-REEL7
AD8065ARZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +105°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
Package Option
Branding
R-8
R-8
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
AD8065ARZ-REEL
AD8065ARZ-REEL7
AD8065ART-R2
AD8065ART-REEL
AD8065ART-REEL7
AD8065ARTZ-R2
AD8065ARTZ-REEL
AD8065ARTZ-REEL7
AD8065WARTZ-REEL7
AD8065ART-EBZ
AD8065AR-EBZ
AD8066AR
AD8066AR-REEL7
AD8066ARZ
AD8066ARZ-RL
AD8066ARZ-R7
AD8066ARM
HRA
HRA
HRA
HRA #
HRA #
HRA #
H2F#
5-Lead SOT-23
Evaluation Board (8-Lead SOIC_N)
Evaluation Board (5-Lead SOT-23)
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board (8-Lead SOIC_N)
Evaluation Board (5-Lead SOT-23)
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
H1B
H1B
H1B
H7C
H7C
AD8066ARM-REEL
AD8066ARM-REEL7
AD8066ARMZ
AD8066ARMZ-REEL7
AD8066AR-EBZ
AD8066ARM-EBZ
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8065W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02916-0-8/10(J)
Rev. J | Page 28 of 28
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