AD8075 [ADI]
500 MHz, G = +-1 and +2 Triple Video Buffers with Disable; 500兆赫， G = + -1和2三路视频缓冲器，具有禁用
| 型号： | AD8075 |
| 厂家： | 
ADI |
| 描述： | 500 MHz, G = +-1 and +2 Triple Video Buffers with Disable |
| 文件： | 总16页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
500 MHz, G = +1 and +2 Triple
Video Buffers with Disable
a
AD8074/AD8075
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Dual Supply ؎5 V
High-Speed Fully Buffered Inputs and Outputs
600 MHz Bandwidth (–3 dB) 200 mV p-p
500 MHz Bandwidth (–3 dB) 2 V p-p
1600 V/s Slew Rate, G = +1
1350 V/s Slew Rate, G = +2
Fast Settling Time: 4 ns
Low Supply Current: <30 mA
Excellent Video Specifications (RL = 150 ⍀):
Gain Flatness of 0.1 dB to 50 MHz
0.01% Differential Gain Error
0.01؇ Differential Phase Error
“All Hostile“ Crosstalk
AD8074/AD8075
1
2
3
4
5
6
7
8
16
15
V
CC
OE
DGND
IN2
V
CC
G =
+1/+2
14 OUT2
13
V
AGND
IN1
EE
12 OUT1
11
G =
+1/+2
V
AGND
IN0
CC
G =
+1/+2
10 OUT0
V
V
9
EE
EE
–80 dB @ 10 MHz
–50 dB @ 100 MHz
High “OFF” Isolation of 90 dB @ 10 MHz
Low Cost
Fast Output Disable Feature
APPLICATIONS
RGB Buffer in LCD and Plasma Displays
RGB Driver
Video Routers
Table I. Truth Table
OUT0, 1, 2
PRODUCT DESCRIPTION
The AD8074/AD8075 are high-speed triple video buffers with
G = +1 and +2 respectively. They have a –3 dB full signal band-
width in excess of 450 MHz, along with slew rates in excess of
1400 V/µs. With better than –80 dB of all hostile crosstalk and
90 dB isolation, they are useful in many high-speed applica-
tions. The differential gain and differential phase error are 0.01%
and 0.01°. Gain flatness of 0.1 dB up to 50 MHz makes the
AD8074/AD8075 ideal for RGB buffering or driving. They
consume less than 30 mA on a 5 V supply.
OE
0
1
IN0, IN1, IN2
High Z
Both devices offer a high-speed disable feature that allows the
outputs to be put into a high impedance state. This allows the
building of larger input arrays while minimizing “OFF” chan-
nel output loading. The AD8074/AD8075 are offered in a
16-lead TSSOP package.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use,norforanyinfringementsofpatentsorotherrightsofthirdparties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
(TA = 25؇C, VS = ؎5 V, unless otherwise noted.)
AD8074/AD8075–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)
V
V
V
V
V
V
IN = 200 mV p-p, CL = 5 pF
IN = 200 mV p-p, RL = 150 Ω
IN = 2 V p-p, CL = 5 pF
IN = 2 V p-p, RL = 150 Ω
IN = 200 mV p-p, CL = 5 pF
IN = 200 mV p-p, RL = 150 Ω
330/310
250/230
330/300
250/230
600/550
400/400
500/500
350/350
70/65
70/65
1600/1350
4/7.5
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
–3 dB Bandwidth (Large Signal)
0.1 dB Bandwidth
Slew Rate
Settling Time to 0.1%
2 V Step, RL = 1 kΩ/150 Ω
2 V Step, RL = 1 kΩ/150 Ω
NOISE/DISTORTION PERFORMANCE
Differential Gain
Differential Phase
V= 3.58 MHz, 150 Ω
V= 3.58 MHz, 150 Ω
V= 10 MHz, RL = 1 kΩ
V= 100 MHz, RL = 1 kΩ
V= 10 MHz, RL = 150 Ω
V= 10 kHz to 100 MHz
0.01
0.01
–80/–74
–50/–44
90
%
Degrees
dB
dB
dB
All Hostile Crosstalk
OFF Isolation
Voltage Noise
19.5/22
nV/√Hz
DC PERFORMANCE
Voltage Gain Error
Input Offset Voltage
No Load
0.1/ 0.2
2.5
3
10
5
0.15/ 0.65
27/40
%
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Drift
Input Bias Current
9.5/10
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
10
1.5
1.5
2.8/ 1.4
MΩ
pF
pF
V
Channel Enabled
Channel Disabled
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ
+VS – 1.95 +VS – 1.8
–VS + 2.1 –VS + 1.8
V
V
RL = 150 Ω
+VS – 2.35 +VS – 2.2
–VS + 2.30 –VS + 2.2
V
V
Short Circuit Current (Protected)
Output Resistance
70
0.5
7.5
2.2
mA
Ω
MΩ
pF
Enabled
Disabled
Disabled
3.5
Output Capacitance
POWER SUPPLY
Operating Range
4.5
5.5
V
Power Supply Rejection Ratio
+PSRR: +VS = +4.5 V to +5.5 V, –VS = –5 V
–PSRR: –VS = –4.5 V to –5.5 V, +VS = +5 V
All Channels “ON”
All Channels “OFF”
TMIN to TMAX
60
56
74
64
21.5/24
3/4
23/26
dB
dB
mA
mA
mA
Quiescent Current
30
5.5
DIGITAL INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Input Current
Logic “0” Input Current
OE Input
OE Input
OE = 4 V
OE = 0.4 V
2.0
V
V
nA
µA
0.8
100
1
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
θJC
Operating (Still Air)
Operating (Still Air)
Operating
–40
+85
°C
°C/W
°C/W
150.4
27.6
Specifications subject to change without notice.
–2–
REV. A
AD8074/AD8075
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V
Temperature
Range
Package
Description
Package
Option
Internal Power Dissipation2, 3
Model
AD8074/AD8075 16-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W
Input Voltage
AD8074ARU
AD8075ARU
AD8074-EVAL
AD8075-EVAL
–40°C to +85°C 16-Lead Plastic TSSOP RU-16
–40°C to +85°C 16-Lead Plastic TSSOP RU-16
Evaluation Board
IN0, IN1, IN2 . . . . . . . . . . . . . . . . . . . . . . . . . VEE ≤ VIN ≤ VCC
OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND ≤ VIN ≤ VCC
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Indefinite3
Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . 300°C
Evaluation Board
PIN CONFIGURATION
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air (TA = 25°C).
AD8074/AD8075
1
2
3
4
5
6
7
8
16
15
V
CC
OE
DGND
IN2
V
CC
G =
14 OUT2
13
+1/+2
316-lead plastic TSSOP; θJA = 150.4°C/W. Maximum internal power dissipa-
V
AGND
IN1
EE
12 OUT1
11
tion (PD
) should be derated for ambient temperature (TA) such that
PD < (150°C – TA)/θJA
.
G =
+1/+2
V
AGND
IN0
CC
G =
+1/+2
10 OUT0
V
V
9
EE
EE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8074/AD8075 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
1.5
MAXIMUM POWER DISSIPATION
T
= 150؇C
J
The maximum power that can be safely dissipated by the AD8074/
AD8075 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
1.0
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175°C for an extended period can result in
device failure.
0.5
While the AD8074/AD8075 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 1.
0
–50
–30
–10
0
10
30
50
90
70
AMBIENTTEMPERATURE – ؇C
Figure 1. Maximum Power Dissipation vs. Temperature
REV. A
–3–
AD8074/AD8075–Typical Performance Characteristics
1
0.4
1
0.4
GAIN
GAIN
0
0.3
0
0.3
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.2
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.2
2V p-p
0.1
0.1
200mV p-p
FLATNESS
FLATNESS
0
200mV p-p
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
2V p-p
2V p-p
0.1
1
10
FREQUENCY – MHz
100
1000
0.1
1
10
FREQUENCY – MHz
100
1000
TPC 1. AD8074 Frequency Response; RL = 150 Ω
TPC 4. AD8075 Frequency Response; RL = 150 Ω
2
1
0.6
2
1
0.6
0.5
0.5
GAIN
GAIN
0
0.4
0
0.4
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.3
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.3
2V p-p
0.2
0.2
2V p-p
2V p-p
0.1
0.1
FLATNESS
FLATNESS
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
200mV p-p
2V p-p
200mV p-p
200mV p-p
0.1
1
10
FREQUENCY – MHz
100
1000
0.1
1
10
FREQUENCY – MHz
100
1000
TPC 2. AD8074 Frequency Response; RL = 1 kΩ, CL = 5 pF
TPC 5. AD8075 Frequency Response; RL = 1 kΩ, CL = 5 pF
3
3
C
= 10pF
C
= 10pF
2
1
L
2
1
L
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
C
C
= 0pF
C
C
= 0pF
= 5pF
L
L
= 5pF
V
L
L
V
IN
OUT
V
V
IN
OUT
150k⍀
C
1k⍀
L
75⍀
C
L
75⍀
V
= 2V p-p
OUT
V
= 2V p-p
1
OUT
0.1
1
10
FREQUENCY – MHz
100
1000
0.1
10
FREQUENCY – MHz
100
1000
TPC 3. AD8074 Frequency Response vs. Capacitive Load
TPC 6. AD8075 Frequency Response vs. Capacitive Load
–4–
REV. A
AD8074/AD8075
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
R
R
= 2V p-p (ACTIVE CHANNEL(s))
= 1k⍀
= 37.5⍀
V
R
R
= 2V p-p (ACTIVE CHANNEL(s))
OUT
OUT
= 150⍀
L
T
L
T
= 37.5⍀
ALL-HOSTILE
ALL-HOSTILE
ADJACENT
ADJACENT
–100
–110
0.1
1
10
FREQUENCY – MHz
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
TPC 7. AD8074 Crosstalk vs. Frequency (All Hostile and
Adjacent RL = 1 kΩ)
TPC 9. AD8075 Crosstalk vs. Frequency (All Hostile and
Adjacent RL = 150 Ω)
0
0
V
R
R
= 2V p-p
= 150⍀
= 37.5⍀
V
R
R
= 2V p-p
= 150⍀
= 37.5⍀
OUT
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
L
T
L
T
SECOND
HARMONIC
SECOND
HARMONIC
THIRD
HARMONIC
–80
–90
THIRD
HARMONIC
–100
1
10
100
1000
1
10
100
1000
FUNDAMENTAL FREQUENCY – MHz
FUNDAMENTAL FREQUENCY – MHz
TPC 8. AD8074 Distortion vs. Frequency
TPC 10. AD8075 Distortion vs. Frequency
REV. A
–5–
AD8074/AD8075
–20
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–30
–40
–50
–60
–70
–80
–90
R
= 1k⍀
L
R
= 1k⍀
L
R
= 150⍀
L
R
= 150⍀
L
–100
–110
0.1
1
10
100
1000
0.1
1
10
FREQUENCY – MHz
100
1000
FREQUENCY – MHz
TPC 14. AD8075 Off Isolation vs. Frequency
TPC 11. AD8074 Off Isolation vs. Frequency
20
10
0
10
0
–10
–PSRR
–10
–20
–30
–40
–50
–60
–70
–80
+PSRR
–20
–30
–40
+PSRR
–PSRR
–50
–60
–70
0.1
1
10
100
1000
0.1
1
10
FREQUENCY – MHz
100
1000
FREQUENCY – MHz
TPC 15. AD8075 PSRR vs. Frequency
TPC 12. AD8074 PSRR vs. Frequency
350
400
350
300
250
200
150
100
50
300
250
200
150
100
50
0
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 16. AD8075 Voltage Noise vs. Frequency
TPC 13. AD8074 Voltage Noise vs. Frequency
–6–
REV. A
AD8074/AD8075
10000
10000
1000
100
10
1000
100
10
1
1
0.1
0.01
0.1
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 17. AD8074 Input Impedance vs. Frequency
TPC 20. AD8075 Input Impedance vs. Frequency
1000
1000
100
100
10
1
10
1
0.1
0.1
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 21. AD8075 Output Impedance vs. Frequency;
Enabled
TPC 18. AD8074 Output Impedance vs. Frequency;
Enabled
1000
100
10
1000
100
10
1
1
0.1
0.01
0.1
0.01
0.001
0.001
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 19. AD8074 Output Impedance vs. Frequency;
Disabled
TPC 22. AD8075 Output Impedance vs. Frequency;
Disabled
REV. A
–7–
AD8074/AD8075
0.15
0.10
0.05
0
0.15
V
= 200mV STEP
O
V
= 200mV STEP
O
0.10
0.05
0
–0.05
–0.05
–0.10
–0.10
–0.15
2ns
2ns
–0.15
TPC 23. AD8074 Small Signal Pulse Response (RL = 1 kΩ,
CL = 5 pF)
TPC 26. AD8075 Small Signal Pulse Response (RL = 150 kΩ)
0.8
0.7
0.8
0.7
V
= 700mV STEP
0.6
0.5
0.4
O
V
= 700mV STEP
0.6
0.5
0.4
0.3
0.2
0.1
0
O
0.3
0.2
0.1
0
2ns
–0.1
–0.2
2ns
–0.1
TPC 24. AD8074 Video Amplitude Pulse Response
TPC 27. AD8075 Video Amplitude Pulse Response
(RL = 1 kΩ, CL = 5 pF)
(RL = 150 Ω)
1.5
1.5
V
= 2V STEP
O
V = 2V STEP
O
1.0
0.5
1.0
0.5
0
–0.5
–1.0
–1.5
0
–0.5
–1.0
2ns
2ns
–1.5
TPC 25. AD8074 Large Signal Pulse Response
(RL = 1 kΩ, CL = 5 pF)
TPC 28. AD8075 Large Signal Pulse Response (RL = 150 Ω)
–8–
REV. A
AD8074/AD8075
THEORY OF OPERATION
APPLICATIONS
Response Tuning
The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel,
high-speed buffers with TTL-compatible output enable control.
Optimized for buffering RGB (red, green, blue) video sources,
the devices have high peak slew rates, maintaining their band-
width for large signals. Additionally, the buffers are compensated
for high phase margin, minimizing overshoot for good pixel
resolution. The buffers also have video specifications that are
suitable for buffering NTSC or PAL composite signals.
It has been mentioned in passing that the primary cause of over-
shoot for the AD8074 and AD8075 is the presence of large
reactive loads at the output. If the system exhibits excessive
ringing while settling, a 10 Ω–50 Ω series resistor may be used
at the output to isolate the emitter-follower output buffer from
the reactive load. If the output exhibits an overdamped response,
the system designer may add a few pF shunt capacitance at the
output to tune for a faster edge transition. A system with a small
degree of overshoot will settle faster than an overdamped system.
The buffers are organized as three independent channels, each
with an input transconductance stage and an output trans-
impedance stage. Each channel is characterized by low input
capacitance and high input impedance. The transconductance
stages, NPN differential pairs, source signal current into the folded
cascode output stages. Each output stage contains a compensat-
ing network and emitter follower output buffer. Internal voltage
feedback sets the gain, the AD8074 being configured as a unity
gain follower, and the AD8075 as a gain-of-two amplifier with a
feedback network. The architecture provides drive for a reverse-
terminated video load (150 Ω) with low differential gain and
phase error for relatively low power consumption. Careful chip
design and layout allow excellent crosstalk isolation between
channels.
2.0
R
C
= 10⍀
= 10pF
S
L
1.5
1.0
R
C
= 0⍀
= 5pF
S
L
0.5
R
C
= 20⍀
= 15pF
S
L
0
–0.5
–1.0
–1.5
–2.0
R
S
V
V
OUT
IN
C
1k⍀
L
75⍀
2ns
One logic pin, OE, controls whether the three outputs are
enabled, or disabled to a high-impedance state. The high imped-
ance disable allows larger matrices to be built when busing the
outputs together. When disabled, the AD8074 and AD8075 con-
sume a fifth the power as when enabled. In the case of the
AD8075 (G = +2), a feedback isolation scheme is used so that
the impedance of the gain-of-two feedback network does not
load the output.
Figure 2. Driving Capacitive Loads
Single Supply Operation
The AD8074 and AD8075 may be operated from a single 10 V
supply. In this configuration, the AD8075’s AGND pins must
be tied near midsupply, as AGND provides the reference for the
ground buffer, to which the internal gain network is terminated.
Full power bandwidth for an undistorted sinusoid is often calcu-
lated using peak slew rate from the equation:
Logic is referenced to DGND. The buffers are disabled in single
supply operation for VOE > VDGND + ~2.0 V and enabled for
V
OE < VDGND + 0.8 V. TTL logic levels are expected. The fol-
Peak Slew Rate
Full Power Bandwidth =
lowing restrictions are placed upon the digital ground potential:
2 × π × Sinusoidal Amplitude
3.5V ≤VAVCC –VDGND ≤ 12V
VDGND ≥ VAVEE
Peak slew rate is not the same as average slew rate (25% to
75%) which is typically specified. For a natural response, peak
slew rate may be 2.7 times larger than average slew rate. There-
fore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result.
The architecture of the output buffer is such that the output
voltage can swing to within ~2.3 V of either rail. For example, if
the output need swing only 2 V, then the buffers could be oper-
ated on dual 3.5 V or single 7 V supplies. It is cautioned that
saturation effects may become noticeable when the output swings
within 2.6 V of either rail. The system designer may opt to
use this characteristic to his or her advantage by using the
soft-saturation regime, (2.2 V–2.6 V from the supply rails), to
tame excessive overshoot. The designer is cautioned that a
charge storage associated time delay of several nanoseconds is
incurred when recovering from soft-saturation. This effect
results in longer settling tails.
The primary cause of overshoot in these amplifiers is the pres-
ence of large reactive loads at the output and insufficient series
isolation of the load. However, it is possible to overdrive these
amplifiers with 1 V, subnanosecond input-pulse edges. The
ensuing dynamics may give rise to subnanosecond overshoot. To
reduce these effects, an edge-rate limiting network at the input
should be considered for input transition times less than 0.5 ns.
REV. A
–9–
AD8074/AD8075
RGB Buffer for Second Monitor
can be connected to the same signal, as is done in some studio-
type TV monitors.
The RGB signals for PC monitors are driven through coax
cables whose characteristic impedance is 75 Ω. The graphics
chip will generally have current-source output drivers that should
be double terminated with a 75 Ω shunt termination at each end.
On the transmit end, the shunt terminations are provided to
ground close to the graphics IC, while the monitor terminates
its end via internal termination resistors. While this scheme works
well and is virtually foolproof for a single monitor, it leaves no
means for passively connecting a second monitor to the same source.
A way around this problem is to connect the first monitor to the
RGB channels in the standard fashion, and then to provide a
triple gain-of-two buffer to drive the second monitor. The AD8075
is designed to provide this function and also provide excellent
high-frequency performance for high-resolution graphics signals.
Figure 3 shows a schematic of this circuit.
The outputs of the AD8075 are low impedance voltage sources
and are therefore series-terminated with 75 Ω resistors. The
internal resistors in Monitor #2 provide the terminations at its
end. The overall effect of this type of termination scheme is to
divide the signal amplitude by two. This is compensated by the
gain of two provided by the AD8075.
A second monitor that is connected simply in parallel will pro-
vide an extra set of terminations that will upset the signal levels.
To keep costs low, most computer monitors do not have the ability
to open-circuit the terminations in order that an additional monitor
MONITOR #1
PC GRAPHICS IC
R
75⍀
75⍀
CURRENT SOURCE
OUTPUT DRIVERS
G
INTERNAL
75⍀
75⍀
TERMINATIONS
B
75⍀
75⍀
+5V
+5V
+5V
+
25F
0.1F
0.1F
0.1F
MONITOR #2
75⍀
75⍀
75⍀
75⍀
AD8075
INTERNAL
TERMINATIONS
75⍀
75⍀
25F
0.1F
0.1F
0.1F
+
–5V
–5V
–5V
Figure 3. Buffer
–10–
REV. A
AD8074/AD8075
Triple Video Multiplexer
and the amplifier output are disabled to a high impedance to
provide a high-impedance disabled state.
The AD8074 and AD8075 each have an output-enable function
that can be used to disable the outputs and put them in a high-
impedance state. Usually, for a unity-gain device, it is relatively
easy to provide high disabled impedance, because the feedback
path is from the output to a high-impedance input. However, for a
non-unity-gain part, the feedback provides a resistive path to
ground. This will usually dominate the disabled output imped-
ance, and make it a much lower value than the unity-gain device.
To construct a multiplexer, the outputs from one or more devices
are connected in parallel and only one device is enabled at a
time while all of the others are disabled. The two sets of inputs
are applied individually to each of the separate device inputs.
Figure 4 shows the circuit details for this function. The first RGB
Source 1 is input to the first AD8075. Each of the individual
signals is terminated to ground with 75 Ω to provide proper
termination for the input cables. In a similar fashion, the Source
2 signals are input to the second AD8075.
The AD8075 has an internal buffer that provides a low-impedance,
ground level output that terminates the feedback path during
enabled operation. In the disabled state, both this buffer output
+5V
+5V
+5V
+
25F
0.1F
0.1F
0.1F
75⍀
R
R
G
B
75⍀
75⍀
75⍀
AD8075
75⍀
75⍀
SOURCE 1
G
B
OUTPUT
OE
25F
0.1F
0.1F
0.1F
+
–5V
–5V
–5V
SEL1/SEL2
+5V
+5V
+5V
+
25F
0.1F
0.1F
0.1F
OE
75⍀
75⍀
75⍀
R
G
B
75⍀
75⍀
75⍀
AD8075
SOURCE 2
25F
0.1F
0.1F
0.1F
+
–5V
–5V
–5V
Figure 4. Mux
–11–
REV. A
AD8074/AD8075
Each of the six outputs has a 75 Ω series resistor that is used to
reverse-terminate the output transmission line. The correspond-
ing outputs are then wired in parallel and delivered to the output
cable. The termination resistors in this position help to isolate
the off capacitance of the disabled device’s outputs from loading
the enabled device’s outputs. The gain-of-two of the AD8075
compensates for the signal halving that occurs as a result of the
output terminations.
A major area of focus should be the power distribution system.
There should be a full ground plane that provides the reference
and return paths for both the inputs and outputs. The ground
also provides isolation between the input signals to minimize the
crosstalk. This ground plane should cover as wide an area as
possible and be minimally interrupted in order to keep its
impedance to a minimum.
The power planes should also be as broad as possible to provide
minimal inductance, which is required for high-slew-rate sig-
nals. These power planes layers should be spaced closely to the
ground plane to increase the interplane capacitance between the
supplies and ground.
A select signal is provided directly to the OE of the second
AD8075 and an inverted version is used to drive the other device’s
OE. This will ensure that only one device is active at a time. Since
there is a total of 150 Ω in series between any two outputs, it is
not essential to be overly concerned about the exact timing of
the making and breaking of the enable signals.
Each supply pin should be bypassed with a low inductance
0.1 µF ceramic capacitance with minimal excess circuit length
to minimize the series impedance. A 25 µF tantalum electro-
lytic capacitor will supply a charge reservoir for lower frequency,
high-amplitude transitions.
Additional inputs can easily be added to the circuit shown to
make wider multiplexers. The outputs of all of the devices will
be wired in parallel, and the logic must allow that only one output
be enabled at a time.
The input and output signals should be run as directly as pos-
sible in order to minimize the effects of parasitics. If they must
run over a longer distance of more than a few centimeters, con-
trolled impedance PCB traces should be used to minimize the
effect of reflections due to mismatches in impedance and the
proper termination should be provided.
If it is desired to make a triple 3:1 multiplexer, a triple 2:1 mul-
tiplexer, like the AD8185 can be used along with the AD8075.
The same general guidelines for input and output treatment
should be followed and the logic must perform the proper function.
If it is desired to design such a multiplexer at unity gain, the
AD8074 should be used. For a triple 3:1 multiplexer, an
AD8183 (triple 2:1 mux) can be combined with an AD8074 to
provide this function.
To avoid excess crosstalk, the above recommendations should
be followed carefully. The power system and signal routing are
the most important aspects of preventing excess crosstalk.
Beyond these techniques, shielding can be provided by ground
traces between adjacent signals, especially those that travel
parallel over long distances.
Layout and Grounding
The AD8074 and AD8075 are extreme bandwidth, high-slew-rate
devices that are designed to drive up to the highest resolution
monitors and provide excellent resolution. To realize their full
performance potential, it is essential to adhere to the best prac-
tices of high-speed PCB layout.
–12–
REV. A
AD8074/AD8075
TP2
+
DO NOT INSTALL
V
EE
V
V
P1
1
EE
EE
50⍀ IMPEDANCE LINE
C2
10F
TP3
TP4
AGND
AGND
V
CC
AGND
P1
P1
2
3
AGND
R16
20k⍀
AGND
AGND
TP1
DO NOT INSTALL
V
CC
W2
V
V
CC
CC
+
50⍀ IMPEDANCE LINE
C1
10F
TP5
AGND
50⍀ IMPEDANCE LINE
DISOUT
AGND
DISOUT
R11
50⍀
V
CC
DO NOT INSTALL
C15
0.01F
C14
0.01F
AGND
IN2
75⍀ IMPEDANCE LINE
IN2
AGND
AGND
C3
0.1F
DO NOT INSTALL
75⍀ IMPEDANCE LINE
R7
75⍀
OUT2
OUT2
R1
C7
AGND
75⍀
R6
150⍀
0.1F
DUT
V
EE
C13
AGND
IN1
AGND
DO NOT INSTALL
AGND
V
0.01F
1
2
3
4
5
6
7
8
16
CC
OE
DGND
75⍀ IMPEDANCE LINE
75⍀ IMPEDANCE LINE
AGND
AGND
AGND
IN1
IN0
V
15
CC
AGND
IN2
OUT2 14
R2
75⍀
75⍀ IMPEDANCE LINE
R8
75⍀
AGND
IN1
V
13
12
11
10
9
EE
OUT1
OUT1
OUT1
AGND
IN0
R10
150⍀
AGND
AGND
IN0
V
V
CC
CC
C12
0.01F
OUT0
DO NOT INSTALL
V
V
V
V
EE
EE
EE
EE
AGND
C6
0.1F
C8
C11
0.01F
R3
75⍀
AD8074
AGND
0.01F
AGND
R9
75⍀
75⍀ IMPEDANCE LINE
AGND
AGND
AGND
OUT0
OUT0
R12
150⍀
AGND
DO NOT INSTALL
AGND
Figure 5. Evaluation Board Schematic
REV. A
–13–
AD8074/AD8075
Figure 6. Component Side
Figure 8. Silkscreen Top
Figure 9. Silkscreen Bottom
Figure 7. Circuit Side
Figure 10. Internal 2
–14–
REV. A
AD8074/AD8075
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Controlling Dimension: Metric, shown in parentheses.
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
REV. A
–15–
AD8074/AD8075
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Addition to equation in SINGLE SUPPLY OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
–16–
REV. A
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