AD807A-155BRRL7 [ADI]
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming; 光纤接收器与量化器和时钟恢复和数据重定时
| 型号： | AD807A-155BRRL7 |
| 厂家： | 
ADI |
| 描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming |
| 文件： | 总12页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
a
AD807
FEATURES
Meets CCITT G.958 Requirem ents
for STM-1 Regenerator—Type A
frequency acquisition without false lock. T his eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
Meets Bellcore TR-NWT-000253 Requirem ents for OC-3
Output J itter: 2.0 Degrees RMS
155 Mbps Clock Recovery and Data Retim ing
Accepts NRZ Data, No Pream ble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
T he AD807 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. T he frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. T he phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD807.
Quantizer Sensitivity: 2 m V
Level Detect Range: 2.0 m V to 30 m V
Single Supply Operation: +5 V or –5.2 V
Low Pow er: 170 m W
10 KH ECL/ PECL Com patible Output
Package: 16-Pin Narrow 150 m il SOIC
T he device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.0 degrees rms. T his low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. T he device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
P RO D UCT D ESCRIP TIO N
T he AD807 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
155 Mbps NRZ data. T he device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-3 or SDH ST M-1
fiber optic receiver.
T he user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCIT T G.958 T ype A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
T he receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. T he threshold is set with a single external resistor. T he sig-
nal level detect circuit 3 dB optical hysteresis prevents chatter at
the signal level detect output.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock out-
put frequency to the VCO center frequency.
T he AD807 consumes 140 mW and operates from a single
power supply at either +5 V or –5.2 V.
T he PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
FUNCTIO NAL BLO CK D IAGRAM
CF1 CF2
QUANTIZER
PIN
COMPENSATING
ZERO
LOOP
FILTER
Φ
∑
DET
NIN
PHASE-LOCKED LOOP
VCO
SIGNAL
THRADJ
LEVEL
F
CLKOUTP
CLKOUTN
DET
DETECTOR
LEVEL
DATAOUTP
DATAOUTN
RETIMING
DEVICE
DETECT
COMPARATOR/
BUFFER
AD807
SDOUT
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD807–SPECIFICATIONS (T = T to T , V = V to V , C = 0.1 F, unless otherwise noted)
A
MIN
MAX
S
MIN
MAX
D
P aram eter
Condition
Min
Typ
Max
Units
QUANT IZER–DC CHARACT ERIST ICS
Input Voltage Range
Input Sensitivity, VSENSE
Input Overdrive, VOD
Input Offset Voltage
Input Current
Input RMS Noise
Input Pk-Pk Noise
@ PIN or NIN
2.5
2
0.001
VS
V
mV
V
µV
µA
µV
µV
PIN–NIN, Figure 1, BER = ≤ 1 × 10–10
Figure 1, BER = ≤ 1 × 10–10
2.5
500
10
50
5
50
650
BER = ≤ 1 × 10–10
BER = ≤ 1 × 10–10
QUANT IZER–AC CHARACT ERIST ICS
Upper –3 dB Bandwidth
Input Resistance
180
1
2
MHz
MΩ
pF
Input Capacitance
Pulse Width Distortion
100
ps
LEVEL DET ECT
Level Detect Range
RT HRESH = INFINIT E
RT HRESH = 49.9 kΩ
RT HRESH = 3.4 kΩ
DC Coupled
RT HRESH = INFINIT E
RT HRESH = 49.9 kΩ
RT HRESH = 3.4 kΩ
Load = +4 mA
0.8
4
14
0.1
2.3
3.0
3.0
3.6
2
5
20
4.0
7.4
25
1.5
10.0
9.0
10.0
mV
mV
mV
µs
dB
dB
dB
V
Response T ime
Hysteresis (Electrical)
4.0
5.0
7.0
SDOUT Output Logic High
SDOUT Output Logic Low
Load = –1.2 mA
0.4
V
PHASE-LOCKED LOOP NOMINAL
CENT ER FREQUENCY
155.52
MHz
MHz
MHz
Degrees
ns
CAPT URE RANGE
155
155
156
156
20
T RACKING RANGE
ST AT IC PHASE ERROR
27–1 PRN Sequence
Figure 2
4
SET UP T IME (tSU
HOLD T IME (tH )
PHASE DRIFT
JIT T ER
)
3.0
3.0
3.2
3.1
3.5
3.3
40
Figure 2
ns
240 Bits, No T ransitions
Degrees
27–1 PRN Sequence
2.0
2.0
Degrees RMS
Degrees RMS
223–1 PRN Sequence
2.7
JIT T ER T OLERANCE
f = 10 Hz
3000
7.6
1.0
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
f = 6.5 kHz
f = 65 kHz
f = 1.3 MHz
4.5
0.45
0.45
0.67
JIT T ER T RANSFER
Peaking (Figure 20)
CD = 0.15 µF
CD = 0.33 µF
0.08
0.04
92
dB
dB
kHz
Bandwidth
65
130
Acquisition T ime
CD = 0.1 µF
CD = 0.33 µF
223–1 PRN Sequence, T A = +25°C
VCC = 5 V, VEE = GND
4 × 105 2 × 106 Bit Periods
2 × 106
Bit Periods
POWER SUPPLY VOLT AGE
POWER SUPPLY CURRENT
VMIN to VMAX
4.5
25
5.5
Volts
VCC = 5.0 V, VEE = GND,
T A = +25°C
34.5
39.5
mA
PECL OUT PUT VOLT AGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
–1.2
–2.0
–1.0
–1.8
–0.7
–1.7
Volts
Volts
Referenced to VCC
SYMMET RY (Duty Cycle)
ρ = 1/2, T A = +25°C,
Recovered Clock Output, Pin 5
VCC = 5 V, VEE = GND
50.1
54.1
%
OUT PUT RISE / FALL T IMES
Rise T ime (tR)
Fall T ime (tF)
20%–80%
80%–20%
1.1
1.1
1.5
1.5
ns
ns
Specifications subject to change without notice.
–2–
REV. A
AD807
P IN FUNCTIO N D ESCRIP TIO NS
ABSO LUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V
Maximum Junction T emperature . . . . . . . . . . . . . . . . . +165°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . 500 V
P in
No.
Mnem onic
D escription
1
DAT AOUT N
DAT AOUT P
VCC2
Differential Retimed Data Output
Differential Retimed Data Output
Digital VCC for ECL Outputs
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital VCC for Internal Logic
Loop Damping Capacitor
Loop Damping Capacitor
Analog VEE
2
NOT ES
3
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
T hermal Characteristics:
4
CLKOUT N
CLKOUT P
VCC1
5
6
7
CF1
16-Pin Narrow Body SOIC Package: θJA = 110°C/Watt.
8
CF2
OUTPUT
9
AVEE
NOISE
1
10
11
12
13
14
15
16
T HRADJ
AVCC1
Level Detect T hreshold Adjust
Analog VCC for PLL
NIN
Quantizer Differential Input
Quantizer Differential Input
Analog VCC for Quantizer
Signal Detect Output
0
PIN
INPUT (V)
OFFSET
AVCC2
OVERDRIVE
SENSITIVITY
SDOUT
VEE
Digital VEE for Internal Logic
Figure 1. Input Sensitivity, Input Overdrive
SETUP
t SU
HOLD
t H
P IN CO NFIGURATIO N
DATAOUTP
(PIN 2)
DATAOUTN
DATAOUTP
V
1
2
3
16
V
EE
15 SDOUT
14 AV
CC2
CLKOUTP
(PIN 5)
2
CC
AD807
TOP VIEW
CLKOUTN
CLKOUTP
13 PIN
12 NIN
4
5
6
7
8
(NOT TO SCALE)
Figure 2. Setup and Hold Tim e
V
CC
11 AV
CC1
1
CF1
CF2
10 THRADJ
9
AV
EE
O RD ERING GUID E
Tem perature Range
Model
P ackage D escription
P ackage O ption
AD807-155BR or AD807A-155BR
AD807-155BR-REEL7 or AD807A-155BRRL7
AD807-155BR-REEL or AD807A-155BRRL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Pin Narrowbody SOIC
750 Pieces, 7" Reel
2500 Pieces, 13" Reel
R-16A
R-16A
R-16A
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD807 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD807
Tr acking Range
D EFINITIO N O F TERMS
T his is the range of input data rates over which the AD807 will
remain in lock.
Maxim um , Minim um and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. T ypical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. T his procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guard-
banded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Captur e Range
T his is the range of input data rates over which the AD807 will
acquire lock.
Static P hase Er r or
T his is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling in-
stant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals pro-
hibit direct measurement of static phase error.
D ata Tr ansition D ensity, ρ
Input Sensitivity and Input O ver dr ive
T his is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
Sensitivity and Overdrive specifications for the Quantizer in-
volve offset voltage, gain and noise. T he relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
Jitter
T his is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but oc-
cur over a range of input voltages. Within this Zone of Confu-
sion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. T he width of this zone is determined by the
input voltage noise of the quantizer (650 µV at the 1 × 10–10
confidence level). T he center of the Zone of Confusion is the
quantizer input offset voltage (±500 µV maximum). Input Over-
drive is the magnitude of signal required to guarantee correct
logic level with 1 × 10–10 confidence level.
O utput Jitter
T his is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter Toler ance
Jitter T olerance is a measure of the AD807’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
With a single-ended PIN-T IA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some common-
mode potential. Observing the Quantizer input with an oscillo-
scope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instan-
taneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Over-
drive. T he AD807 Quantizer has 2 mV Sensitivity.
T he PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. T he modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low fre-
quencies, the integrator of the AD807 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. T he AD807
output will have a bit error rate less than 1 × 10–10 when in lock
and retiming input data that has the CCIT T G.958 specified
jitter applied to it.
With a differential T IA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
T his is an illusion caused by the use of a single-ended probe. A
1 mV peak-to-peak signal appears to drive the AD807 Quan-
tizer. However, the single-ended probe measures only half the
signal. T he true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the sig-
nal being observed.
Jitter Tr ansfer (Refer to Figur e 20)
T he AD807 exhibits a low-pass filter response to jitter applied
to its input data.
Response Tim e
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT . T he re-
sponse time of the AD807 (1.5 µs maximum) is much faster
Bandwidth
T his describes the frequency at which the AD807 attenuates
sinusoidal input jitter by 3 dB.
than the SONET /SDH requirement (3 µs
≤ response time ≤
100 µs). In practice, the time constant of the ac coupling at the
Quantizer input determines the LOS response time.
P eaking
T his describes the maximum jitter gain of the AD807 in dB.
Nom inal Center Fr equency
T his is the frequency at which the VCO will oscillate with the
loop damping capacitor, CD, shorted.
–4–
REV. A
AD807
AV
CC2
D am ping Factor , ζ
400Ω
400Ω
Damping factor, ζ describes the compensation of the second or-
der PLL. A larger value of ζ corresponds to more damping and
less peaking in the jitter transfer function.
DIFFERENTIAL
INPUT
V
ഡ 0.8V
BE
CURRENT SOURCES
HEADROOM ≥ 0.7V
Acquisition Tim e
T his is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
0.5mA
1mA
0.5mA
AV
EE
Sym m etr y—Recover ed Clock D uty Cycle
a. Quantizer Differential Input Stage
Symmetry is calculated as (100 × on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
1.2V +V
BE
Bit Er r or Rate vs. Signal-to-Noise Ratio
5.9kΩ
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in Figure 11. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
THRADJ
94.6kΩ
AV
EE
b. Threshold Adjust
2mVp-p
V
CM
V
CC1
EPITAXX ERM504
SCOPE
PROBE
I
AD807 QUANTIZER
OH
150Ω
BINARY
OUTPUT
SDOUT
150Ω
I
OL
V
CM
V
EE
c. Signal Detect Output (SDOUT)
a. Single-Ended Input Application
V
CC2
1mVp-p
V
CM
450Ω
450Ω
AD8015
DIFFERENTIAL
OUTPUT TIA
SCOPE
PROBE
DIFFERENTIAL
OUTPUT
AD807 QUANTIZER
+OUT
BINARY
OUTPUT
2.5mA
–OUT
V
EE
V
CM
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Sim plified Schem atics
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
POWER COMBINER
0.47µF
+
∑
PIN
+
50Ω
50Ω
DIFFERENTIAL
SIGNAL
SOURCE
D.U.T.
AD807
POWER
COMBINER
0.47µF
+
∑
NIN
–
POWER
SPLITTER
75Ω 1.0µF
100Ω
+5V
100MHz FILTER
GND
NOISE
SOURCE
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
REV. A
–5–
AD807–Typical Characteristic Curves
200.0E+3
180.0E+3
160.0E+3
35.000E–3
30.000E–3
25.000E–3
20.000E–3
15.000E–3
R
= 0Ω
THRESH
140.0E+3
120.0E+3
100.0E+3
80.0E+3
60.0E+3
40.0E+3
10.000E–3
5.000E–3
R
= 49.9k
= OPEN
THRESH
20.0E+3
0.0E+0
R
THRESH
000.000E+0
000.0E+0
5.0E–3
10.0E–3 15.0E–3
20.0E–3 25.0E–3 30.0E–3 35.0E–3
4.4
4.6
4.8
5.0
5.2
5.4
5.6
SIGNAL DETECT LEVEL – Volts
SUPPLY VOLTAGE – Volts
Figure 6. Signal Detect Level vs. RTHRESH
Figure 9. Signal Detect Level vs. Supply Voltage
35.0E–3
30.0E–3
25.0E–3
20.0E–3
15.0E–3
8.00
7.00
R
= 0Ω
THRESH
R
= 0Ω
THRESH
6.00
5.00
4.00
3.00
2.00
1.00
0.00
R
= 49.9kΩ
THRESH
R
= OPEN
THRESH
10.0E–3
5.0E–3
R
= 49.9k
THRESH
R
= OPEN
60
THRESH
000.0E+0
–40
–20
0
20
40
80
100
4.4
4.6
4.8
5.0
5.2
5.4
5.6
TEMPERATURE – °C
POWER SUPPLY – V
Figure 7. Signal Detect Level vs. Tem perature
Figure 10. Signal Detect Hysteresis vs. Power Supply
9.00
8.00
1E-1
5E-2
3E-2
2E-2
R
= 0Ω
THRESH
7.00
1E-2
1
2
1
2 2
S
N
erfc
R
= 49.9k
THRESH
6.00
5.00
4.00
3.00
1E-3
1E-4
1278
1E-5
1E-6
NSN
R
= OPEN
THRESH
1279
14
1276
1E-8
1E-10
1E-12
1277
–40
–20
0
20
40
60
80
100
TEMPERATURE – °C
10
12
16
S/N – dB
18
20
22
24
Figure 8. Signal Detect Hysteresis vs. Tem perature
Figure 11. Bit Error Rate vs. Signal-to-Noise Ratio
REV. A
–6–
AD807
30
25
20
15
10
5
XFCB’s dielectric isolation allows the different blocks within
this mixed-signal IC to be isolated from each other, hence the
2 mV Sensitivity is achieved. T raditionally, high speed compara-
tors are plagued by crosstalk between outputs and inputs, often
resulting in oscillations when the input signal approaches 10 mV.
T he AD807 quantizer toggles at ±650 µV (1.3 mV sensitivity) at
the input without making bit errors. When the input signal is
lowered below ±650 µV, circuit performance is dominated by
input noise, and not crosstalk.
TEST CONDITIONS
WORST CASE:
– 40°C, 4.5V
0.1µF
PIN 13
500Ω
500Ω
QUANTIZER
INPUT
0.1µF
0
NIN 12
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
10E+6
1.0
OPTIONAL FILTER
FERRITE BEAD
RMS JITTER – Degrees
50Ω
50Ω
0.1µF
309Ω
0.1µF
AD807
311MHz
NOISE
INPUT
3.65kΩ
0.1µF
Figure 12. Output J itter Histogram
50Ω
AV
14
11
CC2
1E+3
100E+0
10E+0
1E+0
CHOKE
"BIAS TEE"
0.1µF
0.1µF
0.1µF
0.1µF
+5V
AV
CC1
10µF
V
CC
V
CC
6
3
1
2
AD807
Figure 15. Power Supply Noise Sensitivity Test Circuit
0.1µF
PIN 13
500Ω
500Ω
QUANTIZER
INPUT
SONET MASK
0.1µF
NIN 12
100E–3
10E+0
100E+0
10E+3
100E+3
1E+6
1E+3
50Ω
50Ω
0.1µF
309Ω
FREQUENCY – Hz
AD807
311MHz
NOISE
INPUT
3.65kΩ
50Ω
CHOKE
"BIAS TEE"
Figure 13. J itter Tolerance
0.1µF
AV
14
11
CC2
3.0
2.0
1.0
0
0.1µF
0.1µF
0.1µF
0.1µF
+5V
AV
CC1
10µF
V
CC
V
CC
6
3
1
2
PSR – NO FILTER
CMR
Figure 16. Com m on-Mode Rejection Test Circuit
Signal D etect
T he input to the signal detect circuit is taken from the first stage
of the quantizer. T he input signal is first processed through a
gain stage. T he output from the gain stage is fed to both a posi-
tive and a negative peak detector. T he threshold value is sub-
tracted from the positive peak signal and added to the negative
peak signal. T he positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT , will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
T he circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
T his means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. T his corresponds to a 3 dB optical hysteresis.
PSR – WITH FILTER
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9
NOISE – Vp-p @311MHz
Figure 14. Output J itter vs. Supply Noise and
Output J itter vs. Com m on Mode Noise
TH EO RY O F O P ERATIO N
Q uantizer
T he quantizer (comparator) has three gain stages, providing a
net gain of 350. T he quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. T he input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. T he input offset
voltage is factory trimmed and guaranteed to be less than 500 µV.
REV. A
–7–
AD807
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisi-
tion time no longer scales directly with capacitor value. T he
acquisition time has two components: frequency acquisition and
phase acquisition. T he frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop band-
width of the PLL and is independent of the damping ratio.
T hus, the 0.06% fractional loop bandwidth sets a minimum
acquisition time of 2000 bit periods. Note the acquisition time
for a damping factor of one is 15,000 bit periods. T his com-
prises 13,000 bit periods for frequency acquisition and 2,000 bit
periods for phase acquisition. Compare this to the 400,000 bit
periods acquisition time specified for a damping ratio of 5; this
consists entirely of frequency acquisition, and the 2,000 bit
periods of phase acquisition is negligible.
THRESHOLD
BIAS
AD807
PIN
NIN
IHYS
COMPARATOR STAGES
& CLOCK RECOVERY PLL
+
+
∑
ITHR
POSITIVE
PEAK
DETECTOR
LEVEL
SHIFT
DOWN
SDOUT
NEGATIVE
PEAK
DETECTOR
LEVEL
SHIFT
UP
Figure 17. Signal Level Detect Circuit Block Diagram
P hase-Locked Loop
T he phase-locked loop recovers clock and retimes data from
NRZ data. T he architecture uses a frequency detector to aid ini-
tial frequency acquisition; refer to Figure 18 for a block dia-
gram. Note the frequency detector is always in the circuit. When
the PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is al-
ways in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
While a lower damping ratio affords faster acquisition, it also al-
lows more peaking in the jitter transfer response (jitter peaking).
For example, with a damping ratio of 10, the jitter peaking is
0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.
Center Fr equency Clam p (Figur e 19)
An N-channel FET circuit can be used to bring the AD807
VCO center frequency to within ±10% of 155 MHz when
SDOUT indicates a Loss of Signal (LOS). T his effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. T he N-FET can have “on” resistance as high
as 1 kΩ and still attain effective clamping. However, the chosen
N-FET should have greater than 10 MΩ “off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
1
S
Φ
DATA
INPUT
∑
S + 1
DET
VCO
F
RECOVERED CLOCK
OUTPUT
DET
RETIMING
DEVICE
RETIMED DATA
OUTPUT
Figure 18. PLL Block Diagram
T he frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
T hese pulses occur on the cycle slips between the data fre-
quency and the VCO frequency. With a maximum density data
pattern (1010 . . . ), every cycle slip will produce a pulse at the
frequency detector output. However, with random data, not
every cycle slip produces a pulse. T he density of pulses at the
frequency detector output increases with the density of data
transitions. T he probability that a cycle slip will produce a pulse
increases as the frequency error approaches zero. After the fre-
quency error has been reduced to zero, the frequency detector
output will have no further pulses. At this point the PLL begins
the process of phase acquisition, with a settling time of roughly
2000 bit periods.
1
2
3
DATAOUTN
DATAOUTP
V
16
EE
SDOUT 15
AV
CC2
14
V
CC2
CLKOUTN
CLKOUTP
PIN 13
NIN 12
4
5
6
7
8
V
CC
AV
CC1
11
1
N_FET
CF1
CF2
THRADJ 10
C
D
AV
EE
9
AD807
Figure 19. Center Frequency Clam p Schem atic
CD PEAK
0.1
0.12
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector (pat-
ented). Briefly, the measurement of zero phase error does not
cause the VCO phase to increase to above the average run rate
set by the data frequency. T he jitter created by a 27–1 pseudo-
random code is 1/2 degree, and this is small compared to ran-
dom jitter.
0.15 0.08
0.22 0.06
0.33 0.04
T he jitter bandwidth for the PLL is 0.06% of the center fre-
quency. T his figure is chosen so that sinusoidal input jitter at
92 kHz will be attenuated by 3 dB.
10
100
1k
FREQUENCY IN kHz
10k
20k
T he damping ratio of the PLL is user programmable with a
single external capacitor. At 155 MHz, a damping ratio of 5 is
obtained with a 0.15 µF capacitor. More generally, the damping
Figure 20. J itter Transfer vs. CD
ratio scales as (fDAT A × CD)1/2
.
–8–
REV. A
AD807
C1 0.1µF
R1
J5
TP7 TP8
50Ω STRIP LINE
EQUAL LENGTH
SDOUT
R13
R2
R9
R10
100Ω 100Ω
154Ω
154Ω
C12 0.1µF
J1 C3 0.1µF
R5 100Ω
1
2
3
VEE 16
DATAOUTN
DATAOUTP
DATAOUTN
DATAOUTP
R6 100Ω
15
14
SDOUT
R16 3.65kΩ
J2
C4 0.1µF
C5 0.1µF
301Ω
AV
R14
R15
49.9Ω
CC2
V
CC2
C9
C13 0.1µF
J6
J7
49.9Ω
C7
J3
CLKOUTN
R7 100Ω
R8 100Ω
4
5
6
PIN 13
NIN 12
PIN
NIN
CLKOUTN
CLKOUTP
CLKOUTP
J4
C14 0.1µF
C6 0.1µF
11
AV
V
CC1
CC1
C8
C10
VECTOR PINS SPACED FOR RN55C
TYPE RESISTOR; COMPONENT
SHOWN FOR REFERENCE ONLY
TP1
R4
R3
100Ω
TP5
7
8
10
9
R11
154Ω
CF1
CF2
THRADJ
100Ω
CD
R
THRESH
R12
154Ω
AV
EE
TP2
AD807
NOTE:
C2
0.1µF
TP6
NOTE: INTERCONNECT RUN
UNDER DUT
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
C11
10µF
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TP3
TP4
+5V
GND
TPx TEST POINTS ARE VECTORBOARD K24A/M PINS
o
Figure 21. Evaluation Board Schem atic
CIRCUIT SIDE
08-002901-02
REV A
INT2
08-002901-08
REV A
INT1
08-002901-07
REV A
SILKSCREEN TOP
08-002901-03
REV A
COMPONENT SIDE
08-002901-01
REV A
SOLDERMASK TOP
08-002901-04
REV A
Figure 22. Evaluation Board Pictorials
REV. A
–9–
AD807
C1 0.1µF
SDOUT
TP7
C2
0.1µF
R1 R2
R9 R10
154 154
R17
C12
R16
301
R5 100
R6 100
C13
0.1µF
100 100
3.65k 2.2µF
1
2
3
VEE 16
DATAOUTN
DATAOUTP
DATAOUTN
DATAOUTP
C3
0.1µF
15
14
SDOUT
C11
C4
0.1µF
AV
CC
R14
50
R15
50
V
CC2
C7
R7 100
R8 100
4
5
6
PIN 13
NIN 12
CLKOUTN
CLKOUTP
CLKOUTN
CLKOUTP
C10
TP6
C5
0.1µF
11
10
9
AV
CC
V
CC1
C8
TP1
R4
100
R3
100
7
8
CF1
CF2
THRADJ
C15
0.1µF 0.1µF
C14
CD
R13
THRADJ
TP5
R11
154
R12
154
AV
EE
TP2
AD807
C6
0.1µF
C9
10µF
0.1µF
10µF
GND
TP4
50Ω
LINE
50Ω
LINE
5V TP3
1
2
NC
IIN
ABB HAFO 1A227
FC HOUSING
+VS
8
7
6
5
150nH
15pF
NOTES
1. ALL CAPS ARE CHIP,
15pF ARE MICA.
+OUT
0.8 A/W, 0.7pF
NC
3
4
–OUT
–VS
2.5GHz
2. 150nH ARE SMT
150nH
15pF
VBYP
AD8015
NC = NO CONNECT
0.1µF
0.01µF
Figure 23. Low Cost 155 Mbps Fiber Optic Receiver Schem atic
Table I. AD 807—AD 8015 Fiber O ptic Receiver Circuit:
O utput Bit Error Rate & O utput Jitter vs. Input P ower
Average O ptical
Input P ower
(dBm )
O utput Bit
Error Rate
O utput Jitter
(ps rm s)
–6.4
–6.5
–6.6
–6.7
Loses Lock
7.5 × 10–3
9.4 × 10–4
0 × 10–14
–7.0 to –35.5
–36.0
0 × 10–14
3 × 10–12
<40
<40
4.8 × 10–10
2.8 × 10–8
1.3 × 10–5
1.0 × 10–3
1.9 × 10–3
Loses Lock
Figure 24. Receiver Output (Data) Eye Diagram ,
–7.0 dBm Optical Input
–36.5
–37.0
–38.0
–39.0
–39.2
–39.3
AP P LICATIO NS
Low Cost 155 Mbps Fiber O ptic Receiver
T he AD807 and AD8015 can be used together for a complete
155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery,
and T ransimpedance Amplifier) as shown in Figure 23.
T he PIN diode front end is connected to a single mode 1300 nm
laser source. T he PIN diode has 3.3 V reverse bias, 0.8 A/W re-
sponsively, 0.7 pF capacitance, and 2.5 GHz bandwidth.
T he AD8015 outputs (POUT and NOUT ) drive a differential, con-
stant impedance (50 Ω) low-pass filter with a 3 dB cutoff of
100 MHz. T he outputs of the low-pass filter are ac coupled to
the AD807 inputs (PIN and NIN). T he AD807 PLL damping
factor is set at 7 using a 0.22 µF capacitor.
Figure 25. Receiver Output (Data) Eye Diagram ,
–36.0 dBm Optical Input
–10–
REV. A
AD807
C1 0.1µF
SDOUT
C12 0.1
C2
0.1µF
R1 R2
R9 R10
154 154
R5 100
R6 100
100 100
1
2
3
VEE 16
J1
J2
DATAOUTN
DATAOUTP
R16
330
C3
0.1µF
C13
0.1
15
14
SDOUT
R17
3.9k
PIN TIA
2
1µF
R15
47
R14
47
C4
0.1µF
AV
CC2
EPITAXX
ERM504
V
CC2
120nH
1
C11 0.1
R7 100
R8 100
C7 0.1µF
4
5
6
PIN 13
NIN 12
CLKOUTN
CLKOUTP
J3
J4
C14
0.1
30pF
30pF
C10 0.1
C5
0.1µF
V
CC1
11
AV
CC1
3
NOISE FILTER
C8
CD
0.1µF
R4
100
R3
100
CF1
CF2
7
8
10
9
R11
150
THRADJ
R12
150
NOTE
R13
THRADJ
AVEE
0.1µF
PIN TIA PIN 4 (CASE)
IS CONNECTED TO
GROUND
AD807
C6
0.1µF
C9 10
+5V
Figure 26. AD807 Application with Epitaxx PIN—Transim pedance Am plifier Module
T he entire circuit was enclosed in a shielded box. T able I sum-
marizes results of tests performed using a 223-1 PRN Sequence,
and varying the average power at the PIN diode.
250mV
T he circuit acquires and maintains lock with an average input
power as low as –39.25 dBm.
50mV/
DIV
Table II. AD 807—Epitaxx ERM504 P IN TIA 155 Mbps
Fiber O ptic Receiver Circuit:
O utput Bit Error Rate & Output Jitter vs. Average Input P ower
Average O ptical
Input P ower
(dBm )
O utput Bit
Error Rate
O utput Jitter
(ps rm s)
–250mV
48.12ns
1ns/DIV
38.12ns
0
–3
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.0 × 10–10
0.5 × 10–10
4 × 10–6
29
35
40
37
33
35
36
39
40
41
42
43
50
Figure 27. Receiver Output (Data) Eye Diagram ,
0 dBm Optical Input
–10
–20
–30
–32
–34
–35
–35.5
–36
–37.0
–37.6
–38.0
250mV
50mV/
DIV
SO NET (O C-3)/SD H (STM-1) Fiber O ptic Receiver Cir cuit
A light wave receiver circuit for SONET /SDH application at
155 Mbps is shown in Figure 26, with test results given in T able
II. T he circuit operates from a single +5 V supply, and uses two
major components: an Epitaxx ERM504 PIN-T IA module with
AGC, and the AD807 IC.
–250mV
48.12ns
1ns/DIV
38.12ns
Figure 28. Receiver Output (Data) Eye Diagram ,
–38 dBm Optical Input
A 120 MHz, third order, low-pass Butterworth filter at the out-
put of the PIN-T IA module provides adequate bandwidth (70%
of the bit rate), and attenuates high frequency (out of band)
noise.
REV. A
–11–
AD807
AD 807 O utput Squelch Cir cuit
USING TH E AD 807
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure
29). T he VCC2 supply pin draws roughly 61 mA (14 mA for each
of 4 ECL loads, plus 5 mA for all 4 ECL output stages). T his
means that selection of a FET with ON RESIST ANCE of
0.5 Ω will affect the common mode of the ECL outputs by only
31 mV.
Gr ound P lanes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
P ower Supply Connections
Use of a 10 µF capacitor between VCC and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to VCC2 (Pin 3). T he VCC2 pin is used inside the device to pro-
vide the CLKOUT and DAT AOUT signals.
TO V
, AV , AV
CC
CC1
CC2
Use of 0.1 µF capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 21,
for recommended connections.
5V
P_FET
1
2
3
DATAOUTN
DATAOUTP
V
16
EE
Tr ansm ission Lines
Use of 50 Ω transmission lines are recommended for PIN, NIN,
CLKOUT , and DAT AOUT signals.
SDOUT 15
AV
CC2
14
V
CC2
BYPASS
CAP
CLKOUTN
CLKOUTP
PIN 13
NIN 12
4
5
6
7
8
Ter m inations
T ermination resistors should be used for PIN, NIN, CLKOUT ,
and DATAOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. T ermination resistors for the PIN, NIN sig-
nals should be placed as close as possible to the PIN, NIN pins.
V
AV
11
1
CC
CC1
CF1
CF2
THRADJ 10
AV
EE
9
AD807
Connections from +5 V to load resistors for PIN, NIN,
CLKOUT , and DAT AOUT signals should be individual, not
daisy chained. T his will avoid crosstalk on these signals.
Figure 29. Squelch Circuit Schem atic
Loop D am ping Capacitor , C D
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.15 µF, +20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead Sm all O utline IC P ackage
(R-16A)
16
1
9
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
8
0.3937 (10.00)
0.3859 (9.80)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0688 (1.75)
0.0532 (1.35)
8°
0°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
–12–
REV. A
相关型号：
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