AD8129_05 [ADI]
Low Cost 270 MHz Differential Receiver Amplifiers; 低成本的270 MHz差分接收器放大器
| 型号： | AD8129_05 |
| 厂家： | 
ADI |
| 描述： | Low Cost 270 MHz Differential Receiver Amplifiers |
| 文件： | 总40页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost 270 MHz
Differential Receiver Amplifiers
AD8129/AD8130
CONNECTION DIAGRAM
FEATURES
High speed
AD8129/
AD8130
AD8130: 270 MHz, 1090 V/μs @ G = +1
AD8129: 200 MHz, 1060 V/μs @ G = +10
High CMRR
94 dB min, dc to 100 kHz
80 dB min @ 2 MHz
1
2
3
4
8
7
6
5
–IN
+V
+IN
–
V
S
S
+
OUT
FB
PD
REF
70 dB @ 10 MHz
High input impedance: 1 MΩ differential
Input common-mode range 10.5 V
Low noise
AD8130: 12.5 nV/√Hz
AD8129: 4.5 nV/√Hz
Low distortion, 1 V p-p @ 5 MHz
AD8130, −79 dBc worst harmonic @ 5 MHz
AD8129, −74 dBc worst harmonic @ 5 MHz
User-adjustable gain
No external components for G = +1
Power supply range +4.5 V to 12.6 V
Power-down
Figure 1.
The AD8129/AD8130 are differential-to-single-ended amplifiers
with extremely high CMRR at high frequency. Therefore, they
can also be effectively used as high speed instrumentation amps
or for converting differential signals to single-ended signals.
The AD8129 is a low noise, high gain (10 or greater) version
intended for applications over very long cables, where signal
attenuation is significant. The AD8130 is stable at a gain of 1
and can be used for applications where lower gains are required.
Both have user-adjustable gain to help compensate for losses in
the transmission line. The gain is set by the ratio of two resistor
values. The AD8129/AD8130 have very high input impedance
on both inputs, regardless of the gain setting.
APPLICATIONS
High speed differential line receivers
Differential-to-single-ended converters
High speed instrumentation amps
Level shifting
GENERAL DESCRIPTION
The AD8129/AD8130 have excellent common-mode rejection
(70 dB @ 10 MHz), allowing the use of low cost, unshielded
twisted-pair cables without fear of corruption by external noise
sources or crosstalk. The AD8129/AD8130 have a wide power
supply range from single +5 V to 12 V, allowing wide common-
mode and differential-mode voltage ranges while maintaining
signal integrity. The wide common-mode voltage range enables
the driver-receiver pair to operate without isolation transformers
in many systems where the ground potential difference between
drive and receive locations is many volts. The AD8129/AD8130
have considerable cost and performance improvements over
op amps and other multiamplifier receiving solutions.
The AD8129/AD8130 are designed as receivers for the
transmission of high speed signals over twisted-pair cables to
work with the AD8131 or AD8132 drivers. Either can be used
for analog or digital video signals and for high speed data
transmission.
120
110
100
90
80
70
60
+V
S
PD
3
1
8
V
IN
7
2
50
40
30
V
6
OUT
4
5
10k
100k
1M
10M
100M
R
R
G
F
FREQUENCY (Hz)
–V
Figure 2. AD8129 CMRR vs. Frequency
S
V
= V [1+(R /R )]
IN
OUT
F
G
Figure 3. Typical Connection Configuration
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8129/AD8130
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 32
Op Amp Configuration............................................................. 32
Applications..................................................................................... 33
Basic Gain Circuits..................................................................... 33
Applications....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
AD8129/AD8130 Specifications..................................................... 3
5 V Specifications ......................................................................... 3
5 V Specifications....................................................................... 5
12 V Specifications..................................................................... 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
AD8130 Frequency Response Characteristics........................ 10
AD8129 Frequency Response Characteristics........................ 13
AD8130 Harmonic Distortion Characteristics ...................... 16
AD8129 Harmonic Distortion Characteristics ...................... 18
AD8130 Transient Response Characteristics.......................... 23
AD8129 Transient Response Characteristics.......................... 26
Twisted-Pair Cable, Composite Video Receiver with
Equalization Using an AD8130................................................... 33
Output Offset/Level Translator ................................................ 34
Resistorless Gain of 2................................................................. 35
Summer ....................................................................................... 35
Cable-Tap Amplifier .................................................................. 35
Power-Down ............................................................................... 36
Extreme Operating Conditions................................................ 36
Power Dissipation....................................................................... 37
Layout, Grounding, and Bypassing.......................................... 38
Outline Dimensions....................................................................... 39
Ordering Guide .......................................................................... 40
REVISION HISTORY
11/05—Rev. B to Rev. C
3/05—Rev. 0 to Rev. A
Changes to 5 V Specifications......................................................... 3
Changes to Table 4 and Maximum Power Dissipation Section.. 9
Changes to Figure 16...................................................................... 11
Changes to Figure 17...................................................................... 12
Changes to Specifications.................................................................2
Replaced Figure 3 ..............................................................................5
Changes to Ordering Guide.............................................................6
Updated Outline Dimensions....................................................... 27
Revision 0: Initial Version
9/05—Rev. A to Rev. B
Extended Temperature Range...........................................Universal
Deleted Figure 5................................................................................ 5
Added Thermal Resistance Section ............................................... 9
Updated Outline Dimensions....................................................... 39
Changes to Ordering Guide .......................................................... 40
Rev. C | Page 2 of 40
AD8129/AD8130
AD8129/AD8130 SPECIFICATIONS
5 V SPECIFICATIONS
PD
AD8129 G = +10, AD8130 G = +1, TA = 25°C, +VS = 5 V, −VS = 0 V, REF = 2.5 V,
TMIN to TMAX = −40°C to +125°C, unless otherwise noted.
≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted.
Table 1.
Model
Parameter
AD8129
Typ
AD8130
Typ
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT ≤ 0.3 V p-p
VOUT = 1 V p-p
VOUT ≤ 0.3 V p-p,
SOIC/MSOP
160
160
185
185
25/40
220
180
250
205
25
MHz
MHz
MHz
Bandwidth for 0.1 dB
Flatness
Slew Rate
VOUT = 2 V p-p, 25%
to 75%
810
930
810
930
V/μs
Settling Time
Rise and Fall Times
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p, 10%
to 90%
20
1.8
20
1.5
ns
ns
Output Overdrive Recovery
NOISE/DISTORTION
20
30
ns
Second Harmonic/Third
Harmonic
V
OUT = 1 V p-p, 5 MHz
−68/−75
−72/−79
dBc
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
−62/−64
−63/−70
−56/−58
−67
25
4.5
−65/−71
−60/−62
−68/−68
−70
26
12.3
dBc
dBc
dBc
dBc
IMD
Output IP3
Input Voltage Noise (RTI)
dBm
nV/√Hz
pA/√Hz
pA/√Hz
Input Current Noise (+IN, −IN) f ≥ 100 kHz
1
1.4
1
1.4
Input Current Noise
(REF, FB)
f ≥ 100 kHz
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
AD8130, G = +2, NTSC
100 IRE, RL ≥ 150 Ω
AD8130, G = +2, NTSC
100 IRE, RL ≥ 150 Ω
0.3
0.1
0.13
0.15
%
Degrees
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = 1.5 V to 3.5 V
86
96
86
80
96
dB
VCM = 1 V p-p @ 1 MHz 80
VCM = 1 V p-p @ 10 MHz
dB
dB
dB
70
80
70
72
CMRR with VOUT = 1 V p-p
VCM = 1 V p-p @ 1 kHz,
VOUT = 0.5 V dc
Common-Mode Voltage
Range
V+IN − V−IN = 0 V
1.25 to
3.7
1.25 to
3.8
V
Differential Operating Range
Differential Clipping Level
Resistance
0.5
0.75
1
4
3
2.5
2.8
6
4
3
V
V
MΩ
MΩ
pF
pF
0.6
0.85
2.3
3.3
Differential
Common mode
Differential
Capacitance
Common mode
4
4
Rev. C | Page 3 of 40
AD8129/AD8130
Model
Parameter
AD8129
Typ
AD8130
Typ
Conditions
Min
Max
1.25
Min
Max
Unit
DC PERFORMANCE
Closed-Loop Gain Error
VOUT = 1 V, RL ≥ 150 Ω
TMIN to TMAX
0.25
20
0.1
20
0.6
%
ppm/°C
dB
ppm
mV
μV/°C
mV
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
VOUT = 1 V
VOUT = 1 V
86
71
250
0.2
2
200
0.4
20
0.8
1.8
TMIN to TMAX
TMIN to TMAX
1.4
3.5
Input Offset Voltage vs.
Supply
+VS = 5 V, −VS = −0.5 V
to +0.5 V
−VS = 0 V, +VS = +4.5 V
to +5.5 V
−88
−100
0.5
1
−80
−74
−90
0.5
1
−70
dB
−86
2
−76
2
dB
Input Bias Current
(+IN, −IN)
Input Bias Current
(REF, FB)
μA
3.5
3.5
μA
TMIN to TMAX (+IN, −IN,
REF, FB)
5
5
nA/°C
Input Offset Current
(+IN, −IN, REF, FB)
TMIN to TMAX
0.08
0.2
0.4
3.9
0.08
0.2
0.4
3.9
μA
nA/°C
OUTPUT PERFORMANCE
Voltage Swing
RLOAD ≥ 150 Ω
1.1
1.1
V
Output Current
Short-Circuit Current
35
35
mA
mA
μA/°C
pF
To common
TMIN to TMAX
PD
≤ VIL, in power-
−60/+55
−240
10
−60/+55
−240
10
Output Impedance
down mode
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total supply voltage
TMIN to TMAX
2.25
12.6
10.6
2.25
12.6
10.6
V
9.9
33
0.65
9.9
33
0.65
mA
μA/°C
mA
mA
PD
PD
0.85
1
0.85
1
≤ VIL
≤ VIL, TMIN to TMAX
PD
PIN
VIH
+VS − 1.5
+VS − 1.5
V
VIL
IIH
+VS − 2.5
−30
+VS − 2.5
−30
V
PD
PD
PD
PD
μA
μA
kΩ
kΩ
μs
°C
= min VIH
IIL
−50
−50
= max VIL
Input Resistance
12.5
100
0.5
12.5
100
0.5
≤ +VS − 3 V
≥ +VS − 2 V
Enable Time
OPERATING TEMPERATURE
RANGE
−40
+125
−40
+125
Rev. C | Page 4 of 40
AD8129/AD8130
5 V SPECIFICATIONS
PD
AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = 5 V, REF = 0 V,
= −40°C to +125°C, unless otherwise noted.
≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to TMAX
Table 2.
AD8129
Typ
AD8130
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT ≤ 0.3 V p-p
VOUT = 2 V p-p
VOUT ≤ 0.3 V p-p,
SOIC/MSOP
175
170
200
190
30/50
240
140
270
155
45
MHz
MHz
MHz
Bandwidth for 0.1 dB
Flatness
Slew Rate
VOUT = 2 V p-p,
25% to 75%
925
1060
950
1090
V/μs
Settling Time
Rise and Fall Times
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p,
10% to 90%
20
1.7
20
1.4
ns
ns
Output Overdrive Recovery
NOISE/DISTORTION
30
40
ns
Second Harmonic/Third
Harmonic
V
OUT = 1 V p-p, 5 MHz
−74/−84
−79/−86
dBc
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
−68/−74
−67/−81
−61/−70
−67
25
4.5
−74/−81
−74/−80
−74/−76
−70
26
12.5
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise
(+IN, −IN)
f ≥ 100 kHz
1
1
Input Current Noise
(REF, FB)
f ≥ 100 kHz
1.4
0.3
0.1
1.4
pA/√Hz
%
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.13
0.15
Degrees
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = −3 V to +3.5 V
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 2 V p-p @ 1 kHz,
VOUT = 0.5 V dc
94
80
110
90
80
110
dB
dB
dB
dB
70
100
70
83
CMRR with VOUT = 1 V p-p
Common-Mode Voltage
Range
Differential Operating
Range
V+IN − V−IN = 0 V
3.5
0.5
3.8
2.5
V
V
Differential Clipping Level
Resistance
0.6
0.75
0.85
2.3
2.8
3.3
V
Differential
Common mode
Differential
1
4
3
4
6
4
3
4
MΩ
MΩ
pF
pF
Capacitance
Common mode
Rev. C | Page 5 of 40
AD8129/AD8130
AD8129
Typ
AD8130
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Closed-Loop Gain Error
VOUT = 1 V, RL ≥ 150 Ω
TMIN to TMAX
VOUT = 1 V
0.4
20
88
250
0.2
2
1.5
0.15
10
74
200
0.4
20
0.6
%
ppm/°C
dB
ppm
mV
μV/°C
mV
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
VOUT = 1 V
0.8
1.8
TMIN to TMAX
TMIN to TMAX
1.4
3.5
Input Offset Voltage vs.
Supply
+VS = +5 V, −VS = −4.5 V
to −5.5 V
−VS = −5 V, +VS = +4.5 V
to +5.5 V
−90
−94
0.5
−84
−78
−80
0.5
−74
dB
−86
2
−74
2
dB
μA
Input Bias Current
(+IN, −IN)
Input Bias Current (REF, FB)
1
5
3.5
1
5
3.5
μA
nA/°C
TMIN to TMAX (+IN, −IN,
REF, FB)
Input Offset Current
(+IN, −IN, REF, FB)
TMIN to TMAX
0.08
0.2
0.4
0.08
0.2
0.4
μA
nA/°C
OUTPUT PERFORMANCE
Voltage Swing
RLOAD = 150 Ω/1 kΩ
3.6/4.0
3.6/4.0
V
Output Current
Short-Circuit Current
40
40
mA
mA
μA/°C
pF
To common
TMIN to TMAX
PD
≤ VIL, in power-
−60/+55
−240
10
−60/+55
−240
10
Output Impedance
down mode
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total supply voltage
TMIN to TMAX
2.25
12.6
11.6
2.25
12.6
11.6
V
10.8
36
0.68
10.8
36
0.68
mA
μA/°C
mA
mA
PD
PD
0.85
1
0.85
1
≤ VIL
≤ VIL, TMIN to TMAX
PD
PIN
VIH
+VS − 1.5
+VS − 1.5
V
VIL
IIH
+VS − 2.5
−30
+VS − 2.5
−30
V
PD
PD
PD
PD
μA
μA
kΩ
kΩ
μs
°C
= min VIH
IIL
−50
−50
= max VIL
Input Resistance
12.5
100
0.5
12.5
100
0.5
≤ +VS − 3 V
≥ +VS − 2 V
Enable Time
OPERATING TEMPERATURE
RANGE
−40
+125
−40
+125
Rev. C | Page 6 of 40
AD8129/AD8130
12 V SPECIFICATIONS
PD
AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = 12 V, REF = 0 V,
TMAX = −40°C to +85°C, unless otherwise noted.
≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to
Table 3.
AD8129
Typ
AD8130
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT ≤ 0.3 V p-p
VOUT = 2 V p-p
175
170
200
195
50/70
250
150
290
175
110
MHz
MHz
MHz
Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p,
SOIC/MSOP
Slew Rate
VOUT = 2 V p-p, 25%
to 75%
935
1070
960
1100
V/μs
Settling Time
Rise and Fall Times
VOUT = 2 V p-p, 0.1%
VOUT ≤ 1 V p-p, 10%
to 90%
20
1.7
20
1.4
ns
ns
Output Overdrive Recovery
NOISE/DISTORTION
40
40
ns
Second Harmonic/Third
Harmonic
V
OUT = 1 V p-p, 5 MHz
−71/−84
−79/−86
dBc
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
−65/−74
−65/−82
−59/−70
−67
25
4.6
−74/−81
−74/−80
−74/−74
−70
26
13
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise
(+IN, −IN)
f ≥ 100 kHz
1
1
Input Current Noise
(REF, FB)
f ≥ 100 kHz
1.4
0.3
0.1
1.4
pA/√Hz
%
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.13
0.2
Degrees
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = 10 V
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 4 V p-p @ 1 kHz,
VOUT = 0.5 V dc
92
80
105
88
80
105
dB
dB
dB
dB
70
93
70
80
CMRR with VOUT = 1 V p-p
Common-Mode Voltage
Range
V+IN − V–IN = 0 V
10.3
10.5
V
Differential Operating Range
Differential Clipping Level
Resistance
0.5
0.75
1
4
3
2.5
2.8
6
4
3
V
V
MΩ
MΩ
pF
pF
0.6
0.85
2.3
3.3
Differential
Common mode
Differential
Capacitance
Common mode
4
4
Rev. C | Page 7 of 40
AD8129/AD8130
AD8129
Typ
AD8130
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Closed-Loop Gain Error
VOUT = 1 V, RL ≥ 150 Ω
TMIN to TMAX
VOUT = 1 V
0.8
20
87
250
0.2
2
1.8
0.15
10
73
200
0.4
20
0.6
%
ppm/°C
dB
ppm
mV
μV/°C
mV
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
VOUT = 1 V
0.8
1.8
TMIN to TMAX
TMIN to TMAX
1.4
3.5
Input Offset Voltage vs. Supply +VS = +12 V, −VS =
–11.0 V to −13.0 V
−88
−92
−82
−77
−88
−70
dB
−VS = −12 V, +VS =
+11.0 V to +13.0 V
−84
−70
dB
Input Bias Current (+IN, −IN)
Input Bias Current (REF, FB)
0.25
0.5
2
3.5
0.25
0.5
2
3.5
μA
μA
TMIN to TMAX
2.5
2.5
nA/°C
(+IN, −IN, REF, FB)
Input Offset Current
(+IN, −IN, REF, FB)
TMIN to TMAX
0.08
0.2
0.4
0.08
0.2
0.4
μA
nA/°C
OUTPUT PERFORMANCE
Voltage Swing
RLOAD = 700 Ω
10.8
10.8
V
Output Current
Short-Circuit Current
40
40
mA
mA
μA/°C
pF
To common
TMIN to TMAX
PD
≤ VIL, in power-
−60/+55
−240
10
−60/+55
−240
10
Output Impedance
down mode
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total supply voltage
TMIN to TMAX
2.25
12.6
13.9
2.25
12.6
13.9
V
13
43
0.73
13
43
0.73
mA
μA°C
mA
mA
PD
PD
0.9
1.1
0.9
1.1
≤ VIL
≤ VIL, TMIN to TMAX
PD
PIN
VIH
+VS − 1.5
+VS − 1.5
V
VIL
IIH
+VS − 2.5
−30
+VS − 2.5
−30
V
PD
PD
PD
PD
μA
μA
kΩ
kΩ
μs
°C
= min VIH
IIL
−50
−50
= max VIL
Input Resistance
3
3
≤ +VS − 3 V
≥ +VS − 2 V
100
0.5
100
0.5
Enable Time
OPERATING TEMPERATURE
RANGE
−40
+85
−40
+85
Rev. C | Page 8 of 40
AD8129/AD8130
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive
depends upon the particular application. The power due to
load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Rating
Supply Voltage
Power Dissipation
26.4 V
Refer to Figure 4
−VS − 0.3 V to +VS + 0.3 V
Input Voltage (Any Input)
Differential Input Voltage (AD8129)
VS ≥ 11.5 V
Differential Input Voltage (AD8129)
VS < 11.5 V
Differential Input Voltage (AD8130)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
0.5 V
6.2 V
8.4 V
−65°C to +150°C
300°C
150°C
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and MSOP (θJA = 142°C/W) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
1.75
1.50
1.25
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
1.00
SOIC
Table 5. Thermal Resistance
Package Type
0.75
MSOP
θJA
Unit
°C/W
°C/W
0.50
8-Lead SOIC/4-Layer
8-Lead MSOP/4-Layer
121
142
0.25
0
Maximum Power Dissipation
–40–30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110120
AMBIENT TEMPERATURE (°C)
The maximum safe power dissipation in the AD8129/AD8130
packages is limited by the associated rise in junction temp-
erature (TJ) on the die. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8129/AD8130.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in the silicon devices, potentially
causing failure.
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 9 of 40
AD8129/AD8130
TYPICAL PERFORMANCE CHARACTERISTICS
AD8130 FREQUENCY RESPONSE CHARACTERISTICS
G = +1, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.
3
6
V
= 0.3V p-p
V
= ±5V
OUT
C
= 20pF
S
L
V
= ±2.5V
2
S
5
4
3
2
1
1
0
C
= 10pF
= 5pF
L
V
= ±5V
S
C
L
–1
–2
V
= ±12V
S
–3
–4
–5
0
–1
C
= 2pF
L
–2
–3
–6
–7
–4
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
400
Figure 5. AD8130 Frequency Response vs. Supply, VOUT = 0.3 V p-p
Figure 8. AD8130 Frequency Response vs. Load Capacitance
3
0.7
V
= 1V p-p
V
= ±2.5V
R = 1kΩ
L
OUT
S
2
1
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= ±5V
S
V
= ±2.5V
S
0
V
= ±5V
–1
–2
–3
–4
–5
–6
–7
S
V
= ±12V
S
–0.1
–0.2
–0.3
V
= ±12V
S
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
300
Figure 9. AD8130 Fine Scale Response vs. Supply, RL = 1 kΩ
Figure 6. AD8130 Frequency Response vs. Supply, VOUT = 1 V p-p
3
0.5
0.4
0.3
0.2
R
= 150Ω
V
= 2V p-p
L
OUT
2
V
= ±5V
S
V
= ±2.5V
S
1
0
V
= ±2.5V
= ±5V
S
V
S
0.1
–1
–2
V
= ±12V
S
0
–0.1
–3
–4
–5
–6
–7
–0.2
–0.3
–0.4
–0.5
V
= ±12V
S
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
300
Figure 7. AD8130 Frequency Response vs. Supply, VOUT = 2 V p-p
Figure 10. AD8130 Fine Scale Response vs. Supply, RL = 150 Ω
Rev. C | Page 10 of 40
AD8129/AD8130
3
2
3
2
G = +2
= ±5V
R
= 150Ω
R
= R = 1kΩ
L
F
G
V
S
V
= ±2.5V
S
R
= R = 750Ω
G
F
1
1
0
0
–1
–2
–1
–2
R
= R = 499Ω
V
= ±5V
F
G
S
V
= ±12V
S
–3
–4
–5
R
= R = 250Ω
–3
–4
–5
–6
–7
F
G
–6
–7
1
10
FREQUENCY (MHz)
100
400
1
10
FREQUENCY (MHz)
100
300
Figure 11. AD8130 Frequency Response vs. Supply, RL = 150 Ω
Figure 14. AD8130 Frequency Response for Various RF/RG
3
0.3
G = +2
G = +2
= 1kΩ
V
= 0.3V p-p
R
V
= ±2.5V
OUT
L
S
2
1
0.2
0.1
V
= ±2.5V
S
0
0
V
= ±5V
S
–1
–0.1
V
= ±12V
S
–2
–3
–4
–5
–6
–7
–0.2
–0.3
V
= ±5V
S
–0.4
–0.5
–0.6
–0.7
V
= ±12V
S
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
Figure 12. AD8130 Frequency Response vs. Supply,
G = +2, VOUT = 0.3 V p-p
Figure 15. AD8130 Fine Scale Response vs. Supply,
G = +2, RL = 1 kΩ
0.3
0.2
0.1
0
3
2
G = +2
G = +2
= 2V p-p
R
= 150Ω
V
L
OUT
V
= ±2.5V
S
1
V
= ±2.5V
S
0
–0.1
–0.2
V
= ±5V
–1
–2
–3
–4
–5
–6
–7
S
V
= ±5V
S
V
= ±12V
S
–0.3
–0.4
–0.5
–0.6
–0.7
V
= ±12V
S
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
300
Figure 16. AD8130 Fine Scale Response vs. Supply,
G = +2, RL = 150 Ω
Figure 13. AD8130 Frequency Response vs. Supply,
G = +2, VOUT = 2 V p-p
Rev. C | Page 11 of 40
AD8129/AD8130
3
3
2
G = +2
R
= 150Ω
L
R
= 150Ω
L
2
1
V
= ±2.5V
S
1
0
V
= ±5V, ±12V
G = +5
S
V
= ±5V
S
0
–1
–2
–1
–2
–3
–4
–5
G = +10
V
= ±12V
S
V
= ±2.5V
S
–3
–4
–5
V
= ±5V, ±12V
S
–6
–7
–6
–7
1
10
FREQUENCY (MHz)
100
300
0.1
1
10
100
FREQUENCY (MHz)
Figure 17. AD8130 Frequency Response vs. Supply,
G = +2, RL = 150 Ω
Figure 20. AD8130 Frequency Response vs. Supply,
G = +5, G = +10, RL = 150 Ω
0.3
0.2
12
6
V
= 2V p-p
0dB = 1V rms
OUT
V
= ±2.5V
V
= ±5V
S
S
0.1
0
0
–6
–0.1
–0.2
–0.3
–12
–18
–24
–30
–36
–42
V
= ±12V
S
V
S
= ±2.5V
S
V
= ±5V, ±12V
–0.4
–0.5
G = +10
G = +5
–0.6
–0.7
V
= ±5V
S
–48
0.1
1
FREQUENCY (MHz)
10
30
10
100
400
FREQUENCY (MHz)
Figure 18. AD8130 Fine Scale Response vs. Supply,
G = +5, G = +10, VOUT = 2 V p-p
Figure 21. AD8130 Frequency Response for Various Output Levels
3
2
1
V
= 2V p-p
OUT
1
8
TEK P6245
FET PROBE
50Ω
6
0
4
5
R
C
L
–1
L
–2
–3
–4
–5
–6
–7
V
= ±12V
R
R
F
S
G = +5
G
V
= ±5V, ±12V
S
G
R
R
G
F
V
= ±2.5V
S
1
2
5
0Ω
499Ω
8.06kΩ
4.99kΩ
–
499Ω
2kΩ
549Ω
G = +10
10
10
0.1
1
100
FREQUENCY (MHz)
Figure 19. AD8130 Frequency Response vs. Supply,
G = +5, G = +10, VOUT = 2 V p-p
Figure 22. AD8130 Basic Frequency Response Test Circuit
Rev. C | Page 12 of 40
AD8129/AD8130
AD8129 FREQUENCY RESPONSE CHARACTERISTICS
G = +10, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.
3
4
V
= 0.3V p-p
C
= 20pF
V
= ±5V
OUT
L
S
2
3
V
= ±2.5V
S
V = ±5V
S
C
= 10pF
L
1
2
0
1
–1
–2
0
V
= ±12V
S
C
= 5pF
L
–1
C
= 2pF
L
–3
–4
–5
–6
–7
–2
–3
–4
–5
–6
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
300
Figure 23. AD8129 Frequency Response vs. Supply, VOUT = 0.3 V p-p
Figure 26. AD8129 Frequency Response vs. Load Capacitance
3
0.5
V
= ±2.5V
V
= 1V p-p
S
OUT
R
= 1kΩ
V
= ±5V
L
S
2
0.4
0.3
V
= ±2.5V
S
1
0
V
= ±5V
S
0.2
V
= ±12V
0.1
–1
–2
S
0
V
= ±12V
S
–3
–4
–5
–0.1
–0.2
–0.3
–0.4
–0.5
–6
–7
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
300
Figure 24. AD8129 Frequency Response vs. Supply, VOUT = 1 V p-p
Figure 27. AD8129 Fine Scale Response vs. Supply, RL = 1 kΩ
3
0.3
V
= 2V p-p
R
= 150Ω
OUT
L
V
= ±2.5V
S
V
= ±2.5V
0.2
0.1
2
S
1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–1
–2
V
= ±5V
S
V
= ±5V
S
V
= ±12V
S
V
= ±12V
S
–3
–4
–5
–6
–7
1
10
FREQUENCY (MHz)
100
300
1
10
FREQUENCY (MHz)
100
300
Figure 25. AD8129 Frequency Response vs. Supply, VOUT = 2 V p-p
Figure 28. AD8129 Fine Scale Response vs. Supply, RL = 150 Ω
Rev. C | Page 13 of 40
AD8129/AD8130
0.8
0.6
0.4
0.2
0
3
G = +10
= ±5V
R
= 150Ω
2k
Ω
/221
Ω
L
V
S
2
1
909
Ω
/100
Ω
V
= ±2.5V
S
499
Ω
/54.9
Ω
0
SOIC
–1
–2
–3
–4
–5
–6
–7
V
= ±5V
499
Ω/54.9
Ω
S
–0.2
0.2
0
909
Ω
/100Ω
V
= ±12V
S
μ
SOIC
–0.2
–0.4
–0.6
2kΩ/221Ω
10
100
FREQUENCY (MHz)
300
1
10
FREQUENCY (MHz)
100
300
Figure 29. AD8129 Frequency Response vs. Supply, RL = 150 Ω
Figure 32. AD8129 Fine Scale Response vs. SOIC and MSOP
for Various RF/RG
0.2
3
G = +20
G = +20
V
= 0.3V p-p
R = 1kΩ
OUT
L
0.1
0
2
1
V
= ±5V
S
V
= ±5V, ±12V
S
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
–1
–2
–3
–4
–5
–6
–7
V
= ±12V
S
V
= ±2.5V
S
V
= ±2.5V
S
1
10
30
1
10
FREQUENCY (MHz)
100
300
FREQUENCY (MHz)
Figure 30. AD8129 Frequency Response vs. Supply,
G = +20, VOUT = 0.3 V p-p
Figure 33. AD8129 Fine Scale Response vs. Supply
0.3
0.2
3
2
G = +20
G = +20
R
= 150Ω
V
= 2V p-p
L
OUT
0.1
1
V
= ±5V, ±12V
S
V
= ±5V, ±12V
S
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–1
–2
–3
–4
–5
–6
–7
V
= ±2.5V
S
V
= ±2.5V
S
0.1
1
10
30
1
10
FREQUENCY (MHz)
100
300
FREQUENCY (MHz)
Figure 31. AD8129 Frequency Response vs. Supply,
G = +20, VOUT = 2 V p-p
Figure 34. AD8129 Fine Scale Response vs. Supply
Rev. C | Page 14 of 40
AD8129/AD8130
3
2
3
2
G = +20
= 150
R
= 150Ω
L
R
Ω
L
1
1
0
0
V
= ±5V, ±12V
S
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
–7
G = +100
G = +50
V
= ±2.5V
S
V
= ±5V
S
V
= ±2.5V
S
V
±12V
S =
0.1
1
10
50
1
10
FREQUENCY (MHz)
100
300
FREQUENCY (MHz)
Figure 38. AD8129 Frequency Response vs. Supply,
G = +50, G = +100, RL = 150 Ω
Figure 35. AD8129 Frequency Response vs. Supply,
G = +20, RL = 150 Ω
12
0.2
0dB = 1V rms
V
= 2V p-p
OUT
6
0
V
= ±12V
0.1
0
S
–6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
G = +100
G = +50
–12
–18
–24
–30
–36
–42
–48
V
= ±2.5V
S
V
S
= ±5V
V
= ±12V
S
V
= ±5V
S
10
100
400
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. AD8129 Fine Scale Response vs. Supply,
G = +50, G = +100, VOUT = 2 V p-p
Figure 39. AD8129 Frequency Response for Various Output Levels
3
2
V
= 2V p-p
OUT
1
1
8
TEK P6245
FET PROBE
0
50Ω
–1
–2
–3
–4
–5
–6
–7
G = +50
6
G = +100
4
5
R
C
L
L
V
= ±2.5V
S
R
R
F
G
V
= ±5V
S
R
R
G
G
F
V
±12V
S =
10
20
50
2kΩ
2kΩ
2kΩ
2kΩ
221Ω
105Ω
41.2Ω
20Ω
0.1
1
10
50
100
FREQUENCY (MHz)
Figure 37. AD8129 Frequency Response vs. Supply,
G = +50, G = +100, VOUT = 2 V p-p
Figure 40. AD8129 Basic Frequency Response Test Circuit
Rev. C | Page 15 of 40
AD8129/AD8130
AD8130 HARMONIC DISTORTION CHARACTERISTICS
RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.
–60
–51
–57
–63
–69
–75
–81
–87
–93
–99
V
= 1V p-p
V
= 1V p-p
OUT
OUT
G = +1
= ±5V
V
S
G = +1
–66
–72
–78
–84
–90
V
= ±12V
S
V
= ±12V
S
V
= ±5V
S
G = +1
V
V
= ±12V
S
G = +1
V
= ±5V
= ±12V
S
S
G = +2
G = +2
1
10
FREQUENCY (MHz)
40
1
10
40
FREQUENCY (MHz)
Figure 41. AD8130 Second Harmonic Distortion vs. Frequency
Figure 44. AD8130 Third Harmonic Distortion vs. Frequency
–54
–45
–51
–57
–63
–69
–75
–81
–87
–93
V
= 2V p-p
V
= 2V p-p
OUT
OUT
G = +2, V = ±12V
S
G = +2, V = ±5V
S
G = +1
= ±5V
–60
–66
–72
–78
–84
V
S
V
= ±12V
S
V
= ±5V
S
G = +1
V
= ±12V
S
G = +1
V = ±12V
S
G = +2
V
= ±5V
G = +2
S
1
10
FREQUENCY (MHz)
40
1
10
40
FREQUENCY (MHz)
Figure 42. AD8130 Second Harmonic Distortion vs. Frequency
Figure 45. AD8130 Third Harmonic Distortion vs. Frequency
–46
–52
–58
–64
–70
–76
–82
–88
–94
–55
fC = 5MHz
f = 5MHz
C
V
= ±12V
V
= ±12V
= ±5V
S
S
V
= ±5V
S
–61
–67
–73
–79
–85
–91
V
S
G = +1
G = +1
G = +2
V
= ±12V
S
V
= ±12V
S
G = +2
V
= ±5V
S
V
= ±5V
S
0.5
1
10
0.5
1
10
V
(V p-p)
V
(V p-p)
OUT
OUT
Figure 43. AD8130 Second Harmonic Distortion vs. Output Voltage
Figure 46. AD8130 Third Harmonic Distortion vs. Output Voltage
Rev. C | Page 16 of 40
AD8129/AD8130
–43
–49
–55
–61
–67
–73
–79
–46
–52
–58
–64
–70
–76
–82
–88
–94
V
= ±2.5V
V = ±2.5V
S
fC = 5MHz
S
G = +2, HD3
G = +1, HD3
G = +1
V
= 2V p-p
OUT
G = +1, HD2
G = +2, HD2
G = +2
G = +2, HD2
G = +2, HD3
G = +1
V
= 1V p-p
OUT
G = +2
1
10
FREQUENCY (MHz)
40
0
0.5
1.0
1.5
(V p-p)
2.0
2.5
3.0
V
OUT
Figure 49. AD8130 Harmonic Distortion vs. Output Voltage
Figure 47. AD8130 Second Harmonic Distortion vs. Frequency
–42
V
= ±2.5V
S
–48
–54
–60
–66
–72
–78
–84
–90
–96
V
= 2V p-p
OUT
G = +2
G = +1
G = +1
G = +2
V
= 1V p-p
OUT
1
10
FREQUENCY (MHz)
40
Figure 48. AD8130 Third Harmonic Distortion vs. Frequency
Rev. C | Page 17 of 40
AD8129/AD8130
AD8129 HARMONIC DISTORTION CHARACTERISTICS
RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.
–51
–54
–60
–66
–72
–78
–84
–90
–96
V
= 1V p-p
V
= 1V p-p
OUT
OUT
G = +10,
= ±5V
V
S
–57
–63
–69
–75
–81
–87
G = +10,
= ±12V
V
S
G = +10,
= ±12V
V
S
G = +10,
= ±5V
G = +20,
= ±5V
V
S
V
S
G = +20,
= ±12V
V
S
G = +20,
= ±12V
G = +20,
= ±5V
V
S
V
S
1
10
FREQUENCY (MHz)
40
1
10
FREQUENCY (MHz)
40
Figure 50. AD8129 Second Harmonic Distortion vs. Frequency
Figure 53. AD8129 Third Harmonic Distortion vs. Frequency
–42
–45
–51
–57
–63
–69
–75
–81
–87
V
= 2V p-p
V
= 2V p-p
OUT
OUT
G = +10,
= ±5V
V
S
–48
–54
–60
–66
–72
–78
–84
G = +10
G = +20
G = +10,
= ±12V
V
S
G = +10,
= ±12V
V
S
G = +10,
= ±12V
V
G = +20,
= ±12V
S
V
S
G = +20,
= ±5V
G = +10,
= ±5V
G = +10,
V
S
V
S
V
= ±5V
S
G = +20,
G = +20,
V = ±12V
S
V
= ±5V
S
1
10
FREQUENCY (MHz)
40
1
10
40
FREQUENCY (MHz)
Figure 54. AD8129 Third Harmonic Distortion vs. Frequency
Figure 51. AD8129 Second Harmonic Distortion vs. Frequency
–48
–50
fC = 5MHz
fC = 5MHz
G = +10,
= ±12V
–54
V
S
–56
G = +10,
= ±5V
–60
–66
–72
–78
–84
–90
–96
V
S
–62
G = +10,
V
= ±12V
S
–68
–74
–80
–86
G = +10,
= ±5V
V
S
G = +20,
= ±5V
V
G = +20,
= ±5V
S
V
S
G = +20,
= ±12V
V
G = +20,
= ±12V
S
V
S
0.5
1
10
0.5
1
10
V
(V p-p)
OUT
V
(V p-p)
OUT
Figure 55. AD8129 Third Harmonic Distortion vs. Output Voltage
Figure 52. AD8129 Second Harmonic Distortion vs. Output Voltage
Rev. C | Page 18 of 40
AD8129/AD8130
–44
–50
–56
–62
–68
–74
–80
–39
–45
–51
–57
–63
–69
–75
–81
–87
V
= ±2.5V
S
G = +1
V
V
= 2V p-p
OUT
= ±5V
V
= 2V p-p
OUT
S
R
= 1kΩ
L
f
= 5MHz
C
G = +20
V
= 1V p-p
OUT
HD2
HD3
0
G = +10
1
10
FREQUENCY (MHz)
40
–5
–4
–3
–2
–1
1
2
3
4
V
(V)
CM
Figure 56. AD8129 Second Harmonic Distortion vs. Frequency
Figure 59. AD8130 Harmonic Distortion vs. Common-Mode Voltage
–42
–61
V
= ±2.5V
G = +1
S
V
= 1V p-p
HD2
OUT
f
= 5MHz
C
–48
–54
–60
–66
–72
–78
–84
–90
–67
–73
–79
–85
–91
–97
V
= 2V p-p
OUT
V
= ±2.5V
S
HD2
= ±5V, ±12V
V
S
G = +20
V
= 1V p-p
OUT
HD3
= ±5V
V
S
G = +10
HD3
= ±12V
V
S
HD3
= ±2.5V
V
S
1
10
FREQUENCY (MHz)
40
100
R
(Ω)
L
Figure 60. AD8130 Harmonic Distortion vs. Load Resistance
Figure 57. AD8129 Third Harmonic Distortion vs. Frequency
–50
–50
G = +1
= 5MHz
V
= ±2.5V
S
V
= 2V p-p
OUT
f
C
fC = 5MHz
–56
–62
–68
–74
–80
–86
–56
–62
–68
–74
–80
–86
HD2
= ±2.5V
V
S
G = +20
HD2
G = +20
HD3
HD2
= ±5V, ±12V
G = +10
HD2
V
S
G = +10
HD3
HD3
= ±2.5V
V
S
HD3
= ±5V, ±12V
V
S
0
0.5
1.0
1.5
(V p-p)
2.0
2.5
3.0
100
V
R (Ω)
L
OUT
Figure 58. AD8129 Harmonic Distortion vs. Output Voltage
Figure 61. AD8130 Harmonic Distortion vs. Load Resistance
Rev. C | Page 19 of 40
AD8129/AD8130
–36
G = +10
V
V
R
= 2V p-p
–42
–48
–54
–60
–66
–72
–78
OUT
= ±5V
S
V
CM
= 1kΩ
L
fC = 5MHz
200Ω
R
L
1:2
R
L
C
L
HD2
R
R
G
F
HD3
1
G
R
R
G
F
®
MINI-CIRCUITS
# T4-6T, fC ≤ 10MHz
# TC4-1W, fC > 10MHz
:
1
2
0Ω
–
499Ω
2kΩ
2kΩ
499Ω
221Ω
105Ω
–5
–4
–3
–2
–1
0
2
3
4
20
V
(V)
CM
Figure 65. AD8129/AD8130 Basic Distortion Test Circuit,
VCM = 0 V, Unless Otherwise Noted
Figure 62. AD8129 Harmonic Distortion vs. Common-Mode Voltage
100
10
–48
G = +10
V
= 1V p-p
OUT
fC = 5MHz
–54
–60
–68
–72
–78
–84
–90
V
V
V
= ±2.5V
= ±12V
= ±5V
S
S
S
HD2
V
= ±12V
S
V
= ±5V
S
1.0
0.1
HD3
V
= ±2.5V
S
10
100
1k
10k
100k
1M
10M
100
R
(Ω)
FREQUENCY (Hz)
L
Figure 66. AD8129/AD8130 Input Current Noise vs. Frequency
Figure 63. AD8129 Harmonic Distortion vs. Load Resistance
100
–44
G = +10
V
= 2V p-p
OUT
fC = 5MHz
V
V
V
= ±2.5V
S
S
S
–50
–56
–62
–68
–74
–80
= ±12V
= ±5V
AD8130
10
V
= ±2.5V
S
AD8129
V
= ±12V
HD3
S
V
= ±5V
S
1
10
100
100
1k
10k
100k
1M
10M
R
(Ω)
L
FREQUENCY (Hz)
Figure 67. AD8129/AD8130 Input Voltage Noise vs. Frequency
Figure 64. AD8129 Harmonic Distortion vs. Load Resistance
Rev. C | Page 20 of 40
AD8129/AD8130
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
V
= ±2.5V
–80
S
V
= ±2.5V
–90
S
–90
–100
–110
–120
–100
–110
–120
V
= ±5V, ±12V
1M
S
V = ±5V, ±12V
S
ꢀ
ꢀ
10k
100k
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 68. AD8130 Common-Mode Rejection vs. Frequency
Figure 71. AD8139 Common-Mode Rejection vs. Frequency
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= ±12V
S
V
= ±12V
S
V
= ±2.5V
V
= ±5V
S
S
V
= ±2.5V
S
V
= ±5V
S
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 69. AD8130 Positive Power Supply Rejection vs. Frequency
Figure 72. AD8129 Positive Power Supply Rejection vs. Frequency
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
V
= ±2.5V
S
–70
–80
V
= ±5V
100k
S
–80
–90
V
= ±12V
10k
S
–90
V
= ±5V
S
V
= ±12V
S
V
= ±2.5V
1M
S
–100
–100
1k
10k
100k
1M
10M
100M
1k
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 70. AD8130 Negative Power Supply Rejection vs. Frequency
Figure 73. AD8129 Negative Power Supply Rejection vs. Frequency
Rev. C | Page 21 of 40
AD8129/AD8130
80
70
60
50
40
100
10
V
= ±5V
S
180
135
90
45
0
GAIN
1
AD8130, G = +1
30
PHASE
+
100m
10m
1m
–
VOUT
20
10
+
–
2pF
1k
Ω
100
Ω
1kΩ
0
VIN
φ
= 58°
M
AD8129, G = +10
100k
–10
1k
10k
100k
1M
10M
100M 300M
1k
10k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 74. AD8130 Open-Loop Gain and Phase vs. Frequency
Figure 76. Closed-Loop Output Impedance vs. Frequency
90
80
70
60
50
40
30
20
10
0
180
GAIN
135
90
45
0
PHASE
= 56°
VOUT
2pF
1M
1k
Ω
100
Ω
1k
Ω
φ
M
VIN
1k
10k
100k
10M
100M
300M
FREQUENCY (Hz)
Figure 75. AD8129 Open-Loop Gain and Phase vs. Frequency
Rev. C | Page 22 of 40
AD8129/AD8130
AD8130 TRANSIENT RESPONSE CHARACTERISTICS
G = +1, RL = 1 kΩ, CL = 2 pF, VS = 5 V, TA = 25°C, unless otherwise noted.
V
= ±2.5V
S
V
= 0.2V p-p
OUT
V
V
= 1V p-p
OUT
= ±2.5V
V = ±5V
S
S
V
= ±12V
S
50mV
5.00ns
250mV
5.00ns
Figure 77. AD8130 Transient Response, VS = 2.5 V, VOUT = 1 V p-p
Figure 80. AD8130 Transient Response vs. Supply, VOUT = 0.2 V p-p
V
V
= 1V p-p
V
C
= 1V p-p
OUT
= ±5V
OUT
= 5pF
V
= ±2.5V
S
V
= ±5V
S
L
S
V
= ±12V
S
250mV
5.00ns
250mV
5.00ns
Figure 78. AD8130 Transient Response, VS = 5 V, VOUT = 1 V p-p
Figure 81. AD8130 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF
V
V
= 1V p-p
OUT
= ±12V
V
= 2V p-p
OUT
C = 5pF
L
V
= ±2.5V
S
S
V
= ±5V
S
V
= ±12V
S
250mV
5.00ns
500mV
5.00ns
Figure 82. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF
Figure 79. AD8130 Transient Response, VS = 12 V, VOUT = 1 V p-p
Rev. C | Page 23 of 40
AD8129/AD8130
V
= 1V p-p
C
= 10pF
V
= 0.2 V p-p
OUT
G = +2
L
OUT
C
= 5pF
L
V
= ±5V, C = 10pF
L
S
C
= 2pF
L
V
= ±5V, C = 2pF
L
S
50mV
10.00ns
250mV
5.00ns
Figure 83. AD8130 Transient Response vs. Load Capacitance,
VOUT = 0.2 V p-p
Figure 86. AD8130 Transient Response vs. Load Capacitance,
VOUT = 1 V p-p, G = +2
V
= 2V p-p
OUT
G = +2
V
= ±5V
S
2V p-p
1V p-p
V
= ±12V
S
0.5V p-p
500mV
5.00ns
5.00ns
500mV
Figure 84. AD8130 Transient Response vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
Figure 87. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, G = +2
V
= 8V p-p
G = +2
OUT
V
= ±5V
S
4V p-p
2V p-p
C
= 10pF
L
C
= 2pF
L
1V p-p
1.00V
5.00ns
5.00ns
2.00V
Figure 85. AD8130 Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
Figure 88. AD8130 Transient Response vs. Load Capacitance,
VOUT = 8 V p-p
Rev. C | Page 24 of 40
AD8129/AD8130
G = +5
V
= ±5V
S
C
= 10pF
L
4V p-p
2V p-p
V
IN
V
OUT
1V p-p
1.00V
10.0ns
5.00ns
1.00V
Figure 89. AD8130 Transient Response with +3 V Common-Mode Input
Figure 92. AD8130 Transient Response vs. Output Amplitude
V
= 8V p-p
G = +5
OUT
V
= ±5V
S
C
= 10pF
L
V
OUT
V
IN
2.00V
10.0ns
5.00ns
1.00V
Figure 90. AD8130 Transient Response with −3 V Common-Mode Input
Figure 93. AD8130 Transient Response, VOUT = 8 V p-p, G = +5, VS = 5 V
G = +2
S
G = +5
V
= 10V p-p
V
= 20V p-p
OUT
OUT
V
= ±12V
V
= ±12V
= 10pF
S
C
L
5.00ns
2.50V
10.0ns
5.00V
Figure 94. AD8130 Transient Response, VOUT = 20 V p-p, G = +5, VS = 12 V
Figure 91. AD8130 Transient Response, VOUT = 10 V p-p, G = +2, VS = 12 V
Rev. C | Page 25 of 40
AD8129/AD8130
AD8129 TRANSIENT RESPONSE CHARACTERISTICS
G = +10, RF = 2 kΩ, RG = 221 Ω, RL = 1 kΩ, CL = 1 pF, VS = 5 V, TA = 25°C, unless otherwise noted.
V
= ±2.5V
V = ±5V
S
S
V
= 0.4V p-p
V
= 1V p-p
OUT
OUT
V
= ±2.5V
S
V
= ±12V
S
100mV
5.00ns
250mV
5.00ns
Figure 95. AD8129 Transient Response, VS = 2.5 V, VOUT = 1 V p-p
Figure 98. AD8129 Transient Response vs. Supply, VOUT = 0.4 V p-p
V
C
= 1V p-p
V
= ±5V
OUT
= 5pF
S
V
= 1V p-p
OUT
V
= ±5V
S
L
V
= ±2.5V
S
V
= ±12V
S
5.00ns
250mV
5.00ns
250mV
Figure 99. AD8129 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF
Figure 96. AD8129 Transient Response, VS = 5 V, VOUT = 1 V p-p
V
C
= 2V p-p
OUT
= 5pF
V
= ±2.5V
V
= ±12V
V
= 1V p-p
OUT
S
S
L
V
= ±5V
S
V
= ±12V
S
5.00ns
250mV
250mV
5.00ns
Figure 97. AD8129 Transient Response, VS = 12 V, VOUT = 1 V p-p
Figure 100. AD8129 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF
Rev. C | Page 26 of 40
AD8129/AD8130
G = +20
L
V
= 0.4V p-p
C
= 5pF
OUT
V
= 1V p-p
L
OUT
C
= 20pF
C
= 10pF
L
C
= 2pF
L
5.00ns
100mV
250mV
5.00ns
Figure 101 Transient Response vs. Load Capacitance, VOUT = 0.4 V p-p
Figure 104. AD8129 Transient Response, VOUT = 1 V p-p, VS = 2.5 V to 12 V
G = +20
V
= 2V p-p
OUT
C
= 20pF
V
= 2V p-p
L
O
V
= 1V p-p
O
V
= 0.5V p-p
O
5.00ns
500mV
5.00ns
500mV
Figure 102. Transient Response vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
Figure 105. AD8129 Transient Response, VOUT = 2 V p-p, VS = 5 V
G = +20
V
= 8V p-p
OUT
C
= 20pF
L
V
= 4V p-p
O
V
= 2V p-p
O
V
= 1V p-p
O
5.00ns
1.00V
2.00V
5.00ns
Figure 106. AD8129 Transient Response, VOUT = 8 V p-p, VS = 5 V
Figure 103. Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
Rev. C | Page 27 of 40
AD8129/AD8130
G = +50
V
C
= ±5V
= 20pF
S
V
IN
4V p-p
L
2V p-p
V
OUT
1V p-p
1.00V
5.00ns
12.5ns
1.00V
Figure 107. AD8129 Transient Response
with +3.5 V Common-Mode Input
Figure 110. AD8129 Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
V
= 8V p-p
G = +50
OUT
V
= ±5V
S
C
= 20pF
L
V
OUT
V
IN
12.5ns
2.00V
Figure 111. AD8129 Transient Response, VOUT = 8 V p-p, G = +50, VS = 5 V
Figure 108. AD8129 Transient Response
with −3.5 V Common-Mode Input
G = +20
V
= 20V p-p
G = +50
= ±12V
OUT
V
= 10V p-p
OUT
V
= ±12V
= 20pF
V
S
S
C
C
= 10pF
L
L
2.50V
5.00ns
12.5ns
5.00V
Figure 109. AD8129 Transient Response, VOUT = 10 V p-p, G = +20
Figure 112. AD8129 Transient Response, VOUT = 20 V p-p, G = +50, VS = 12 V
Rev. C | Page 28 of 40
AD8129/AD8130
23
20
17
14
11
G = +1
G = +1
= ±5V
V
= ±5V
V
S
S
R
= 1kΩ
L
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
–5
–4
–3
–2
–1
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT (V)
Figure 116. AD8130 Gain Nonlinearity, VOUT = 2 V p-p
Figure 113. AD8130 DC Power Supply Current vs. Differential Input Voltage
37
G = +1
G = +1
V
= ±5V
S
V
= ±10V
S
R
= 1kΩ
L
31
25
19
13
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT (V)
Figure 114. AD8129 DC Power Supply Current vs. Differential Input Voltage
Figure 117. AD8130 Gain Nonlinearity, VOUT = 5 V p-p
4
3
3.0
V
= ±5V
S
AD8130
2.0
V
= 100mV AC @ 1kHz
OUT
2
1.0
0
1
AD8129
AD8129
0
–1
–2
–3
–4
–1.0
–2.0
–3.0
AD8130
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50 –35 –20
–5
10
25
40
55
70
85
100
DIFFERENTIAL INPUT (V)
TEMPERATURE(°C)
Figure 118. AD8130 Differential Input Clipping Level
Figure 115. AD8129/AD8130 Input Differential Voltage Range vs.
Temperature, 1% Gain Compression
Rev. C | Page 29 of 40
AD8129/AD8130
15
14
13
12
11
G = +10
V
= ±5V
S
R
= 1kΩ
L
10
9
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
0
5
10
15
20
25
30
OUTPUT VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
Figure 122. Quiescent Power Supply Current vs. Total Supply Voltage
Figure 119. AD8129 Gain Nonlinearity, VOUT = 2 V p-p
17
16
15
G = +10
V
= ±12V
S
R
= 1kΩ
L
V
= ±12
S
14
13
12
11
10
9
V
= ±5
S
V
= ±2.5
S
8
7
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50 –35 –20 –5 10 25 40 55 70 85 100
115
125
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 120. AD8129 Gain Nonlinearity, VOUT = 10 V p-p
Figure 123. Quiescent Power Supply Current vs. Temperature
8
6
4
2
0
40
0.60
0.45
0.30
0.15
V
= ±10V
S
I
B
30
20
10
I
OS
–2
–4
–6
–8
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
–50 –35 –20
–5
10
25
40
55
70
85
100
DIFFERENTIAL INPUT (V)
TEMPERATURE (°C)
Figure 121. AD8129 Differential Input Clipping Level
Figure 124. Input Bias Current and Input Offset Current vs. Temperature
Rev. C | Page 30 of 40
AD8129/AD8130
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
4.0
3.5
3.0
2.0
1.5
1.0
V
= 5V
S
AD8130
AD8129
= 5V
SOURCING
+100°C
V
S
–40°C
+25°C
V
= 100mV
OUT
AC AT 1kHz
SINKING
AD8129
AD8130
70
V
= 100mV
OUT
AC AT 1kHz
–50 –35 –20
–5
10
25
40
55
85
100
0
5
10
15
20
25
30 35
40
40
40
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 125. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
Figure 128. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
4.00
4.0
3.5
V
= ±5V
S
3.75
AD8130
3.50
3.25
= ±5V
V
AD8129
S
3.00
2.75
3.0
+100°C
–40°C
+25°C
V
= 100mV
OUT
AC AT 1kHz
–3.00
–3.25
–3.50
–3.75
–4.00
–3.0
–3.5
–4.0
AD8129
AD8130
V
= 100mV
AC AT 1kHz
OUT
–50 –35 –20
–5
10
25
40
55
70
85
100
0
5
10
15
20
25
30 35
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 126. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
Figure 129. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
11.0
11
10
V
= ±12V
S
10.5
AD8130
10.0
V
= ±12V
S
AD8129
9.5
9.0
9
V
= 100mV
+100°C
–40°C
+25°C
OUT
AC AT 1kHz
8.5
–9.0
–9.5
–10.0
–10.5
–11.0
–9
AD8129
40
–10
–11
AD8130
70
–50 –35 –20
–5
10
25
55
85
100
0
5
10
15
20
25
30
35
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
Figure 127. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
Figure 130. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
Rev. C | Page 31 of 40
AD8129/AD8130
THEORY OF OPERATION
The AD8129/AD8130 use an architecture called active feedback,
which differs from that of conventional op amps. The most
obvious differentiating feature is the presence of two separate
pairs of differential inputs compared with a conventional op
amp’s single pair. Typically, for the active feedback architecture,
one of these input pairs is driven by a differential input signal,
while the other is used for the feedback. This active stage in the
feedback path is where the term active feedback is derived.
Therefore, the input dynamic ranges are limited to about
2.5 V for the AD8130 and 0.5 V for the AD8129 (see the
AD8129/AD8130 Specifications section for more detail). For
this and other reasons, it is not recommended to reverse the
input and feedback stages of the AD8129/AD8130, even though
some apparently normal functionality may be observed under
some conditions. A few simple circuits can illustrate how the
active feedback architecture of the AD8129/AD8130 operates.
The active feedback architecture offers several advantages over a
conventional op amp in many types of applications. Among these
are excellent common-mode rejection, wide input common-mode
range, and a pair of inputs that are high impedance and completely
balanced in a typical application. In addition, while an external
feedback network establishes the gain response as in a conventional
op amp, its separate path makes it completely independent of
the signal input. This eliminates any interaction between the
feedback and input circuits, which traditionally causes problems
with CMRR in conventional differential-input op amp circuits.
OP AMP CONFIGURATION
If only one of the input stages of the AD8129/AD8130 is used, it
functions very much like a conventional op amp (see Figure 131).
Classical inverting and noninverting op amps circuits can be
created, and the basic governing equations are the same as for a
conventional op amp. The unused input pins form the second
input and should be shorted together and tied to ground or a
midsupply voltage when they are not used.
+V
Another advantage is the ability to change the polarity of the
gain merely by switching the differential inputs. A high input-
impedance inverting amplifier can be made. Besides a high
input impedance, a unity-gain inverter with the AD8130 has
a noise gain of unity. This produces lower output noise and
higher bandwidth than op amps that have noise gain equal
to 2 for a unity-gain inverter.
10μF
0.1μF
3
7
1
8
+
+
PD +V
S
6
V
OUT
4
5
V
IN
–V
S
2
R
F
R
G
The two differential input stages of the AD8129/AD8130 are
each transconductance stages that are well matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensation
capacitor is in the summing circuit.
10μF
0.1μF
–V
NOTES
1. THIS CIRCUIT IS PROVIDED TO DEMONSTRATE
DEVICE OPERATION. IT IS NOT RECOMMENDED
TO USE THIS CIRCUIT IN PLACE OF AN OP AMP.
Figure 131. With Both Inputs Grounded, the Feedback Stage Functions like
an Op Amp: VOUT = VIN (1 + RF/RG).
When the feedback path is closed around the part, the output
drives the feedback input to the voltage that causes the internal
currents to sum to 0. This occurs when the two differential
inputs are equal and opposite; that is, their algebraic sum is 0.
With the unused pair of inputs shorted, there is no differential
voltage between them. This dictates that the differential input
voltage of the used inputs is also 0 for closed-loop applications.
Because this is the governing principle of conventional op amp
circuits, an active feedback amplifier can function as a
conventional op amp under these conditions.
In a closed-loop application, a conventional op amp has its
differential input voltage driven to near 0 under nontransient
conditions. The AD8129/AD8130 generally has differential
input voltages at each of its input pairs, even under equilibrium
conditions. As a practical consideration, it is necessary to limit
the differential input voltage internally with a clamp circuit.
Note that this circuit is presented only for illustration purposes
to show the similarities of the active feedback architecture
functionality to conventional op amp functionality. If it is
desired to design a circuit that can be created from a conven-
tional op amp, it is recommended to choose a conventional
op amp with specifications that are better suited to that application.
These op amp principles are the basis for offsetting the output,
as described in the Output Offset/Level Translator section.
Rev. C | Page 32 of 40
AD8129/AD8130
APPLICATIONS
BASIC GAIN CIRCUITS
TWISTED-PAIR CABLE, COMPOSITE VIDEO
RECEIVER WITH EQUALIZATION USING AN AD8130
The gain of the AD8129/AD8130 can be set with a pair of
feedback resistors. The basic configuration is shown in Figure 132.
The gain equation is the same as that of a conventional op amp:
G = 1 + RF/RG. For unity-gain applications using the AD8130,
RF can be set to 0 (short circuit), and RG can be removed (see
Figure 133). The AD8129 is compensated to operate at gains of
10 and higher; therefore, shorting the feedback path to obtain
unity gain causes oscillation.
The AD8130 has excellent common-mode rejection at its
inputs. This makes it an ideal candidate for a receiver for signals
that are transmitted over long distances on twisted-pair cables.
Category 5 cables are very common in office settings and are
extensively used for data transmission. These cables can also be
used for the analog transmission of signals such as video.
These long cables pick up noise from the environment they pass
through. This noise does not favor one conductor over another
and therefore is a common-mode signal. A receiver that rejects
the common-mode signal on the cable can greatly enhance the
signal-to-noise ratio performance of the link.
+V
AD8129/
AD8130
10μF
0.1μF
3
7
1
8
+V
+
+
PD
S
V
IN
The AD8130 is also very easy to use as a differential receiver,
because the differential inputs and the feedback inputs are
entirely separate. This means that there is no interaction
between the feedback network and the termination network,
as there would be in conventional op amp types of receivers.
6
V
OUT
4
5
–V
S
2
R
F
R
G
10μF
0.1μF
–V
Another issue with long cables is that there is more attenuation
of the signal at longer distances. Attenuation is also a function
of frequency; it increases to roughly the square root of frequency.
Figure 132. Basic Gain Circuit: VOUT = VIN (1 + RF/RG)
+V
For good fidelity of video circuits, the overall frequency
response of the transmission channel should be flat vs.
frequency. Because the cable attenuates the high frequencies, a
frequency-selective boost circuit can be used to undo this effect.
These circuits are called equalizers.
AD8130
10μF
0.1μF
3
7
+V
1
8
+
+
PD
S
V
IN
6
V
OUT
4
5
–V
An equalizer uses frequency-dependent elements (Ls and Cs) to
create a frequency response that is the opposite of the rest of the
channel’s response to create an overall flat response. There are
many ways to create such circuits, but a common technique is to
put the frequency-selective elements in the feedback path of an
op amp circuit. The AD8130 in particular makes this easier
than other circuits, because, once again, the feedback path is
completely independent of the input path and there is no
interaction.
S
2
10μF
0.1μF
–V
Figure 133. An AD8130 with Unity Gain
The input signal can be applied either differentially or in a
single-ended fashion—all that matters is the magnitude of the
differential signal between the two inputs. For single-ended
input applications, applying the signal to the +IN with −IN
grounded creates a noninverting gain, while reversing these
connections creates an inverting gain. Because the two inputs
are high impedance and matched, both of these conditions
provide the same high input impedance. Thus, an advantage of
the active feedback architecture is the ability to make a high
input impedance inverting op amp. If conventional op amps are
used, a high impedance buffer followed by an inverting stage is
needed. This requires two op amps.
The circuit in Figure 134 was developed as a receiver/equalizer
for transmitting composite video over 300 meters of Category 5
cable. This cable has an attenuation of approximately 20 dB at
10 MHz for 300 meters. At 100 MHz, the attenuation is
approximately 60 dB (see Figure 135).
Rev. C | Page 33 of 40
AD8129/AD8130
+V
7
It is difficult to calculate the exact component values via strictly
mathematical means, because the equations for the cable
attenuation are approximate and have functions that are not
simply related to the responses of RC networks. The method
used in this design was to approximate the required response
via graphical means from the frequency response and then
select components that would approximate this response. The
circuit was then built, measured, and finally adjusted to obtain
an acceptable response—in this case, flat to 9 MHz to within
approximately 1 dB (see Figure 137).
AD8130
10μF
0.1μF
3
+V
1
8
+
+
PD
S
V
100
Ω
IN
6
V
OUT
4
5
–V
S
2
R
1k
F
Ω
R1
R
G
100
Ω
10μF
0.1μF
499Ω
–V
C1
200pF
20
Figure 134. An Equalizer Circuit for Composite Video Transmissions
over 300 Meters of Category-5 Cable
10
0
20
10
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 137. Combined Response of Cable Plus Equalizer
10k
100k
1M
10M
100M
OUTPUT OFFSET/LEVEL TRANSLATOR
FREQUENCY (Hz)
The circuit in Figure 133 has the reference input (Pin 4) tied to
ground, which produces a ground-referenced output signal. If it
is desired to offset the output voltage from ground, the REF
input can be used (see Figure 138). The level VOFFSET appears at
the output with unity gain.
Figure 135. Transmission Response of 300 Meters of Category-5 Cable
The feedback network is between Pin 6 and Pin 5 and from
Pin 5 to ground. C1 and RF create a corner frequency of about
800 kHz. The gain increases to provide about 15 dB of boost
at 8 MHz. The response of this circuit is shown in Figure 136.
+V
20
10
AD8130
10μF
0.1μF
0
3
7
+V
1
8
+
+
PD
S
V
–10
–20
–30
–40
–50
–60
–70
–80
IN
V
= V +V
IN OFFSET
OUT
6
V
4
5
OFFSET
–V
S
2
0.1
μ
F
10μF
–V
Figure 138. The Voltage Applied to Pin 4 to the Unity-Gain Output Voltage
Produced by VIN
10k
100k
1M
10M
100M
FREQUENCY (Hz)
If the circuit has a gain higher than unity, the gain must be
factored in. If RG is connected to ground, the voltage applied to
REF is multiplied by the gain of the circuit and appears at the
output—just like a noninverting conventional op amp. This
situation is not always desirable; the user may want VOFFSET to
appear at the output with unity gain.
Figure 136. Frequency Response of Equalizer Circuit
Rev. C | Page 34 of 40
AD8129/AD8130
+V
One way to accomplish this is to drive both REF and RG with
the desired offset signal (see Figure 139). Superposition can be
used to solve this circuit. First, break the connection between
AD8130
0.1
μF
10μF
3
7
VOFFSET and RG. With RG grounded, the gain from Pin 4 to VOUT
V
1
8
+V
IN
+
+
PD
S
is 1 + RF/RG. With Pin 4 grounded, the gain though RG to VOUT
is −RF/RG. The sum of these is 1. If VREF is delivered from a low
impedance source, this works fine. However, if the delivered
offset voltage is derived from a high impedance source, such as
a voltage divider, its impedance affects the gain equation. This
makes the circuit more complicated because it creates an
interaction between the gain and offset voltage.
6
V
OUT
4
5
–V
S
2
10μF
0.1μF
–V
+V
Figure 141. Gain-of-2 Connections with No Resistors
AD8129/
AD8130
SUMMER
10μF
0.1μF
3
7
A general summing circuit can be made by the previous
technique. A unity-gain configured AD8130 has one signal
applied to +IN, while the other signal is applied to REF. The
output is the sum of the two input signals (see Figure 142).
+V
1
8
+
+
PD
S
V
IN
V
V
=
OUT
6
V
4
5
× (1 + R /R ) + V
F G OFFSET
OFFSET
IN
–V
S
R
G
2
+V
R
F
10μF
0.1
μ
F
AD8130
0.1
μ
F
10μF
–V
3
7
V1
V2
1
8
+V
+
+
PD
S
Figure 139. In this Circuit, VOFFSET Appears at the Output with Unity Gain. This
Circuit Works Well if the VOFFSET Source Impedance Is Low.
6
V
= V1 + V2
OUT
4
5
–V
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the
amplifier and then apply this voltage to the high impedance
REF input. This circuit first divides the desired offset voltage
by the gain, and the amplifier multiplies it back up to unity (see
Figure 140).
S
2
10μF
0.1μF
–V
Figure 142. A Summing Circuit that is Noninverting
with High Input Impedance
+V
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both high
impedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
AD8129/
AD8130
0.1
μ
F
10μF
3
7
1
8
+V
+
+
PD
S
V
IN
V
V
=
OUT
6
R
F
V
4
5
× (1 + R /R ) + V
OFFSET
OFFSET
IN
F
G
–V
R
S
G
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for each additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s
and then summing the two outputs by a third AD8130.
2
R
F
R
G
10μF
0.1μF
–V
Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at
the Output with Unity Gain.
CABLE-TAP AMPLIFIER
RESISTORLESS GAIN OF 2
It is often desirable to have a video signal drive several pieces of
equipment. However, the cable should only be terminated once at
its endpoint; therefore, it is not appropriate to have a termination
at each device. A loop-through connection allows a device to tap
the video signal while not disturbing it by any excessive loading.
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there is unity gain from VIN
and unity gain from VREF. Thus, the circuit has a gain of 2 and
requires no resistors (see Figure 141).
Rev. C | Page 35 of 40
AD8129/AD8130
Such a connection, also referred to as a cable-tap amplifier, can
be simply made with an AD8130 (see Figure 143). The circuit is
configured with unity gain, and if no output offset is desired,
the REF pin is grounded. The negative differential input is
connected directly to the shield of the cable (or an associated
connector) at the point at which it wants to be tapped.
EXTREME OPERATING CONDITIONS
The AD8129/AD8130 are designed to provide high
performance over a wide range of supply voltages. However,
there are some extremes of operating conditions that have
been observed to produce suboptimal results. One of these
conditions occurs when the AD8130 is operated at unity gain
with low supply voltage—less than approximately 4 V.
+V
AD8130
At unity gain, the output drives FB directly. With supplies of
VS less than approximately 4 V at unity gain, the output can
drive FB’s voltage too close to the rail for the circuit to stay
properly biased. This can lead to a parasitic oscillation.
75Ω
0.1
μ
F
10μF
3
7
1
8
+V
+
+
PD
S
6
V
OUT
4
5
A way to prevent this is to limit the input signal swing with
clamp diodes. Common silicon-junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flows through them. Two series pairs of such
diodes connected antiparallel across the differential inputs can
be used to clamp the input signal and prevent this condition. It
should be noted that the REF input can also shift the output
signal; therefore, this technique only works when REF is at
ground or close to it (see Figure 145).
–V
S
2
VIDEO
IN
10μF
0.1μF
–V
75Ω
Figure 143. The AD8130 Can Tap the Video Signal at Any Point Along the
Cable Without Loading the Signal.
The center conductor connects to the positive differential input
of the AD8130. The amplitude of the video signal at this point is
unity, because it is between the two termination resistors. The
AD8130 provides a high impedance to this signal so that the
signal is not disturbed. A buffered unity-gain version of the
video signal appears at the output.
+V
AD8130
0.1
μF
10μF
V
V
3
7
IN
1N4148
1
8
+V
+
+
PD
S
6
POWER-DOWN
V
OUT
4
5
IN
–V
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
S
2
PD
used. A logic low level on the
pin causes the part to power
down. Because there is no ground pin on the AD8129/AD8130,
there is no logic reference to interface to standard logic levels.
10μF
0.1μF
–V
PD
For this reason, the reference level for the
input is VS. If
Figure 145. Clamping Diodes at the Input Limits the Input Swing Amplitude
the AD8129/AD8130 are run with VS = 5 V, there is direct
compatibility with logic families. However, if VS is higher than
this, a level-shift circuit is needed to interface to conventional
logic levels. A simple level-shifting circuit that is compatible
with common logic families is presented in Figure 144.
+V
S
7
1kΩ
+V
S
3
PD
4.99kΩ
2N2222
OR EQ
LOW =
POWER-DOWN
AD8129/
AD8130
Figure 144. Circuit that Shifts the Logic Level When VS Is Not Equal to
Approximately 5 V.
Rev. C | Page 36 of 40
AD8129/AD8130
The power dissipation is a function of several operating
conditions, including the supply voltage, the input differential
voltage, the output load, and the signal frequency.
Another problem can occur with the AD8129 operating
at a supply voltage of greater than or equal to 12 V. The
architecture causes the supply current to increase as the input
differential voltage increases. If the AD8129 differential inputs
are overdriven too far, excessive current can flow into the device
and potentially cause permanent damage.
A basic starting point is to calculate the quiescent power
dissipation with no signal and no differential input voltage.
This is just the product of the total supply voltage and the
quiescent operating current. The maximum operating supply
voltage is 26.4 V, and the quiescent current is 13 mA. This
causes a quiescent power dissipation of 343 mW. For the
MSOP package, the θJA specification is 142°C/W. Therefore,
the quiescent power causes about a 49°C rise above ambient
in the MSOP package.
A practical means to prevent this from occurring is to clamp the
inputs differentially with a pair of antiparallel Schottky diodes
(see Figure 146). These diodes have a lower forward voltage of
approximately 0.4 V. If the differential voltage across the inputs
is restricted to these conditions, no excess current is drawn by
the AD8129 under these operating conditions.
The current consumption is also a function of the differential
input voltage (see Figure 113 and Figure 114). This current
should be added onto the quiescent current and then multiplied
by the total supply voltage to calculate the power.
If the supply voltage is restricted to less than 11 V, the internal
clamping circuit limits the differential voltage and excessive
supply current is not drawn. The external clamp circuit is not
needed.
+V
The AD8129/AD8130 can directly drive loads of as low as
100 Ω, such as a terminated 50 Ω cable. The worst-case power
dissipation in the output stage occurs when the output is at
midsupply. As an example, for a 12 V supply with the output
driving a 250 Ω load to ground, the maximum power dissipation
in the output occurs when the output voltage is 6 V. The load
current is 6 V/250 Ω = 24 mA. This same current flows through
the output across a 6 V drop from VS. It dissipates 144 mW. For
the 8-lead MSOP package, this causes a temperature rise of
20°C above ambient. Although this is a worst-case number, it is
apparent that this can be a considerable additional amount of
power dissipation.
AD8129
0.1
μ
F
10μF
V
IN
3
7
3
1
8
+V
+
+
PD
S
AGILENT
HSMS 2822
6
V
OUT
1
2
4
5
V
IN
–V
S
2
10μF
0.1μF
–V
Figure 146. Schottky Diodes Across the Inputs
Limits the Input Differential Voltage
Several changes can be made to alleviate this. One is to use the
standard 8-lead SOIC package. This lowers the thermal impedance
to 121°C/W, which is a 15% improvement. Another is to use a
lower supply voltage unless absolutely necessary.
In both circuits, the input series resistors function to limit the
current through the diodes when they are forward biased. As a
practical matter, these resistors must be matched so that the
CMRR is preserved at high frequencies. These resistors have
minimal effect on the CMRR at low frequency.
Finally, do not use the AD8129/AD8130 when it is operating on
high supply voltages to directly drive a heavy load. It is best to
use a second op amp after the output stage. Some of the gain
can be shifted to this stage so that the signal swing at the output
of the AD8129/AD8130 is not too large.
POWER DISSIPATION
The AD8129/AD8130 can operate with supply voltages from
+5 V to 12 V. The major reason for such a wide supply range is
to provide a wide input common-mode range for systems that
can require this. This would be encountered when significant
common-mode noise couples into the input path. For applications
that do not require a wide dynamic range for the input or output, it
is recommended to operate with lower supply voltages.
The AD8129/AD8130 is also available in a very small 8-lead
MSOP package. This package has higher thermal impedance
than larger packages and operates at a higher temperature with
the same amount of power dissipation. Certain operating
conditions that are within the specifications range of the parts can
cause excess power dissipation. Caution should be exercised.
Rev. C | Page 37 of 40
AD8129/AD8130
LAYOUT, GROUNDING, AND BYPASSING
The AD8129/AD8130 are very high speed parts that can be
sensitive to the PCB environment in which they operate.
Realizing their superior specifications requires attention to
various details of standard high speed PCB design practice.
The first requirement is for a good solid ground plane that
covers as much of the board area around the AD8129/AD8130
as possible. The only exception to this is that the ground plane
around the FB pin should be kept a few millimeters away, and
the ground should be removed from the inner layers and the
opposite side of the board under this pin. This minimizes the
stray capacitance on this node and helps preserve the gain
flatness vs. frequency.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used, and the bypassing
should be done with a capacitance value of 0.01 μF to 0.1 μF for
each supply. Farther away, low frequency bypassing should be
provided with 10 μF tantalum capacitors from each supply to
ground.
The signal routing should be short and direct to avoid parasitic
effects. Where possible, signals should be run over ground
planes to avoid radiating or to avoid being susceptible to other
radiation sources.
Rev. C | Page 38 of 40
AD8129/AD8130
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 147. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 148. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 39 of 40
AD8129/AD8130
ORDERING GUIDE
Model
AD8129AR
AD8129AR-REEL
AD8129AR-REEL7
AD8129ARZ2
AD8129ARZ-REEL2
AD8129ARZ-REEL72
AD8129ARM
AD8129ARM-REEL
AD8129ARM-REEL7
AD8129ARMZ2
AD8129ARMZ-REEL2
AD8129ARMZ-REEL72
AD8130AR
AD8130AR-REEL
AD8130AR-REEL7
AD8130ARZ2
AD8130ARZ-REEL2
AD8130ARZ-REEL72
AD8130ARM
Temperature Range1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
R-8
R-8
R-8
R-8
Branding
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
HQA
HQA
HQA
HQA#
HQA#
HQA#
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
HPA
HPA
HPA
HPA#
HPA#
HPA#
AD8130ARM-REEL
AD8130ARM-REEL7
AD8130ARMZ2
AD8130ARMZ-REEL2
AD8130ARMZ-REEL72
1 Operating temperature range for 5 V or +5 V operation is −40°C to +125°C.
2 Z = Pb-free part; # indicates lead-free, may be top or bottom marked.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02464–0–11/05(C)
Rev. C | Page 40 of 40
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