AD8129 [ADI]
Low-Cost 270 MHz Differential Receiver Amplifiers; 低成本的270 MHz差分接收器放大器
| 型号： | AD8129 |
| 厂家： | 
ADI |
| 描述： | Low-Cost 270 MHz Differential Receiver Amplifiers |
| 文件： | 总28页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low-Cost 270 MHz
Differential Receiver Amplifiers
a
AD8129/AD8130
FEATURES
High Speed
CONNECTION DIAGRAM
(Top View)
AD8130: 270 MHz, 1090 V/ꢀs @ G = 1
AD8129: 200 MHz, 1060 V/ꢀs @ G = 10
High CMRR
94 dB Min, DC to 100 kHz
80 dB Min @ 2 MHz
SO-8 (R) and Micro_SO-8 (RM)
AD8129/
AD8130
1
2
3
4
8
7
6
5
–IN
+V
+IN
–V
S
S
+
70 dB @ 10 MHz
OUT
FB
PD
High-Input Impedance: 1 Mꢁ Differential
Input Common-Mode Range ꢂ10.5 V
Low Noise
REF
AD8130: 12.5 nV/√Hz
data transmission. The AD8129 and AD8130 are differential-
to-single-ended amplifiers with extremely high CMRR at high
frequency. Therefore, they can also be effectively used as
high-speed instrumentation amps or for converting differential
signals to single-ended signals.
AD8129: 4.5 nV/√Hz
Low Distortion, 1 V p-p @ 5 MHz:
AD8130, –79 dBc Worst Harmonic @ 5 MHz
AD8129, –74 dBc Worst Harmonic @ 5 MHz
User-Adjustable Gain
The AD8129 is a low-noise high-gain (10 or greater) version
intended for applications over very long cables where signal
attenuation is significant. The AD8130 is stable at a gain of one
and can be used for those applications where lower gains are
required. Both have user adjustable gain to help compensate for
losses in the transmission line. The gain is set by the ratio of
two resistor values. The AD8129 and AD8130 have very high
input impedance on both inputs regardless of the gain setting.
No External Components for G = 1
Power Supply Range +4.5 V to ꢂ12.6 V
Power-Down
APPLICATIONS
High-Speed Differential Line Receiver
Differential-to-Single-Ended Converter
High-Speed Instrumentation Amp
Level-Shifting
The AD8129 and AD8130 have excellent common-mode rejec-
tion (70 dB @ 10 MHz) allowing the use of low cost unshielded
twisted-pair cables without fear of corruption by external noise
sources or crosstalk.
GENERAL DESCRIPTION
The AD8129 and AD8130 are designed as receivers for the
transmission of high-speed signals over twisted-pair cables to
work with the AD8131 or AD8132 drivers. Either can be
used for analog or digital video signals and for high-speed
The AD8129 and AD8130 have a wide power supply range
from single 5 V supply to 12 V, allowing wide common-mode
and differential-mode voltage ranges while maintaining signal
integrity. The wide common-mode voltage range will enable
the driver receiver pair to operate without isolation transform-
ers in many systems where the ground potential difference
between drive and receive locations is many volts. The AD8129
and AD8130 have considerable cost and performance improve-
ments over op amps and other multi-amplifier receiving solutions.
120
110
100
90
80
70
60
+V
S
PD
V
IN
50
40
30
V
OUT
10k
100k
1M
10M
100M
FREQUENCY – Hz
R
R
G
F
Figure 1. AD8129 CMRR vs. Frequency
–V
S
V
= V [1+(R /R )]
IN
OUT
F
G
Figure 2. Typical Connection Configuration
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD8129/AD8130–SPECIFICATIONS
ꢂ5 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25ꢃC, VS = ꢂ5 V, REF = 0 V, PD ≥ VIH, RL = 1 kꢁ, CL = 2 pF, unless
otherwise noted. TMIN to TMAX = –40ꢃC to +85ꢃC, unless otherwise noted.)
Model
Parameter
AD8129A
Typ
AD8130A
Typ
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT ≤ 0.3 V p-p
175
170
200
190
30/50
1060
20
240
140
270
155
45
1090
20
MHz
MHz
MHz
V/µs
ns
VOUT = 2 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
VOUT = 2 V p-p, 25% to 75%
925
950
VOUT = 2 V p-p, 0.1%
Rise and Fall Time
Output Overdrive Recovery
VOUT ≤ 1 V p-p, 10% to 90%
1.7
30
1.4
40
ns
ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic
VOUT = 1 V p-p, 5 MHz
–74/–84
–68/–74
–67/–81
–61/–70
–67
25
4.5
1
1.4
0.3
0.1
–79/–86
–74/–81
–74/–80
–74/–76
–70
26
12.5
1
1.4
0.13
0.15
dBc
dBc
dBc
dBc
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
f ≥ 100 kHz
f ≥ 100 kHz
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise (+IN, –IN)
Input Current Noise (REF, FB)
Differential Gain Error
Differential Phase Error
dBc
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω
AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω
Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
DC to 100 kHz, VCM = –3 V to +3.5 V
94
80
110
90
80
110
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 2 V p-p @ 1 kHz, VOUT = 0.5 V dc
70
100
3.5
0.5
0.75
1
4
3
4
70
83
3.8
2.5
2.8
6
4
3
4
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
V+IN – V–IN = 0 V
0.6
0.85
2.3
3.3
Differential
Common-Mode
Differential
Capacitance
Common-Mode
DC PERFORMANCE
Closed-Loop Gain Error
VOUT
=
1 V, RL ≥ 150 Ω
0.4
20
88
250
0.2
2
1.5
0.8
0.15
10
74
200
0.4
10
0.6
1.8
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
TMIN to TMAX
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
VOUT
VOUT
=
=
1 V
1 V
TMIN to TMAX
TMIN to TMAX
+VS = +5 V, –VS = –4.5 V to –5.5 V
–VS = –5 V, +VS = +4.5 V to +5.5 V
1.4
–84
–86
2
3.5
–74
–74
2
Input Offset Voltage vs. Supply
–90
–94
0.5
1
–78
–80
0.5
1
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
3.5
3.5
TMIN to TMAX (+IN, –IN, REF, FB)
5
5
Input Offset Current
(+IN, –IN, REF, FB)
TMIN to TMAX
0.08
0.2
0.4
0.08
0.2
0.4
OUTPUT PERFORMANCE
Voltage Swing
Output Current
RLOAD = 150 Ω/1 kΩ
3.6/4.0
2.25
3.6/4.0
2.25
V
40
40
mA
mA
µA/°C
pF
Short Circuit Current
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
–60/+55
–240
10
–60/+55
–240
10
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total Supply Voltage
12.6
11.6
12.6
11.6
V
10.8
36
0.68
10.8
36
0.68
mA
µA/°C
mA
mA
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
0.85
1
0.85
1
PD PIN
VIH
+VS – 1.5
+VS – 1.5
V
VIL
IIH
IIL
+VS – 2.5
–30
–50
+VS – 2.5
–30
–50
V
PD = Min VIH
PD = Max VIL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
µA
µA
kΩ
kΩ
µs
Input Resistance
12.5
100
0.5
12.5
100
0.5
Enable Time
Specifications subject to change without notice.
–2–
REV. 0
AD8129/AD8130
ꢂ12 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25ꢃC, VS = ꢂ12 V, REF = 0 V, PD ≥ VIH, RL = 1 kꢁ, CL = 2 pF,
unless otherwise noted. TMIN to TMAX = –40ꢃC to +85ꢃC, unless otherwise noted.)
Model
Parameter
AD8129A
Typ
AD8130A
Typ
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT ≤ 0.3 V p-p
175
170
200
195
50/70
1070
20
250
150
290
175
110
1100
20
MHz
MHz
MHz
V/µs
ns
VOUT = 2 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
V
OUT = 2 V p-p, 25% to 75%
935
960
VOUT = 2 V p-p, 0.1%
Rise and Fall Time
Output Overdrive Recovery
VOUT ≤ 1 V p-p, 10% to 90%
1.7
40
1.4
40
ns
ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz
VOUT = 2 V p-p, 5 MHz
–71/–84
–65/–74
–65/–82
–59/–70
–67
–79/–86
–74/–81
–74/–80
–74/–74
–70
dBc
dBc
dBc
dBc
V
OUT = 1 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
IMD
dBc
Output IP3
V
OUT = 2 V p-p, 10 MHz
25
4.6
1
1.4
0.3
0.1
26
13
1
1.4
0.13
0.2
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
Input Voltage Noise (RTI)
Input Current Noise (+IN, –IN)
Input Current Noise (REF, FB)
Differential Gain Error
Differential Phase Error
f ≥ 10 kHz
f ≥ 100 kHz
f ≥ 100 kHz
AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω
AD8130, G = 2, NTSC 200 IRE, RL ≥ 150 Ω
Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
DC to 100 kHz, VCM
VCM = 1 V p-p @ 2 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 4 V p-p @ 1 kHz, VOUT
V+IN – V–IN = 0 V
=
10 V
92
80
105
88
80
105
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
70
93
10.3
0.5
0.75
1
4
3
4
70
80
10.5
2.5
2.8
6
4
3
4
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
= 0.5 V dc
0.6
0.85
2.3
3.3
Differential
Common-Mode
Differential
Capacitance
Common-Mode
DC PERFORMANCE
Closed-Loop Gain Error
VOUT
TMIN to TMAX
VOUT
VOUT
=
1 V, RL ≥ 150 Ω
0.8
20
87
250
0.2
2
1.8
0.15
10
73
200
0.4
10
0.6
1.8
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
=
=
1 V
1 V
0.8
T
MIN to TMAX
TMIN to TMAX
+VS = +12 V, –VS = –11.0 V to –13.0 V
–VS = –12 V, +VS = +11.0 V to +13.0 V
1.4
–82
–84
2
3.5
–70
–70
2
Input Offset Voltage vs. Supply
–88
–92
0.25
0.5
2.5
0.08
0.2
–77
–88
0.25
0.5
2.5
0.08
0.2
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
3.5
3.5
T
MIN to TMAX (+IN, –IN, REF, FB)
Input Offset Current
(+IN, –IN, REF, FB)
TMIN to TMAX
0.4
0.4
OUTPUT PERFORMANCE
Voltage Swing
Output Current
RLOAD = 700 Ω
10.8
10.8
2.25
V
40
40
mA
mA
µA/°C
pF
Short Circuit Current
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
–60/+55
–240
10
–60/+55
–240
10
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total Supply Voltage
2.25
12.6
13.9
12.6
13.9
V
13
43
0.73
13
43
0.73
mA
µA/°C
mA
mA
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
0.9
1.1
0.9
1.1
PD PIN
VIH
+VS – 1.5
+VS – 1.5
V
VIL
IIH
IIL
+VS – 2.5
–30
–50
+VS – 2.5
–30
–50
V
PD = Min VIH
PD = Max VIL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
µA
µA
kΩ
kΩ
µs
Input Resistance
3
100
0.5
3
100
0.5
Enable Time
Specifications subject to change without notice.
–3–
REV. 0
AD8129/AD8130–SPECIFICATIONS
5 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25ꢃC, +VS = 5 V, –VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 kꢁ, CL = 2 pF
unless otherwise noted. TMIN to TMAX = –40ꢃC to +85ꢃC, unless otherwise noted.)
Model
Parameter
AD8129A
Typ
AD8130A
Typ
Conditions
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
VOUT ≤ 0.3 V p-p
160
160
185
185
25/40
930
20
220
180
250
205
25
930
20
MHz
MHz
MHz
V/µs
ns
V
OUT = 1 V p-p
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
VOUT ≤ 0.3 V p-p, SOIC/µSOIC
VOUT = 2 V p-p, 25% to 75%
VOUT = 2 V p-p, 0.1%
810
810
Rise and Fall Time
Output Overdrive Recovery
VOUT ≤ 1 V p-p, 10% to 90%
1.8
20
1.5
30
ns
ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic
V
OUT = 1 V p-p, 5 MHz
–68/–75
–62/–64
–63/–70
–56/–58
–67
25
4.5
1
1.4
0.3
0.1
–72/–79
–65/–71
–60/–62
–68/–68
–70
26
12.3
1
1.4
0.13
0.15
dBc
dBc
dBc
dBc
VOUT = 2 V p-p, 5 MHz
VOUT = 1 V p-p, 10 MHz
V
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 10 MHz
f ≥ 10 kHz
f ≥ 100 kHz
f ≥ 100 kHz
OUT = 2 V p-p, 10 MHz
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise (+IN, –IN)
Input Current Noise (REF, FB)
Differential Gain Error
Differential Phase Error
dBc
dBm
nV/√Hz
pA/√Hz
pA/√Hz
%
AD8130, G = 2, NTSC 100 IRE, RL ≥ 150 Ω
AD8130, G = 2, NTSC 100 IRE, RL ≥ 150 Ω
Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
DC to 100 kHz, VCM = 1.5 V to 3.5 V
86
80
96
86
80
96
dB
dB
dB
dB
V
V
V
MΩ
MΩ
pF
pF
V
CM = 1 V p-p @ 1 MHz
VCM = 1 V p-p @ 10 MHz
VCM = 1 V p-p @ 1 kHz, VOUT
70
80
70
72
CMRR with VOUT = 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
=
0.5 V dc
V
+IN – V–IN = 0 V
1.25 to 3.7
0.5
1.25 to 3.8
2.5
2.8
0.6
0.75
0.85
2.3
3.3
Differential
Common-Mode
Differential
1
4
3
4
6
4
3
4
Capacitance
Common-Mode
DC PERFORMANCE
Closed-Loop Gain Error
VOUT
=
1 V, RL ≥ 150 Ω
0.25
20
86
250
0.2
2
1.25
0.1
20
71
200
0.4
10
0.6
1.8
%
ppm/°C
dB
ppm
mV
µV/°C
mV
dB
dB
µA
µA
nA/°C
µA
nA/°C
TMIN to TMAX
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
VOUT
VOUT
=
=
1 V
1 V
0.8
TMIN to TMAX
TMIN to TMAX
+VS = 5 V, –VS = –0.5 V to +0.5 V
–VS = 0 V, +VS = +4.5 V to +5.5 V
1.4
–80
–86
2
3.5
–70
–76
2
Input Offset Voltage vs. Supply
–88
–100
0.5
1
–74
–90
0.5
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
3.5
1
3.5
T
MIN to TMAX (+IN, –IN, REF, FB)
5
5
Input Offset Current
(+IN, –IN, REF, FB)
TMIN to TMAX
0.08
0.2
0.4
0.08
0.2
0.4
3.9
OUTPUT PERFORMANCE
Voltage Swing
Output Current
RLOAD ≥ 150 Ω
1.1
3.9
1.1
V
35
35
mA
mA
µA/°C
pF
Short Circuit Current
To Common
TMIN to TMAX
PD ≤ VIL, In Power-Down Mode
–60/+55
–240
10
–60/+55
–240
10
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total Supply Voltage
2.25
12.6
10.6
2.25
12.6
10.6
V
9.9
33
0.65
9.9
33
0.65
mA
µA/°C
mA
mA
TMIN to TMAX
PD ≤ VIL
PD ≤ VIL, TMIN to TMAX
0.85
1
0.85
1
PD PIN
VIH
+VS – 1.5
+VS – 1.5
V
VIL
IIH
IIL
+VS – 2.5
–30
–50
+VS – 2.5
–30
–50
V
PD = Min VIH
PD = Max VIL
PD ≤ +VS – 3 V
PD ≥ +VS – 2 V
µA
µA
kΩ
kΩ
µs
Input Resistance
12.5
100
0.5
12.5
100
0.5
Enable Time
Specifications subject to change without notice.
–4–
REV. 0
AD8129/AD8130
ABSOLUTE MAXIMUM RATINGS1, 2
2.0
1.5
1.0
0.5
0
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . Refer to Figure 3
Input Voltage (Any Input) . . . . . . . –VS – 0.3 V to +VS + 0.3 V
Differential Input Voltage (AD8129)3 VS ≥ 11.5 V . . . 0.5 V
Differential Input Voltage (AD8129)3 VS < 11.5 V . . . 6.2 V
Differential Input Voltage (AD8130) . . . . . . . . . . . . . . 8.4 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
T
(MAX) = 150ꢃC
J
8-LEAD SOIC
PACKAGE
8-LEAD
MICRO_SO
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢃC
2Thermal Resistance measured on SEMI standard 4-layer board.
8-Lead SOIC: θJA= 121°C/W; 8-Lead Micro_SO: θJA = 142°C/W
3Refer to Applications section, Extreme Operating Condition, and Power Dissipation.
Figure 3. Maximum Power Dissipation vs. Temperature
CONNECTION DIAGRAM
(Top View)
SO-8 (R) and Micro_SO-8 (RM)
AD8129/
AD8130
1
2
3
4
8
7
6
5
–IN
+IN
+V
–V
S
S
+
OUT
FB
PD
REF
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Information
Model
AD8129AR
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead Micro_SO
8-Lead Micro_SO
8-Lead Micro_SO
Evaluation Board with SOIC
SO-8
AD8129AR-REEL1
AD8129AR-REEL72
AD8129ARM
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
HQA
HQA
HQA
AD8129ARM-REEL3
AD8129ARM-REEL72
AD8129-EVAL
AD8130AR
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead Micro_SO
8-Lead Micro_SO
8-Lead Micro_SO
Evaluation Board with SOIC
SO-8
AD8130AR-REEL1
AD8130AR-REEL72
AD8130ARM
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
HPA
HPA
HPA
AD8130ARM-REEL3
AD8130ARM-REEL72
AD8130-EVAL
NOTES
113" Reel of 2500 each.
27" Reel of 1000 each.
313" Reel of 3000 each.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8129/AD8130 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD8129/AD8130
AD8130 Frequency Response Characteristics
(G = 1, RL = 1 kꢁ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25ꢃC, unless otherwise noted.)
3
2
3
2
3
2
V
= ꢂ2.5V
V
= ꢂ2.5V
V
= 0.3V p-p
V
= 1V p-p
S
V
= 2V p-p
S
OUT
OUT
OUT
V
= ꢂ2.5V
S
1
1
1
0
0
0
V
= ꢂ5V
V
= ꢂ5V
S
S
–1
–1
–1
V
= ꢂ5V
S
V
= ꢂ12V
V
= ꢂ12V
S
S
–2
–3
–2
–3
–2
–3
V
= ꢂ12V
S
–4
–5
–6
–7
–4
–5
–6
–7
–4
–5
–6
–7
1
10
FREQUENCY – MHz
100
400
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
100
300
TPC 3. AD8130 Frequency Response
vs. Supply, VOUT = 2 V p-p
TPC 1. AD8130 Frequency Response
vs. Supply, VOUT = 0.3 V p-p
TPC 2. AD8130 Frequency Response
vs. Supply, VOUT = 1 V p-p
6
0.5
0.7
C
= 20pF
V
= ꢂ5V
L
R
= 1kꢁ
V
= ꢂ2.5V
V = ꢂ2.5V
S
S
R
= 150ꢁ
L
S
L
5
4
3
2
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
C
= 10pF
L
V
= ꢂ5V
S
C
= 5pF
L
V
= ꢂ5V
S
1
0
0.0
0.2
0.1
–0.1
V
= ꢂ12V
S
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0.0
–0.1
–0.2
–0.3
C
= 2pF
L
V
= ꢂ12V
S
1
10
FREQUENCY – MHz
100
300
1
10
100
300
1
10
FREQUENCY – MHz
100
300
FREQUENCY – MHz
TPC 4. AD8130 Frequency Response
vs. Load Capacitance
TPC 5. AD8130 Fine Scale Response
vs. Supply, RL = 1 kΩ
TPC 6. AD8130 Fine Scale Response
vs. Supply, RL = 150 Ω
3
3
3
R
= 150ꢁ
G = 2
OUT
G = 2
OUT
L
2
1
V
= 0.3V p-p
V
= ꢂ2.5V
V
= 2V p-p
2
1
2
1
S
V
= ꢂ2.5V
V
= ꢂ2.5V
S
S
0
0
0
V
= ꢂ5V
–1
S
–1
–1
V
= ꢂ5V
V
= ꢂ5V
S
S
–2
–3
–2
–3
–2
–3
V
= ꢂ12V
V
= ꢂ12V
V
= ꢂ12V
S
S
S
–4
–5
–6
–7
–4
–5
–6
–7
–4
–5
–6
–7
1
10
FREQUENCY – MHz
100
400
1
10
FREQUENCY – MHz
100
300
1
10
100
300
FREQUENCY – MHz
TPC 7. AD8130 Frequency Response
vs. Supply, RL = 150 Ω
TPC 8. AD8130 Frequency Response
vs. Supply, G = 2, VOUT = 0.3 V p-p
TPC 9. AD8130 Frequency Response
vs. Supply, G = 2, VOUT = 2 V p-p
–6–
REV. 0
AD8129/AD8130
3
2
0.3
0.2
0.1
0
0.3
0.2
0.1
0
G = 2
= 150ꢁ
G = 2
= 1kꢁ
V
= ꢂ2.5V
S
R
= R = 1kꢁ
G
F
R
L
R
L
R
= R = 750ꢁ
G
V
= ꢂ2.5V
F
S
1
0
R
= R = 499ꢁ
G
–1
–0.1
–0.1
F
V
= ꢂ5V
V
= ꢂ5V
S
S
–2
–3
–0.2
–0.3
–0.2
–0.3
R
= R = 250ꢁ
G
F
V
= ꢂ12V
S
V
= ꢂ12V
S
–4
–5
–6
–7
–0.4
–0.5
–0.6
–0.7
–0.4
–0.5
–0.6
–0.7
G = 2
= ꢂ5V
V
S
1
10
FREQUENCY – MHz
100
300
1
10
100
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 11. AD8130 Fine Scale Response
vs. Supply, G = 2, RL = 1 kΩ
TPC 10. AD8130 Frequency
Response for Various RF/RG
TPC 12. AD8130 Fine Scale Response
vs. Supply, G = 2, RL = 150 Ω
0.3
3
2
3
V
= 2V p-p
V
= 2V p-p
G = 2
L
OUT
OUT
0.2
0.1
0
R
= 150ꢁ
2
1
V
= ꢂ5V
V
= ꢂ2.5V
S
S
V
= ꢂ2.5V
1
S
0
0
V
= ꢂ5V
S
G = 5
–0.1
–1
–1
V
= ꢂ12V
S
V
= ꢂ12V
V
= ꢂ12V
S
S
–0.2
–0.3
–2
–3
–2
–3
V
= ꢂ2.5V
S
V
= ꢂ5V, ꢂ12V
S
G = 5
V
= ꢂ2.5V
S
–0.4
–0.5
–0.6
–0.7
–4
–5
–6
–7
–4
–5
–6
–7
V
= ꢂ5V, ꢂ12V
S
G = 10
G = 10
0.1
1
10
30
1
10
FREQUENCY – MHz
100
300
0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 14. AD8130 Fine Scale Response
vs. Supply, G = 5, G = 10, VOUT = 2 V p-p
TPC13. AD8130FrequencyResponse
vs. Supply, G = 2, RL = 150 Ω
TPC 15. AD8130 Frequency Response
vs. Supply, G = 5, G = 10, VOUT = 2 V p-p
12
3
0dB = 1V RMS
R
= 150ꢁ
1
8
TEK P6245
FET PROBE
L
6
0
2
1
50ꢁ
V
= ꢂ5V, ꢂ12V
6
S
4
5
–6
–12
–18
–24
–30
–36
–42
0
R
C
L
L
–1
G = 5
G = 10
–2
–3
R
R
F
G
V
= ꢂ2.5V
S
V
= ꢂ5V, ꢂ12V
S
–4
–5
–6
–7
G
R
R
G
F
1
2
5
0ꢁ
–
499ꢁ
8.06kꢁ
499ꢁ
2kꢁ
V
= ꢂ5V
S
10 4.99kꢁ 549ꢁ
–48
10
100
400
0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 18. AD8130 Basic Frequency
Response Test Circuit
TPC 17. AD8130 Frequency Response
for Various Output Levels
TPC16. AD8130FrequencyResponse
vs. Supply, G = 5, G = 10, RL = 150 Ω
REV. 0
–7–
AD8129/AD8130
AD8129 Frequency Response Characteristics
(G = 10, RL = 1 kꢁ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25ꢃC, unless otherwise noted.)
3
2
3
2
3
2
V
= 2V p-p
V
= 1V p-p
V = ꢂ5V
S
V
= 0.3V p-p
OUT
OUT
OUT
V
= ꢂ5V
S
V
= ꢂ2.5V
V
= ꢂ2.5V
V = ꢂ2.5V
S
S
S
1
1
1
0
0
0
V
= ꢂ5V
S
–1
–1
–1
V
= ꢂ12V
V = ꢂ12V
S
S
V
= ꢂ12V
S
–2
–3
–2
–3
–2
–3
–4
–5
–6
–7
–4
–5
–6
–7
–4
–5
–6
–7
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
100
300
TPC 19. AD8129 Frequency Response
vs. Supply, VOUT = 0.3 V p-p
TPC 20. AD8129 Frequency Response
vs. Supply, VOUT = 1 V p-p
TPC21. AD8129FrequencyResponse
vs. Supply, VOUT = 2 V p-p
4
0.5
0.3
C
C
C
C
= 20pF
= 10pF
= 5pF
V
= ꢂ5V
R
= 1kꢁ
V
V
= ꢂ2.5V
= ꢂ5V
R = 150ꢁ
L
V
= ꢂ2.5V
S
L
L
L
L
L
S
S
3
2
1
0
0.4
0.3
0.2
0.1
0.2
0.1
0
S
= 2pF
V
= ꢂ5V
–0.1
S
–1
–2
0
–0.2
–0.3
V
= ꢂ12V
V
= ꢂ12V
S
S
–0.1
–3
–4
–5
–6
–0.2
–0.3
–0.4
–0.5
–0.4
–0.5
–0.6
–0.7
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
100
300
TPC 24. AD8129 Fine Scale Response
vs. Supply, RL = 150 Ω
TPC 22. AD8129 Frequency Response
vs. Load Capacitance
TPC 23. AD8129 Fine Scale Response
vs. Supply, RL = 1 kΩ
3
3
3
G = 20
OUT
G = 20
OUT
R
= 150ꢁ
L
V
= 0.3V p-p
2
1
V
= 2V p-p
2
1
2
1
V
= ꢂ2.5V
S
V
= ꢂ5V, ꢂ12V
0
–1
–2
–3
–4
–5
–6
–7
0
0
S
V
= ꢂ5V, ꢂ12V
S
–1
–1
V
= ꢂ5V
S
–2
–3
–2
–3
V
= ꢂ12V
S
V
= ꢂ2.5V
–4
–5
–6
–7
–4
–5
–6
–7
S
V
= ꢂ2.5V
S
1
10
FREQUENCY – MHz
100
300
10
100
300
1
10
FREQUENCY – MHz
100
300
FREQUENCY – MHz
TPC 27. AD8129 Frequency Response
vs. Supply, G = 20, VOUT = 2 V p-p
TPC 25. AD8129 Frequency Response
vs. Supply, RL = 150 Ω
TPC 26. AD8129 Frequency Response
vs. Supply, G = 20, VOUT = 0.3 V p-p
–8–
REV. 0
AD8129/AD8130
0.8
0.6
0.4
0.2
0
0.2
0.1
0
0.3
0.2
0.1
0
2kꢁ/221ꢁ
G = 20
= 1kꢁ
G = 20
= 150ꢁ
G = 10
= ꢂ5V
R
L
R
L
V
S
909ꢁ/100ꢁ
V
= ꢂ5V
499ꢁ/54.9ꢁ
S
V
= ꢂ5V, ꢂ12V
S
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
SOIC
–0.1
–0.2
0.2
0
–0.2
–0.3
499ꢁ/54.9ꢁ
909ꢁ/100ꢁ
V
= ꢂ12V
S
ꢀSOIC
–0.4
–0.5
–0.6
–0.7
V
= ꢂ2.5V
V
= ꢂ2.5V
S
S
2kꢁ/221ꢁ
–0.2
–0.4
–0.6
1
10
FREQUENCY – MHz
100
300
1
10
FREQUENCY – MHz
30
0.1
1
10
30
FREQUENCY – MHz
TPC 28. AD8129 Fine Scale Response
vs. SOIC and µSOIC for Various RF/RG
TPC 30. AD8129 Fine Scale Response
vs. Supply
TPC 29. AD8129 Fine Scale Response
vs. Supply
3
3
0.2
G = 20
L
V
= 2V p-p
V
= 2V p-p
OUT
OUT
R
= 150ꢁ
2
1
2
1
0.1
0
V
= ꢂ12V
S
0
0
–0.1
–0.2
G = 50
G = 100
–1
–1
G = 50
G = 100
V
= ꢂ5V, ꢂ12V
S
V
= ꢂ2.5V
S
–2
–3
–2
–3
–0.3
–0.4
V
= ꢂ5V
S
V
= ꢂ2.5V
S
–4
–5
–6
–7
–4
–5
–6
–7
–0.5
–0.6
–0.7
–0.8
V
= ꢂ2.5V
S
V
= ꢂ5V
S
V
= ꢂ12V
S
V
= ꢂ12V
S
1
10
FREQUENCY – MHz
100
300
0.1
1
10
50
0.1
1
10
FREQUENCY – MHz
FREQUENCY – MHz
TPC 33. AD8129 Frequency Response
vs. Supply, G = 50, G = 100,
VOUT = 2 V p-p
TPC 31. AD8129 Frequency Response
vs. Supply, G = 20, RL = 150 Ω
TPC 32. AD8129 Fine Scale Response
vs. Supply, G = 50, G = 100,
VOUT = 2 V p-p
3
12
R
= 150ꢁ
L
0dB = 1V RMS
6
1
8
TEK P6245
FET PROBE
2
1
0
–6
50ꢁ
6
4
5
0
R
C
L
L
–1
–12
–18
–24
–30
–36
–42
G = 50
G = 100
–2
–3
R
G
R
F
V
= ꢂ2.5V
S
–4
–5
–6
–7
V
= ꢂ5V
S
G
R
R
G
F
V
= ꢂ12V
10
20
50
2kꢁ
2kꢁ
2kꢁ
2kꢁ
221ꢁ
105ꢁ
41.2ꢁ
20ꢁ
S
V
= ꢂ5V
S
100
–48
10
0.1
1
10
50
100
400
FREQUENCY – MHz
FREQUENCY – MHz
TPC 36. AD8129 Basic Frequency
Response Test Circuit
TPC 35. AD8129 Frequency Response
for Various Output Levels
TPC 34. AD8129 Frequency Response
vs. Supply, G = 50, G = 100,
RL = 150 Ω
REV. 0
–9–
AD8129/AD8130
AD8130 Harmonic Distortion Characteristics
(RL = 1 kꢁ, CL = 2 pF, TA = 25ꢃC, unless otherwise noted.)
–54
–55
–61
–67
–73
–79
–60
V
= 2V p-p
V
= 1V p-p
OUT
OUT
V = ꢂ12V
S
f
= 5MHz
C
V
= ꢂ5V
S
–60
–66
G = 1
V
= ꢂ5V
S
V
= ꢂ12V
S
G = 1
–66
–72
–78
–84
–72
–78
–84
–90
G = 1
= ꢂ12V
V
= ꢂ12V
S
V
V
= ꢂ5V
S
S
V
= ꢂ5V
S
G = 1
G = 2
V
= ꢂ12V
–85
–91
S
V
= ꢂ12V
S
G = 2
G = 2
V
= ꢂ5V
S
1
10
40
0.5
1
10
1
10
FREQUENCY – MHz
40
V
– V p-p
FREQUENCY – MHz
OUT
TPC 38. AD8130 Second Harmonic
Distortion vs. Frequency
TPC 39. AD8130 Second Harmonic
Distortion vs. Output Voltage
TPC 37. AD8130 Second Harmonic
Distortion vs. Frequency
–46
–51
–45
G = 1
V
= 2V p-p
V
= 1V p-p
fC = 5MHz
–52
OUT
G = 2,V = ꢂ12V
OUT
S
V
= ꢂ5V
S
–57
–51
G = 2,V = ꢂ5V
V
= ꢂ12V
= ꢂ5V
G = 1
S
S
S
V
= ꢂ12V
–58
–64
–70
–76
–82
–88
–94
–63
–69
–75
–81
–87
–93
–99
–57
–63
–69
–75
–81
–87
–93
V
S
V
S
= ꢂ12V
G = 2
G = 1
V
= ꢂ5V
S
V
= ꢂ12V
V
= ꢂ5V
S
S
V
= ꢂ12V
G = 1
G = 1
S
V
= ꢂ5V
S
G = 2
G = 2
0.5
1
10
1
10
FREQUENCY – MHz
40
1
10
FREQUENCY – MHz
40
V
– V p-p
OUT
TPC 40. AD8130 Third Harmonic
Distortion vs. Frequency
TPC 41. AD8130 Third Harmonic
Distortion vs. Frequency
TPC 42. AD8130 Third Harmonic
Distortion vs. Output Voltage
–46
–43
–42
G = 2, HD3
V
f
= ꢂ2.5V
= 5MHz
V
= ꢂ2.5V
V
= ꢂ2.5V
S
S
S
–48
–52
–58
–64
–70
–76
–82
–88
–94
C
G = 1, HD3
–49
–54
–60
G = 1
–55
–61
G = 1, HD2
V
= 2V p-p
V
= 2V p-p
OUT
OUT
–66
–72
G = 2, HD2
G = 2
G = 2, HD2
G = 2
G = 1
–67
–73
–79
–78
–84
–90
–96
G = 1
G = 2
G = 2, HD3
G = 1
V
= 1V p-p
OUT
V
= 1V p-p
OUT
G = 2
0
0.5
1.0
V
1.5
2.0
2.5
3.0
1
10
40
1
10
FREQUENCY – MHz
40
– V p-p
OUT
FREQUENCY – MHz
TPC 43. AD8130 Second Harmonic
Distortion vs. Frequency
TPC 44. AD8130 Third Harmonic
Distortion vs. Frequency
TPC 45. AD8130 Harmonic Distortion
vs. Output Voltage
–10–
REV. 0
AD8129/AD8130
AD8129 Harmonic Distortion Characteristics
(RL = 1 kꢁ, CL = 2 pF, TA = 25ꢃC, unless otherwise noted.)
–51
–57
–63
–69
–75
–81
–87
–50
–42
–48
–54
–60
–66
–72
–78
V
= 1V p-p
V
= 2V p-p
OUT
OUT
f = 5MHz
C
–56
–62
G = 10
G = 20
G = 10,
V = ꢂ12V
S
G = 10,
= ꢂ12V
G = 10,
= ꢂ12V
V
V
S
S
G = 20,
= ꢂ12V
–68
–74
V
G = 10,
= ꢂ5V
G = 10,
= ꢂ5V
S
V
V
S
S
G = 20,
= ꢂ12V
G = 10,
G = 20,
= ꢂ5V
V
S
V
= ꢂ5V
V
S
S
–80
–86
G = 20,
G = 20,
G = 20,
= ꢂ5V
V
= ꢂ5V
V
= ꢂ12V
V
S
S
S
–84
1
10
FREQUENCY – MHz
40
0.5
1
10
1
10
40
V
– V p-p
FREQUENCY – MHz
OUT
TPC 46. AD8129 Second Harmonic
Distortion vs. Frequency
TPC 47. AD8129 Second Harmonic
Distortion vs. Frequency
TPC 48. AD8129 Second Harmonic
Distortion vs. Output Voltage
–45
–54
–48
V
= 1V p-p
V
= 2V p-p
OUT
OUT
G = 10,
= ꢂ5V
f
= 5MHz
G = 10,
= ꢂ12V
C
G = 10,
= ꢂ5V
V
–54
V
S
–60
–51
–57
–63
–69
–75
–81
–87
V
S
S
G = 10,
V
= ꢂ5V
G = 10,
= ꢂ12V
–60
–66
–72
–78
–84
S
–66
–72
–78
–84
–90
–96
G = 10,
= ꢂ12V
V
S
V
S
G = 10,
= ꢂ12V
V
S
G = 20,
= ꢂ5V
V
S
G = 20,
= ꢂ5V
G = 20,
= ꢂ5V
V
S
G = 10,
= ꢂ5V
V
S
V
S
G = 20,
= ꢂ12V
–90
–96
G = 20,
= ꢂ12V
G = 20,
= ꢂ12V
V
S
V
V
S
S
1
10
FREQUENCY – MHz
40
1
10
FREQUENCY – MHz
40
0.5
1
10
V
– V p-p
OUT
TPC 50. AD8129 Third Harmonic
Distortion vs. Frequency
TPC 49. AD8129 Third Harmonic
Distortion vs. Frequency
TPC 51. AD8129 Third Harmonic
Distortion vs. Output Voltage
–42
–44
–50
V
= ꢂ2.5V
V
= ꢂ2.5V
S
V
f
= ꢂ2.5V
= 5MHz
S
V
= 2V p-p
S
OUT
V
= 2V p-p
–48
–54
–60
–66
–72
–78
–84
–90
OUT
C
–50
–56
–62
–68
–74
–80
–56
–62
–68
–74
–80
–86
G = 20
HD3
G = 20
HD2
G = 20
G = 10
HD2
V
= 1V p-p
V
= 1V p-p
G = 20
OUT
OUT
G = 10
G = 10
HD3
G = 10
0
0.5
1.0
V
1.5
– V p-p
2.0
2.5
3.0
1
10
FREQUENCY – MHz
40
1
10
FREQUENCY – MHz
40
OUT
TPC 53. AD8129 Third Harmonic
Distortion vs. Frequency
TPC 52. AD8129 Second Harmonic
Distortion vs. Frequency
TPC 54. AD8129 Harmonic Distor-
tion vs. Output Voltage
REV. 0
–11–
AD8129/AD8130
–61
–39
–50
–56
–62
–68
–74
–80
–86
G = 1
= 5MHz
G = 1
OUT
V
= 1V p-p
V
= 2V p-p
G = 1
= 5MHz
OUT
OUT
f
C
V
= 2V p-p
f
–45
–51
–57
–63
–69
–75
–81
–87
C
–67
–73
–79
V
= ꢂ5V
S
HD2
= ꢂ2.5V
R
f
= 1kꢁ
= 5MHz
HD2
= ꢂ2.5V
L
V
S
V
S
C
HD2
= ꢂ5V, ꢂ12V
V
S
HD2
= ꢂ5V, ꢂ12V
HD3
= ꢂ5V
V
S
V
S
–85
–91
–97
HD2
HD3
= ꢂ12V
V
HD3
= ꢂ2.5V
S
V
S
HD3
HD3
= ꢂ2.5V
HD3
= ꢂ5V, ꢂ12V
V
S
V
S
100
1k
–5 –4 –3 –2 –1
0
1
2
3
4
5
100
1k
V
– V
R
– ꢁ
CM
L
R
– ꢁ
L
TPC 57. AD8130 Harmonic Distortion
vs. Load Resistance
TPC 55. AD8130 Harmonic Distortion
vs. Common-Mode Voltage
TPC 56. AD8130 Harmonic Distortion
vs. Load Resistance
–36
–44
–48
G = 10
C
G = 10
G = 10
C
V
= 2V p-p
V
= 1V p-p
OUT
OUT
f
= 5MHz
V
= 2V p-p
f = 5MHz
OUT
= ꢂ5V
–42
–48
–54
–60
–66
–72
–54
V
–50
–56
–62
–68
–74
–80
S
R
= 1kꢁ
V
V
V
= ꢂ2.5V
= ꢂ12V
= ꢂ5V
V
V
V
= ꢂ2.5V
= ꢂ12V
= ꢂ5V
L
S
S
S
S
–60
–66
–72
–78
–84
–90
fC = 5MHz
S
S
HD2
V
= ꢂ12V
= ꢂ5V
S
S
V
= ꢂ2.5V
S
V
V
= ꢂ12V
HD2
S
HD3
HD3
HD3
1
V
= ꢂ2.5V
S
V
= ꢂ5V
S
–78
–5 –4 –3 –2 –1
0
2
3
4
5
100
1k
100
1k
V
– V
R
– ꢁ
CM
R
– ꢁ
L
L
TPC 58. AD8129 Harmonic Distortion
vs. Common-Mode Voltage
TPC 59. AD8129 Harmonic Distortion
vs. Load Resistance
TPC 60. AD8129 Harmonic Distortion
vs. Load Resistance
V
100
10
100
CM
200ꢁ
1:2
AD8130
R
L
C
L
10
R
R
F
G
AD8129
1.0
0.1
G
R
R
G
F
1
2
10
20
0ꢁ
499ꢁ
2kꢁ
2kꢁ
–
MINI CIRCUITS:
# T4 – 6T, fC Յ 10MHz
# TC4 – 1W, fC Ͼ 10MHz
499ꢁ
221ꢁ
105ꢁ
1.0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 61. AD8129/AD8130 Basic Distor-
tion Test Circuit, VCM = 0 V Unless
Otherwise Noted
TPC 62. AD8129/AD8130 Input
Current Noise vs. Frequency
TPC 63. AD8129/AD8130 Input
Voltage Noise vs. Frequency
–12–
REV. 0
AD8129/AD8130
–30
–40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–50
–60
–70
–80
V
= ꢂ2.5V
V
= ꢂ2.5V
S
–90
S
V
= ꢂ12V
S
–100
–110
–120
V
S
= ꢂ5V, ꢂ12V
V
= ꢂ5V
S
V
= ꢂ2.5V
V
= ꢂ12V
V
= ꢂ5V
S
S
S
10k
100k
1M
10M
100M
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 65. AD8130 Positive Power
Supply Rejection vs. Frequency
TPC 64. AD8130 Common-Mode
Rejection vs. Frequency
TPC 66. AD8130 Negative Power
Supply Rejection vs. Frequency
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= ꢂ2.5V
–80
–90
S
–60
–70
V
= ꢂ5V
V
= ꢂ12V
S
S
–100
–110
–120
–80
–90
V
= ꢂ2.5V
V
= ꢂ12V
S
S
V
= ꢂ5V, ꢂ12V
S
V
= ꢂ2.5V
V
= ꢂ5V
S
S
–100
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 67. AD8129 Common-Mode
Rejection vs. Frequency
TPC 69. AD8129 Negative Power
Supply Rejection vs. Frequency
TPC 68. AD8129 Positive Power
Supply Rejection vs. Frequency
100
10
80
90
80
180
70
60
50
40
30
20
10
0
180
135
GAIN
GAIN
70
V
= ꢂ5V
S
60
50
135
90
1
AD8130, G = 1
+
PHASE
90
40
PHASE
100m
10m
1m
V
–
V
OUT
OUT
30
+
2pF
2pF
1kꢁ
1kꢁ
–
20
45
0
45
0
1kꢁ
100ꢁ
1kꢁ
1kꢁ
φ
= 56ꢃ
M
10
0
V
V
IN
φ
= 58ꢃ
IN
M
AD8129, G = 10
–10
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M 100M 300M
1k
10k
100k
1M
10M 100M 300M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 70. AD8130 Open Loop Gain
and Phase vs. Frequency
TPC 72. Closed-Loop Output
Impedance vs. Frequency
TPC 71. AD8129 Open Loop Gain
and Phase vs. Frequency
REV. 0
–13–
AD8129/AD8130
AD8130 Transient Response Characteristics
(G = 1, RL = 1 kꢁ, CL = 2 pF, VS = ꢂ5 V, TA = 25ꢃC, unless otherwise noted.)
V
= 1V p-p
V
= 1V p-p
V
= 1V p-p
OUT
OUT
OUT
V
= ꢂ5V
V
= ꢂ12V
V
= ꢂ2.5V
S
S
S
5.00ns
250mV
5.00ns
5.00ns
250mV
250mV
TPC 73. AD8130 Transient Response,
VS = 2.5 V, VOUT = 1 V p-p
TPC 74. AD8130 Transient Response,
VS = 5 V, VOUT = 1 V p-p
TPC 75. AD8130 Transient Response,
VS = 12 V, VOUT = 1 V p-p
V
= ꢂ2.5V
V
= ꢂ2.5V
S
S
V
= 1V p-p
V
= 2V p-p
V
= 0.2V p-p
V = ꢂ2.5V
S
OUT
OUT
OUT
C
= 5pF
V
= ꢂ5V
C = 5pF
V
= ꢂ5V
L
S
L
S
V = ꢂ5V
S
V = ꢂ12V
S
V
= ꢂ12V
S
V
= ꢂ12V
S
5.00ns
250mV
5.00ns
5.00ns
500mV
50mV
TPC 77. AD8130 Transient Response
vs. Supply, VOUT = 1 V p-p, CL = 5 pF
TPC 76. AD8130 Transient Response
vs. Supply, VOUT = 0.2 V p-p
TPC 78. AD8130 Transient Response
vs. Supply, VOUT = 2 V p-p, CL = 5 pF
C
= 10pF
V
= 0.2V
p-p
L
OUT
C
C
= 5pF
= 2pF
L
2V p-p
1V p-p
4V p-p
2V p-p
L
1V p-p
0.5V p-p
10.0ns
50mV
5.00ns
500mV
5.00ns
1.00V
TPC 79. AD8130 Transient Response
vs. Load Capacitance, VOUT = 0.2 V p-p
TPC 80. AD8130 Transient Response
vs. Output Amplitude,
TPC 81. AD8130 Transient Response
vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
–14–
REV. 0
AD8129/AD8130
V
= 2V p-p
V
G = 2
= 1V p-p
OUT
G = 2
G = 2
= ꢂ5V
V
= 8V p-p
OUT
OUT
V
= ꢂ5V, C = 10pF
L
V
S
V
= ꢂ5V
S
S
C
= 10pF
L
V
= ꢂ5V, C = 2pF
L
V
= ꢂ12V
S
S
C
= 2pF
L
5.00ns
5.00ns
250mV
500mV
5.00ns
2.00V
TPC 82. AD8130 Transient Response
vs. Load Capacitance, VOUT = 1 V p-p,
G = 2
TPC 83. AD8130 Transient Response
vs. Supply, VOUT = 2 V p-p, G = 2
TPC 84. AD8130 Transient Response
vs. Load Capacitance, VOUT = 8 V p-p
G = 2
S
V
= 10V p-p
V
= ꢂ12V
OUT
V
IN
V
V
OUT
OUT
V
IN
5.00ns
1.00V
5.00ns
2.50V
5.00ns
1.00V
TPC 87. AD8130 Transient Response,
TPC 85. AD8130 Transient Response
with +3 V Common-Mode Input
TPC 86. AD8130 Transient Response
with –3 V Common-Mode Input
VOUT = 10 V p-p, G = 2, VS = 12 V
G = 5
S
G = 5
S
V
= 20V p-p
OUT
G = 5
S
V
= 8V p-p
V
= ꢂ12V
V
= ꢂ5V
OUT
V
= ꢂ5V
4V p-p
2V p-p
C
= 10pF
C
= 10pF
L
L
C
= 10pF
L
1V p-p
10.0ns
10.0ns
5.00V
10.0ns
2.00V
1.00V
TPC 90. AD8130 Transient Response,
OUT = 20 V p-p, G = 5, VS = 12 V
TPC 88. AD8130 Transient Response
vs. Output Amplitude
TPC 89. AD8130 Transient Response,
VOUT = 8 V p-p, G = 5, VS = 5 V
V
REV. 0
–15–
AD8129/AD8130
AD8129 Transient Response Characteristics
(G = 10, RF = 2 kꢁ, RG = 221 ꢁ, RL = 1 kꢁ, CL = 1 pF, VS = ꢂ5 V, TA = 25ꢃC, unless otherwise noted.)
V
= 1V p-p
V
= ꢂ12V
V
= 1V p-p
V
= 1V p-p
V
= ꢂ5V
V
= ꢂ2.5V
OUT
S
OUT
OUT
S
S
5.00ns
250mV
5.00ns
5.00ns
250mV
250mV
TPC 93. AD8129 Transient Response,
VS = 12 V, VOUT = 1 V p-p
TPC 91. AD8129 Transient Response,
VS = 2.5 V, VOUT = 1 V p-p
TPC 92. AD8129 Transient Response,
VS = 5 V, VOUT = 1 V p-p
V
= ꢂ5V
V = ꢂ2.5V
S
V
= 0.4V p-p
V
C
= 1V p-p
= 5pF
V
= ꢂ5V
V
C
= 2V p-p
= 5pF
S
OUT
OUT
S
OUT
V = ꢂ5V
V
= ꢂ2.5V
S
S
V
= ꢂ2.5V
L
L
S
V
= ꢂ12V
V
= ꢂ12V
V
= ꢂ12V
S
S
S
5.00ns
5.00ns
100mV
250mV
5.00ns
500mV
TPC 94. AD8129 Transient Response
vs. Supply, VOUT = 0.4 V p-p
TPC 95. AD8129 Transient Response
vs. Supply, VOUT = 1 V p-p, CL = 5 pF
TPC 96. AD8129 Transient Response
vs. Supply, VOUT = 2 V p-p, CL = 5 pF
C
= 5pF
V
= 0.4V p-p
L
OUT
V
= 2V p-p
= 1V p-p
V = 4V p-p
O
O
C
= 10pF
L
V
V
= 2V p-p
O
O
C
= 2pF
L
V
= 0.5V p-p
V
= 1V p-p
O
O
5.00ns
5.00ns
100mV
500mV
5.00ns
1.00V
TPC 97. AD8129 Transient Response
vs. Load Capacitance, VOUT = 0.4 V p-p
TPC 98. AD8129 Transient Response
vs. Output Amplitude,
TPC 99. AD8129 Transient Response
vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
–16–
REV. 0
AD8129/AD8130
V
= 2V p-p
V
= 1V p-p
V
= 8V p-p
G = 20
= 20pF
G = 20
= 20pF
OUT
OUT
G = 20
= 20pF
OUT
C
C
C
L
L
L
5.00ns
500mV
5.00ns
5.00ns
250mV
2.00V
TPC 101. AD8129 Transient Response,
VOUT = 2 V p-p, VS = 5 V
TPC 100. AD8129 Transient Response,
TPC 102. AD8129 Transient Response,
OUT = 8 V p-p, VS = 5 V
VOUT = 1 V p-p, VS = 2.5 V to 12 V
V
V
= 10V p-p
G = 20
S
OUT
V
V
= ꢂ12V
IN
C
= 20pF
L
V
OUT
V
OUT
V
IN
5.00ns
5.00ns
1.00V
2.50V
TPC 104. AD8129 Transient Response
with –3.5 V Common-Mode Input
TPC 103. AD8129 Transient Response
with +3.5 V Common-Mode Input
TPC105. AD8129TransientResponse,
VOUT = 10 V p-p, G = 20
V
= 8V p-p
G = 50
= ꢂ5V
V
= 20V p-p
G = 50
= ꢂ12V
G = 50
S
OUT
OUT
V
V
V
= ꢂ5V
S
S
4V p-p
2V p-p
C
= 20pF
C
= 10pF
C
= 20pF
L
L
L
1V p-p
12.5ns
2.00V
12.5ns
12.5ns
1.00V
5.00V
TPC 107. AD8129 Transient Response,
VOUT = 8 V p-p, G = 50, VS = 5 V
TPC 106. AD8129 Transient Response
vs. Output Amplitude, VOUT = 1 V p-p,
2 V p-p, 4 V p-p
TPC108. AD8129TransientResponse,
VOUT = 20 V p-p, G = 50, VS = 12 V
REV. 0
–17–
AD8129/AD8130
3.0
2.0
AD8130
= 100mV AC @ 1kHz
23
20
17
14
11
37
31
25
19
13
G = 1
= ꢂ5V
G = 10
= ꢂ10V
V
V
S
S
V
OUT
1.0
AD8129
AD8130
0.0
–1.0
–2.0
–3.0
–5 –4 –3 –2 –1
0
1
2
3
4
5
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL INPUT – V
DIFFERENTIAL INPUT – V
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
TPC 109. AD8130 DC Power Supply
Current vs. Differential Input Voltage
TPC 111. AD8129/AD8130 Input
Differential Voltage Range vs. Tem-
perature, 1% Gain Compression
TPC 110. AD8129 DC Power Supply
Current vs. Differential Input Voltage
4
3
G = 1
G = 1
V
= ꢂ5V
= 1kꢁ
S
V
= ꢂ5V
= 1kꢁ
S
V
= ꢂ5V
R
S
L
R
L
2
1
0
–1
–2
–3
–4
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5
–5 –4 –3 –2 –1
0
1
2
3
4
5
OUTPUTVOLTAGE – V
OUTPUTVOLTAGE – V
DIFFERENTIAL INPUT – V
TPC 112. AD8130 Gain Nonlinearity,
VOUT = 2 V p-p
TPC 113. AD8130 Gain Nonlinearity,
VOUT = 5 V p-p
TPC 114. AD8130 Differential Input
Clipping Level
8
6
G = 10
G = 10
V
= ꢂ5V
= 1kꢁ
V
= ꢂ12V
= 1kꢁ
S
S
V
= ꢂ10V
R
R
S
L
L
4
2
0
–2
–4
–6
–8
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
–5 –4 –3 –2 –1
0
1
2
3
4
5
OUTPUTVOLTAGE – V
DIFFERENTIAL INPUT – V
OUTPUTVOLTAGE – V
TPC 116. AD8129 Gain Nonlinearity,
VOUT = 10 V p-p
TPC 115. AD8129 Gain Nonlinearity,
VOUT = 2 V p-p
TPC 117. AD8129 Differential Input
Clipping Level
–18–
REV. 0
AD8129/AD8130
17
16
15
14
13
0.60
0.45
0.30
0.15
40
30
20
10
15
14
13
12
11
10
9
V
= ꢂ12V
I
S
B
V
= ꢂ5V
S
I
OS
12
11
10
9
V
= ꢂ2.5V
S
8
7
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
0
5
10
15
20
25
30
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
TOTAL SUPPLYVOLTAGE – V
TPC 119. Quiescent Power Supply
Current vs. Temperature
TPC 118. Quiescent Power Supply
Current vs. Total Supply Voltage
TPC 120. Input Bias Current and
Input Offset Current vs. Temperature
4.00
3.75
4.00
3.75
11.0
10.5
AD8130
AD8130
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
3.50
3.25
AD8130
10.0
AD8129
= 5V
V
= ꢂ12V
S
9.5
9.0
AD8129
V
S
V
= ꢂ5V
AD8129
= 100mV
S
3.00
V
= 100mV
OUT
V
OUT
AC AT 1kHz
V
= 100mV
AC AT 1kHz
2.75
8.5
OUT
AC AT 1kHz
–3.00
–3.25
–3.50
–3.75
–4.00
–9.0
–9.5
–10.0
–10.5
–11.0
AD8129
AD8130
AD8129
AD8130
AD8130
AD8129
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – ꢃC
TPC 121. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
TPC 122. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
TPC 123. Common-Mode Voltage
Range vs. Temperature, Typical 1%
Gain Compression
11
4.0
4.0
V
= ꢂ5V
V
= ꢂ12V
V
= 5V
S
S
S
10
9
3.5
3.0
3.5
3.0
SOURCING
+100ꢃC –40ꢃC +25ꢃC
+100ꢃC –40ꢃC +25ꢃC
+100ꢃC –40ꢃC +25ꢃC
–9
–10
–11
–3.0
–3.5
–4.0
2.0
1.5
1.0
SINKING
V
= 100mV
V
= 100mV
OUT
V
= 100mV
OUT
OUT
AC AT 1kHz
AC AT 1kHz
AC AT 1kHz
0
5
10 15
20
25
30
35 40
0
5
10 15
20
25
30
35 40
0
5
10 15
20
25
30
35 40
OUTPUT CURRENT – mA
OUTPUT CURRENT – mA
OUTPUT CURRENT – mA
TPC 125. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
TPC 124. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
TPC 126. Output Voltage Range vs.
Output Current, Typical 1% Gain
Compression
REV. 0
–19–
AD8129/AD8130
THEORY OF OPERATION
Thus, the input dynamic ranges are limited to about 2.5 V for
the AD8130 and 0.5 V for the AD8129 (see Specification
section for more detail). For this and other reasons, it is not
recommended to reverse the input and feedback stages of the
AD8129/AD8130, even though some apparently normal func-
tionality might be observed under some conditions.
The AD8129/AD8130 use an architecture called active feed-
back which differs from that of conventional op amps. The
most obvious differentiating feature is the presence of two sepa-
rate pairs of differential inputs compared to a conventional op
amp’s single pair. Typically for the active-feedback architecture,
one of these input pairs is driven by a differential input signal,
while the other is used for the feedback. This active stage in the
feedback path is where the term “active feedback” is derived.
A few simple circuits can illustrate how the active feedback
architecture of the AD8129/AD8130 operates.
Op Amp Configuration
The active feedback architecture offers several advantages over a
conventional op amp in several types of applications. Among
these are excellent common-mode rejection, wide input common-
mode range and a pair of inputs that are high-impedance and
totally balanced in a typical application. In addition, while an
external feedback network establishes the gain response as
in a conventional op amp, its separate path makes it totally
independent of the signal input. This eliminates any interaction
between the feedback and input circuits, which traditionally
causes problems with CMRR in conventional differential-input
op amp circuits.
If only one of the input stages of the AD8129/AD8130 is used,
it will function very much like a conventional op amp. (See
Figure 4.) Classical inverting and noninverting op amps circuits
can be created, and the basic governing equations will be the
same as for a conventional op amp. The unused input pins form
the second input and should be shorted together and tied to
ground or some midsupply voltage when they are not used.
+V
0.1ꢀF
10ꢀF
Another advantage is the ability to change the polarity of the
gain merely by switching the differential inputs. A high input-
impedance inverting amplifier can be made. Besides a high
input impedance, a unity-gain inverter with the AD8130 will
have a noise gain of unity. This will produce lower output noise
and higher bandwidth than op amps that have noise gain equal
to 2 for a unity gain inverter.
+
+
PD +V
S
V
OUT
V
IN
–V
S
R
F
The two differential input stages of the AD8129/AD8130 are each
transconductance stages that are well matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensa-
tion capacitor is in the summing circuit.
R
G
0.1ꢀF
10ꢀF
–V
Figure 4. With both inputs grounded, the feedback stage
functions like an op amp: VOUT = VIN (1 + RF/RG). NOTE: This
circuit is provided to demonstrate device operation. It is
not suggested to use this circuit in place of an op amp.
When the feedback path is closed around the part, the output
will drive the feedback input to that voltage which causes the
internal currents to sum to zero. This occurs when the two
differential inputs are equal and opposite; that is, their algebraic
sum is zero.
With the unused pair of inputs shorted, there is no differential
voltage between them. This dictates that the differential input
voltage of the used inputs will also be zero for closed-loop
applications. Since this is the governing principle of conven-
tional op amp circuits, an active feedback amplifier can function
as a conventional op amp under these conditions.
In a closed-loop application, a conventional op amp will have its
differential input voltage driven to near zero under nontransient
conditions. The AD8129/AD8130 generally will have differential
input voltages at each of its input pairs, even under equilibrium
conditions. As a practical consideration, it is necessary to inter-
nally limit the differential input voltage with a clamp circuit.
Note that this circuit is presented only for illustration purposes,
to show the similarities of the active feedback architecture func-
tionality to conventional op amp functionality. If it is desired to
design a circuit that can be created from a conventional op amp,
it is recommended to choose a conventional op amp whose
specifications are better suited to that application. These op amp
principles are the basis for offsetting the output as described in
the Output Offset/Level Translator section.
–20–
REV. 0
AD8129/AD8130
Twisted-Pair Cable, Composite Video Receiver with Equal-
ization Using an AD8130
APPLICATIONS
Basic Gain Circuits
The AD8130 has excellent common-mode rejection at its inputs.
This makes it an ideal candidate for a receiver for signals that
are transmitted over long distances on twisted-pair cables. Cat-
egory 5 type cables are now very common in office settings and
are extensively used for data transmission. These same cables
can also be used for the analog transmission of signals like video.
The gain of the AD8129/AD8130 can be set with a pair of feed-
back resistors. The basic configuration is shown in Figure 5.
The gain equation is the same as that of a conventional op amp:
G = 1 + RF/RG. For unity gain applications using the AD8130,
RF can be set to zero (short circuit), and RG can be removed.
(See Figure 6.) The AD8129 is compensated to operate at gains
of 10 and higher, so shorting the feedback path to obtain unity
gain will cause oscillation.
These long cables will pick up noise from the environment they
pass through. This noise will not favor one conductor over an-
other, and will therefore be a common-mode signal. A receiver
that rejects the common-mode signal on the cable can greatly
enhance the signal-to-noise ratio performance of the link.
+V
AD8129/
AD8130
0.1ꢀF
10ꢀF
The AD8130 is also very easy to use as a differential receiver,
because the differential inputs and the feedback inputs are
entirely separate. This means that there is no interaction of the
feedback network and the termination network as there would
be in conventional op amp-type receivers.
+
+
+V
S
PD
V
IN
V
OUT
–V
S
Another issue to be dealt with on long cables is the attenuation
of the signal at longer distances. This attenuation is a function of
frequency and increases as roughly as the square root of frequency.
R
F
R
G
0.1ꢀF
10ꢀF
For good fidelity of video circuits, the overall frequency response
of the transmission channel should be flat versus frequency. Since
the cable attenuates the high frequencies, a frequency-selective
boost circuit can be used to undo this effect. These circuits
are called equalizers.
–V
Figure 5. Basic Gain Circuit: VOUT = VIN (1 + RF/RG)
+V
An equalizer uses frequency-dependent elements (Ls and Cs) in
order to create a frequency response that is the opposite of the
rest of the channel’s response in order to create an overall flat
response. There are many ways to create such circuits, but a
common technique is to put the frequency-selective elements in
the feedback path of an op amp circuit. The AD8130 in particu-
lar makes this easier than other circuits, because, once again, the
feedback path is totally independent of the input path and there
is no interaction.
AD8130
10ꢀF
0.1ꢀF
+
+
+V
S
PD
V
IN
V
OUT
–V
S
The circuit in Figure 7 was developed as a receiver/equalizer for
transmitting composite video over 300 m of Category 5 cable. This
cable has an attenuation of approximately 20 dB at 10 MHz
for 300 m. At 100 MHz, the attenuation is approximately
60 dB. (See Figure 8.)
0.1ꢀF 10ꢀF
–V
Figure 6. An AD8130 with Unity Gain
The input signal can be applied either differentially or single-
endedly—all that matters is the magnitude of the differential
signal between the two inputs. For single-ended input applica-
tions, applying the signal to the +IN with –IN grounded will
create a noninverting gain, while reversing these connections
will create an inverting gain. Since the two inputs are high-
impedance and matched, both of these conditions will provide
the same high input impedance. Thus, an advantage of the
active feedback architecture is the ability to make a high-input-
impedance, inverting op amp. If conventional op amps are used,
a high impedance buffer followed by an inverting stage is needed.
This requires two op amps.
+V
AD8130
10ꢀF
0.1ꢀF
+
+
+V
S
PD
V
100ꢁ
IN
V
OUT
–V
S
R
1kꢁ
F
R1
100ꢁ
R
G
10ꢀF
0.1ꢀF
499ꢁ
–V
C1
200pF
Figure 7. An Equalizer Circuit for Composite Video
Transmission over 300 m of Category 5 Cable
REV. 0
–21–
AD8129/AD8130
20
10
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 10. Combined Response of Cable Plus Equalizer
Figure 8. Transmission Response of 300 m of
Category 5 Cable
Output Offset/Level Translator
The circuit in Figure 6 has the reference input (Pin 4) tied to
ground, which produces a ground-referenced output signal. If it is
desired to offset the output voltage from ground, the REF input
can be used. (See Figure 11). The level VOFFSET appears at the
output with unity gain.
The feedback network is between Pins 6 and 5 and from Pin 5
to ground. C1 and RF create a corner frequency of about 800 kHz.
The gain increases to provide about 15 dB of boost at 8 MHz.
The response of this circuit is shown in Figure 9.
20
10
+V
0
AD8130
10ꢀF
0.1ꢀF
–10
–20
–30
–40
–50
–60
–70
–80
+
+
+V
S
PD
V
IN
V
= V +V
IN
OUT
OFFSET
V
OFFSET
–V
S
0.1ꢀF
10ꢀF
–V
10k
100k
1M
10M
100M
Figure 11. The voltage applied to Pin 4 adds to the unity-
gain output voltage produced by VIN.
FREQUENCY – Hz
Figure 9. Frequency Response of Equalizer Circuit
If the circuit has a gain higher than unity, the gain has to be
factored in. If RG is connected to ground, the voltage applied to
REF will be multiplied by the gain of the circuit and appear at
the output; just like a noninverting conventional op amp, This
situation is not always desirable and one may want VOFFSET to
appear at the output with unity gain.
It is difficult to come up with the exact component values via
strictly mathematical means, because the equations for the cable
attenuation are approximate and have functions that are not
simply related to the responses of RC networks. The method
used in this design was to approximate the required response via
graphical means from the frequency response, and then select
components that would approximate this response. The circuit
was then built and measured, and finally adjusted to obtain an
acceptable response—in this case flat to 9 MHz to within
approximately 1 dB. (See Figure 10.)
One way to accomplish this is to drive both REF and RG with
the desired offset signal. (See Figure 12.) Superposition can be
used to solve this circuit. First break the connection between
VOFFSET and RG. With RG grounded the gain from Pin 4 to
VOUT will be 1 + RF/RG. With Pin 4 grounded, the gain though
RG to VOUT is –RF/RG. The sum of these is +1. If VREF is delivered
from a low-impedance source, this will work fine. However, if
the delivered offset voltage is derived from a high-impedance
source, like a voltage divider, its impedance will affect the gain
equation. This makes the circuit more complicated as it creates
an interaction between the gain and offset voltage.
–22–
REV. 0
AD8129/AD8130
Summer
+V
+V
A general summing circuit can be made by the above technique.
A unity-gain configured AD8130 has one signal applied to +IN,
while the other signal is applied to REF. The output will be the
sum of the two input signals. (See Figure 15.)
AD8129/
AD8130
10ꢀF
0.1ꢀF
+
+
PD
S
V
IN
+V
V
V
=
OUT
ꢄ (1+ R /R ) +V
OFFSET
V
OFFSET
IN
F
G
–V
S
AD8130
R
G
10ꢀF
0.1ꢀF
V1
V2
+
+
+V
PD
S
R
F
0.1ꢀF
10ꢀF
V
= V1 + V2
OUT
–V
–V
S
Figure 12. In this circuit, VOFFSET appears at the output
with unity gain. This circuit works well if the VOFFSET
Source Impedance is low.
0.1ꢀF
10ꢀF
–V
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the ampli-
fier, and then apply this voltage to the high-impedance REF
input. This circuit will first divide the desired offset voltage by
the gain, and the amplifier will multiply it back up to unity. (See
Figure 13.)
Figure 15. A Summing Circuit that is Noninverting with
High Input Impedance
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both high-
impedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
+V
AD8129/
AD8130
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for every additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s,
and then summing the two outputs by a third AD8130.
10ꢀF
0.1ꢀF
+
+
+V
S
PD
V
IN
V
V
=
OUT
R
F
V
ꢄ (1+R /R ) + V
OFFSET
IN
F
G
OFFSET
–V
S
R
G
Cable-Tap Amplifier
R
It is often desirable to have a video signal drive several different
pieces of equipment. However, the cable should only be termi-
nated once at its end point, so it is not appropriate to have a
termination at each device. A “loop-through” connection allows
a device to tap the video signal while not disturbing it by any
excessive loading.
F
R
G
0.1ꢀF
10ꢀF
–V
Figure 13. Adding an attenuator at the offset input causes
it to appear at the output with unity gain.
Resistorless Gain-of-Two
Such a connection, also referred to as a cable-tap amplifier, can
be simply made with an AD8130. (See Figure 16.) The circuit is
configured with unity gain, and if no output offset is desired,
the REF pin is grounded. The negative differential input is
connected directly to the shield of the cable (or an associated
connector) at the point at which it wants to be “tapped.”
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there will be unity gain from
VIN and unity gain from VREF. Thus, the circuit will have a gain
of two, and requires no resistors. (See Figure 14.)
+V
+V
AD8130
AD8130
75ꢁ
10ꢀF
0.1ꢀF
10ꢀF
0.1ꢀF
+
+
+V
PD
S
V
+
+
+V
IN
PD
S
V
OUT
V
OUT
–V
S
–V
S
VIDEO
IN
0.1ꢀF
10ꢀF
0.1ꢀF
10ꢀF
–V
–V
75ꢁ
Figure 16. The AD8130 can tap the video signal at any
point along the cable without loading the signal.
Figure 14. Gain-of-Two Connections with No Resistors
REV. 0
–23–
AD8129/AD8130
+V
+V
The center conductor connects to the positive differential input
of the AD8130. The amplitude of the video signal at this point
is unity, because it is between the two termination resistors. The
AD8130 provides a high impedance to this signal, so it does not
disturb it. A buffered, unity-gain version of the video signal
appears at the output.
AD8130
10ꢀF
0.1ꢀF
V
V
IN
+
PD
S
1N4148
V
OUT
+
Power-Down
IN
–V
S
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
used. A logic low level on the PD pin will cause the part to
power down.
0.1ꢀF
10ꢀF
–V
Since there is no “Ground” pin on the AD8129/AD8130, there
is no logic reference to interface to standard logic levels. For
this reason, the reference level for the PD input is +VS. If the
AD8129/AD8130 are run with +VS = 5 V, there will be direct
compatibility with logic families. However, if +VS is higher
than this, a level-shift circuit will be needed to interface to con-
ventional logic levels. A simple level-shifting circuit that is
compatible with common logic families is presented in Figure 17.
Figure 18. Clamping Diodes at the Input Limit the Input
Swing Amplitude
Another problem can occur with the AD8129 operating at supply
voltage of greater than or equal to 12 V. The architecture
causes the supply current to increase as the input differential
voltage increases. If the AD8129 differential inputs are over-
driven too far, excessive current can flow in the device and
potentially cause permanent damage.
+V
S
A practical means to prevent this from occurring is to differentially
clamp the inputs with a pair of antiparallel Schottky diodes.
(See Figure 19.) These diodes have a lower forward voltage
of approximately 0.4 V. If the differential voltage across the
inputs is restricted to these conditions, no excess current will
be drawn by the AD8129 under these operating conditions.
7
+V
1kꢁ
S
3
PD
4.99kꢁ
2N2222
OR EQ
LOW=
POWER-DOWN
AD8129/
AD8130
If the supply voltage is restricted to less than 11 V, the internal
clamping circuit will limit the differential voltage and excessive
supply current will not be drawn. The external clamp circuit is
not needed.
Figure 17. Circuit that Shifts the Logic Level when +VS Is
Not Equal to Approximately 5 V
Extreme Operating Conditions
The AD8129/AD8130 are designed to provide high perfor-
mance over a wide range of supply voltages. However, there are
some extremes of operating conditions that have been observed
to produce non-optimal results. One of these conditions occurs
when the AD8130 is operated at unity gain with low supply
voltage—less than approximately 4 V.
+V
AD8129
10ꢀF
0.1ꢀF
V
IN
3
+
+
+V
PD
S
AGILENT
HSMS 2822
V
OUT
1
2
V
At unity gain, the output drives FB directly. At supplies of VS
less than approximately 4 V and unity gain, the voltage on FB
can be driven by the output too close to the rail for the circuit to
stay properly biased. This can lead to a parasitic oscillation.
IN
–V
S
A way to prevent this is to limit the input signal swing with
clamp diodes. Common silicon junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flow through them. Two series pairs of such
diodes connected antiparallel across the differential inputs can
be used to clamp the input signal and prevent this condition. It
should be noted that the REF input can also shift the output
signal, so this technique will only work when REF is at ground
or close to it. (See Figure 18.)
0.1ꢀF
10ꢀF
–V
Figure 19. Schottky Diodes Across the Inputs Limits the
Input Differential Voltage
In both circuits, the input series resistors function to limit the
current through the diodes when they are forward-biased. As a
practical matter, these resistors need to be matched to the degree
that the CMRR needs to be preserved at high frequency. These
resistor will have minimal effect on the CMRR at low frequency.
–24–
REV. 0
AD8129/AD8130
Power Dissipation
The load current will be 6 V/250 Ω = 24 mA. This same current
will flow through the output across a 6 V drop from +VS. This
will dissipate 144 mW. For the Micro_SO-8 package, this causes a
temperature rise of 20°C above ambient. Although this is a worst-
case number, it is apparent that this can be a considerable
additional amount of power dissipation.
The AD8129/AD8130 can operate with supply voltages from
+5 V to 12 V. The major reason for such a wide supply range
is to provide a wide input common-mode range for systems
that might require this. This would be encountered when sig-
nificant common-mode noise couples into the input path. For
applications that do not require a wide input or output dynamic
range, it is recommended to operate with lower supply voltages.
Several changes can be made to alleviate this. One is to use the
standard SO-8 package. This will lower the thermal impedance
to 121°C/W, which is a 15% improvement. Next is to use a
lower supply voltage unless absolutely necessary.
The AD8129/AD8130 is also available in a very small Micro_SO-8
package. This has higher thermal impedance than larger packages
and will operate at a higher temperature with the same amount
of power dissipation. Certain operating conditions that are within
the specification range of the parts can cause excess power dissi-
pation. Caution should be exercised.
Finally, do not use the AD8129/AD8130 to directly drive a
heavy load when it is operating on high supply voltages. It is
best to use a second op amp after the output stage. Some of the
gain can be shifted to this stage so that the signal swing at the
output of the AD8129/AD8130 is not too large.
The power dissipation is a function of several operating condi-
tions. These include the supply voltage, the input differential
voltage, the output load and the signal frequency.
Layout, Grounding and Bypassing
The AD8129/AD8130 are very high-speed parts that can be
sensitive to the PCB environment in which they have to oper-
ate. Realizing their superior specifications requires attention
to various details of standard high-speed PCB design practice.
A basic starting point is to calculate the quiescent power dissipa-
tion with no signal and no differential input voltage. This is just
the product of the total supply voltage and the quiescent operat-
ing current. The maximum operating supply voltage is 26.4 V
and the quiescent current is 13 mA. This causes a quiescent
power dissipation of 343 mW. For the Micro_SO package, the
The first requirement is for a good solid ground plane that cov-
ers as much of the board area around the AD8129/AD8130 as
possible. The only exception to this is that the ground plane
around the FB pin should be kept a few mm away, and ground
should be removed from inner layers and the opposite side of
the board under this pin. This will minimize the stray capaci-
tance on this node and help preserve the gain flatness versus
frequency.
θ
JA specification is 142°C/W. So the quiescent power will cause
about a 49°C rise above ambient in the Micro_SO package.
The current consumption is also a function of the differential
input voltage. (See TPCs 109 and 110.) This current should be
added on to the quiescent current and then multiplied by the
total supply voltage to calculate the power.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high-frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be provided
with 10 µF tantalum capacitors from each supply to ground.
The AD8129/AD8130 can directly drive loads of as low as
100 Ω, such as a terminated 50 Ω cable. The worst-case power
dissipation in the output stage occurs when the output is at
midsupply. As an example, for a 12 V supply and the output
driving a 250 Ω load to ground, the maximum power dissipation
in the output will occur when the output voltage is 6 V.
The signal routing should be short and direct in order to avoid
parasitic effects. Where possible, signals should be run over
ground planes to avoid radiating, or to avoid being susceptible
to other radiation sources.
REV. 0
–25–
AD8129/AD8130
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
ꢄ 45ꢃ
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8ꢃ
0ꢃ
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
8-Lead Micro_SO
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33ꢃ
0.018 (0.46)
0.008 (0.20)
27ꢃ
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
–26–
REV. 0
–27–
–28–
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