AD8131ARMZ-REEL7 [ADI]
Low Cost, High Speed Differential Driver; 低成本，高速差分驱动器
| 型号： | AD8131ARMZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Cost, High Speed Differential Driver |
| 文件： | 总20页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, High Speed
Differential Driver
AD8131
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High speed
400 MHz, −3 dB full power bandwidth
2000 V/μs slew rate
Fixed gain of 2 with no external components
Internal common-mode feedback to improve gain and phase
balance: −60 dB @ 10 MHz
–D
1
2
3
4
8
7
6
5
+D
IN
IN
750Ω
750Ω
V
NC
OCM
V+
V–
1.5kΩ
1.5kΩ
+OUT
–OUT
AD8131
Separate input to set the common-mode output voltage
Low distortion: 68 dB SFDR @ 5 MHz 200 Ω load
Power supply range +2.7 V to 5 V
NC = NO CONNECT
Figure 1.
APPLICATIONS
Video line driver
Digital line driver
Low power differential ADC driver
Differential in/out level shifting
Single-ended input to differential output driver
GENERAL DESCRIPTION
–20
–30
–40
–50
The AD8131 is a differential or single-ended input to
differential output driver requiring no external components for
a fixed gain of 2. The AD8131 is a major advancement over op
amps for driving signals over long lines or for driving
differential input ADCs. The AD8131 has a unique internal
feedback feature that provides output gain and phase matching
that are balanced to −60 dB at 10 MHz, reducing radiated EMI
and suppressing harmonics. Manufactured on the Analog
Devices, Inc. next generation XFCB bipolar process, the
AD8131 has a −3 dB bandwidth of 400 MHz and delivers a
differential signal with very low harmonic distortion.
ΔV
ΔV
= 2V p-p
OUT, dm
OUT, cm
/ΔV
OUT, dm
V
= +5V
S
–60
–70
–80
V
= ±5V
S
The AD8131 is a differential driver for the transmission of
high-speed signals over low-cost twisted pair or coax cables.
The AD8131 can be used for either analog or digital video
signals or for other high-speed data transmission. The AD8131
driver is capable of driving either Cat3 or Cat5 twisted pair or
coax with minimal line attenuation. The AD8131 has
considerable cost and performance improvements over discrete
line driver solutions.
1
10
100
1000
FREQUENCY (MHz)
Figure 2. Output Balance Error vs. Frequency
The AD8131’s differential output also helps balance the input
for differential ADCs, optimizing the distortion performance of
the ADCs. The common-mode level of the differential output is
adjustable by a voltage on the VOCM pin, easily level-shifting the
input signals for driving single-supply ADCs with dual supply
signals. Fast overload recovery preserves sampling accuracy.
The AD8131 can replace transformers in a variety of applications,
preserving low frequency and dc information. The AD8131 does
not have the susceptibility to magnetic interference and hysteresis
of transformers. It is smaller, easier to work with, and has the high
reliability associated with ICs.
The AD8131 is available in both SOIC and MSOP packages for
operation over −40°C to +125°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
AD8131
TABLE OF CONTENTS
Specifications..................................................................................... 3
Estimating the Output Noise Voltage...................................... 16
DIN to OꢀT Specifications...................................................... 3
VOCM to OꢀT Specifications ..................................................... 4
DIN to OꢀT Specifications...................................................... 5
VOCM to OꢀT Specifications ..................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Operational Description................................................................ 15
Theory of Operation ...................................................................... 16
Analyzing an Application Circuit............................................. 16
Closed-Loop Gain ...................................................................... 16
Calculating the Input Impedance of an
Application Circuit..................................................................... 16
Input Common-Mode Voltage Range in
Single-Supply Applications ....................................................... 17
Setting the Output Common-Mode Voltage.......................... 17
Driving a Capacitive Load......................................................... 17
Applications..................................................................................... 18
Twisted-Pair Line Driver........................................................... 18
3 V Supply Differential A-to-D Driver.................................... 18
ꢀnity-Gain, Single-Ended-to-Differential Driver ................. 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/05—Rev. A to Rev. B
ꢀpdated Format..................................................................ꢀniversal
Changed ꢀpper Operating Limit .....................................ꢀniversal
Changes to Ordering Guide .......................................................... 20
Rev. B | Page 2 of 20
AD8131
SPECIFICATIONS
DIN TO OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, 10% to 90%
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V Step
400
320
85
2000
14
MHz
MHz
MHz
V/μs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
5
ns
VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
f = 20 MHz
NTSC, RL, dm = 150 Ω
NTSC, RL, dm = 150 Ω
−68
−63
−95
−79
−94
−70
−101
−77
−54
30
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
IP3
dBc
dBm
nV/√Hz
%
Voltage Noise (RTO)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Input Resistance
25
0.01
0.06
degrees
Single-ended input
Differential input
1.125
1.5
1
−7.0 to +5.0
−70
kΩ
kΩ
pF
V
Input Capacitance
Input Common-Mode Voltage
CMRR
ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = 0.5 V
dB
OUTPUT CHARACTERISTICS
Offset Voltage (RTO)
VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 0 V
TMIN to TMAX variation
VOCM = float
TMIN to TMAX variation
Maximum ΔVOUT; single-ended output
2
8
4
10
7
mV
μV/°C
mV
μV/°C
V
mA
V/V
dB
Output Voltage Swing
Linear Output Current
Gain
−3.6 to +3.6
60
2
ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = 0.5 V
ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V
1.97
2.03
Output Balance Error
−70
Rev. B | Page 3 of 20
AD8131
VOCM TO OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
ΔVOCM = 600 mV
VOCM = −1 V to +1 V
210
500
MHz
V/μs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
3.6
120
1.5
2.5
0.5
−60
1
V
kΩ
mV
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V
VOCM = float
7
Input Bias Current
VOCM CMRR
Gain
ΔVOUT, dm/ΔVOCM; ΔVOCM = 0.5 V
ΔVOUT, cm/ΔVOCM; ΔVOCM = 1 V
0.988
1.012
POWER SUPPLY
Operating Range
Quiescent Current
1.4
10.5
5.5
12.5
V
VDIN+ = VDIN− = VOCM = 0 V
TMIN to TMAX variation
ΔVOUT, dm/ΔVS; ΔVS = 1 V
11.5
25
−70
mA
μA/°C
dB
Power Supply Rejection Ratio
−56
OPERATING TEMPERATURE RANGE
−40
+125
°C
Rev. B | Page 4 of 20
AD8131
DIN TO OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, 10% to 90%
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V Step
385
285
65
1600
18
MHz
MHz
MHz
V/μs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
5
ns
VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
f = 20 MHz
NTSC, RL, dm = 150 Ω
NTSC, RL, dm = 150 Ω
−67
−56
−94
−77
−74
−67
−95
−74
−51
29
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
IMD
IP3
dBc
dBm
nV/√Hz
%
Voltage Noise (RTO)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Input Resistance
25
0.02
0.08
degrees
Single-ended input
Differential input
1.125
1.5
1
−1.0 to +4.0
−70
kΩ
kΩ
pF
V
Input Capacitance
Input Common-Mode Voltage
CMRR
ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = 0.5 V
dB
OUTPUT CHARACTERISTICS
Offset Voltage (RTO)
VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 2.5 V
TMIN to TMAX variation
VOCM = float
TMIN to TMAX variation
Maximum ΔVOUT; single-ended output
3
8
4
7
mV
μV/°C
mV
μV/°C
V
mA
V/V
dB
10
1.0 to 3.7
45
Output Voltage Swing
Linear Output Current
Gain
ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = 0.5 V
ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V
1.96
2
2.04
Output Balance Error
−62
Rev. B | Page 5 of 20
AD8131
VOCM TO OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
ΔVOCM = 600 mV
VOCM = 1.5 V to 3.5 V
200
450
MHz
V/μs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
1.0 to 3.7
30
5
10
0.5
−60
1
V
kΩ
mV
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V
VOCM = float
12
Input Bias Current
VOCM CMRR
Gain
ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V 0.5 V
ΔVOUT, cm/ΔVOCM; ΔVOCM = 2.5 V 1 V
0.985
1.015
POWER SUPPLY
Operating Range
Quiescent Current
2.7
9.25
11
11.25
V
VDIN+ = VDIN− = VOCM = 2.5 V
TMIN to TMAX variation
ΔVOUT, dm/ΔVS; ΔVS = 0.5 V
10.25
20
−70
mA
μA/°C
dB
Power Supply Rejection Ratio
−56
OPERATING TEMPERATURE RANGE
−40
+125
°C
Rev. B | Page 6 of 20
AD8131
ABSOLUTE MAXIMUM RATINGS
Table 5.1
Parameter
Supply Voltage
VOCM
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
1 Thermal resistance measured on SEMI standard 4-layer board.
8-lead SOIC: θJA = 121°C/W.
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only, functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
5.5 V
VS
250 mW
−40°C to +125°C
−65°C to +150°C
300°C
2.0
T
= 150°C
J
8-lead MSOP: θJA = 142°C/W.
8-LEAD SOIC
PACKAGE
1.5
1.0
0.5
0
8-LEAD
MSOP
PACKAGE
100
130
–50
–20
10
40
70
AMBIENT TEMPERATURE (°C)
Figure 3. Plot of Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 20
AD8131
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–D
1
2
3
4
8
7
6
5
+D
IN
IN
750Ω
750Ω
V
NC
OCM
V+
V–
1.5kΩ
1.5kΩ
+OUT
–OUT
AD8131
NC = NO CONNECT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
−DIN
VOCM
Negative Input.
Common-Mode Output Voltage. Voltage applied to this pin sets the common-mode output voltage with a ratio of
1:1. For example, 1 V dc on VOCM will set the dc bias level on +OUT and −OUT to 1 V.
3
4
5
6
7
8
V+
Positive Supply Voltage.
+OUT
−OUT
V−
NC
+DIN
Positive Output. Note: the voltage at −DIN is inverted at +OUT.
Negative Output. Note: the voltage at +DIN is inverted at −OUT.
Negative Supply Voltage.
No Connect.
Positive Input.
Rev. B | Page 8 of 20
AD8131
TYPICAL PERFORMANCE CHARACTERISTICS
12
9
V
V
= 2V p-p
OUT
= ±5V
S
1500Ω
MSOP
6
3
750Ω
49.9Ω
R
= 200Ω
SOIC
AD8131
L, dm
750Ω
24.9Ω
0
1500Ω
–3
1
10
100
1000
FREQUENCY (MHz)
Figure 5. Basic Test Circuit
Figure 8. Large Signal Frequency Response
12
9
12
9
V
V
= 200mV p-p
OUT
= ±5V
V
= 2V p-p
OUT
S
V
= ±5V
S
MSOP
6
3
6
3
V
= +5V
S
SOIC
0
0
–3
–3
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response
Figure 6. Small Signal Frequency Response
12
9
V
= 200mV p-p
OUT
1500Ω
V
= ±5V
2:1 TRANSFORMER
S
6
3
750Ω
750Ω
300Ω
HPF
= 50Ω
LPF
49.9Ω
Z
IN
AD8131
300Ω
V
= +5V
S
24.9Ω
0
1500Ω
–3
1
10
100
1000
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response
Figure 10. Harmonic Distortion Test Circuit (RL, dm = 800 Ω)
Rev. B | Page 9 of 20
AD8131
–50
–60
–70
–80
–50
–60
–70
–80
R
V
= 800Ω
V
R
= 5V
L, dm
S
= 1V p-p
= 800Ω
OUT, dm
L, dm
HD3 (F = 20MHz)
HD3 (V = 3V)
S
HD3 (V = 5V)
S
HD2 (F = 20MHz)
HD3 (F = 5MHz)
HD2 (V = 3V)
S
–90
–90
–100
–110
HD2 (V = 5V)
S
–100
HD2 (F = 5MHz)
–110
0
10
20
30
40
50
60
70
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 11. Harmonic Distortion vs. Frequency
Figure 14. Harmonic Distortion vs. Differential Output Voltage
–50
–40
V
R
= 3V
R
= 800Ω
= 2V p-p
S
L, dm
HD3 (V = ±5V)
S
HD3 (F = 5MHz)
= 800Ω
V
L, dm
OUT, dm
–50
–60
–60
–70
–80
HD3 (F = 20MHz)
HD3 (V = +5V)
S
–70
–80
HD2 (F = 20MHz)
HD2 (V = ±5V)
S
–90
HD2 (V = +5V)
S
–90
–100
–110
HD2 (F = 5MHz)
–100
–110
0
10
20
30
40
50
60
70
0.25
0.50
0.75
1.0
1.25
1.5
1.75
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 12. Harmonic Distortion vs. Frequency
Figure 15. Harmonic Distortion vs. Differential Output Voltage
–50
–55
–65
–75
–85
V
V
= ±5V
S
V
R
= ±5V
S
HD3 (F = 20MHz)
= 2V p-p
OUT, dm
= 800Ω
L, dm
–60
–70
–80
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (F = 20MHz)
–90
HD2 (F = 5MHz)
–95
–100
–110
–105
HD3 (F = 5MHz)
4
HD2 (F = 5MHz)
HD3 (F = 5MHz)
300 400
–115
0
200
500
600
700
800
900
1000
1
2
3
5
6
R
(Ω)
LOAD
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 16. Harmonic Distortion vs. RLOAD
Figure 13. Harmonic Distortion vs. Differential Output Voltage
Rev. B | Page 10 of 20
AD8131
–50
–60
–70
–80
45
40
35
30
V
V
= 5V
S
R
= 800Ω
L, dm
= 2V p-p
OUT, dm
HD2 (F = 20MHz)
HD3 (F = 20MHz)
V
= ±5V
S
–90
25
20
15
HD2 (F = 5MHz)
V
= +5V
S
–100
–110
HD3 (F = 5MHz)
200
300
400
500
600
700
800
900
1000
0
10
20
30
40
50
60
70
80
R
(Ω)
FREQUENCY (MHz)
LOAD
Figure 20. Third Order Intercept vs. Frequency
Figure 17. Harmonic Distortion vs. RLOAD
–50
–60
–70
–80
V
V
= 3V
S
= 1V p-p
V
= ±5V
OUT, dm
S
HD3 (F = 20MHz)
HD2 (F = 20MHz)
V
OUT, dm
V
OUT+
V
OUT–
–90
HD2 (F = 5MHz)
V
HD3 (F = 5MHz)
+DIN
–100
–110
5ns
1V
200
300
400
500
600
700
800
900
1000
R
(Ω)
LOAD
Figure 18. Harmonic Distortion vs. RLOAD
Figure 21. Large Signal Transient Response
10
0
fC = 500MHz
= ±5V
V
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
R
= 800Ω
L, dm
V
= +5V
S
V
= ±5V
S
–100
–110
49.5
50.0
50.5
5ns
40mV
FREQUENCY (MHz)
Figure 19. Intermodulation Distortion
Figure 22. Small Signal Transient Response
Rev. B | Page 11 of 20
AD8131
V
= 2V p-p
OUT
V
= +5V
S
1500Ω
AD8131
1500Ω
V
= ±5V
S
750Ω
750Ω
24.9Ω
24.9Ω
C
150Ω
L
49.9Ω
24.9Ω
400mV
5ns
Figure 26. Capacitor Load Drive Test Circuit
Figure 23. Large Signal Transient Response
V
= ±5V
V
= 1.5V p-p
S
OUT
C
= 5pF
L
C
= 0pF
L
V
= 3V
S
C
= 20pF
L
400mV
1.25ns
300mV
5ns
Figure 27. Large Signal Transient Response for Various Capacitor Loads
Figure 24. Large Signal Transient Response
0
ΔV
OUT, dm
V
= ±5V
S
–10
–20
–30
–40
ΔV
S
2mV/DIV
+PSRR
V
OUT, dm
(V = ±5V, +5V)
S
–50
–60
–70
–80
1V/DIV
–PSRR
(V = ±5V)
S
V
+DIN
4ns
1
10
100
1000
FREQUENCY (MHz)
Figure 25. 0.1% Settling Time
Figure 28. PSRR vs. Frequency
Rev. B | Page 12 of 20
AD8131
1500Ω
AD8131
1500Ω
1500Ω
AD8131
1500Ω
750Ω
750Ω
750Ω
750Ω
100Ω
100Ω
100Ω
V
V
OUT, cm
OUT, dm
49.9Ω
24.9Ω
100Ω
24.9Ω
Figure 29. CMRR Test Circuit
Figure 32. Output Balance Error Test Circuit
–20
–30
–40
–20
–30
–40
–50
ΔV
= 2V p-p
OUT, dm
V
V
= ±5V
S
ΔV
/ΔV
= 1V p-p
OUT, cm
OUT, dm
IN, cm
–50
ΔV
/ΔV
OUT, dm
IN, cm
V
= +5V
S
–60
–70
–80
–60
–70
–80
ΔV
/ΔV
OUT, cm
IN, cm
10
V
= ±5V
S
1
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. CMRR vs. Frequency
Figure 33. Output Balance Error vs. Frequency
100
10
15
13
SINGLE-ENDED OUTPUT
V
= ±5V
S
11
9
V
= +5V
S
1
V
= +5V
S
V
S
= ±5V
7
0.1
5
–50
1
10
100
–20
10
40
70
100
130
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 31. Single-Ended ZOUT vs. Frequency
Figure 34. Quiescent Current vs. Temperature
Rev. B | Page 13 of 20
AD8131
–20
110
V
= ±5V
ΔV
S
V
= ±5V
OUT, cm
S
ΔV
OCM
–30
–40
–50
–60
–70
–80
–90
90
ΔV
OCM
= 600mV p-p
70
50
30
ΔV
= 2V p-p
OCM
10
0.1k
1k
10k
100k
1M
10M
100M
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 35. Voltage Noise vs. Frequency
Figure 37. VOCM CMRR vs. Frequency
6
3
V
S
= ±5V
ΔV
OUT, cm
V
V
= 5V
S
ΔV
OCM
= –1V TO +1V
OCM
V
OUT, cm
ΔV
= 600mV p-p
OCM
0
–3
ΔV
= 2V p-p
OCM
–6
400mV
5ns
–9
1
10
100
1000
FREQUENCY (MHz)
Figure 38. VOCM Transient Response
Figure 36. VOCM Gain Response
Rev. B | Page 14 of 20
AD8131
OPERATIONAL DESCRIPTION
R
F
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
R
G
+IN
–OUT
AD8131
+OUT
+D
IN
–OUT
VOUT,cm V+OUT + V−OUT 2
=
R
V
V
L, dm
OCM
OUT, dm
+OUT
–D
IN
–IN
R
G
Balance is a measure of how well differential signals are
matched in amplitude and exactly 180 degrees apart in phase.
Balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider’s midpoint
with the magnitude of the differential signal. By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential-
mode voltage.
R
F
Figure 39. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) shown in
Figure 39 is defined as
VOUT,dm
=
V+OUT − V−OUT
VOUT, cm
Output Balance Error =
VOUT, dm
V
+OꢀT and V–OꢀT refer to the voltages at the +OꢀT and −OꢀT
terminals with respect to a common reference.
Rev. B | Page 15 of 20
AD8131
THEORY OF OPERATION
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
The AD8131 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on high open-loop gain and negative
feedback to force these outputs to the desired voltages. The
AD8131 behaves much like a standard voltage feedback op amp
and makes it easy to perform single-ended-to-differential
conversion, common-mode level-shifting, and amplification of
differential signals.
CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 39 can be
described by the following equation:
VOUT, dm
RF
RG
=
= 2
VIN, dm
Previous discrete and integrated differential driver designs used
two independent amplifiers and two independent feedback
loops, one to control each of the outputs. When these circuits
are driven from a single-ended source, the resulting outputs are
typically not well balanced. Achieving a balanced output
typically required exceptional matching of the amplifiers and
feedback networks.
where RF = 1.5 kΩ and RG = 750 Ω nominally.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and −IN, by the
circuit noise gain. The noise gain is defined as
DC common-mode level shifting has also been difficult with
previous differential drivers. Level shifting required the use of a
third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
GN = 1 +
= 3
The total output referred noise for the AD8131, including the
contributions of RF, RG, and op amp, is nominally 25 nV/√Hz
at 20 MHz.
The AD8131 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set by internal resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy
to arbitrarily set the common-mode output level. It is forced, by
internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit such as that in
Figure 39, at +DIN and −DIN, will depend on whether the
amplifier is being driven by a single-ended or differential signal
source. For balanced differential input signals, the input
impedance (RIN, dm) between the inputs (+DIN and −DIN) is
RIN, dm = 2 × RG = 1.5 kΩ
The AD8131 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring
external components or adjustments. The common-mode
feedback loop forces the signal component of the output
common-mode voltage to be zeroed. The result is nearly
perfectly balanced differential outputs, of identical amplitude
and exactly 180 degrees apart in phase.
In the case of a single-ended input signal (for example if −DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes
⎛
⎜
⎞
⎟
RG
RF
RG + RF
⎜
⎜
⎟
⎟
RIN, dm
=
=1.125 kΩ
1 −
⎜
⎜
⎟
⎟
ANALYZING AN APPLICATION CIRCUIT
2 ×
(
)
⎝
⎠
The AD8131 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN in
The input impedance is effectively higher than it would be for a
conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
Figure 39. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
Rev. B | Page 16 of 20
AD8131
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The AD8131 is optimized for level-shifting ground referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at −DIN in Figure 39 would be zero
volts when the amplifier’s negative power supply voltage (at V−)
was also set to zero volts.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bondwire
inductance of the AD8131 resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to
place a small resistor in series with the amplifier’s outputs as
shown in Figure 26.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The AD8131’s VOCM pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 25 mV
of the expected value.
Rev. B | Page 17 of 20
AD8131
APPLICATIONS
TWISTED-PAIR LINE DRIVER
3 V SUPPLY DIFFERENTIAL A-TO-D DRIVER
The AD8131 has on-chip resistors that provide for a gain of 2
without any external parts. Several on-chip resistors are
trimmed to ensure that the gain is accurate, the common-mode
rejection is good, and the output is well balanced. This makes
the AD8131 very suitable as a single-ended-to-differential
twisted-pair line driver.
Many newer ADCs can run from a single 3 V supply, which can
save significant system power. In order to increase the dynamic
range at the analog input, they have differential inputs, which
double the dynamic range with respect to a single-ended input.
An added benefit of using a differential input is that the
distortion can be improved.
Figure 40 shows a circuit of an AD8131 driving a twisted-pair
line, like a Category 3 or Category 5 (Cat3 or Cat5), that is
already installed in many buildings for telephony and data
communications. The characteristic impedance of such a
transmission line is usually about 100 Ω. The outstanding
balance of the AD8131 output will minimize the common-
mode signal and therefore the amount of EMI generated by
driving the twisted pair.
The low distortion and ability to run from a single 3 V supply make
the AD8131 suited as an A-to-D driver for some 10-bit, single-
supply applications. Figure 41 shows a schematic for a circuit for an
AD8131 driving an AD9203, a 10-bit, 40 MSPS ADC.
The common mode of the AD8131 output is set at midsupply
by the voltage divider connected to VOCM, and ac-bypassed with
a 0.1 μF capacitor. This provides for maximum dynamic range
between the supplies at the output of the AD8131. The 110 Ω
resistors at the AD8131 output, along with the shunt capacitors
form a one pole, low-pass filter for lowering noise and
antialiasing.
The two resistors in series with each output terminate the line at
the transmit end. Since the impedances of the outputs of the
AD8131 are very low, they can be thought of as a short-circuit,
and the two terminating resistors form a 100 Ω termination at
the transmit end of the transmission line. The receive end is
directly terminated by a 100 Ω resistor across the line.
3V
3V
+
10
F
0.1
F
0.1 F
28
2
DRVDD
AVDD
AINN
26
110Ω
This back-termination of the transmission line divides the
output signal by two. The fixed gain of 2 of the AD8131 will
create a net unity gain for the system from end to end.
3
20pF
8
2
LPF
AD8131
DIGITAL
OUTPUTS
AD9203
49.9Ω
V
OCM
0.1
F
1
In this case, the input signal is provided by a signal generator
with an output impedance of 50 Ω. This is terminated with a
49.9 Ω resistor near +DIN of the AD8131. The effective parallel
resistance of the source and termination is 25 Ω.The 24.9 Ω
resistor from −DIN to ground matches the +DIN source
impedance and minimizes any dc and gain errors.
25
20pF
+3V
AINP
AVSS
27
24.9Ω
6
110Ω
DRVSS
1
10kΩ
10kΩ
Figure 41. Test Circuit for AD8131 Driving an AD9203, 10-Bit, 40 MSPS ADC
If +DIN is driven by a low-impedance source over a short
distance, such as the output of an op amp, then no termination
resistor is required at +DIN. In this case, the −DIN can be directly
tied to ground.
Figure 42 shows an FFT plot that was taken from the combined
devices at an analog input frequency of 2.5 MHz and a 40 MSPS
sampling rate. The performance of the AD8131 compares very
favorably with a center-tapped transformer drive, which has
typically been the best way to drive this ADC. The AD8131 has
the advantage of maintaining dc performance, which a
transformer solution cannot provide.
+5V
+
10
μF
0.1
μF
49.9
Ω
3
8
2
5
49.9Ω
100Ω
RECEIVER
AD8131
4
6
1
24.9Ω
49.9
0.1
Ω
10μF
μ
F
+
–5V
Figure 40. Single-Ended-to-Differential 100 Ω Line Driver
Rev. B | Page 18 of 20
AD8131
10
0
+5V
INPUT
+
10 F
–10
–20
0.1 F
–30
–40
–OUT
3
8
2
1
5
–50
–60
49.9Ω
AD8131
4
6
–70
+OUT
–80
–90
10 F
0.1 F
+
–100
–110
–120
–5V
Figure 43. Unity Gain, Single-Ended-to-Differential Amplifier
2.0
2.1
2.2
2.3
2.4
2.5 2.6
2.7
2.8
2.9
3.0
FREQUENCY (MHz)
As shown above, when −DIN is left floating, there is 100%
feedback of +OꢀT to −IN via the internal feedback resistor.
This contrasts with the typical gain of 2 operation where −DIN is
grounded and one third of the +OꢀT is fed back to −IN. The
result is a closed-loop differential gain of 1.
Figure 42. FFT Plot for AD8131/AD9203
UNITY-GAIN, SINGLE-ENDED-TO-DIFFERENTIAL
DRIVER
If it is not necessary to offset the output common-mode voltage
(via the VOCM pin), then the AD8131 can make a simple unity-
gain single-ended-to-differential amplifier that does not require
any external components. Figure 43 shows the schematic for
this circuit.
ꢀpon careful observation, it can be seen that only +DIN and VOCM
are referenced to ground. The ground voltage at VOCM is the
reference for this circuit. In this unity gain configuration, if a dc
voltage is applied to VOCM to shift the common-mode voltage, a
differential dc voltage will be created at the output, along with the
common-mode voltage change. Thus, this configuration cannot
be used when it is desired to offset the common-mode voltage of
the output with respect to the input at +DIN.
Rev. B | Page 19 of 20
AD8131
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
3.00
BSC
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
4
4.90
BSC
3.00
BSC
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
PIN 1
0.65 BSC
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
1.10 MAX
0.15
0.00
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AA
COPLANARITY
0.10
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 44. 8-Lead Standard Small Outline Package [SOIC_N]
Figure 45. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8131AR
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
Branding
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
8-Lead Mini Small Outline Package [MSOP]
8-Lead MSOP, 13” Tape and Reel
8-Lead MSOP, 7” Tape and Reel
8-Lead Mini Small Outline Package [MSOP]
8-Lead MSOP, 13” Tape and Reel
8-Lead MSOP, 7” Tape and Reel
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
AD8131AR-REEL
AD8131AR-REEL7
AD8131ARZ1
AD8131ARZ-REEL1
AD8131ARZ-REEL71
AD8131ARM
AD8131ARM-REEL
AD8131ARM-REEL7
AD8131ARMZ1
AD8131ARMZ-REEL1
AD8131ARMZ-REEL71
HJA
HJA
HJA
HJA#
HJA#
HJA#
1 Z = Pb-free part, # denotes Pb-free part; may be top or bottom marked.
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01072–0–6/05(B)
Rev. B | Page 20 of 20
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