AD8138ARZ-R7 [ADI]
Low Distortion Differential ADC Driver; 低失真差分ADC驱动器
| 型号： | AD8138ARZ-R7 |
| 厂家： | 
ADI |
| 描述： | Low Distortion Differential ADC Driver |
| 文件： | 总24页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Distortion
Differential ADC Driver
AD8138
FEATURES
PIN CONFIGURATION
Easy to use, single-ended-to-differential conversion
Adjustable output common-mode voltage
Externally adjustable gain
–IN
1
2
3
4
8
7
6
5
+IN
NC
V
OCM
V+
V–
+OUT
–OUT
Low harmonic distortion
AD8138
−94 dBc SFDR @ 5 MHz
NC = NO CONNECT
−85 dBc SFDR @ 20 MHz
Figure 1.
−3 dB bandwidth of 320 MHz, G = +1
Fast settling to 0.01% of 16 ns
Slew rate 1150 V/μs
TYPICAL APPLICATION CIRCUIT
5V
5V
499Ω
Fast overdrive recovery of 4 ns
Low input voltage noise of 5 nV/√Hz
1 mV typical offset voltage
Wide supply range +3 V to 5 V
Low power 90 mW on 5 V
499Ω
AVDD
DVDD
V
+
IN
AIN
AIN
V
OCM
DIGITAL
OUTPUTS
ADC
AD8138
499Ω
–
V
AVSS
REF
499Ω
0.1 dB gain flatness to 40 MHz
Available in 8-Lead SOIC and MSOP packages
Figure 2.
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The AD8138 is a major advancement over op amps for
differential signal processing. The AD8138 can be used as a
single-ended-to-differential amplifier or as a differential-to-
differential amplifier. The AD8138 is as easy to use as an op
amp and greatly simplifies differential signal amplification and
driving. Manufactured on ADI’s proprietary XFCB bipolar
process, the AD8138 has a −3 dB bandwidth of 320 MHz and
delivers a differential signal with the lowest harmonic distortion
available in a differential amplifier. The AD8138 has a unique
internal feedback feature that provides balanced output gain
and phase matching, suppressing even order harmonics. The
internal feed-back circuit also minimizes any gain error that
would be associated with the mismatches in the external gain
setting resistors.
The AD8138 eliminates the need for a transformer with high
performance ADCs, preserving the low frequency and dc infor-
mation. The common-mode level of the differential output is
adjustable by a voltage on the VOCM pin, easily level-shifting the
input signals for driving single-supply ADCs. Fast overload
recovery preserves sampling accuracy.
The AD8138 distortion performance makes it an ideal ADC
driver for communication systems, with distortion performance
good enough to drive state-of-the-art 10-bit to 16-bit converters
at high frequencies. The AD8138’s high bandwidth and IP3 also
make it appropriate for use as a gain block in IF and baseband
signal chains. The AD8138 offset and dynamic performance
makes it well suited for a wide variety of signal processing and
data acquisition applications.
The AD8138’s differential output helps balance the input to
differential ADCs, maximizing the performance of the ADC.
The AD8138 is available in both SOIC and MSOP packages for
operation over −40°C to +85°C temperatures.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8138
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Analyzing an Application Circuit ............................................ 17
Setting the Closed-Loop Gain .................................................. 17
Estimating the Output Noise Voltage...................................... 17
The Impact of Mismatches in the Feedback Networks......... 18
Calculating an Application Circuit’s Input Impedance......... 18
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DIN to OUT Specifications...................................................... 3
VOCM to OUT Specifications ..................................................... 4
DIN to OUT Specifications...................................................... 5
VOCM to OUT Specifications ..................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 15
Operational Description................................................................ 16
Definition of Terms.................................................................... 16
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 18
Setting the Output Common-Mode Voltage.......................... 18
Driving a Capacitive Load......................................................... 18
Layout, Grounding, and Bypassing.............................................. 19
Balanced Transformer Driver....................................................... 20
High Performance ADC Driving ................................................. 21
3 V Operation ................................................................................. 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/02—Rev. C to Rev. D
Addition of TPC 35 and TPC 36.....................................................8
1/06—Rev. E to Rev. F
Changes to Features.......................................................................... 1
Added Thermal Resistance Section and Maximum Power
Dissipation Section........................................................................... 7
Changes to Balanced Transformer Driver Section..................... 20
Changes to Ordering Guide .......................................................... 23
6/01—Rev. B to Rev. C
Edits to Specifications ......................................................................2
Edits to Ordering Guide ...................................................................4
12/00—Rev. A to Rev. B
9/99—Rev. 0 to Rev. A
3/03—Rev. D to Rev. E
3/99—Rev. 0: Initial Version
Changes to Specifications................................................................ 2
Changes to Ordering Guide ............................................................ 4
Changes to TPC 16........................................................................... 6
Changes to Table I ............................................................................ 9
Added New Paragraph after Table I............................................. 10
Updated Outline Dimensions....................................................... 14
Rev. F | Page 2 of 24
AD8138
SPECIFICATIONS
DIN to OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 0, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 5 V to 0 V step, G = +2
290
320
225
30
265
1150
16
MHz
MHz
MHz
MHz
V/μs
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE1
Second Harmonic
4
ns
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
−94
−87
−62
−114
−85
−57
−77
37
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
Offset Voltage
5
2
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V
TMIN to TMAX variation
−2.5
1
4
+2.5
7
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
3.5
−0.01
6
3
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
1
−4.7 to +3.4
−77
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V
−70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; single-ended output
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
7.75
95
−66
V p-p
mA
dB
Output Balance Error
1 Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 3 of 24
AD8138
VOCM to OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 0, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
250
330
17
MHz
V/μs
INPUT VOLTAGE NOISE (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
f = 0.1 MHz to 100 MHz
nV/√Hz
3.8
200
1
0.5
−75
1
V
kΩ
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V
–3.5
+3.5
∆VOUT, dm/∆VOCM; ∆VOCM = 1 V
∆VOUT, cm/∆VOCM; ∆VOCM = 1 V
Gain
0.9955
1.0045
POWER SUPPLY
Operating Range
Quiescent Current
1.4
18
5.5
23
V
20
40
−90
mA
μA/°C
dB
TMIN to TMAX variation
∆VOUT, dm/∆VS; ∆VS = 1 V
Power Supply Rejection Ratio
−70
+85
OPERATING TEMPERATURE RANGE
−40
°C
Rev. F | Page 4 of 24
AD8138
DIN to OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential output, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 2.5 V to 0 V step, G = +2
280
310
225
29
265
950
16
MHz
MHz
MHz
MHz
V/μs
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE1
Second Harmonic
4
ns
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
−90
−79
−60
−100
−82
−53
−74
35
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
Offset Voltage
5
2
VOS, dm = VOUT, dm/2; VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX variation
−2.5
1
4
+2.5
7
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
3.5
−0.01
6
3
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
1
−0.3 to +3.2
−77
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V
−70
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; single-ended output
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
2.9
95
−65
V p-p
mA
dB
Output Balance Error
1 Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 5 of 24
AD8138
VOCM TO OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential output, unless otherwise noted.
Table 4.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
220
250
17
MHz
V/μs
INPUT VOLTAGE NOISE (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
f = 0.1 MHz to 100 MHz
nV/√Hz
1.0 to 3.8
100
1
0.5
−70
1
V
kΩ
mV
μA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V
−5
+5
∆VOUT, dm/∆VOCM; ∆VOCM = 2.5 V 1 V
∆VOUT, cm/∆VOCM; ∆VOCM = 2.5 V 1 V
Gain
0.9968
1.0032
POWER SUPPLY
Operating Range
Quiescent Current
2.7
15
11
21
V
20
40
−90
mA
μA/°C
dB
TMIN to TMAX variation
∆VOUT, dm/∆VS; ∆VS = 1 V
Power Supply Rejection Ratio
−70
+85
OPERATING TEMPERATURE RANGE
−40
°C
Rev. F | Page 6 of 24
AD8138
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
The power dissipated in the package (PD) is the sum of the
Ratings
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of the differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
internal common-mode feedback loop. The internal resistor tap
used in the common-mode feedback loop places a negligible
differential load on the output. RMS voltages and currents
should be considered when dealing with ac signals.
Supply Voltage
VOCM
5.5 V
VS
550 mW
−40°C to +85°C
−65°C to +150°C
300°C
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and 8-lead MSOP (θJA = 145°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
1.75
Table 6.
Package Type
1.50
1.25
θJA
Unit
°C/W
°C/W
8-Lead SOIC/4-Layer
8-Lead MSOP/4-Layer
121
145
1.00
SOIC
Maximum Power Dissipation
0.75
The maximum safe power dissipation in the AD8138 packages
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8138. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
MSOP
0.50
0.25
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 24
AD8138
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
1
2
3
4
8
7
6
5
+IN
NC
V
OCM
V+
V–
+OUT
–OUT
AD8138
NC = NO CONNECT
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
−IN
VOCM
Negative Input Summing Node.
Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example,
1 V dc on VOCM sets the dc bias level on +OUT and −OUT to 1 V.
3
4
5
6
7
8
V+
Positive Supply Voltage.
+OUT
−OUT
V−
NC
+IN
Positive Output. Note that the voltage at −DIN is inverted at +OUT (see Figure 42).
Negative Output. Note that the voltage at +DIN is inverted at −OUT (see Figure 42).
Negative Supply Voltage.
No Connect.
Positive Input Summing Node.
Rev. F | Page 8 of 24
AD8138
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Gain = 1, RG = RF = RL, dm = 499 V, TA = 25°C; refer to Figure 39 for test setup.
6
6
V
C
= 2V p-p
V
C
= 0.2V p-p
= 0pF
IN
= 0pF
IN
F
F
3
3
V
= +5V
S
V
= +5V
S
0
0
V
= ±5V
S
V
= ±5V
S
–3
–6
–9
–3
–6
–9
1
1
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response
Figure 8. Large Signal Frequency Response
6
3
6
3
V
V
= ±5V
V
V
= 2V p-p
= ±5V
S
IN
S
= 0.2V p-p
IN
C
= 0pF
F
C
= 0pF
F
0
0
C
= 1pF
F
C
= 1pF
F
–3
–6
–9
–3
–6
–9
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response
Figure 9. Large Signal Frequency Response
0.5
0.3
30
20
10
V
C
V
R
= ±5V
= 0pF
S
V
V
= ±5V
S
F
= 0.2V p-p
IN
= 0.2V p-p
OUT, dm
= 499Ω
G
G = 10, R = 4.99kΩ
F
C
F
= 0pF
G = 5, R = 2.49kΩ
F
0.1
G = 2, R = 1kΩ
F
–0.1
–0.3
–0.5
C
F
= 1pF
G = 1, R = 499Ω
F
0
–10
1
10
FREQUENCY (MHz)
100
10
100
1000
FREQUENCY (MHz)
Figure 7. 0.1 dB Flatness vs. Frequency
Figure 10. Small Signal Frequency Response for Various Gains
Rev. F | Page 9 of 24
AD8138
–50
V
–60
–70
= 2V p-p
= 800Ω
OUT, dm
V
R
= ±5V
= 800Ω
S
R
L
L
HD3 (F = 20MHz)
–60
–70
HD2 (F = 20MHz)
–80
HD2 (V = +5V)
S
–80
HD2 (V = ±5V)
S
–90
–90
HD2 (F = 5MHz)
–100
–100
–110
HD3 (V = +5V)
S
HD3 (F = 5MHz)
–110
–120
HD3 (V = ±5V)
S
–120
0
10
20
30
40
50
60
70
70
4
0
1
2
3
4
5
6
FUNDAMENTAL FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 11. Harmonic Distortion vs. Frequency
Figure 14. Harmonic Distortion vs. Differential Output Voltage
–60
–40
V
= 4V p-p
V
R
= 5V
OUT, dm
S
R
= 800Ω
= 800Ω
L
L
–50
–60
–70
–80
–90
HD3 (V = +5V)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
S
HD3 (F = 20MHz)
–70
HD2 (V = +5V)
S
–80
HD2 (V = ±5V)
S
–100
–90
HD3 (F = 5MHz)
–110
–120
–100
HD3 (V = ±5V)
S
–110
0
10
20
30
40
50
60
0
1
2
3
4
FUNDAMENTAL FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 15. Harmonic Distortion vs. Differential Output Voltage
Figure 12. Harmonic Distortion vs. Frequency
–60
–30
V
V
= 3V
= 2V p-p
OUT, dm
S
R
= 800Ω
R
= 800Ω
L
L
F
= 20MHz
–40
–50
O
–70
–80
–90
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD2 (V = +5V)
S
–60
–70
HD3 (V = +5V)
S
HD2 (F = 5MHz)
–80
HD3 (V = ±5V)
S
–100
–110
HD3 (F = 5MHz)
–90
HD2 (V = ±5V)
S
–100
0.25
0.50
0.75
1.00
1.25
1.50
1.75
–4
–3
–2
–1
0
1
2
3
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
V
DC OUTPUT (V)
OCM
Figure 16. Harmonic Distortion vs. Differential Output Voltage
Figure 13. Harmonic Distortion vs. VOCM
Rev. F | Page 10 of 24
AD8138
–60
–70
45
40
35
30
25
R
= 800Ω
L
V
V
= 5V
S
= 2V p-p
OUT, dm
HD2 (F = 20MHz)
HD3 (F = 20MHz)
–80
V
= ±5V
S
–90
V
= +5V
S
HD2 (F = 5MHz)
–100
HD3 (F = 5MHz)
1000
–110
0
20
40
FREQUENCY (MHz)
60
80
200
600
1400
1800
R
(Ω)
LOAD
Figure 17. Harmonic Distortion vs. RLOAD
Figure 20. Third-Order Intercept vs. Frequency
–60
–70
V
= ±5V
S
V
V
= ±5V
S
= 2V p-p
OUT, dm
V
OUT, dm
V
HD2 (F = 20MHz)
HD3 (F = 20MHz)
–80
OUT–
–90
V
OUT+
HD2 (F = 5MHz)
–100
–110
–120
V
+DIN
HD3 (F = 5MHz)
1V
5ns
200
600
1000
1400
1800
R
(Ω)
LOAD
Figure 18. Harmonic Distortion vs. RLOAD
Figure 21. Large Signal Transient Response
10
–10
–30
–50
–70
–90
–110
V
V
= 0.2V p-p
OUT, dm
= ±5V
S
F
V
= 50MHz
= ±5V
C
C
= 0pF
F
S
C
= 1pF
F
40mV
5ns
49.5
49.7
49.9
50.1
50.3
50.5
FREQUENCY (MHz)
Figure 19. Intermodulation Distortion
Figure 22. Small Signal Transient Response
Rev. F | Page 11 of 24
AD8138
V
C
= 2V p-p
V
S
= ±5V
OUT, dm
= 0pF
F
V
OUT, dm
V
= +5V
S
V
= ±5V
S
F = 20MHz
V
= 8V p-p
+DIN
G = 3 (R = 1500)
F
V
+DIN
400mV
5ns
4V
30ns
Figure 23. Large Signal Transient Response
Figure 26. Output Overdrive
V
V
= 2V p-p
C
= 0pF
V
C
= ±5V
= 0pF
OUT, dm
F
S
= ±5V
S
F
C
= 10pF
L
C
= 5pF
L
C
= 1pF
C
= 20pF
F
L
400mV
5ns
400mV
2.5ns
Figure 24. Large Signal Transient Response
Figure 27. Large Signal Transient Response for Various Cap Loads (See Figure 40)
–20
V
= ±5V
S
ΔV
/ΔV
IN, cm
OUT, dm
V
C
= ±5V
= 1pF
200µV
S
–30
–40
–50
–60
–70
–80
F
V
OUT, dm
V
+DIN
1V
4ns
1
10
100
1k
FREQUENCY (MHz)
Figure 28. CMRR vs. Frequency
Figure 25. Settling Time
Rev. F | Page 12 of 24
AD8138
–20
–30
–40
–50
–60
–70
5.0
2.5
V
= 2V p-p
IN
V
= ±5V
S
V
= +5V
S
0
V
= ±5V
S
V
= +3V
S
–2.5
V
= +5V
S
–5.0
1
10
100
1k
–40
–20
0
20
40
60
80
100
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 29. Output Balance Error vs. Frequency (See Figure 41)
Figure 32. Output Referred Differential Offset Voltage vs. Temperature
–10
5
ΔV
/ΔV
S
OUT, dm
–20
–30
–40
–50
–60
–70
–80
–90
4
–PSRR
S
(V = ±5V)
V
= ±5V, +5V
S
3
2
1
+PSRR
S
V
= +3V
S
(V = +5V, 0V AND ±5V)
1
10
100
1k
–40
–20
0
20
40
60
80
100
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 30. PSRR vs. Frequency
Figure 33. Input Bias Current vs. Temperature
100
10
1
30
25
20
15
10
5
SINGLE-ENDED OUTPUT
V
V
= ±5V
= +5V
S
V
= +5V
S
S
V
= +3V
S
V
= ±5V
S
0.1
1
10
FREQUENCY (MHz)
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 34. Supply Current vs. Temperature
Figure 31. Output Impedance vs. Frequency
Rev. F | Page 13 of 24
AD8138
100
10
1
6
V
= +5V
S
V
= ±5V
S
3
0
–3
–6
1.1pA/ Hz
–9
1
10
100
1k
10k
100k
1M
10
100
1k
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 35. VOCM Frequency Response
Figure 37. Current Noise (RTI)
1000
100
V
V
= ±5V
S
= –1V TO +1V
OCM
V
OUT, cm
10
5.7nV/ Hz
1
400mV
5ns
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 36. VOCM Transient Response
Figure 38. Voltage Noise (RTI)
Rev. F | Page 14 of 24
AD8138
TEST CIRCUITS
499Ω
R
= 499Ω
F
R
= 499Ω
499Ω
499Ω
249Ω
249Ω
G
49.9Ω
49.9Ω
R
= 499Ω
AD8138
L, dm
AD8138
R
= 499Ω
G
24.9Ω
24.9Ω
499Ω
R
= 499Ω
F
Figure 41. Test Circuit for Output Balance
Figure 39. Basic Test Circuit
499Ω
499Ω
24.9Ω
24.9Ω
49.9Ω
499Ω
C
453Ω
AD8138
L
24.9Ω
499Ω
Figure 40. Test Circuit for Cap Load Drive
Rev. F | Page 15 of 24
AD8138
OPERATIONAL DESCRIPTION
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
DEFINITION OF TERMS
C
F
V
OUT, cm = (V+OUT + V−OUT)/2
R
F
R
Balance is a measure of how well differential signals are
matched in amplitude and exactly 180° apart in phase. Balance
is most easily determined by placing a well-matched resistor
divider between the differential voltage nodes and comparing
the magnitude of the signal at the divider’s midpoint with the
magnitude of the differential signal (see Figure 41). By this
definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage:
G
G
+IN
–IN
–OUT
+OUT
+D
IN
V
R
V
OUT, dm
OCM
AD8138
L, dm
–D
IN
R
R
C
F
F
Figure 42. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as
VOUT, cm
Output Balance Error =
VOUT, dm
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Rev. F | Page 16 of 24
AD8138
THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on high open-loop gain and negative
feedback to force these outputs to the desired voltages. The
AD8138 behaves much like a standard voltage feedback op
amp and makes it easy to perform single-ended-to-differential
conversion, common-mode level-shifting, and amplification of
differential signals. Also like an op amp, the AD8138 has high
input impedance and low output impedance.
ANALYZING AN APPLICATION CIRCUIT
The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN in Figure 42.
For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be
assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
SETTING THE CLOSED-LOOP GAIN
Neglecting the capacitors CF, the differential-mode gain of the
circuit in Figure 42 can be determined to be described by
S
VOUT, dm
RF
=
S
VOUT, dm RG
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range
has proven difficult with this approach.
S
S
This assumes the input resistors, RG , and feedback resistors, RF ,
on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and −IN, by the
circuit noise gain. The noise gain is defined as
The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy
to arbitrarily set the output common-mode level. It is forced, by
internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
RF
RG
GN = 1+
To compute the total output referred noise for the circuit of
Figure 42, consideration must also be given to the contribution
of the Resistors RF and RG. Refer to Table 8 for the estimated
output noise voltage densities at various closed-loop gains.
The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs of identical amplitude and exactly
180° apart in phase.
Table 8.
Output
Noise
Bandwidth AD8138
Output
Noise
AD8138 +
RG
RF
Gain (Ω) (Ω)
−3 dB
Only
RG, RF
1
2
499 499
499 1.0 k
320 MHz
180 MHz
10 nV/√Hz 11.6 nV/√Hz
15 nV/√Hz 18.2 nV/√Hz
30 nV/√Hz 37.9 nV/√Hz
55 nV/√Hz 70.8 nV/√Hz
5
10
499 2.49 k 70 MHz
499 4.99 k 30 MHz
Rev. F | Page 17 of 24
AD8138
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
When using the AD8138 in gain configurations where
RF
RG
The effective input impedance of a circuit such as the one in
Figure 42, at +DIN and –DIN, depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
of one feedback network is unequal to
balanced differential input signals, the input impedance (RIN, dm
)
RF
RG
between the inputs (+DIN and −DIN) is simply
R
IN, dm =2 × RG
of the other network, there is a differential output noise due to
input-referred voltage in the VOCM circuitry. The output noise is
defined in terms of the following feedback terms (refer to
Figure 42):
In the case of a single-ended input signal (for example if −DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes
⎛
⎜
⎞
⎟
RG
β1 =
RG
RF
RG + RF
⎜
⎜
⎟
⎟
RF + RG
RIN, dm
=
1−
⎜
⎟
2×
(
)
⎝
⎠
for −OUT to +IN loop, and
RG
β2 =
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
RF + RG
for +OUT to −IN loop. With these defined,
⎡
⎢
⎤
⎥
β1 − β2
β + β
VnOUT, dm = 2VnIN,V
OCM
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
⎢
⎣
⎥
⎦
1
2
where VnOUT, dm is the output differential noise, and V
is
nIN,VCOM
The AD8138 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at −DIN in Figure 42 would be 0 V
when the amplifier’s negative power supply voltage (at V−) is
also set to 0 V.
the input-referred voltage noise in VOCM
.
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback
networks (RF/RG) are mismatched, the internal common-mode
feedback loop still forces the outputs to remain balanced. The
amplitudes of the signals at each output remains equal and 180°
out of phase. The input-to-output differential-mode gain varies
proportionately to the feedback mismatch, but the output
balance is unaffected.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The AD8138’s VOCM pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about
100 mV of the expected value.
Ratio matching errors in the external resistors result in a
degradation of the circuit’s ability to reject input common-
mode signals, much the same as for a four-resistor difference
amplifier made from a conventional op amp.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The output common-mode offset listed in the Specifications
section assumes the VOCM input is driven by a low impedance
voltage source.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to
place a small capacitor across each of the feedback resistors. The
added capacitance should be small to avoid destabilizing the
amplifier. An alternative technique is to place a small resistor in
series with the amplifier’s outputs, as shown in Figure 40.
Rev. F | Page 18 of 24
AD8138
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high
speed PCB design.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 μF to 0.1 μF for each
supply. Further away, low frequency bypassing should be provided
with 10 μF tantalum capacitors from each supply to ground.
The first requirement is for a good solid ground plane that
covers as much of the board area around the AD8138 as
possible. The only exception to this is that the two input pins
(Pin 1 and Pin 8) should be kept a few millimeters from the
ground plane, and ground should be removed from inner layers
and the opposite side of the board under the input pins. This
minimizes the stray capacitance on these nodes and helps
preserve the gain flatness vs. frequency.
The signal routing should be short and direct to avoid parasitic
effects. Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize
the balance performance. When running differential signals
over a long distance, the traces on the PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This reduces the
radiated energy and makes the circuit less susceptible to
interference.
Rev. F | Page 19 of 24
AD8138
BALANCED TRANSFORMER DRIVER
Transformers are among the oldest devices used to perform a
single-ended-to-differential conversion (and vice versa). Trans-
formers can also perform the additional functions of galvanic
isolation, step-up or step-down of voltages, and impedance
transformation. For these reasons, transformers always find
uses in certain applications.
The well-balanced outputs of the AD8138 provide a drive signal
to each of the transformer’s primary inputs that are of equal
amplitude and 180° out of phase. Therefore, depending on how
the polarity of the secondary is connected, the signals that
conduct across the interwinding capacitance either both assist
the transformer’s secondary signal equally, or both buck the
secondary signals. In either case, the parasitic effect is
symmetrical and provides a well-balanced transformer output
(see Figure 45).
However, when driving the transformer in a single-ended
manner, there is an imbalance at the output due to the parasitics
inherent in the transformer. The primary (or driven) side of the
transformer has one side at dc potential (usually ground), while
the other side is driven. This can cause problems in systems that
require good balance of the transformer’s differential output
signals.
SIGNAL IS COUPLED
ON THIS SIDE VIA C
STRAY
C
STRAY
500Ω
0.005%
V
UNBAL
PRIMARY
SECONDARY V
52.3Ω
DIFF
500Ω
0.005%
If the interwinding capacitance (CSTRAY) is assumed to be
uniformly distributed, a signal from the driving source couples
to the secondary output terminal that is closest to the primary’s
driven side. On the other hand, no signal is coupled to the
opposite terminal of the secondary because its nearest primary
terminal is not driven (see Figure 43). The exact amount of this
imbalance depends on the particular parasitics of the trans-
former, but is mostly a problem at higher frequencies.
C
STRAY
NO SIGNAL IS COUPLED
ON THIS SIDE
Figure 43. Transformer Single-Ended-to-Differential Converter Is Inherently
Imbalanced
499Ω
C
STRAY
49.9Ω
OUT–
The balance of a differential circuit can be measured by
499Ω
+IN
–IN
500Ω
V
0.005%
UNBAL
connecting an equal-valued resistive voltage divider across the
differential outputs and then measuring the center point of the
circuit with respect to ground. Since the two differential outputs
are supposed to be of equal amplitude, but 180° opposite phase,
there should be no signal present for perfectly balanced outputs.
AD8138
OUT+
V
DIFF
499Ω
500Ω
0.005%
49.9Ω
C
STRAY
499Ω
Figure 44. AD8138 Forms a Balanced Transformer Driver
The circuit in Figure 43 shows a Mini-Circuits® T1-6T
transformer connected with its primary driven single-endedly
and the secondary connected with a precision voltage divider
across its terminals. The voltage divider is made up of two
500 Ω, 0.005% precision resistors. The voltage VUNBAL, which is
also equal to the ac common-mode voltage, is a measure of how
closely the outputs are balanced.
0
–20
V
, FOR TRANSFORMER
UNBAL
WITH SINGLE-ENDED DRIVE
–40
Figure 45 compares the transformer being driven single-
endedly by a signal generator and being driven differentially
using an AD8138. The top signal trace of Figure 45 shows the
balance of the single-ended configuration, while the bottom
shows the differentially driven balance response. The 100 MHz
balance is 35 dB better when using the AD8138.
–60
–80
V
, DIFFERENTIAL DRIVE
100 500
UNBAL
–100
0.3
1
10
FREQUENCY (MHz)
Figure 45. Output Balance Error for Circuits of Figure 43 and Figure 44
Rev. F | Page 20 of 24
AD8138
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 46 shows a simplified front-end
connection for an AD8138 driving an AD9224, a 12-bit,
40 MSPS ADC. The ADC works best when driven differentially,
which minimizes its distortion. The AD8138 eliminates the
need for a transformer to drive the ADC and performs single-
ended-to-differential conversion, common-mode level-shifting,
and buffering of the driving signal.
The signal generator has a ground-referenced, bipolar output,
that is, it drives symmetrically above and below ground.
Connecting VOCM to the CML pin of the AD9224 sets the output
common-mode of the AD8138 at 2.5 V, which is the midsupply
level for the AD9224. This voltage is bypassed by a 0.1 μF
capacitor.
The full-scale analog input range of the AD9224 is set to
4 V p-p, by shorting the SENSE terminal to AVSS. This has
been determined to be the scaling to provide minimum
harmonic distortion.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9 Ω resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it
runs from supplies of 5 V.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180° out of phase. With a
common-mode voltage at the output of 2.5 V, each AD8138
output swings between 1.5 V and 3.5 V.
The AD8138 is configured with unity gain for a single-ended,
input-to-differential output. The additional 23 Ω, 523 Ω total, at
the input to −IN is to balance the parallel impedance of the
50 Ω source and its 50 Ω termination that drives the
noninverting input.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used to
test the circuit in Figure 46. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the spurious-free
dynamic range (SFDR) was measured at −85 dBc.
+5V
+5V
0.1pF
0.1pF
499Ω
15 26
28
3
49.9Ω
49.9Ω
499Ω
AVDD DRVDD
AD9224
5
8
2
+
24
23
VINB
DIGITAL
OUTPUTS
V
OCM
50Ω
SOURCE
49.9Ω
AD8138
523Ω
1
4
VINA
AVSS SENSE CML DRVSS
16 25
6
17
22
27
0.1pF
499Ω
–5V
Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC
Rev. F | Page 21 of 24
AD8138
3 V OPERATION
The circuit in Figure 47 shows a simplified front-end
The circuit was tested with a −0.5 dBFS signal at various
frequencies. Figure 48 shows a plot of the total harmonic
distortion (THD) vs. frequency at signal amplitudes of 1 V and
2 V differential drive levels.
connection for an AD8138 driving an AD9203, a 10-bit,
40 MSPS ADC that is specified to work on a single 3 V supply.
The ADC works best when driven differentially to make the
best use of the signal swing available within the 3 V supply.
The appropriate outputs of the AD8138 are connected to the
appropriate differential inputs of the AD9203 via a low-pass filter.
–40
–45
–50
The AD8138 is configured for unity gain for a single-ended
input to differential output. The additional 23 Ω at the input to
−IN is to balance the impedance of the 50 Ω source and its 50 Ω
termination that drives the noninverting input.
–55
AD8138–2V
–60
–65
AD8138–1V
The signal generator has ground-referenced, bipolar output,
that is, it can drive symmetrically above and below ground.
Even though the AD8138 has ground as its negative supply, it
can still function as a level-shifter with such an input signal.
–70
–75
–80
0
5
10
15
20
25
The output common mode is raised up to midsupply by the
voltage divider that biases VOCM. In this way, the AD8138
provides dc coupling and level-shifting of a bipolar signal,
without inverting the input signal.
FREQUENCY (MHz)
Figure 48. AD9203 THD @ −0.5 dBFS AD8138
Figure 49 shows the signal-to-noise-plus distortion (SINAD)
under the same conditions as above. For the smaller signal
swing, the AD8138 performance is quite good, but its
performance degrades when trying to swing too close to the
supply rails.
The low-pass filter between the AD8138 and the AD9203
provides filtering that helps to improve the signal-to-noise ratio
(SNR). Lower noise can be realized by lowering the pole
frequency, but the bandwidth of the circuit is lowered.
65
63
61
3V
3V
0.1µF
0.1µF
499Ω
0.1µF
10kΩ
28
2
3
59
49.9Ω
499Ω
AVDD DRVDD
+
5
8
2
25
AINN
57
20pF
DIGITAL
OUTPUTS
AD8138–1V
49.9Ω
AD9203
AD8138
AINP
523Ω
49.9Ω
55
26
4
1
AVSS DRVSS
27
6
AD8138–2V
20pF
1
53
0.1µF
10kΩ
499Ω
51
49
47
45
Figure 47. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter
0
5
10
15
20
25
FREQUENCY (MHz)
Figure 49. AD9203 SINAD @ −0.5 dBFS AD8138
Rev. F | Page 22 of 24
AD8138
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
8
1
5
4
5.15
4.90
4.65
6.20 (0.2440)
5.80 (0.2284)
3.20
3.00
2.80
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
PIN 1
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.65 BSC
0.25 (0.0098)
0.10 (0.0040)
0.95
0.85
0.75
1.10 MAX
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.80
0.60
0.40
SEATING
PLANE
0.40 (0.0157)
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AA
SEATING
PLANE
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Figure 50. 8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8138AR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
Branding
8-Lead SOIC
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
AD8138AR-REEL
AD8138AR-REEL7
AD8138ARZ1
AD8138ARZ-RL1
AD8138ARZ-R71
AD8138ARM
AD8138ARM-REEL
AD8138ARM-REEL7
AD8138ARMZ1
AD8138ARMZ-REEL1
AD8138ARMZ-REEL71
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
HBA
HBA
HBA
HBA#
HBA#
HBA#
1 Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. F | Page 23 of 24
AD8138
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01073-0-1/06(F)
Rev. F | Page 24 of 24
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