AD8139ARDZ-REEL7 [ADI]
Low Noise Rail-to-Rail Differential ADC Driver; 低噪声，轨到轨差分ADC驱动器
| 型号： | AD8139ARDZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Noise Rail-to-Rail Differential ADC Driver |
| 文件： | 总24页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise Rail-to-Rail
Differential ADC Driver
AD8139
FEATURES
APPLICATIONS
Fully differential
ADC drivers to 18 bits
Low noise
2.25 nV/√Hz
Single-ended-to-differential converters
Differential filters
2.1 pA/√Hz
Level shifters
Low harmonic distortion
98 dBc SFDR @ 1 MHz
Differential PCB board drivers
Differential cable drivers
85 dBc SFDR @ 5 MHz
72 dBc SFDR @ 20 MHz
High speed
FUNCTIONAL BLOCK DIAGRAM
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance @ 1 MHz
80 dB dc CMRR
AD8139
–IN
1
2
8
7
6
5
+IN
NC
V
OCM
V+
V–
3
4
+OUT
–OUT
Low offset: 0.5 mV max
Low input offset current: 0.5 µA max
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
NC = NO CONNECT
Figure 1.
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in small SOIC package
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
GENERAL DESCRIPTION
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high SFDR,
and wide bandwidth, it is an ideal choice for driving ADCs with
resolutions to 18 bits. The AD8139 is easy to apply, and its in-
ternal common-mode feedback architecture allows its output
common-mode voltage to be controlled by the voltage applied
to one pin. The internal feedback loop also provides out-
standing output balance as well as suppression of even-order
harmonic distortion products. Fully differential and single-
ended-to-differential gain configurations are easily realized by
the AD8139. Simple external feedback networks consisting of a
total of four resistors determine the amplifier’s closed-loop gain.
100
10
1
The AD8139 is manufactured on ADI’s proprietary second gen-
eration XFCB process, enabling it to achieve low levels of distor-
tion with input voltage noise of only 1.85 nV/√Hz.
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 2. Input Voltage Noise vs. Frequency
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8139
TABLE OF CONTENTS
VS = 5 V, VOCM = 0 V Specifications.............................................. 3
Typical Connection and Definition of Terms ........................ 18
Applications..................................................................................... 19
VS = 5 V, VOCM = 2.5 V Specifications ............................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 18
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks.................................................................... 19
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/04—Data Sheet Changed from a Rev. 0 to Rev. A.
Added 8-Lead LFCSP.........................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 2.......................................................................... 1
Changes to VS = 5 V, VOCM = 0 V Specifications ......................... 3
Changes to VS = 5 V, VOCM = 2.5 V Specifications......................... 5
Changes to Table 4............................................................................ 7
Changes to Maximum Power Dissipation Section....................... 7
Changes to Figure 26 and Figure 29............................................. 12
Inserted Figure 39 and Figure 42.................................................. 14
Changes to Figure 45 to Figure 47................................................ 15
Inserted Figure 48........................................................................... 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6.......................................................................... 19
Changes to Voltage Gain Section.................................................. 19
Changes to Driving a Capacitive Load Section .......................... 22
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 24
5/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8139
VS = ± ± V, VOCM = 0 V SPECIFICATIONS
@ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V Step
VO, dm = 2 V Step, CF = 2 pF
G = 2, VIN, dm = 12 V p-p Triangle Wave
340
210
410
240
45
800
45
MHz
MHz
MHz
V/µs
ns
30
ns
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2V p-p, fC = 5 MHz
VO, dm = 2 V p-p, fC = 20 MHz
VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz
f = 100 KHz
98
85
72
−90
2.25
2.1
dB
dB
dB
dBc
nV/√Hz
pA/√Hz
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
f = 100 KHz
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−500
150
+500
µV
µV/ºC
µA
µA
dB
1.25
2.25
0.12
114
8.0
0.5
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
−4
80
+4
V
Differential
Common Mode
Common Mode
∆VICM = 1 V dc, RF = RG = 10 kΩ
600
1.5
1.2
84
kΩ
MΩ
pF
dB
Input Capacitance
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each Single-Ended Output, RF = RG = 10 kΩ
Each Single-Ended Output,
−VS + 0.20
−VS + 0.15
+VS – 0.20
+VS – 0.15
V
V
RL, dm = Open Circuit, RF = RG = 10 kΩ
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Each Single-Ended Output
f = 1 MHz
100
−69
mA
dB
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
515
250
1.000 1.001
MHz
V/µs
V/V
Gain
0.999
−3.8
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
+3.8
3.5
300
3.5
1.3
88
V
MΩ
µV
nV/√Hz
µA
dB
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
−900
+900
4.5
∆VOCM/∆VO, dm, ∆VOCM = 1 V
74
Rev. A | Page 3 of 24
AD8139
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
4.5
6
25.5
V
24.5
112
109
mA
dB
dB
°C
Change in +VS = 1V
Change in −VS = 1V
95
95
−PSRR
OPERATING TEMPERATURE RANGE
−40
+125
Rev. A | Page 4 of 24
AD8139
VS = ± V, VOCM = 2.± V SPECIFICATIONS
@ 25°C, Diff. Gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
SFDR
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V Step
VO, dm = 2 V Step
G = 2, VIN, dm = 7 V p-p Triangle Wave
330
135
385
165
34
540
55
MHz
MHz
MHz
V/μs
ns
35
ns
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz, (RL = 800 Ω)
VO, dm = 2 V p-p, fC = 20 MHz, (RL = 800 Ω)
VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz
f = 100 kHz
99
87
75
−87
2.25
2.1
dB
dB
dB
dBc
nV/√Hz
pA/√Hz
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
f = 100 kHz
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
VIP = VIN = VOCM =0 V
TMIN to TMAX
TMIN to TMAX
−500
150
1.25
2.2
0.13
112
+500
µV
µV/ºC
μA
µA
dB
7.5
0.5
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
1
4
V
Differential
Common-Mode
Common-Mode
ꢀVICM = 1 V dc, RF = RG = 10 kΩ
600
1.5
1.2
79
KΩ
MΩ
pF
dB
Input Capacitance
CMRR
75
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each Single-Ended Output, RF = RG = 10 kΩ
Each Single-Ended Output,
−VS + 0.15
−VS + 0.10
+VS − 0.15
+VS − 0.10
V
V
RL, dm = Open Circuit, RF = RG = 10 kΩ
Output Current
Output Balance Error
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Each Single-Ended Output
f = 1 MHz
80
−70
mA
dB
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
440
150
1.000
MHz
V/μs
V/V
Gain
0.999
1.0
1.001
3.8
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
V
3.5
MΩ
mV
nV/√Hz
μA
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 2.5 V
f = 100 KHz
−1.0
0.45 +1.0
3.5
1.3
79
4.2
ꢀVOCM/ꢀVO(dm), ꢀVOCM = 1 V
67
dB
Rev. A | Page 5 of 24
AD8139
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
+4.5
6
22.5
V
21.5
97
105
mA
dB
dB
°C
Change in +VS = 1 V
Change in −VS = 1 V
86
92
−PSRR
OPERATING TEMPERATURE RANGE
−40
+125
Rev. A | Page 6 of 24
AD8139
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 3.
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Parameter
Rating
Supply Voltage
12 V
VOCM
VS
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
See Figure 3
VS
–65°C to +125°C
–40°C to +125°C
300°C
Junction Temperature
150°C
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EP) SOIC-8 (θJA = 70°C/W) package and LFCSP (θJA
=
70°C/W) on a JEDEC standard 4-layer board. θJA values are
approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
4.0
3.5
Table 4. Thermal Resistance
Package Type
θJA
70
70
Unit
°C/W
°C/W
3.0
SOIC-8 with EP/4-Layer
LFCSP/4-Layer
2.5
2.0
Maximum Power Dissipation
1.5
The maximum safe power dissipation in the AD8139 package is
limited by the associated rise in junction temperature (TJ) on the
die. At approximately 150°C, which is the glass transition tem-
perature, the plastic will change its properties. Even temporarily
exceeding this temperature limit may change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in the
silicon devices potentially causing failure.
SOIC
AND LFCSP
1.0
0.5
0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. A | Page 7 of 24
AD8139
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8139
–IN
1
2
8
7
6
5
+IN
NC
V
OCM
V+
V–
3
4
+OUT
–OUT
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
−IN
VOCM
Inverting Input.
An internal feedback loop drives the output common-mode voltage to be equal to the
voltage applied to the VOCM pin, provided the amplifier’s operation remains linear.
3
4
5
6
7
8
V+
Positive Power Supply Voltage.
Positive Side of the Differential Output.
Negative Side of the Differential Output.
Negative Power Supply Voltage.
No Internal Connection.
+OUT
−OUT
V−
NC
+IN
Noninverting Input.
R
C
F
50Ω
50Ω
F
R
R
= 200Ω
= 200Ω
G
–
60.4Ω
60.4Ω
V
V
R
= 1kΩ
V
TEST
AD8139
OCM
L, dm
O, dm
+
TEST
G
C
F
F
SIGNAL
SOURCE
R
Figure 5. Basic Test Circuit
R
= 200Ω
F
50Ω
50Ω
R
R
R
R
= 200Ω
= 200Ω
S
S
G
–
60.4Ω
60.4Ω
V
V
C
R
V
TEST
AD8139
OCM
L, dm
L, dm
O, dm
+
TEST
G
SIGNAL
SOURCE
R
= 200Ω
F
Figure 6. Capacitive Load Test Circuit, G = +1
Rev. A | Page 8 of 24
AD8139
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Diff. Gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = 5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in
Figure 5 for the definition of terms.
2
1
2
1
G = 1
G = 1
0
0
G = 2
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
G = 5
G = 2
G = 5
G = 10
G = 10
R
= 200Ω
G
R
= 200Ω
G
V
= 2.0V p-p
O, dm
V
= 0.1V p-p
O, dm
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
5
4
3
2
V
= +5V
S
3
2
1
0
1
–1
–2
0
V
= ±5V
V
= ±5V
S
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–3
–4
V
= +5V
S
–5
–6
–7
–8
–9
–10
–11
–12
V
= 2.0V p-p
V
= 0.1V p-p
O, dm
O, dm
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 8. Small Signal Frequency Response for Various Power Supplies
Figure 11. Large Signal Frequency Response for Various Power Supplies
3
3
+125°C
+125°C
+85°C
2
2
1
+85°C
1
0
–1
–2
–3
–4
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–5
–40°C
–6
–7
–8
–9
+25°C
–40°C
–10
–11
–12
10
V
= 0.1V p-p
O, dm
V
= 2.0V p-p
O, dm
+25°C
100
1000
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response at Various ΩTemperatures
Figure 12. Large Signal Frequency Response at Various Temperatures
Rev. A | Page 9 of 24
AD8139
3
2
2
1
R
= 100Ω
R
= 200Ω
R
= 100Ω
L
L
L
1
0
R
= 500Ω
L
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
R
= 500Ω
L
R
= 1kΩ
L
V
= 0.1V p-p
V
= 2.0V p-p
O, dm
O, dm
R
= 200Ω
R
= 1kΩ
L
L
–12
10
10
100
FREQUENCY (MHz)
1000
100
1000
FREQUENCY (MHz)
Figure 16. Large Signal Frequency Response for Various Loads
Figure 13. Small Signal Frequency Response for Various Loads
2
3
C
= 0pF
C
= 1pF
C
= 0pF
F
F
F
1
0
2
1
C
= 1pF
F
–1
0
–2
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
C
= 2pF
F
–3
–4
C
= 2pF
F
–5
–6
–7
–8
–9
–10
–11
–12
–13
V = 2.0V p-p
O, dm
V
= 0.1V p-p
O, dm
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for Various CF
Figure 14. Small Signal Frequency Response for Various CF
0.5
0.4
6
R
= 100Ω
L
V
= +4.3V
V
= +4V
OCM
OCM
(V
= 0.1V p-p)
5
4
O, dm
V
= –4.3V
OCM
R
= 100Ω
L
0.3
(V
= 2.0V p-p)
3
O, dm
V
= –4V
OCM
2
R
= 1kΩ
L
0.2
(V
= 2.0V p-p)
1
O, dm
0.1
0
V
= 0V
OCM
–1
–2
–3
–4
–5
–6
–7
–8
–9
R = 1kΩ
L
= 0.1V p-p)
0
(V
O, dm
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 0.1V p-p
O, dm
1
10
FREQUENCY (Hz)
100
10
100
FREQUENCY (MHz)
1000
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
Figure 15. Small Signal Frequency Response at Various VOCM
Rev. A | Page 10 of 24
AD8139
–30
–40
–30
–40
V = 2.0V p-p
O, dm
V
= 2.0V p-p
O, dm
–50
–50
V
= +5V
S
–60
–60
V
= ±5V
S
–70
–70
V
= ±5V
S
–80
–80
V
= +5V
S
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
–30
–30
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–40
–50
–60
–60
G = 1
–70
–70
–80
–80
G = 5
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
G = 2
G = 1
G = 2
G = 5
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
–30
–30
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–40
–50
R
= 100Ω
L
–60
–60
R
= 100Ω
L
R
= 200Ω
L
–70
–70
R
= 200Ω
L
–80
–80
–90
–90
R
= 500Ω
L
–100
–110
–120
–130
–100
–110
–120
–130
R
= 1kΩ
L
R
= 500Ω
L
R
= 1kΩ
L
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 21. Second Harmonic Distortion vs. Frequency and Load
Figure 24. Third Harmonic Distortion vs. Frequency and Load
Rev. A | Page 11 of 24
AD8139
–30
–30
–40
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–50
–60
–60
–70
–70
R
= 200Ω
F
–80
–80
R
= 500Ω
F
–90
–90
R
= 200Ω
F
–100
–110
–120
–130
–100
–110
–120
–130
R
= 1kΩ
F
R
= 1kΩ
F
R
= 500Ω
F
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 25. Second Harmonic Distortion vs. Frequency and RF
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–80
–80
F = 2MHz
C
F
= 2MHz
C
V
V
= ±5V
S
S
–90
–100
–110
–120
–130
–140
–150
–90
V
= +5V
= +5V
S
–100
–110
–120
–130
–140
–150
V
= ±5V
S
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
V
(V p-p)
V
(V p-p)
O, dm
O, dm
Figure 26. Second Harmonic Distortion Vs. Output Amplitude
Figure 29. Third Harmonic Distortion vs. Output Amplitude
–60
–60
V
F
= 2V p-p
V
F
= 2V p-p
= 2MHz
O, dm
= 2MHz
O, dm
C
C
–70
–80
–70
–80
–90
–90
SECOND HARMONIC
SECOND HARMONIC
–100
–110
–120
–130
–100
–110
–120
–130
THIRD HARMONIC
THIRD HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–5
–4
–3
–2
–0
0
1
2
3
4
5
V
(V)
V
(V)
OCM
OCM
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
Figure 30. Harmonic Distortion vs. VOCM, VS = 5 V
Rev. A | Page 12 of 24
AD8139
100
75
2.5
2.0
C
= 0pF
V
= 100mV p-p
F
O, dm
4V p-p
2V p-p
C
= 2pF
F
1.5
C
= 0pF
F
50
C
F
= 0pF
(C = 0pF,
1.0
V
O, dm
(C = 2pF, V
S
F
C
= 2pF
= ±5V)
F
25
F
V
= ±5V)
S
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–25
–50
–75
–100
5ns/DIV
5ns/DIV
TIME (ns)
TIME (ns)
Figure 31. Small Signal Transient Response for Various CF
Figure 34. Large Signal Transient Response For CF
0.100
0.075
0.050
0.025
0
1.5
R
C
= 63.4Ω
L, dm
R
C
= 31.6Ω
L, dm
S
S
= 15pF
= 30pF
1.0
0.5
R
C
= 31.6
Ω
S
L, dm
= 30pF
R
C
= 63.4
Ω
S
L, dm
= 15pF
0
–0.025
–0.050
–0.075
–0.100
–0.5
–1.0
–1.5
5ns/DIV
5ns/DIV
TIME (ns)
TIME (ns)
Figure 32. Small Signal Transient Response for Capacitive Loads
Figure 35. Large Signal Transient Response for Capacitive Loads
5
0
–5
1.5
600
400
200
0
V
F
= 2V p-p
1 = 10MHz
2 = 10.1MHz
C
= 2pF
F
O, dm
V
= 2.0V p-p
C
O, dm
F
C
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
1.0
0.5
0
ERROR
–0.5
–1.0
–1.5
–200
–400
–600
V
O, dm
35ns/DIV
V
IN
9.55 9.65 9.75 9.85 9.95 10.05 10.15 10.25 10.35 10.45 10.55
FREQUENCY (MHz)
TIME (ns)
Figure 36. Settling Time (0.01%)
Figure 33. Intermodulation Distortion
Rev. A | Page 13 of 24
AD8139
6
5
1.5
±5V
4
1.0
V
= +5V
S
3
2
+5V
0.5
1
0
V
= 0.1V p-p
O, cm
–1
–2
–3
–4
–5
–6
–7
–8
–9
0
V
=
±
5V
V = ±5V
S
S
V
= 2.0V p-p
O, cm
–0.5
–1.0
–1.5
V
V
= 2V p-p
= 0V
O, cm
IN, dm
V
= +5V
S
10ns/DIV
10
100
FREQUENCY (MHz)
1000
500
1G
TIME (ns)
Figure 40. VOCM Frequency Response for Various Supplies
Figure 37. VOCM Large Signal Transient Response
0
0
V
V
= 0.2V p-p
V
= 0.2V p-p
IN, cm
O, cm
OCM
CMRR =
∆
V
/∆V
INPUT CMRR =
∆V
/∆V
O, cm IN, cm
O, dm O, cm
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
R
= R = 10kΩ
G
F
R
= R = 200Ω
G
F
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
500
Figure 41. VOCM CMRR vs. Frequency
Figure 38. CMRR vs. Frequency
100
10
1
100
10
1
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. Input Voltage Noise vs. Frequency
Figure 42. VOCM Voltage Noise vs. Frequency
Rev. A | Page 14 of 24
AD8139
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
14
12
10
8
2
× V
IN, dm
R
= 1k
Ω
G = 2
L, dm
PSRR =
∆V
/∆V
O, dm S
V
O, dm
6
4
2
–PSRR
0
+PSRR
–2
–4
–6
–8
–10
–12
–14
50ns/DIV
1
10
FREQUENCY (MHz)
100
500
1000
10k
TIME (ns)
Figure 46. Overdrive Recovery
Figure 43. PSRR vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
V
= 1V p-p
O, dm
OUTPUT BALANCE =
100
10
∆V
/∆V
O, cm O, dm
V
= +5V
S
V
= ±5V
S
1
0.1
1
10
FREQUENCY (MHz)
100
500
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 47. Output Balance vs. Frequency
Figure 44. Single-Ended Output Impedance vs. Frequency
300
250
200
150
100
50
–50
700
V
= ±5V
S
G = 1 (R = R = 200Ω)
R
F
G
600
500
= 1kΩ
L, dm
–100
–150
–200
–250
–300
V
– V
OP
S+
400
300
V
V
– V
OP
S+
200
100
V
= +5V
0
V
= ±5V
S
S
–100
–200
–300
–400
–500
–600
–700
– V
ON
S–
V
– V
60
ON
S–
–40
–20
0
20
40
80
100
120
100
1k
RESISTIVE LOAD (Ω)
TEMPERATURE (°C)
Figure 45. Output Saturation Voltage vs. Output Load
Figure 48. Output Saturation Voltage vs. Temperature
Rev. A | Page 15 of 24
AD8139
3.0
170
145
120
95
26
25
24
23
22
21
20
V
= ±5V
S
I
OS
2.5
2.0
1.5
I
BIAS
V
= +5V
S
1.0
–40
70
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (
°
C)
Figure 49. Input Bias and Offset Current vs. Temperature
Figure 52. Supply Current vs. Temperature
300
250
200
150
100
50
600
10
8
6
V
OS, cm
400
200
0
V
= ±5V
S
4
V
= +5V
S
2
0
V
OS, dm
–2
–4
–6
–8
–10
–200
–400
–600
0
–40
–20
0
20
40
60
80
100
120
–5
–4
–3
–2
–1
0
1
2
3
4
5
TEMPERATURE (
°
C)
V
(V)
ACM
Figure 53. Offset Voltage vs. Temperature
Figure 50. Input Bias Current vs.
Input Common-Mode Voltage
50
45
40
35
30
25
20
15
10
5
COUNT = 350
MEAN = –50µV
STD DEV = 100µV
5
4
V
= ±2.5V
S
3
2
V
= ±5V
S
1
0
–1
–2
–3
–4
–5
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(µV)
OS, dm
V
(V)
OCM
Figure 54. VOS, dm Distribution
Figure 51. VO, cm vs. VOCM Input Voltage
Rev. A | Page 16 of 24
AD8139
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
6
4
V
= ±5V
S
V
= +5V
2
S
0
–2
–4
–6
–40
–20
0
20
40
60
80
100
120
–5
–4
–3
–2
–1
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
OCM
Figure 55. VOCM Bias Current vs. Temperature
Figure 56. VOCM Bias Current vs. VOCM Input Voltage
Rev. A | Page 17 of 24
AD8139
THEORY OF OPERATION
balanced differential outputs of identical amplitude and exactly
180 degrees out of phase. The output balance performance does not
require tightly matched external components, nor does it require
that the feedback factors of each loop be equal to each other. Low
frequency output balance is limited ultimately by the mismatch
of an on-chip voltage divider, which is trimmed for optimum
performance.
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second generation eXtra Fast
Complementary Bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response to
either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltage-
feedback operational amplifiers. The common-mode level of the
output voltage is set by a voltage at the VOCM pin and is inde-
pendent of the input common-mode voltage. The AD8139 has
an H-bridge input stage for high slew rate, low noise, and low
distortion operation and rail-to-rail output stages that provide
maximum dynamic output range. This set of features allows for
convenient single-ended-to-differential conversion, a common
need to take advantage of modern high resolution ADCs with
differential inputs.
Output balance is measured by placing a well matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential-
mode voltage:
ΔVO, cm
ΔVO, dm
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Output Balance =
(3)
Figure 57 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input
terminals of the AD8139, VAP and VAN, are used as summing
junctions. An external reference voltage applied to the VOCM
terminal sets the output common-mode voltage. The two
output terminals, VOP and VON, move in opposite directions in a
balanced fashion in response to an input signal.
The block diagram of the AD8139 in Figure 58 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
C
F
VAN = VAP
(4)
R
F
R
R
V
V
V
G
AP
ON
OP
V
–
IP
+
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two 500 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
V
OCM
R
V
AD8139
L, dm
O, dm
+
G
V
AN
V
–
IN
R
F
F
VO, dm
2
VOP =VOCM
+
(5)
C
and
Figure 57. Typical Connection
VO, dm
2
The differential output voltage is defined as
VON =VOCM
−
(6)
VO, dm = VOP − VON
(1)
(2)
R
R
F
G
V
IN
10pF
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
+
+
G
O
V
OP
500Ω
500Ω
MIDSUPPLY
VOP + VON
V
AN
VO, cm
=
G
G
CM
DIFF
2
V
AP
V
V
OCM
Output Balance
G
O
ON
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180 degrees
out of phase with each other. It is the internal common-mode
feedback loop that forces the signal component of the output
common-mode towards zero, resulting in the near perfectly
10pF
V
IP
R
G
R
F
Figure 58. Block Diagram
Rev. A | Page 18 of 24
AD8139
APPLICATIONS
ESTIMATING NOISE, GAIN, AND BANDWIDTH
WITH MATCHED FEEDBACK NETWORKS
The contribution from each RF is computed as
Vo_n4 = 4kTRF
(10)
Estimating Output Noise Voltage
Voltage Gain
The total output noise is calculated as the root-sum-squared
total of several statistically independent sources. Since the
sources are statistically independent, the contributions of each
must be individually included in the root-sum-square calcula-
tion. Table 6 lists recommended resistor values and estimates of
bandwidth and output differential voltage noise for various
closed-loop gains. For most applications, 1% resistors are
sufficient.
The behavior of the node voltages of the single-ended-to-
differential output topology can be deduced from the previous
definitions. Referring to Figure 57, (CF = 0) and setting VIN = 0
one can write
VIP −VAP
V
AP −VON
RF
=
(11)
(12)
RG
RG
RF + RG
⎡
⎤
Table 6. Recommended Values of Gain-Setting Resistors and
Voltage Noise for Various Closed-Loop Gains
3 dB
VAN =VAP = VOP
⎢
⎥
⎣
⎦
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
Bandwidth
(MHz)
Total Output
Noise (nV/√Hz)
Gain
RG (Ω)
200
200
200
200
RF (Ω)
200
400
1 k
1
2
5
10
400
160
53
5.8
9.3
19.7
37
RF
RG
VOP − VON = VO, dm
=
V
(13)
i
2 k
26
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
The differential output voltage noise contains contributions
from the AD8139’s input voltage noise and input current noise
as well as those from the external feedback networks.
Feedback Factor Notation
When working with differential amplifiers, it is convenient to
introduce the feedback factor β, which is defined as
The contribution from the input voltage noise spectral density
is computed as
RG
RF + RG
RF
RG
⎛
⎞
⎟
β =
(14)
Vo_n1 = vn 1+
, or equivalently, v /β
(7)
⎜
n
⎝
⎠
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
The contribution from the input current noise of each input is
computed as
Input Common-Mode Voltage
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Since VAN and VAP are
essentially equal to each other, they are both equal to the ampli-
fier’s input common-mode voltage. Their range is indicated in
the Specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure 57
can be expressed as
Vo_n2 = in
(
RF
)
(8)
where in is defined as the input noise current of one input. Each
input needs to be treated separately since the two input currents
are statistically independent processes.
The contribution from each RG is computed as
VAN =VAP =VACM
=
R
RG
⎛
⎜
⎞
⎟
F
Vo_n3 = 4kTRG
(9)
RF
(VIP +V )
RG
RF + RG
⎛
⎜
⎞
⎟
⎛
⎜
⎞
⎟
IN
×
+
×VOCM
(15)
⎝
⎠
RF + RG
2
⎝
⎠
⎝
⎠
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
where VACM is the common-mode voltage present at the
amplifier input terminals.
Rev. A | Page 19 of 24
AD8139
Using the β notation, Equation 15 can be written as
For a single-ended signal (for example, when VIN is grounded
and the input signal drives VIP), the input impedance becomes
VACM = βVOCM
+
1 − β
VICM
(16)
(17)
RG
RF
2(RG + RF )
(19)
RIN
=
or equivalently,
VACM =VICM + β
1−
VOCM −VICM
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to
the increased input resistance.
where VICM is the common-mode voltage of the input signal, i.e.,
VIP + VIN
VICM
=
.
2
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
Input Common-Mode Swing Considerations
Calculating Input Impedance
In some single-ended-to-differential applications, when using a
single-supply voltage attention must be paid to the swing of the
The input impedance of the circuit in Figure 57 will depend on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input signals,
the differential input impedance (RIN, dm) is simply
input common-mode voltage, VACM
.
Consider the case in Figure 59, where VIN is 5 V p-p swinging
about a baseline at ground and VREF is connected to ground.
RIN,dm = 2RG
(18)
5V
20Ω
0.1µF
200Ω
0.1µF
0.1µF
324Ω
15Ω
3
2.7nF
2.7nF
5
8
2
1
+
AVDD
DVDD
V
OCM
IN–
2.5V
AD8139
+2.5V
GND
V
–
IN
AD7674
4
–2.5V
6
V
IN+
REF
200Ω
324Ω
15Ω
DGND AGND REFGND REF REFBUFIN PDBUF
47µF
+1.7V
V
ACM
= 0
+0.95V
+0.2V
WITH V
REF
ADR431
0.1µF
2.5V
REFERENCE
Figure 59. AD8139 Driving AD7674, 18-Bit, 800 kSPS A/D Converter
Rev. A | Page 20 of 24
AD8139
This estimate assumes a minimum 90 degree phase margin for
the amplifier loop, which is a condition approached for gains
greater than 4. Lower gains will show more bandwidth than
predicted by the equation due to the peaking produced by the
lower phase margin.
The circuit has a differential gain of 1.6 and β = 0.38. VICM has
an amplitude of 2.5 V p-p and is swinging about ground. Using
the results in Equation 16, the common-mode voltage at the
AD8139’s inputs, VACM, is a 1.5 V p-p signal swinging about a
baseline of 0.95 V. The maximum negative excursion of VACM in
this case is 0.2 V, which exceeds the lower input common-mode
voltage limit.
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM is
calculated to be equal to VICM because VOCM = VICM. Therefore,
VACM swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that since VOCM = VACM = VICM no
wasted common-mode current flows. Figure 60 illustrates how
to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider will suffice
to develop the input voltage to the buffer.
The first output error component is calculated as
R + R
RG
⎛
⎜
⎞
⎟
F
G
Vo_e1=VIO
, or equivalently as V /β
(21)
IO
⎝
⎠
where VIO is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 μV.
5V
The second error is calculated as
0.1µF
324Ω
R + R
RG
RGRF
RF + RG
⎛
⎜
⎞⎛
⎞
⎟
F
G ⎟⎜
Vo_e2 = IIO
= I
(
RF
)
(22)
(23)
IO
3
⎝
⎠⎝
⎠
200Ω
5
8
2
1
+
V
OCM
V
IN
0V TO 5V
AD8139
where IIO is defined as the offset between the two input bias
currents.
–
4
6
The third error voltage is calculated as
200Ω
0.1µF
324Ω
TO AD7674 REFBUFIN
5V
0.1µF
Vo_e3 = ∆enr×(VICM −VOCM
)
+
+
AD8031
–
ADR431
2.5V
REFERENCE
where Δenr is the fractional mismatch between the two
feedback resistors.
10µF
The total differential offset error is the sum of these three error
sources.
Figure 60. Low-Z 2.5 V Buffer
Other Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network will still force
the output voltages to remain balanced, even when the RF/RG
feedback networks are mismatched. The mismatch will,
however, cause a gain error proportional to the feedback
network mismatch.
Another way to avoid the input common-mode swing limita-
tion is to use dual power supplies on the AD8139. In this case,
the biasing circuitry is not required.
Bandwidth Versus Closed-Loop Gain
The AD8139’s 3 dB bandwidth decreases proportionally to
increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
Ratio-matching errors in the external resistors will degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors will also produce a differential output component that is
equal to the VOCM input voltage times the difference between the
feedback factors (βs). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.
RG
RG + RF
f −3 dB,VOUT,dm
=
×(300 MHz)
(20)
or equivalently, β(300 MHz).
Rev. A | Page 21 of 24
AD8139
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
Driving a Capacitive Load
A purely capacitive load will react with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance, see Figure 6 and
Figure 61. The resistor and load capacitance will form a first-
order low-pass filter; therefore, the resistor value should be as
small as possible. In some cases, the ADCs require small series
resistors to be added on their inputs.
Figure 62 shows the AD8139 in a unity-gain configuration
driving the AD6645, which is a 14-bit high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a 50 Ω environment.
5
4
3
2
1
R
C
= 30.1Ω
S
L
R
C
= 30.1Ω
S
L
= 5pF
= 15pF
0
R
C
= 0Ω
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of 50 Ω that is seen by the
signal source. In order to have matched feedback loops, each
loop must have the same RG if they have the same RF. In the
input (upper) loop, RG is equal to the 200 Ω resistor in series
with the (+) input plus the parallel combination of RT and the
source resistance of 50 Ω. In the upper loop, RG is therefore
equal to 228 Ω. The closest standard 1% value to 228 Ω is 226 Ω
and is used for RG in the lower loop. Greater accuracy could be
achieved by using two resistors in series to obtain a resistance
closer to 228 Ω.
= 0pF
L, dm
R
C
= 60.4Ω
= 15pF
S
L
R
= 60.4Ω
S
C
= 5pF
L
V
V
=
±
5V
= 0.1V p-p
S
O, dm
G = 1 (R = R = 200Ω)
R
F
G
= 1kΩ
L, dm
10M
100M
FREQUENCY (MHz)
1G
Figure 61. Frequency Response for
Various Capacitive Load and Series Resistance
Things get more complicated when it comes to determining the
feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal
when terminated in 50 Ω. Thus, a 2 V p-p terminated amplitude
is produced by a 4 V p-p amplitude from VS. The Thevenin
equivalent circuit of the signal source and RT must be used
when calculating the closed-loop gain because in the upper loop
RG is split between the 200 Ω resistor and the Thevenin resis-
tance looking back toward the source. The Thevenin voltage of
the signal source is greater than the signal source output voltage
when terminated in 50 Ω because RT must always be greater
than 50 Ω. In this case, it is 61.9 Ω and the Thevenin voltage
and resistance are 2.2 V p-p and 28 Ω, respectively. Now the
upper input branch can be viewed as a 2.2 V p-p source in series
with 228 Ω. Since this is a unity-gain application, a 2 V p-p
differential output is required, and RF must therefore be 228 ×
(2/2.2) = 206 Ω. The closest standard value to this is 205 Ω.
The Typical Performance Characteristics that illustrate transient
response versus the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered to
when designing with the AD8139.A solid ground plane is recom-
mended and good wideband power supply decoupling networks
should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to the
summing nodes should be removed. Small amounts of stray
summing-node capacitance will cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on closed-loop gain into account.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line
termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
Rev. A | Page 22 of 24
AD8139
Exposed Paddle (EP)
Since this is a single-ended-to-differential application on a
single supply, the input common-mode voltage swing must be
checked. From Figure 62, β = 0.52, VOCM = 2.4 V, and VICM is
1.1 V p-p swinging about ground. Using Equation 16, VACM is
calculated to be 0.53 V p-p swinging about a baseline of 1.25 V,
and the minimum negative excursion is approximately 1 V.
The SOIC-8 and LFCSP packages have an exposed paddle on
the underside of its body. In order to achieve the specified
thermal resistance, it must have a good thermal connection to one
of the PCB planes. The exposed paddle must be soldered to a pad
on top of the board that is connected to an inner plane with several
thermal vias.
5V
3.3V
0.01µF
0.01µF
0.01µF
205Ω
25Ω
AV
DV
CC
CC
AIN
AIN
3
2V p-p
50Ω
200Ω
5
8
2
1
+
R
V
T
OCM
V
S
AD8139
61.9Ω
AD6645
SIGNAL
SOURCE
–
4
6
226Ω
GND C1
C2
VREF
205Ω
25Ω
0.1µF
0.1µF
2.4V
Figure 62. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS A/D Converter
Rev. A | Page 23 of 24
AD8139
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
BOTTOM VIEW
(PINS UP)
2.29 (0.092)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
2.29 (0.092)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
1
4
1.27 (0.05)
BSC
0.50 (0.020)
0.25 (0.010)
× 45°
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
1.27 (0.050)
0.40 (0.016)
0.51 (0.020)
0.31 (0.012)
0.25 (0.0098)
0.17 (0.0068)
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 63. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC/EP], Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches)
0.50
0.40
0.30
1
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
0.45
PIN 1
INDICATOR
1.90
1.75
1.60
2.75
BSC SQ
TOP
VIEW
1.50
REF
EXPOSED
PAD
0.50
BSC
(BOTTOM VIEW)
4
5
0.25
MIN
1.60
1.45
1.30
0.80 MAX
0.65TYP
0.90
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP], 3 mm × 3 mm Body (CP-8-2)—Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
Package Option
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
Branding
AD8139ARD
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
AD8139ARD-REEL
AD8139ARD-REEL7
AD8139ARDZ1
AD8139ARDZ-REEL1
AD8139ARDZ-REEL71
AD8139ACP-R2
AD8139ACP-REEL
AD8139ACP-REEL7
AD8139ACPZ-R21
AD8139ACPZ-REEL1
AD8139ACPZ-REEL71
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Small Outline Package (SOIC)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
8-Lead Lead Frame Chip Scale Package (LFCSP)
HEB
HEB
HEB
HEB
HEB
HEB
CP-8-2
1 Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
D04679–0–8/04(A)
Rev. A | Page 24 of 24
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