AD813ACHIPS [ADI]
Single Supply, Low Power Triple Video Amplifier; 单电源，低功耗三通道视频放大器
| 型号： | AD813ACHIPS |
| 厂家： | 
ADI |
| 描述： | Single Supply, Low Power Triple Video Amplifier |
| 文件： | 总19页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Low Power
Triple Video Amplifier
a
AD813
PIN CONFIGURATION
14-Lead DIP and SOIC
FEATURES
Low Cost
Three Video Amplifiers in One Package
Optimized for Driving Cables in Video Systems
Excellent Video Specifications (RL = 150 ⍀)
Gain Flatness 0.1 dB to 50 MHz
0.03% Differential Gain Error
0.06؇ Differential Phase Error
Low Power
Operates on Single +3 V to ؎15 V Power Supplies
5.5 mA/Amplifier Max Power Supply Current
High Speed
OUT2
–IN2
+IN2
DISABLE1
DISABLE2
DISABLE3
14
13
1
2
3
4
5
6
7
12
11
10
9
V +
S
V –
S
AD813
+IN1
–IN1
+IN3
–IN3
OUT3
OUT1
8
125 MHz Unity Gain Bandwidth (–3 dB)
500 V/s Slew Rate
High Speed Disable Function per Channel
Turn-Off Time 80 ns
50 MHz while offering differential gain and phase error of
0.03% and 0.06°. This makes the AD813 ideal for broadcast
and consumer video electronics.
Easy to Use
50 mA Output Current
Output Swing to 1 V of Rails
The AD813 offers low power of 5.5 mA per amplifier max and
runs on a single +3 V power supply. The outputs of each ampli-
fier swing to within one volt of either supply rail to easily accom-
modate video signals. While operating on a single +5 V supply
the AD813 still achieves 0.1 dB flatness to 20 MHz and 0.05%
& 0.05° of differential gain and phase performance. All this is
offered in a small 14-lead plastic DIP or SOIC package. These
features make this triple amplifier ideal for portable and battery
powered applications where size and power are critical.
APPLICATIONS
Video Line Driver
LCD Drivers
Computer Video Plug-In Boards
Ultrasound
RGB Amplifier
CCD Based Systems
The outstanding bandwidth of 125 MHz along with 500 V/µs of
slew rate make the AD813 useful in many general purpose, high
speed applications where a single +3 V or dual power supplies
up to ±15 V are needed. Furthermore the AD813 contains a
high speed disable function for each amplifier in order to power
down the amplifier or high impedance the output. This can then
be used in video multiplexing applications. The AD813 is avail-
able in the industrial temperature range of –40°C to +85°C in
plastic DIP and SOIC packages as well as chips.
PRODUCT DESCRIPTION
The AD813 is a low power, single supply triple video amplifier.
Each of the three current feedback amplifiers has 50 mA of output
current, and is optimized for driving one back-terminated video
load (150 Ω). The AD813 features gain flatness of 0.1 dB to
G = +2
R
= 150⍀
L
0.2
0.1
500mV
500ns
؎15V
100
90
0
–0.1
–0.2
–0.3
–0.4
–0.5
؎5V
3V
5V
10
0%
5V
100k
1M
10M
100M
FREQUENCY – Hz
Figure 1. Fine Scale Gain Flatness vs. Frequency,
G = +2, RL = 150 Ω
Figure 2. Channel Switching Characteristics for a 3:1 Mux
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD813–SPECIFICATIONS
Dual Supply
Model
(@ TA = +25؇C, RL = 150 ⍀, unless otherwise noted)
AD813A
Typ
Conditions
VS
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, No Peaking
±5 V
±15 V
45
75
65
100
MHz
MHz
Bandwidth for 0.1 dB
Flatness
G = +2
±5 V
±15 V
±5 V
±15 V
±5 V
±15 V
15
25
25
50
150
250
225
450
MHz
MHz
V/µs
V/µs
V/µs
V/µs
Slew Rate1
G = +2, RL = 1 kΩ
G = –1, RL = 1 kΩ
150
Settling Time to 0.1%
G = –1, RL = 1 kΩ
VO = 3 V Step
±5 V
±15 V
50
40
ns
ns
VO = 10 V Step
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
fC = 1 MHz, RL = 1 kΩ
f = 10 kHz
f = 10 kHz, +In
–In
±15 V
–90
3.5
1.5
dBc
±5 V, ±15 V
±5 V, ±15 V
±5 V, ±15 V
±5 V
±15 V
±5 V
nV√Hz
pA√Hz
pA√Hz
%
%
Degrees
Degrees
Input Current Noise
18
Differential Gain Error
Differential Phase Error
NTSC, G = ±2, RL = 150 Ω
0.08
0.03
0.13
0.06
0.09
0.12
±15 V
DC PERFORMANCE
Input Offset Voltage
±5 V, ±15 V
2
5
12
mV
mV
µV/°C
µA
T
MIN–TMAX
Offset Drift
–Input Bias Current
±5 V, ±15 V
±5 V, ±15 V
15
5
30
TMIN–TMAX
35
µA
+Input Bias Current
±5 V, ±15 V
±5 V
0.5
76
1.7
2.5
µA
µA
dB
dB
TMIN–TMAX
VO = ±2.5 V, RL = 150 Ω
TMIN–TMAX
Open-Loop Voltage Gain
69
66
VO = ±10 V, RL = 1 kΩ
TMIN–TMAX
±15 V
73
72
82
dB
dB
Open-Loop Transresistance
VO = ±2.5 V, RL = 150 Ω
±5 V
300
200
400
300
500
900
kΩ
kΩ
kΩ
kΩ
T
MIN–TMAX
VO = ±10 V, RL = 1 kΩ
TMIN–TMAX
±15 V
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
±15 V
±15 V
±15 V
±5 V
15
65
1.7
±4.0
±13.5
MΩ
Ω
pF
V
Input Capacitance
Input Common Mode
Voltage Range
±15 V
V
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
±Input Current
Input Offset Voltage
–Input Current
VCM = ±2.5 V
VCM = ±10 V
±5 V
54
57
58
2
0.07
62
1.5
0.05
dB
3
0.15
µA/V
µA/V
dB
µA/V
µA/V
±15 V
3.0
0.1
+Input Current
REV. B
–2–
AD813
Model
AD813A
Typ
Conditions
VS
Min
Max
Units
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150 Ω, TMIN–TMAX
RL = 1 kΩ, TMIN–TMAX
±5 V
±15 V
±5 V
±15 V
±15 V
3.5
13.6
25
3.8
14.0
40
50
100
±V
±V
mA
mA
mA
Output Current
30
Short Circuit Current
G = +2, RF = 715 Ω
VIN = 2 V
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
DC
G = +2, f = 5 MHz
G = +2, f = 40 MHz
±5 V, ±15 V
±15 V
–65
0.1
dB
dB
Input Offset Voltage
–Input Bias Current
TMIN–TMAX
TMIN–TMAX
±5 V, ±15 V
±5 V, ±15 V
0.5
2
3.5
25
mV
µA
POWER SUPPLY
Operating Range
Quiescent Current
±1.2
±18
4.0
5.5
6.7
0.65
1.0
V
Per Amplifier
±5 V
3.5
4.5
mA
mA
mA
mA
mA
±15 V
±15 V
±5 V
TMIN–TMAX
Per Amplifier
Quiescent Current, Powered Down
0.5
0.75
±15 V
Power Supply Rejection Ratio
Input Offset Voltage
–Input Current
VS = ±1.5 V to ±15 V
72
80
0.3
0.005
dB
µA/V
µA/V
0.8
0.05
+Input Current
DISABLE CHARACTERISTICS
Off Isolation
Off Output Impedance
Channel-to-Channel
Isolation
f = 5 MHz
G = +1
2 or 3 Channels
Mux, f = 5 MHz
±5 V, ±15 V
±5 V, ±15 V
±5 V, ±15 V
–57
12.5
–65
dB
pF
dB
Turn-On Time
Turn-Off Time
±5 V, ±15 V
100
80
ns
ns
NOTES
1Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain.
Specifications subject to change without notice.
–3–
REV. B
AD813–SPECIFICATIONS
Single Supply
(@ TA = +25؇C, RL = 150 ⍀, unless otherwise noted)
Model
AD813A
Typ
Conditions
VS
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, No Peaking
+5 V
+3 V
35
25
50
40
MHz
MHz
Bandwidth for 0.1 dB
Flatness
G = +2
+5 V
+3 V
+5 V
+3 V
12
8
20
15
100
50
MHz
MHz
V/µs
Slew Rate1
G = +2, RL = 1 kΩ
V/µs
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
Input Current Noise
f = 10 kHz
f = 10 kHz, +In
–In
NTSC, G = +2, RL = 150 Ω
G = +1
+5 V, +3 V
+5 V, +3 V
+5 V, +3 V
+5 V
+3 V
+5 V
3.5
1.5
18
0.05
0.2
0.05
0.2
nV√Hz
pA√Hz
pA√Hz
%
%
Degrees
Degrees
Differential Gain Error2
Differential Phase Error2
G = +2
G = +1
+3 V
DC PERFORMANCE
Input Offset Voltage
+5 V, +3 V
1.5
5
10
mV
mV
µV/°C
µA
T
MIN–TMAX
Offset Drift
–Input Bias Current
+5 V, +3 V
+5 V, +3 V
7
7
30
TMIN–TMAX
40
µA
+Input Bias Current
+5 V, +3 V
0.5
1.7
2.5
µA
µA
TMIN–TMAX
Open-Loop Voltage Gain
Open-Loop Transresistance
VO = +2.5 V p-p
VO = +0.7 V p-p
VO = +3 V p-p
VO = +1 V p-p
+5 V
+3 V
+5 V
+3 V
65
70
69
300
225
dB
dB
kΩ
kΩ
180
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
+5 V, +3 V
+5 V
15
90
2
MΩ
Ω
pF
V
Input Capacitance
Input Common Mode
Voltage Range
+5 V
+3 V
1.0
1.0
4.0
2.0
V
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
+Input Current
Input Offset Voltage
–Input Current
VCM = 1.25 V to 3.75 V
VCM = 1 V to 2 V
+5 V
+3 V
54
58
3
0.1
56
3.5
0.1
dB
6.5
0.2
µA/V
µA/V
dB
µA/V
µA/V
+Input Current
OUTPUT CHARACTERISTICS
Output Voltage Swing p-p
RL = 150 Ω, TMIN–TMAX
+5 V
+3 V
+5 V
+3 V
+5 V
3.0
1.0
20
3.2
1.3
30
25
40
±V p-p
±V p-p
mA
mA
mA
Output Current
15
Short Circuit Current
G = +2, RF = 715 Ω
VIN = 1 V
–4–
REV. B
AD813
Model
AD813A
Typ
Conditions
VS
Min
Max
Units
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
DC
G = +2, f = 5 MHz
G = +2, f = 20 MHz
+5 V, +3 V
+5 V, +3 V
–65
0.1
dB
dB
Input Offset Voltage
–Input Bias Current
TMIN–TMAX
TMIN–TMAX
+5 V, +3 V
+5 V, +3 V
0.5
2
3.5
25
mV
µA
POWER SUPPLY
Operating Range
Quiescent Current
2.4
36
V
Per Amplifier
+5 V
+3 V
+5 V
+5 V
+3 V
3.2
3.0
4.0
4.0
5.0
0.6
0.5
mA
mA
mA
mA
mA
TMIN–TMAX
Per Amplifier
Quiescent Current, Powered Down
0.4
0.4
Power Supply Rejection Ratio
Input Offset Voltage
–Input Current
VS = +3.0 V to +30 V
76
0.3
0.005
dB
µA/V
µA/V
+Input Current
DISABLE CHARACTERISTICS
Off Isolation
Off Output Impedance
Channel-to-Channel
Isolation
f = 5 MHz
G = +1
2 or 3 Channel
Mux, f = 5 MHz
+5 V, +3 V
+5 V, +3 V
+5 V, +3 V
–55
13
–65
dB
pF
dB
Turn-On Time
Turn-Off Time
+5 V, +3 V
100
80
ns
ns
TRANSISTOR COUNT
NOTES
111
1Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain.
2Single supply differential gain and phase are measured with the ac coupled circuit of Figure 52.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
Temperature
Range
Package
Description
Package
Options
Model
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration
AD813AN
AD813AR-14
AD813ACHIPS
AD813AR-REEL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
14-Lead Plastic DIP N-14
14-Lead Plastic SOIC R-14
Die Form
13" REEL
7" REEL
. . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
AD813AR-REEL7
Storage Temperature Range N, R . . . . . . . . –65°C to +125°C
5962-9559601M2A* –55°C to +125°C 20-Lead LCC
Operating Temperature Range
AD813A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
*Refer to official DSCC drawing for tested specifications and pin configuration.
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
14-Lead Plastic DIP Package: θJA = 75°C/W
14-Lead SOIC Package: θJA = 120°C/W
REV. B
–5–
AD813
2.5
Maximum Power Dissipation
T
= +150 C
J
The maximum power that can be safely dissipated by the
AD813 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for the plastic encap-
sulated parts is determined by the glass transition temperature
of the plastic, about 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
2.0
1.5
1.0
0.5
14-LEAD DIP PACKAGE
14-LEAD SOIC
While the AD813 is internally short circuit protected, this may
not be enough to guarantee that the maximum junction tem-
perature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is important to observe the derating
curves.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE –
C
Figure 3. Maximum Power Dissipation vs. Ambient
Temperature
It must also be noted that in (noninverting) gain configurations
(with low values of gain resistor), a high level of input overdrive
can result in a large input error current, which may result in a
significant power dissipation in the input stage. This power
must be included when computing the junction temperature rise
due to total internal power.
METALIZATION PHOTO
Dimensions shown in inches and (mm).
0.124
(3.15)
V –
S
11
+IN2
12
V –
S
11
V –
S
11
+IN3
10
9
8
–IN3
–IN2 13
OUT3
OUT2 14
0.057
(1.45)
7
OUT1
DISABLE1
1
2
DISABLE2
4
3
6
5
+IN1
DISABLE3
V +
S
–IN1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD813 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. B
AD813
20
20
18
16
15
10
5
V
= ؎15V
S
14
12
10
8
V
= ؎5V
S
0
0
5
10
15
20
–60 –40 –20
0
20
40
60
80 100 120 140
SUPPLY VOLTAGE – ؎Volts
JUNCTION TEMPERATURE –
C
Figure 4. Input Common-Mode Voltage Range vs.
Supply Voltage
Figure 7. Supply Current vs. Junction Temperature
20
13
T
= +25 C
A
12
11
10
15
NO LOAD
10
R
= 150⍀
L
5
0
9
8
0
5
10
15
20
10
SUPPLY VOLTAGE – ±Volts
12
14
16
0
2
4
6
8
SUPPLY VOLTAGE – ؎Volts
Figure 8 Supply Current vs. Supply Voltage at Low
Voltages
Figure 5. Output Voltage Swing vs. Supply Voltage
25
20
30
؎15V SUPPLY
25
15
10
20
15
10
–I , V = ؎5V
B
S
5
0
+I , V = ؎5V, ؎15V
B
S
–5
–10
–15
–20
–I , V = ؎15V
B
S
؎5V SUPPLY
5
–25
0
10
100
1k
10k
–60 –40 –20
0
20
40
60
80 100 120 140
LOAD RESISTANCE – ⍀
JUNCTION TEMPERATURE –
C
Figure 6. Output Voltage Swing vs. Load Resistance
Figure 9. Input Bias Current vs. Junction Temperature
REV. B
–7–
AD813
4
70
2
V
= ؎5V
S
0
–2
60
50
–4
V
= ؎15V
S
–6
–8
40
30
–10
–12
–14
–16
20
–60 –40 –20
0
20
40
60
80 100 120 140
0
5
10
15
20
JUNCTION TEMPERATURE –
C
SUPPLY VOLTAGE – ؎Volts
Figure 10. Input Offset Voltage vs. Junction
Temperature
Figure 13. Linear Output Current vs. Supply Voltage
160
140
120
100
80
1k
V
= ؎15V
G = +2
S
100
10
1
SINK
SOURCE
5V
S
0.1
60
15V
S
0.01
40
10k
100k
1M
FREQUENCY – Hz
10M
100M
–60 –40 –20
0
20
40
60
80 100 120 140
JUNCTION TEMPERATURE –
C
Figure 11. Short Circuit Current vs. Junction
Temperature
Figure 14. Closed-Loop Output Resistance vs.
Frequency
80
70
60
50
1M
100k
10k
V
= ؎5V
S
40
30
20
1k
V
= ؎15V
S
100
100M
10M
1M
FREQUENCY – Hz
–60 –40 –20
0
20
40
60
80 100 120 140
100k
JUNCTION TEMPERATURE –
C
Figure 12. Linear Output Current vs. Junction
Temperature
Figure 15. Output Resistance vs. Frequency, Disabled
State
–8–
REV. B
AD813
0
100
100
10
1
120
100
–45
V
= ؎15V
PHASE
S
–90
–135
–180
INVERTING INPUT CURRENT NOISE
GAIN
V
V
= 3V
S
10
80
60
= ؎15V
S
V
= 3V
S
VOLTAGE NOISE
NONINVERTING INPUT
CURRENT NOISE
1
100k
40
10k
100k
1M
FREQUENCY – Hz
10M
100M
10
100
1k
FREQUENCY – Hz
10k
Figure 19. Open-Loop Transimpedance vs. Frequency
(Relative to 1 Ω)
Figure 16. Input Current and Voltage Noise vs.
Frequency
90
–30
681⍀
G = +2
80
70
60
50
40
30
20
10
681⍀
681⍀
V
V
V
= 2V p-p
= ؎15V: R = 1k⍀
= ؎5V: R = 150⍀
O
S
S
V
V
IN
OUT
L
–50
L
681⍀
–70
–90
2ND HARMONIC
= ؎5V
V
S
V
= 3V
S
3RD HARMONIC
= ؎5V
V
= ؎15V
S
V
= ؎15V
S
V
S
–110
2ND
3RD
–130
10k
100k
1M
FREQUENCY – Hz
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 20. Harmonic Distortion vs. Frequency
Figure 17. Common-Mode Rejection vs. Frequency
10
80
70
GAIN = –1
8
V
= ؎15V
S
؎15V
6
4
2
60
50
؎1.5V
0
1%
0.1%
0.025%
40
–2
–4
30
20
10
0
–6
–8
–10
100k
1M
10M
100M
20
40
60
80
10k
FREQUENCY – Hz
SETTLING TIME – ns
Figure 21. Output Swing and Error vs. Settling Time
Figure 18. Power Supply Rejection vs. Frequency
REV. B
–9–
AD813
700
1000
900
V
R
= ؎15V
= 500⍀
S
L
600
500
800
700
600
G = +10
400
300
G = –1
G = +10
500
400
300
200
G = –1
G = +2
200
100
G = +2
G = +1
100
G = +1
0
0
0
0
1.5
3.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0
1
2
3
4
5
6
7
8
9
10
OUTPUT STEP SIZE – V p-p
SUPPLY VOLTAGE – ؎Volts
Figure 22. Slew Rate vs. Output Step Size
Figure 25. Maximum Slew Rate vs. Supply Voltage
2V
500mV
20ns
50ns
1 00
90
100
V
IN
90
V
IN
10
10
V
V
OUT
OUT
0 %
0%
500mV
2V
Figure 23. Large Signal Pulse Response, Gain = +1,
Figure 26. Small Signal Pulse Response, Gain = +1,
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
+90
R
= 150⍀
PHASE
L
0
V
= ؎15V
140
S
–90
–180
–270
3V
؎5V
120
100
5V
+1
0
GAIN
V
= ؎15V
R
= 866⍀
S
R
= 750⍀
F
80
60
F
–1
3V
5V
–2
–3
–4
–5
R
= 1k⍀
F
؎5V
40
–6
2
4
6
8
10
12
14
16
1
10
100
1000
SUPPLY VOLTAGE – ؎Volts
FREQUENCY – MHz
Figure 24. Closed-Loop Gain and Phase vs. Frequency,
G = +1
Figure 27. –3 dB Bandwidth vs. Supply Voltage, G = +1
–10–
REV. B
AD813
20ns
50mV
50ns
500mV
100
90
100
90
V
IN
V
IN
10
10
V
OUT
V
OUT
0%
0%
500mV
500mV
Figure 31. Small Signal Pulse Response, Gain = +10,
(RF = 357 Ω, RL = 150 Ω, VS = ±5 V)
Figure 28. Large Signal Pulse Response, Gain = +10,
(RF = 357 Ω, RL = 500 Ω, VS = ±15 V)
G = +10
= 150⍀
PHASE
GAIN
PHASE
GAIN
G = +10
= 1k⍀
V
= ؎15V
S
V
= ؎15V
؎5V
0
0
R
S
L
R
L
–90
–90
؎5V
3V
5V
+1
–180
–270
+1
–180
–270
5V
3V
0
0
–1
V
= ؎15V
؎5V
–1
–360
S
V
= ؎15V
S
5V
3V
5V
3V
–2
–2
–3
–4
–3
–4
؎5V
–5
–6
–5
–6
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 32. Closed-Loop Gain and Phase vs. Frequency,
Figure 29. Closed-Loop Gain and Phase vs. Frequency,
G = +10, RL = 1 kΩ
G = +10, RL = 150 Ω
G = +10
G = +10
R
= 150⍀
R
= 1k⍀
L
L
80
70
60
90
80
70
R
= 357⍀
F
R
= 357⍀
= 649⍀
PEAKING 1dB
= 154⍀
F
R
F
50
40
30
20
60
50
40
30
R
R
= 649⍀
F
F
R
= 154⍀
F
20
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎Volts
Figure 30. –3 dB Bandwidth vs. Supply Voltage,
Figure 33. –3 dB Bandwidth vs. Supply Voltage,
G = +10, RL = 150 Ω
G = +10, RL = 1 kΩ
REV. B
–11–
AD813
500mV
20ns
2V
50ns
100
90
100
90
10
10
0%
0%
2V
500mV
Figure 34. Large Signal Pulse Response, Gain = –1,
Figure 37. Small Signal Pulse Response, Gain = –1,
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
V
= ؎15V
G = –1
= 150⍀
G = –10
R = 1k⍀
L
PHASE
GAIN
PHASE
GAIN
S
V
= ؎15V
S
0
0
R
L
؎5V
–90
–90
؎5V
3V
3V
5V
+1
–180
–270
+1
–180
–270
5V
0
0
V
= ؎15V
S
–1
–1
V
= ؎15V
S
3V
–2
–2
3V
؎5V
–3
–4
–3
–4
؎5V
5V
5V
–5
–6
–5
–6
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 38. Closed-Loop Gain and Phase vs. Frequency,
Figure 35. Closed-Loop Gain and Phase vs. Frequency,
G = –10, RL = 1 kΩ
G = –1, RL = 150 Ω
G = –1
G = –10
R
= 150⍀
R
= 1k⍀
L
L
110
100
90
80
70
60
50
40
30
20
R
R
= 357⍀
= 649⍀
PEAKING 1.0dB
= 681⍀
F
R
F
R
= 154⍀
F
80
70
60
50
PEAKING 0.2dB
R
= 715⍀
F
F
40
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎Volts
Figure 36. –3 dB Bandwidth vs. Supply Voltage, G = –1,
RL = 150 Ω
Figure 39. –3 dB Bandwidth vs. Supply Voltage,
G = –10, RL = 1 kΩ
–12–
REV. B
AD813
General Consideration
To estimate the –3 dB bandwidth for closed-loop gains or feed-
back resistors not listed in the above table, the following two
pole model for the AD813 may be used:
The AD813 is a wide bandwidth, triple video amplifier that
offers a high level of performance on less than 5.5 mA per am-
plifier of quiescent supply current. With its fast acting power
down switch, it is designed to offer outstanding functionality
and performance at closed-loop inverting or noninverting gains
of one or greater.
G
ACL
=
(RF +GrIN)CT
2 π f2
S2
+S (RF + GrIN )CT +1
Built on a low cost, complementary bipolar process, and achiev-
ing bandwidth in excess of 100 MHz, differential gain and phase
errors of better than 0.1% and 0.1° (into 150 Ω), and output
current greater than 40 mA, the AD813 is an exceptionally
efficient video amplifier. Using a conventional current feedback
architecture, its high performance is achieved through careful
attention to design details.
where:
A
G
CL= closed-loop gain from “transcapacitance”
= 1 + RF/RG
rIN = input resistance of the inverting input
CT = “transcapacitance,” which forms the
open-loop dominant pole with the
transresistance
RF = feedback resistor
RG = gain resistor
f2 = frequency of second (nondominant) pole
Choice of Feedback & Gain Resistors
Because it is a current feedback amplifier, the closed-loop band-
width of the AD813 depends on the value of the feedback resis-
tor. The bandwidth also depends on the supply voltage. In
addition, attenuation of the open-loop response when driving
load resistors less than about 250 Ω will also affect the band-
width. Table I contains data showing typical bandwidths at
different supply voltages for some useful closed-loop gains when
driving a load of 150 Ω. (Bandwidths will be about 20% greater
for load resistances above a few hundred ohms.)
s
= 2 πj f
Appropriate values for the model parameters at different supply
voltages are listed in Table II. Reasonable approximations for
these values at supply voltages not found in the table can be
obtained by a simple linear interpolation between those tabu-
lated values which ‘bracket’ the desired condition.
Table II. Two Pole Model Parameters at Various Supplies
Table I. –3 dB Bandwidth vs. Closed-Loop Gain and
Feedback Resistor , (RL = 150 ⍀)
VS (V)
rIN (⍀)
CT (pF)
f2 (MHz)
±15
±5
+5
85
90
105
115
2.5
3.8
4.8
5.5
150
125
105
95
VS (V)
Gain
RF (⍀)
BW (MHz)
±15
+1
+2
+10
–1
–10
866
681
357
681
357
125
100
60
100
55
+3
As discussed in many amplifier and electronics textbooks (such
as Roberge’s Operational Amplifiers: Theory and Practice), the
–3 dB bandwidth for the 2-pole model can be obtained as:
±5
+5
+3
+1
+2
+10
–1
–10
750
649
154
649
154
75
65
40
70
40
1/2
1/2
f
= f 1 − 2d2 +(2 − 4d2 + 4d 4
)
[
]
3
n
1/2
f2
f
=
n
where:
and:
(RF + Gr IN ) CT
+1
+2
+10
–1
–10
715
619
154
619
154
60
50
30
50
30
1/2
1
d =
f (RF +GrIN ) CT
2
[
]
2
This model will predict –3 dB bandwidth within about 10% to
15% of the correct value when the load is 150 Ω. However, it is
not accurate enough to predict either the phase behavior or the
frequency response peaking of the AD813.
+1
+2
+10
–1
–10
681
619
154
619
154
50
40
25
40
20
The choice of feedback resistor is not critical unless it is impor-
tant to maintain the widest, flattest frequency response. The
resistors recommended in the table are those (metal film values)
that will result in the widest 0.1 dB bandwidth. In those appli-
cations where the best control of the bandwidth is desired, 1%
metal film resistors are adequate. Wider bandwidths can be
attained by reducing the magnitude of the feedback resistor (at
the expense of increased peaking), while peaking can be reduced
by increasing the magnitude of the feedback resistor.
REV. B
–13–
AD813
Printed Circuit Board Layout Guidelines
A carefully laid-out PC board should be able to achieve the level
of crosstalk shown in the figure. The most significant contribu-
tors to difficulty in achieving low crosstalk are inadequate power
supply bypassing, overlapped input and/or output signal paths,
and capacitive coupling between critical nodes.
As with all wideband amplifiers, printed circuit board parasitics
can affect the overall closed-loop performance. Most important
for controlling the 0.1 dB bandwidth are stray capacitances at
the output and inverting input nodes. Increasing the space be-
tween signal lines and ground plane will minimize the coupling.
Also, signal lines connecting the feedback and gain resistors
should be kept short enough that their associated inductance
does not cause high frequency gain errors.
The bypass capacitors must be connected to the ground plane at
a point close to and between the ground reference points for the
loads. (The bypass of the negative power supply is particularly
important in this regard.) This requires careful planning as
there are three amplifiers in the package, and low impedance
signal return paths must be provided for each load. (Using a
parallel combination of 1 µF, 0.1 µF, and 0.01 µF bypass ca-
pacitors will help to achieve optimal crosstalk.)
Power Supply Bypassing
Adequate power supply bypassing can be very important when
optimizing the performance of high speed circuits. Inductance
in the supply leads can (for example) contribute to resonant
circuits that produce peaking in the amplifier’s response. In
addition, if large current transients must be delivered to a load,
then large (greater than 1 µF) bypass capacitors are required to
produce the best settling time and lowest distortion. Although
0.1 µF capacitors may be adequate in some applications, more
elaborate bypassing is required in other cases.
The input and output signal return paths (to the bypass caps)
must also be kept from overlapping. Since ground connections
are not of perfectly zero impedance, current in one ground
return path can produce a voltage drop in another ground re-
turn path if they are allowed to overlap.
Electric field coupling external to (and across) the package can
be reduced by arranging for a narrow strip of ground plane to be
run between the pins (parallel to the pin rows). Doing this on
both sides of the board can reduce the high frequency crosstalk
by about 5 dB or 6 dB.
When multiple bypass capacitors are connected in parallel, it is
important to be sure that the capacitors themselves do not form
resonant circuits. A small (say 5 Ω) resistor may be required in
series with one of the capacitors to minimize this possibility.
As discussed below, power supply bypassing can have a signifi-
cant impact on crosstalk performance.
Driving Capacitive Loads
When used with the appropriate output series resistor, any load
capacitance can be driven without peaking or oscillation. In
most cases, less than 50 Ω is all that is needed to achieve an
extremely flat frequency response. As illustrated in Figure 44,
the AD813 can be very attractive for driving large capacitive
loads. In this case, the AD813’s high output short circuit cur-
rent allows for a 150 V/µs slew rate when driving a 510 pF
capacitor.
Achieving Low Crosstalk
Measured crosstalk from the output of Amplifier 2 to the input
of Amplifier 1 of the AD813 is shown in Figure 40. All other
crosstalk combinations, (from the output of one amplifier to the
input of another), are a few dB better than this due to the addi-
tional distance between critical signal nodes.
–10
R
= 150⍀
L
R
F
–20
–30
–40
–50
–60
0.1F
1.0F
+V
S
R
G
4
R
S
–70
–80
–90
V
AD813
11
O
V
R
C
IN
L
L
1.0F
0.1F
R
T
–100
–110
–V
S
100k
1M
10M
100M
FREQUENCY – Hz
Figure 41. Circuit for Driving a Capacitive Load
Figure 40. Worst Case Crosstalk vs. Frequency
–14–
REV. B
AD813
Overload Recovery
V
= ؎5V
S
There are three important overload conditions to consider.
They are due to: input common-mode voltage overdrive, out-
put voltage overdrive, and input current overdrive. When the
amplifier is configured for low closed-loop gains, and the input
common-mode voltage range is exceeded, the recovery time will
be very fast, typically under 30 ns. When configured for a
higher gain, and overloaded at the output, the recovery time will
also be short. For example, in a gain of +10, with 6 dB of
input overdrive, the recovery time of the AD813 is about 25 ns
(see Figure 45).
G = +2
R
R
C
= 750⍀
= 1k⍀
= 10pF
F
L
L
9
6
R
= 0
S
3
0
R
= 30⍀
S
R
= 50⍀
S
–3
1V
50ns
1
10
100
1000
100
90
FREQUENCY – MHz
Figure 42. Response to a Small Load Capacitor at
VS = ±5 V
V
= ؎15V
S
G = +2
10
R
R
= 750⍀
= 1k⍀
F
L
0%
2V
9
6
Figure 45. 6 dB Overload Recovery, G = +10,
(RL = 500 Ω, RF = 357 Ω, VS = ±5 V)
C
= 150pF, R = 30⍀
L
S
3
0
In the case of high gains with very high levels of input overdrive,
a longer recovery time will occur. For example, if the input
common-mode voltage range is exceeded in the gain of +10, the
recovery time will be on the order of 100 ns. This is primarily
due to current overloading of the input stage.
C
= 510pF, R = 15⍀
L
S
–3
1
10
100
1000
As noted in the warning under Maximum Power Dissipation, a
high level of input overdrive in a high noninverting gain circuit
can result in a large current flow in the input stage. Though this
current is internally limited to about 40 mA, its effect on the
total power dissipation may be significant.
FREQUENCY – MHz
Figure 43. Response to a Large Load Capacitor at
VS = ±15 V
5V
100ns
100
90
100
10
0%
5V
Figure 44. Circuit of Figure 38 Driving a 510 pF Load
Capacitor, VS = ±15 V (RL = 1 kΩ, RF = RG = 750 Ω,
RS =15 Ω)
REV. B
–15–
AD813
High Performance Video Line Driver
Figures 50 and 51 show the worst case matching; the match
between amplifiers 2 and 3 is typically much better than this.
At a gain of +2, the AD813 makes an excellent driver for a back
terminated 75 Ω video line. Low differential gain and phase
errors and wide 0.1 dB bandwidth can be realized over a wide
range of power supply voltage. Excellent gain and group delay
matching are also attainable over the full operating supply volt-
age range.
G = +2
R
= 150⍀
L
0.2
0.1
؎15V
R
R
G
F
0
+V
S
0.1F
–0.1
–0.2
–0.3
–0.4
–0.5
؎5V
3V
5V
75⍀
CABLE
4
75⍀
75⍀
CABLE
V
AD813
11
OUT
V
75⍀
IN
0.1F
75⍀
100k
1M
10M
100M
–V
S
FREQUENCY – Hz
Figure 46. A Video Line Driver Operating at a Gain of
+2 (RF = RG from Table I)
Figure 49. Fine-Scale Gain (Normalized) vs. Frequency
+90
2.5
PHASE
G = +2
= 150⍀
G = +2
R
0
R = 150⍀
2.0
1.5
L
L
–90
V
= ؎15V
3V
S
S
؎5V
–180
–270
+1
0
1.0
0.5
0
5V
GAIN
–1
–2
–3
–4
–5
–6
V
= ؎15V
S
V
= ؎15V
؎5V
5V
–0.5
V
= 3V
S
–1.0
–1.5
–2.0
3V
–2.5
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 50. Closed-Loop Gain Matching vs. Frequency
Figure 47. Closed-Loop Gain & Phase vs. Frequency for
the Line Driver
10
8
120
R
R
R
= 590⍀
= 681⍀
= 750⍀
110
100
V = 3V
S
F
F
F
5V
؎5V
6
؎15V
4
2
90
80
DELAY
NO PEAKING
70
60
50
1.0
V
= ؎15V
0.5
0
S
40
30
20
3V
–0.5
DELAY MATCHING
–1.0
100k
1M
10M
100M
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY – Hz
SUPPLY VOLTAGE – Volts
Figure 51. Group Delay and Group Delay Matching vs.
Figure 48. –3 dB Bandwidth vs. Supply Voltage for
Gain = +2, RL = 150 Ω
Frequency, G = +2, RL = 150 Ω
–16–
REV. B
AD813
Disable Mode Operation
Operation Using a Single Supply
Pulling the voltage on any one of the Disable pins about 2.5 V
down from the positive supply will put the corresponding ampli-
fier into a disabled, powered down, state. In this condition, the
amplifier’s quiescent supply current drops to about 0.5 mA, its
output becomes a high impedance, and there is a high level of
isolation from input to output. In the case of the gain of two
line driver for example, the impedance at the output node will
be about the same as for a 1.4 kΩ resistor (the feedback plus
gain resistors) in parallel with a 12.5 pF capacitor and the input
to output isolation will be about 65 dB at 1 MHz.
The AD813 will operate with total supply voltages from 36 V
down to 2.4 V. With proper biasing (see Figure 52) it can
make an outstanding single supply video amplifier. Since the
input and output voltage ranges extend to within 1 V of the
supply rails, it will handle a 1.3 V peak-to-peak signal on a
single 3.3 V supply, or a 3 V peak-to-peak signal on a single
5 V supply. The small signal 0.1 dB bandwidths will exceed
10 MHz in either case, and the large signal bandwidths will
exceed 6 MHz.
The capacitively coupled cable driver in Figure 52 will achieve
outstanding differential gain and phase errors of 0.05% and 0.05
degrees respectively on a single 5 V supply. Resistor R2, in this
circuit, is selected to optimize the differential gain and phase by
biasing the amplifier in its most linear region.
Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pins is about 35 kΩ in parallel
with a few pF. When grounded, about 50 µA flows out of a
disable pin on ±5 V supplies.
619⍀
619⍀
Input voltages greater than about 1.5 V peak-to-peak will defeat
the isolation. In addition, large signals (greater than 3 V peak-
to-peak) applied to the output node will cause the output im-
pedance to drop significantly.
R3
C3
1k⍀
30F
+5V
C2
1F
R1
9k⍀
C
47F
OUT
75⍀
CABLE
4
75⍀
C1
2F
V
AD813
OUT
When the Disable pins are driven by complementary output
CMOS logic (such as the 74HC04), the disable time is about
80 ns (until the output goes high impedance) and the enable
time is about 100 ns (to low impedance output) on ±15 V sup-
plies. When operated on ±15 V supplies, the disable pins
should be driven by open drain logic. In this case, pull-up resis-
tors from the disable pins to the plus supply will ensure mini-
mum switching time.
75⍀
V
IN
11
R2
12.4k⍀
Figure 52. Biasing for Single Supply Operation
V
= 5V
S
0
G = +2
R
R
= 619⍀
= 150⍀
PHASE
F
L
–90
–180
–270
0.5
0
464⍀
590⍀
+5V
GAIN
–0.5
–1.0
4
1
6
5
84⍀
84⍀
84⍀
7
14
8
–1.5
–2.0
V
1
IN
75⍀
–2.5
–3.0
–3.5
SELECT1
464⍀
590⍀
1
10
100
1000
FREQUENCY – MHz
Figure 53. Closed-Loop Gain and Phase vs. Frequency,
Circuit of Figure 52
75⍀
CABLE
13
12
V
OUT
V
2
75⍀
IN
2
1V
50ns
75⍀
100
90
V
SELECT2
IN
464⍀
590⍀
9
V
OUT
10
11
3
V
3
10
IN
0%
75⍀
–5V
500mV
SELECT3
Figure 54. Pulse Response for the Circuit of Figure 52
with +VS = 5 V
Figure 55. A Fast Switching 3:1 Video Mux
(Supply Bypassing Not Shown)
REV. B
–17–
AD813
3:1 Video Multiplexer
Single Supply Differential Line Driver
Wiring the amplifier outputs together will form a 3:1 mux with
outstanding gain flatness. Figure 55 shows a recommended
configuration which results in –0.1 dB bandwidth of 20 MHz
and OFF channel isolation of 60 dB at 10 MHz on ±5 V sup-
plies. The time to switch between channels is about 180 ns.
Switching time is only slightly affected by signal level.
Due to its outstanding overall performance on low supply volt-
ages, the AD813 makes possible exceptional differential trans-
mission on very low power. The circuit of Figure 59 will convert
a single-ended, ground referenced signal to a differential signal
whose common-mode reference is set to one half the supply
voltage. This allows for a greater than 2 V peak-to-peak signal
swing on a single 3 V power supply. A bandwidth over 30 MHz
is achieved with 20 mA of output drive on only 30 mW of quies-
cent power (excluding load current).
500mV
500ns
100
90
715⍀
1F
715⍀
V
+
OUT
+3V
R
L1
4
2
+3V
715⍀
10
1k⍀
0%
1F
715⍀
715⍀
715⍀
V
IN
5V
1F
9k⍀
1
715⍀
1F
Figure 56. Channel Switching Characteristic for the
3:1 Mux
10k⍀
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
3
V
–
OUT
11
R
L2
715⍀
715⍀
Figure 59. Single 3 V Supply Differential Line Driver
with 2 V Swing
1V
50ns
V
100
90
IN
100k
1M
10M
100M
FREQUENCY – Hz
Figure 57. 3:1 Mux OFF Channel Feedthrough vs.
Frequency
+
–
0
10
V
– V
OUT
OUT
PHASE
0%
–45
1V
–90
0.5
–135
–180
0
–0.5
–1.0
Figure 60. Differential Driver Pulse Response (VS = 3 V,
L1 = RL2 = 200 Ω)
GAIN
R
–1.5
–2.0
–2.5
–3.0
1
10
100
FREQUENCY – MHz
Figure 58. 3:1 Mux ON Channel Gain and Phase vs.
Frequency
–18–
REV. B
AD813
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
0.795 (20.19)
0.725 (18.42)
14
8
0.280 (7.11)
0.240 (6.10)
1
7
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558) 0.100 0.070 (1.77)
(2.54)
BSC
0.014 (0.356)
0.045 (1.15)
14-Lead SOIC
(R-14)
0.3444 (8.75)
0.3367 (8.55)
14
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45
0.0098 (0.25)
0.0040 (0.10)
8
0
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. B
–19–
相关型号：
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