AD8141ACPZ-R2_技术文档

Low Cost, Triple Differential Drivers

for Wideband Video

AD8141/AD8142

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Triple, high speed differential drivers

255 MHz, −3 dB large signal bandwidth

65 MHz, 0.1 dB flatness

24 23 22 21 20 19

1150 V/μs slew rate

12 ns settling time

AD8141

V

C

DIS

/GND

–IN A

1

2

3

4

5

6

18

17

OCM

Single 5 V or split supply operation

Fixed gain of 2

Internal common-mode feedback network

Output balance error −50 dB at 50 MHz

AD8142 has integrated sync-on-common-mode circuitry

High-Z output when disabled

V

S+

S–

–

+

16 –IN C

15 +IN C

+IN A

/GND

–

+

V

/GND

14

S–

–OUT A

13 –OUT C

7

8

9

10 11 12

Differential-to-differential or single-ended-to-differential

operation

High isolation between amplifiers: −100 dB at 10 MHz

Low power: 44 mA at 5 V

Figure 1.

Available in space-saving packaging: 4 mm × 4 mm LFCSP

24 23 22 21 20 19

AD8142

APPLICATIONS

Keyboard-video-mouse (KVM) networking

Video distribution

Digital signage

DIS

/GND

–IN R

1

SYNC LEVEL

18

17

V

2

3

4

5

6

S+

S–

×2

16 –IN B

15 +IN B

Security cameras

+IN R

/GND

–

+

–

+

V

/GND

14

S–

–OUT R

13 –OUT B

GENERAL DESCRIPTION

7

8

9

10 11 12

The AD8141 and AD8142 are triple, low cost, differential or

single-ended-input-to-differential-output drivers. Each amplifier

has a fixed gain of 2 to compensate for the attenuation of the

line termination resistors. The AD8141 and AD8142 are

specifically designed for RGB signals but can be used for any

type of signals. The amplifiers have very fast slew rate and

settling time while being manufactured on a cost effective

CMOS process. They are optimized for high resolution video

performance with a 0.1 dB flatness of 65 MHz, which allows

driving high resolution video over any type of UTP cable.

Figure 2.

The AD8142 includes a unique sync-on-common-mode feature

that allows the user to transmit balanced horizontal and vertical

video sync signals over the three common-mode channels.

Additionally, the AD8141 and AD8142 both have a disable

feature that, when asserted, produces high-Z outputs, allowing

line isolation and easy multiplexing.

The drivers have an internal common-mode feedback loop

that provides output amplitude and phase matching, achieving

−50 dB balance error at 50 MHz and thereby suppressing even-

order harmonics and minimizing radiated electromagnetic

interference (EMI).

The AD8141 and AD8142 are available in a 24-lead 4 mm × 4 mm

LFCSP and operate over a temperature range of −40°C to +85°C.

They can be used with the AD8145 triple differential-to-single-

ended receiver, AD8123 triple equalizer, AD8120 triple delay

line, and the AD8117 or AD8175 crosspoint switches to produce

a high resolution video distribution system.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8141/AD8142

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Common-Mode Voltage Range in Single-Supply

Applications ................................................................................ 16

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation ..................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 8

Basic Test Circuit........................................................................ 13

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Analyzing an Application Circuit............................................. 15

Closed-Loop Gain ...................................................................... 15

Calculating an Application Circuit’s Input Impedance......... 15

Terminating a Single-Ended Input .......................................... 16

Driving a Capacitive Load......................................................... 17

Disable ......................................................................................... 17

AD8142 Sync-On-Common-Mode......................................... 17

Applications Information.............................................................. 18

Driving RGB Video Over Cat-5 Cable .................................... 18

Single 5 V Supply Application Information............................ 19

AD8142 Signal Levels on Various Supplies ............................ 20

Disable Feature ........................................................................... 20

Driving Multiple Outputs.......................................................... 21

Video Sync-On-Common-Mode (AD8142) .......................... 21

Layout and Power Supply Decoupling Considerations......... 22

Amplifier-to-Amplifier Isolation ............................................. 22

Exposed Paddle (EPAD)............................................................ 22

Typical AD8142 5 V Application Circuit................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD8141/AD8142

SPECIFICATIONS

V_S+= 5 V, V_S−= 0 V, R_{L, dm}= 200 Ω, T_A= 25°C, V_OCM= 1.5 V (AD8141), H_SYNC, V_SYNC, and SYNC LEVEL = 0 V (AD8142), unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIFFERENTIAL INPUT PERFORMANCE

Dynamic Performance

−3 dB Small Signal Bandwidth

−3 dB Large Signal Bandwidth

Bandwidth for 0.1 dB Flatness

Slew Rate

V_O= 0.2 V p-p, AD8141/AD8142

V_O= 2 V p-p, AD8141/AD8142

V_O= 2 V p-p

V_O= 2 V p-p, 25% to 75% (rise/fall)

V_O= 2 V step

275/285

255/265

65

1150/1250

12

MHz

V/μs

ns

Settling Time to 0.1%

Isolation Between Amplifiers

f = 10 MHz, between Amplifier R and

Amplifier G

−100

dB

Differential Input Characteristics

Input Common-Mode Voltage Range

Input Resistance

V_OCM= V_s+/2

Differential

Single-ended input

Differential

ΔV_{OUT, dm}/ΔV_{IN, cm}, ΔV_{IN, cm}

V_S−+ 0.2

V_S+− 1

V

2

1.5

2

kΩ

pF

dB

Input Capacitance

DC CMRR

=

1 V

−60

Differential Output Characteristics

Differential Signal Gain

Output Voltage Swing

Output Offset Voltage

Output Offset Drift

ΔV_{OUT, dm}/ΔV_{IN, dm}, ΔV_{IN, dm}

Each single-ended output

1.95

V_S−+ 0.18

−70

2

2.04

V_S+− 0.4

+70

V/V

V

mV

μV/°C

dB

nV/√Hz

Loads

1.5

30

−50

−66

41

T_MINto T_MAX

f = 50 MHz

DC

f = 20 MHz

1.4 V p-p into 200 Ω per load

Output Balance Error

−43

Output Voltage Noise (RTO)

Maximum Number of Parallel Loads

COMMON-MODE INPUT PERFORMANCE (AD8141)

V_OCMDynamic Performance

−3 dB Bandwidth

4

ΔV_OCM= 100 mV p-p

V_OCM= 0.5 V to 2.5 V, 25% to 75% (rise/fall)

114

130/155

1.00

MHz

V/μs

V/V

Slew Rate

DC Gain

ΔV_OCM

=

1 V

0.98

1.02

V_OCMInput Characteristics

Input Voltage Range

Input Resistance

Input Offset Voltage

DC CMRR

V_S−+ 0.2

−87

V_S+− 0.2

+26

V

Thevenin to midsupply

ΔV_{OUT, dm}/ΔV_OCM; ΔV_OCM

2.8

−30

−60

kΩ

mV

dB

= 1 V

COMMON-MODE SYNC PERFORMANCE (AD8142)

Slew Rate

V_{OUT, cm}= 0.5 V to +2.5 V; 25% to 75%

(rise/fall)

130/155

V_S−+ 1.5

V/μs

V

Nominal Output Common-Mode Level

H_SYNCAND V_SYNCINPUTS (AD8142)

Input Low Voltage

Referenced to GND

0 to 1.6

1.9 to 5

V

Input High Voltage

SYNC LEVEL INPUT (AD8142)

Input Voltage Range

Setting to Achieve 0.5 V Pulse Levels

Gain to Red Common-Mode Output

Gain to Green Common-Mode Output

Gain to Blue Common-Mode Output

Referenced to V_S−

ΔV_{OUT, cm}/ΔV_{SYNC LEVEL}

V_S−

V_S−+ 1

V

V/V

V_S−+ 0.5

1.00

2.00

0.85

1.8

−1.15

1.15

1.2

−0.85

−1.00

Rev. 0 | Page 3 of 24

AD8141/AD8142

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

Operating Range

Quiescent Current

Positive supply

AD8141/AD8142

Disabled

4.5

5.5

56/57

1.6

V

44/47

1.2

−77

mA

dB

PSRR

OUTPUT HIGH-Z PERFORMANCE

DIS Input Low Voltage

DIS Input High Voltage

DIS Assert Time

DIS Deassert Time

Differential Output Impedance Magnitude

With DIS Asserted

0 to 1.6

1.9 to V_S+

5

50

11

V

ns

kΩ

1 MHz, each output, DIS input at V_S+

10 MHz, each output, DIS input at V_S+

1.9

kΩ

ISOLATION

Input-to-Output

1 MHz, each output, DIS input at V_S+

10 MHz, each output, DIS input at V_S+

−78

−58

dB

Rev. 0 | Page 4 of 24

AD8141/AD8142

ABSOLUTE MAXIMUM RATINGS

Table 2.

The power dissipated in the package (P_D) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (V_S) times the

quiescent current (I_S). The load current consists of differential and

common-mode currents flowing to the loads, as well as currents

flowing through the internal differential and common-mode

feedback loops. The internal resistor tap used in the common-

mode feedback loop places a 12.5 kΩ differential load on the

output. RMS output voltages should be considered when

dealing with ac signals.

Parameter

Rating

Supply Voltage

5.5 V

H_SYNC, V_SYNC, SYNC LEVEL

Power Dissipation

V_S−/V_S+

See Figure 3

V_S−/V_S+

−65°C to +125°C

−40°C to +85°C

300°C

Input Common-Mode Voltage

Storage Temperature Range

Operating Temperature Range

Lead Temperature (Soldering 10 sec)

Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Airflow reduces θ_JA. In addition, more metal directly in contact

with the package leads from metal traces, through holes, ground,

and power planes reduce the θ_JA. The exposed pad on the underside

of the package must be soldered to a pad on the PCB surface that is

thermally connected to a PCB plane to achieve the specified θ_JA.

Figure 3 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 24-lead LFCSP

(38°C/W) on a JEDEC standard 4-layer board with the underside

paddle soldered to a pad that is thermally connected to a PCB

plane. θ_JAvalues are approximations.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, θ_JAis

specified for the device soldered in a circuit board in still air.

6

5

4

3

2

1

0

Table 3. Thermal Resistance with the Underside Pad

Thermally Connected to a Copper Plane

Package Type/PCB Type

θ_JA

θ_JC

Unit

24-Lead LFCSP/4-Layer

38

4.7

°C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8141/AD8142

package is limited by the associated rise in junction temperature

(T_J) on the die. At approximately 150°C, which is the glass

transition temperature, the plastic changes its properties. Even

temporarily exceeding this temperature limit can change the

stresses that the package exerts on the die, permanently shifting

the parametric performance of the AD8141/AD8142. Exceeding

a junction temperature of 175°C for an extended period can result

in changes in the silicon devices potentially causing failure.

–40

–20

0

20

40

60

80

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

Rev. 0 | Page 5 of 24

AD8141/AD8142

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

V

C

DIS

/GND

–IN A

1

2

3

4

5

6

18

17

OCM

V

S+

S–

AD8141

TOP VIEW

(Not to Scale)

16 –IN C

15 +IN C

+IN A

/GND

V

/GND

14

13 –OUT C

S–

–OUT A

NOTES

1. CONNECT EXPOSED PADDLE TO GROUND.

Figure 4. AD8141 Pin Configuration

Table 4. AD8141 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DIS

V_S−/GND

−IN A

Disable. This pin places outputs in high-Z condition and lowers supply current.

Negative Power Supply Voltage.

Inverting Input, Amplifier A.

2, 5, 14, 21

3

4

+IN A

Noninverting Input, Amplifier A.

6

7

−OUT A

+OUT A

V_S+

Negative Output, Amplifier A.

Positive Output, Amplifier A.

Positive Power Supply Voltage.

8, 11, 17, 24

9

+OUT B

−OUT B

+OUT C

−OUT C

+IN C

Positive Output, Amplifier B.

Negative Output, Amplifier B.

Positive Output, Amplifier C.

Negative Output, Amplifier C.

Noninverting Input, Amplifier C.

Inverting Input, Amplifier C.

The voltage applied to this pin controls the output common-mode voltage for Amplifier C.

The voltage applied to this pin controls the output common-mode voltage for Amplifier B.

The voltage applied to this pin controls the output common-mode voltage for Amplifier A.

Noninverting Input, Amplifier B.

10

12

13

15

16

18

19

20

22

23

−IN C

V_OCM

C

B

A

+IN B

−IN B

EPAD

Inverting Input, Amplifier B.

Connect Exposed Paddle to Ground.

Rev. 0 | Page 6 of 24

AD8141/AD8142

PIN 1

INDICATOR

SYNC LEVEL

DIS

/GND

–IN R

1

2

3

4

5

6

18

17

V

S+

S–

AD8142

TOP VIEW

(Not to Scale)

16 –IN B

15 +IN B

+IN R

/GND

V

/GND

14

13 –OUT B

S–

–OUT R

NOTES

1. CONNECT EXPOSED PADDLE TO GROUND.

Figure 5. AD8142 Pin Configuration

Table 5. AD8142 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DIS

V_S−/GND

−IN R

Disable. This pin places outputs in high-Z condition and lowers supply current.

Negative Power Supply Voltage. GND is for single 5 V applications.

Inverting Input, Red Amplifier.

2, 5, 14, 21

3

4

+IN R

Noninverting Input, Red Amplifier.

6

7

−OUT R

+OUT R

V_S+

Negative Output, Red Amplifier.

Positive Output, Red Amplifier.

Positive Power Supply Voltage.

8, 11, 17, 24

9

+OUT G

−OUT G

+OUT B

−OUT B

+IN B

Positive Output, Green Amplifier.

Negative Output, Green Amplifier.

Positive Output, Blue Amplifier.

Negative Output, Blue Amplifier.

Noninverting Input, Blue Amplifier.

Inverting Input, Blue Amplifier.

The voltage applied to this pin with respect to V_S−/GND controls the amplitude of the sync pulses

that are applied to the common-mode voltages.

10

12

13

15

16

18

−IN B

SYNC LEVEL

19

20

22

23

H_SYNC

V_SYNC

+IN G

−IN G

EPAD

Horizontal Sync Pulse Input with Respect to Ground.

Vertical Sync Pulse Input with Respect to Ground.

Noninverting Input, Green Amplifier.

Inverting Input, Green Amplifier.

Connect Exposed Paddle to Ground.

Rev. 0 | Page 7 of 24

AD8141/AD8142

TYPICAL PERFORMANCE CHARACTERISTICS

V_S+= 5 V, V_S−= 0 V, R_{L, dm}= 200 Ω, T_A= 25°C, V_OCM= 1.5 V (AD8141), H_SYNC, V_SYNC, and SYNC LEVEL = 0 V (AD8142), unless otherwise noted.

9

V

= 200mV p-p

V

= 2V p-p

OUT, dm

6

3

0

–3

–6

–3

–6

AD8141

AD8142

AD8141

AD8142

1

10

100

1k

1

10

100

1k

FREQUENCY (MHz)

Figure 6. Small Signal Frequency Response

Figure 9. Large Signal Frequency Response

9

V

= 200mV p-p

V

= 2V p-p

OUT, dm

6

3

0

6

3

0

–3

–6

–3

–6

–9

–12

1

10

100

1k

1

10

100

1k

FREQUENCY (MHz)

Figure 7. Small Signal Frequency Response at V_OCM= 2.5 V (AD8141)

Figure 10. Large Signal Frequency Response at V_OCM= 2.5 V (AD8141)

6.7

V

= 200mV p-p

V

= 2V p-p

OUT, dm

6.6

6.5

6.4

6.3

6.2

6.1

6.0

5.9

5.8

6.5

6.4

6.3

6.2

6.1

6.0

5.9

5.8

AD8141

AD8142

AD8141

AD8142

10

5.7

1

10

100

1k

1

100

1k

FREQUENCY (MHz)

Figure 8. Small Signal 0.1 dB Flatness

Figure 11. Large Signal 0.1 dB Flatness

Rev. 0 | Page 8 of 24

AD8141/AD8142

100k

10k

1k

0

∆V

/∆V

OUT, cm

OUT, dm

= 2V p-p

–10

–20

–30

–40

–50

–60

–70

–80

100

10

100

1k

10k

100k

1M

10M

100M

100

1k

1

10

100

1k

100

1k

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 15. Output Voltage Noise Density vs. Frequency

Figure 12. Output Balance Error vs. Frequency

–30

–40

–30

–40

–50

–60

–70

–80

V

= 2V p-p

V

= 2V p-p

OUT, dm

–50

HD2

–60

HD3

–70

HD3

–80

–90

–100

–110

–120

0.1

1

10

FREQUENCY (MHz)

0.1

1

10

FREQUENCY (MHz)

Figure 16. AD8142 Harmonic Distortion vs. Frequency

Figure 13. AD8141 Harmonic Distortion vs. Frequency

–30

–40

–50

–60

–70

–20

–40

–60

–80

DIS INPUT VOLTAGE = 5V

GREEN TO RED,

∆V

R/∆V

G

OUT, dm

IN, dm

RED

–100

–120

–140

–80

–90

1

10

100

1

10

100

FREQUENCY (MHz)

Figure 17. Disabled Input-to-Output Isolation vs. Frequency

Figure 14. Channel-to-Channel Isolation vs. Frequency

Rev. 0 | Page 9 of 24

AD8141/AD8142

–30

–40

–50

–60

–70

–20

∆V

/∆V

OUT, dm

IN, cm

= 1V p-p

±2.5V SUPPLIES

∆SUPPLY = ±0.5V

IN, cm

–30

–40

–50

–60

–70

–80

–90

AD8141 V

AD8142 V

+

AD8141 V –

S

AD8142 V –

S

1

10

100

1k

1

10

100

1k

FREQUENCY (MHz)

Figure 18. Common-Mode Rejection vs. Frequency

Figure 21. Power Supply Rejection vs. Frequency

100k

2.0

1.5

30

V

= +2.5V

= –2.5V

= 0.7V

DIRECTLY AT DRIVER OUTPUT

S+

S–

DIFFERENTIAL OUTPUT

25

20

15

10

5

IN

DC

= GND

OCM

10k

1k

1.0

0.5

0

–0.5

–1.0

–1.5

100

10

DIS PIN

0

–5

0

40

80

120 160 200 240 280 320 360 400

1

10

100

1k

FREQUENCY (MHz)

TIME (ns)

Figure 19. Disabled Output Impedance Magnitude vs. Frequency

Figure 22. Disable Response Time

0.15

1.5

1.0

0.5

0

AD8141

AD8142

AD8141

AD8142

0.10

0.05

0

–0.05

–0.10

–0.15

–0.5

–1.0

–1.5

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

TIME (ns)

Figure 20. Small Signal Transient Response

Figure 23. Large Signal Transient Response

Rev. 0 | Page 10 of 24

AD8141/AD8142

0.15

0.10

0.05

0

1.5

1.0

0.5

0

–0.05

–0.10

–0.15

–0.5

–1.0

–1.5

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

TIME (ns)

Figure 24. Small Signal Transient Response, V_OCM= 2.5 V (AD8141)

Figure 27. Large Signal Transient Response, V_OCM= 2.5 V (AD8141)

7

1.25

10

8

V

= +2.5V

= –2.5V

S+

6

5

4

3

2

OUTPUT

1.00

0.75

S–

= 0V

OCM

6

SINGLE-ENDED DRIVE

INPUT

0.50

4

0.25

2

1

0

ERROR

0

–1

–2

–3

–0.25

–0.50

–0.75

–1.00

–1.25

–2

–4

–6

–8

–10

0.1% SETTLED POINT

2× INPUT

_DIFF

–4

–5

–6

–7

V

OUT

0.5% SETTLED POINT

–4

0

4

8

12

16

20

24

28

32

36

0

100 200 300 400 500 600 700 800 900 1000

TIME (ns)

Figure 28. AD8141 Differential Overdrive Recovery

Figure 25. Differential Settling Time

–35

–37

58

R

= OPEN CIRCUIT

L, dm

R

= OPEN CIRCUIT

L, dm

56

54

52

50

48

46

44

42

40

38

–39

–41

–43

AD8142

AD8141

–45

–47

AD8141

AD8142

–49

–51

–53

–40

–20

0

20

40

60

80

100

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 29. Negative Power Supply Current vs. Temperature

Figure 26. Positive Power Supply Current vs. Temperature

Rev. 0 | Page 11 of 24

AD8141/AD8142

4.0

4.85

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

V

= 5V

= 0V

SINGLE-ENDED OUTPUT VOLTAGE

S+

S–

V

= 2.5V

= 1.5V

OCM

3.5

3.0

2.5

4.80

POSITIVE SWING

4.75

4.70

4.65

4.60

4.55

4.50

OCM

2.0

1.5

1.0

0.5

0

NEGATIVE SWING

0

10

20

30

40

50

60

70

80

90

100

–40

–20

0

20

40

60

80

100

TIME (ns)

TEMPERATURE (°C)

Figure 32. V_OCMLarge Signal Transient Response (AD8141)

Figure 30. Output Saturation vs. Temperature

–40

3

∆V

/∆V

OUT, dm

OCM

= 2V p-p

∆V

/∆V

OUT, cm OCM

OCM

V

= 100mV p-p

OUT, cm

–45

–50

–55

0

–3

–60

–65

–6

–9

–70

–75

–12

1

10

100

1k

1

10

100

1k

FREQUENCY (MHz)

Figure 33. V_OCMCommon-Mode Rejection vs. Frequency

Figure 31. V_OCMFrequency Response (AD8141)

Rev. 0 | Page 12 of 24

AD8141/AD8142

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

17.5

SYNC LEVEL = 0.5V

G

CM

12.5

R

B

CM

7.5

H

V

SYNC

2.5

–2.5

0

10

20

30

40

50

60

70

80

90

100

TIME (ns)

Figure 34. AD8142 Output Common-Mode Signals for Various Sync Pulse Inputs

BASIC TEST CIRCUIT

+5V

V

S+

0.1µF ON ALL V PINS

S+

AD8141/AD8142

50Ω

1kΩ

2kΩ

52.3Ω

–

V

R

200Ω

TEST

OUT, dm

L, dm

+

TEST

SIGNAL

SOURCE

1kΩ

2kΩ

MIDSUPPLY

V

S–

Figure 35. Basic Test Circuit

Rev. 0 | Page 13 of 24

AD8141/AD8142

TERMINOLOGY

Differential Voltage

Output Balance

Output balance is a measure of how well the differential output

signals are matched in amplitude and how close they are to exactly

180° apart in phase. Balance can be easily determined by placing a

well-matched resistor divider between the differential output

voltage nodes and comparing the magnitude of the signal at the

divider’s midpoint with the magnitude of the differential signal.

By this definition, output balance error is the magnitude of the

change in output common-mode voltage divided by the magnitude

of the change in output differential-mode voltage in response to

a differential input signal.

Differential voltage refers to the difference between two node

voltages that are balanced with respect to each other. For example,

in Figure 36, the output differential voltage (or output differential

mode voltage) is defined as

V

_{OUT, dm}= (V_OP− V_ON)

Common-mode voltage refers to the average of two node voltages

with respect to a common reference (usually the local ground).

The output common-mode voltage is defined as

(V_OP+V_ON

)

V_OUT,cm

=

2

ΔV_OUT,cm

Output Balance Error =

ΔV_OUT,dm

Rev. 0 | Page 14 of 24

AD8141/AD8142

THEORY OF OPERATION

The differential drivers contained in the AD8141 and AD8142

differ from conventional op amps in that they have two outputs

whose voltages move in opposite directions. Like op amps, they

rely on high open-loop gain and negative feedback to force these

outputs to the desired voltages. The AD8141 and AD8142

drivers make it easy to perform single-ended-to-differential

conversion, common-mode level-shifting, and amplification

of differential signals.

ANALYZING AN APPLICATION CIRCUIT

The drivers use two negative feedback loops, each with high

open-loop gain, to force their differential and common-mode

output voltages in such a way as to minimize the differential

and common-mode input error voltages. The differential input

error voltage is defined as the voltage between the differential

inputs labeled V_APand V_ANin Figure 36. For most purposes, this

voltage can be assumed to be zero. Similarly, the difference between

the actual output common-mode voltage and the voltage applied to

V_OCMcan also be assumed to be zero. Starting from these two

assumptions, any application circuit can be analyzed.

Previous differential drivers, both discrete and integrated designs,

have been based on using two independent amplifiers and two

independent feedback loops, one to control each of the outputs.

When these circuits are driven from a single-ended source, the

resulting outputs are typically not well balanced. Achieving a

balanced output has generally required exceptional matching

of the amplifiers and feedback networks.

CLOSED-LOOP GAIN

The differential mode gain of the circuit in Figure 36 can be

described by

V_OUT,dm

V_IN,dm

R_F

R_G

DC common-mode level-shifting has also been difficult with

previous differential drivers. Level-shifting has required the

use of a third amplifier and feedback loop to control the output

common-mode level. Sometimes, the third amplifier has also

been used to attempt to correct an inherently unbalanced circuit.

Excellent performance over a wide frequency range has proven

difficult with this approach.

=

= 2

where R_F= 2.0 kΩ and R_G= 1.0 kΩ nominally.

R

F

R

G

V

AP

+

V

IP

OCM

ON

V

R

IN, dm

OUT, dm

OP

L, dm

–

V

IN

V

AN

R

G

Each AD8141/AD8142 driver uses two feedback loops to

separately control the differential and common-mode output

voltages. The differential feedback, set by the internal resistors,

controls the differential output voltage only. The internal common-

mode feedback loop controls the common-mode output voltage

only. This architecture makes it easy to arbitrarily set the output

common-mode level by simply applying a voltage to the V_OCM

input. The output common-mode voltage is forced, by internal

common-mode feedback, to equal the voltage applied to the V_OCM

input, while simultaneously balancing the differential output voltage.

The AD8141 V_OCMinputs are available to the user, whereas the

AD8142 V_OCMinputs are internally connected to sync-on-common-

mode circuitry that automatically imbeds the H_SYNCand V_SYNC

signals on the three output common-mode voltages.

R

F

Figure 36. Circuit Definitions

CALCULATING AN APPLICATION CIRCUIT’S INPUT

IMPEDANCE

The effective input impedance of a circuit such as that in Figure 36

at V_IPand V_INdepends on whether the amplifier is being driven

by a single-ended or differential signal source. For balanced

differential input signals, the differential input impedance, R_{IN, dm}

between the inputs V_IPand V_INis simply

R

_{IN, dm}= 2 × R_G= 2.0 kΩ

In the case of a single-ended input signal (for example, if V_IN

is grounded and the input signal is applied to V_IP), the input

impedance becomes

The overall driver architecture produces outputs that are highly

balanced over a wide frequency range without requiring external

components or adjustments. The common-mode feedback loop

forces the signal component of the output common-mode voltage

to be zeroed. The result is nearly perfectly balanced differential

outputs of identical amplitude that are 180° apart in phase.

⎛

⎜

⎞

⎟

R_G

R_F

R_G+ R_F

⎜

⎟

R_IN

=

=1.5 kꢀ

1−

⎜

⎟

2×

(

)

⎝

⎠

The input impedance of the circuit is higher than for a

conventional op amp connected as an inverter because a

fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor R_G.

Rev. 0 | Page 15 of 24

AD8141/AD8142

R

2kΩ

F

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

R

IN

75Ω

+V

S

R

G

S

The driver inputs are designed to facilitate level-shifting of ground

referenced input signals on a single power supply. For a single-

ended input, this implies, for example, that the voltage at V_INin

Figure 36 is 0 V when the amplifier’s negative power supply

voltage is also set to 0 V.

75Ω

1kΩ

+

R

80.6Ω

T

V

S

AD8141/

AD8142

–

V

R

1.4V p-p

OUT, dm

L

R

G

1kΩ

–V

S

R

2kΩ

F

It is important to ensure that the common-mode voltage at the

amplifier inputs, V_APand V_AN, stays within its specified range.

Because the V_APand V_ANvoltages are driven to be essentially

equal by negative feedback, the amplifier’s input common-mode

voltage can be expressed as a single term, V_ACM. V_ACMcan be

calculated as

Figure 38. Adding Termination Resistor R_T

3. It can be seen from Figure 38 that the effective R_Gin the

upper feedback loop is now greater than the R_Gin the

lower loop due to the addition of the termination resistors.

To compensate for the imbalance of the gain resistors, a

correction resistor (R_TS) is added in series with R_Gin the

lower loop. R_TSis the closest 1% resistor to the Thevenin

equivalent of the source resistance R_Sand the termination

resistance R_T, equal to R_S||R_T.

V_OCM+ 2V_ICM

V_ACM

=

3

where V_ICMis the common-mode voltage of the input signal,

that is,

V_IP+ V_IN

R

75Ω

TH

38.8Ω

S

V_ICM

=

2

R

80.6Ω

T

V

S

TH

0.725V p-p

TERMINATING A SINGLE-ENDED INPUT

1.4V p-p

Each driver has a nominal fixed gain of 2, with R_F= 2.0 kΩ and

R_G= 1.0 kΩ. A typical single-ended video signal source applied to

the AD8141/AD8142 input has a maximum terminated output

voltage of 0.7 V p-p and source resistance of 75 Ω. Because the

terminated output voltage of the source is 0.7 V p-p, the open-

circuit output voltage of the source is 1.4 V p-p. The source shown

in Figure 37 indicates this open-circuit voltage. The following

three steps illustrate how to terminate a signal from a typical

single-ended 75 Ω video source.

Figure 39. Calculating the Thevenin Equivalent

R_TH= R_S||R_T= 38.8 Ω, and R_TS= 38.3 Ω. Note that V_THis

greater than 0.7 V p-p, which was obtained with R_T= 75 Ω

alone. The modified circuit with the Thevenin equivalent of

the terminated source and R_TSin the lower feedback loop is

shown in Figure 40.

R

F

2kΩ

1. The single-ended input impedance is calculated as

R_IN= 1.5 kΩ.

+V

S

R

38.8Ω

R

G

1kΩ

TH

+

V

TH

0.725V p-p

R

F

AD8141/

AD8142

V

R

OUT, dm

L

2kΩ

R

G

VIDEO SOURCE

1kΩ

R

IN

1.5kΩ

+5V

–

R

S

G

R

TS

1kΩ

75Ω

38.3Ω

+

–V

S

V

S

R

F

AD8141/

AD8142

–

V

1.4V p-p

R

L

OUT, dm

2kΩ

R

1kΩ

G

Figure 40. Thevenin Equivalent and Matched Gain Resistors

R

2kΩ

Figure 40 presents a tractable circuit with matched feedback

loops that can be easily evaluated.

F

Figure 37. Calculating Single-Ended Input Impedance, R_IN

It is useful to point out two effects that occur with a terminated

input. The first is that the value of R_Gis increased in both loops,

lowering the overall closed-loop gain. The second is that V_THis

a little larger than 0.7 V p-p, as it is if R_T= 75 Ω alone. These

two effects have opposite impacts on the output voltage, and for

large resistor values in the feedback loops, the effects essentially

cancel each other out. For smaller R_Fand R_G, however, the

diminished closed-loop gain is not canceled completely by the

increased V_TH.

2. To match the 75 Ω source resistance, the termination resistor,

R_T, is calculated using R_T||1.125 kΩ = 75 Ω. The closest

standard 1% value for R_Tis 80.6 Ω.

Rev. 0 | Page 16 of 24

AD8141/AD8142

The desired differential output in this example is 1.4 V p-p

because the terminated input signal is 0.7 V p-p and the closed-

loop gain = 2. The actual differential output voltage is equal to

(0.725 V p-p)(2 kΩ/1038.3 Ω) = 1.4 V p-p. This illustrates how

the two aforementioned effects cancel for large R_Fand R_G.

AD8142 SYNC-ON-COMMON-MODE

The AD8142 includes on-chip, sync-on-common-mode circuitry

that encodes externally applied H_SYNCand V_SYNCsignals onto the

common-mode output voltages of each of the R, G, and B drivers.

The circuit encodes the horizontal and vertical sync pulses in a

way that results in low radiated energy. A simplified circuit that

illustrates how the pulses are encoded is shown in Figure 41.

For a more detailed description of the sync scheme, see the

Applications Information section.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance of

the drivers to reduce phase margin, resulting in high frequency

ringing in the pulse response. The best way to minimize this effect

is to place the source termination resistors immediately at the

amplifier outputs to minimize parasitic capacitances formed by

unnecessarily long traces.

The sync-on-common-mode circuit generates a current based

on the voltage applied to the SYNC LEVEL input pin (Pin 18)

with respect to the negative supply. With SYNC LEVEL input

tied to V_S−, the common-mode output of all drivers is set at 1.5 V

above the negative supply. Using a resistor divider, a voltage can

be applied between V_S−and SYNC LEVEL that determines the

maximum deviation of the common-mode outputs from their

midsupply level. If, for instance, SYNC LEVEL − V_S−= 0.5 V

and the supply voltage is 5 V, then the common-mode outputs

fall within an envelope of 1.5 V 0.5 V. The state of each V_{OUT, cm}

output based on the H_SYNCand V_SYNCinputs is determined by

the equations defined in the Applications Information section.

DISABLE

The AD8141 and AD8142 have disable pins that, when pulled high,

significantly reduce the power consumed while simultaneously

placing the outputs in high-Z states. The disable feature can be

used to multiplex two drivers. See Figure 17, Figure 19, and

Figure 22 for the disabled input-to-output isolation, output

impedance, and response performance. The threshold levels

for the disable pin are listed in Table 1.

An output glitch occurs whenever the disable feature is asserted or

deasserted. See the Applications Information section for details.

For the positive supplies between 2.5 V and 5 V, the sync-on-

common-mode circuit can be used by directly applying standard

H

_SYNCand V_SYNCsignals to the respective AD8142 inputs. These

inputs adhere to standard logic thresholds (see Table 1 for the

exact levels). The H_SYNCand V_SYNCinputs, therefore, can be

driven directly off the output of a computer video card without

concern of being overdriven. The input path from the H_SYNCand

V

_SYNCinputs to the switches in the current mode level-shifting

circuit are well matched to eliminate false switching transients. This

maximizes common-mode balance and minimizes radiated energy.

V

S+

MIRROR

H

V

R

V

H

RED V

OCM

V

H

V

H

SYNC

GREEN V

OCM

BLUE V

OCM

SYNC

SYNC LEVEL

H

V

R

MIRROR

R

V

S–

Figure 41. Sync-On-Common-Mode Simplified Circuit

Rev. 0 | Page 17 of 24

AD8141/AD8142

APPLICATIONS INFORMATION

DRIVING RGB VIDEO OVER CAT-5 CABLE

automatically compensates for the losses incurred by the source

and load terminations. Figure 42 shows the AD8141/AD8142 in

a triple, single-ended-to-differential application when driven from

a 75 Ω video source.

The AD8141 and AD8142 are devices whose foremost application

is driving RGB and component video signals over unshielded

twisted pair (UTP) cable in video distribution networks. Single-

ended video signals are easily converted to differential signals

for transmission over the cable, and the internally fixed gain of 2

+5V

V

S–

AD8141/AD8142

2kΩ

0.1µF ON ALL V

PINS

S+

1kΩ

49.9Ω

75Ω

+

R

80.6Ω

RED UTP

RED

VIDEO

1kΩ

–

SOURCE

38.3Ω

2kΩ

1kΩ

49.9Ω

75Ω

+

G

80.6Ω

GREEN UTP

GREEN

VIDEO

SOURCE

1kΩ

–

2kΩ

1kΩ

49.9Ω

75Ω

+

B

80.6Ω

BLUE UTP

BLUE

VIDEO

SOURCE

1kΩ

–

2kΩ

DISABLE

DIS

V

S–

Figure 42. AD8141/AD8142 in Single-Ended-to-Differential Application on Single 5 V Supply (Sync Pulse Encoding Not Shown)

Rev. 0 | Page 18 of 24

AD8141/AD8142

In Figure 43, V_{R, CM}= V_{O, CM}+ V_SHIFT. If V_{O, CM}= 0 V and V_SHIFT

2 V, V_{R, CM}is 2 V. This is because the receiver ground is shifted

down by 2 V relative to the driver ground, and the common-

mode level on the cable stays constant. It can be seen from this

example that the most margin to absorb ground shifts exists

when the center of the receiver input common-mode voltage

range relative to its ground is the same as the output common-

mode voltage of the driver with respect to its ground.

=

SINGLE 5 V SUPPLY APPLICATION INFORMATION

The AD8141 and AD8142 require a nominal voltage of 5 V

across their V_S+and V_S−power supply pins, and that their EPADs

be connected to system ground; the voltage between V_S+and the

local system ground must be greater than or equal to 2.5 V and

less than or equal to 5 V. These requirements can be met by a

single +5 V supply, or split supplies such as 2.5 V, +3 V/−2 V,

and so on. Operating the AD8141 and AD8142 with 2.5 V

supplies provides considerable power savings compared with

other drivers operating at 5 V supplies, without any disadvantages

with regard to input and output ranges in most cases.

Most receivers operate with their input common-mode ranges

centered at 0 V; therefore, the best case for the driver is to set its

output common-mode voltage to 0 V. This is not possible for the

AD8141 or AD8142on a single 5 V supply, but can be accomplished

using split supplies. If a single 5 V supply is required, the rail-

to-rail output allows the AD8141 output common-mode voltage

to be set to less than 1 V to be as close as possible to the ideal

setting of 0 V. Whereas the AD8141 has uncommitted V_OCMinputs,

the AD8142 has internal sync-encoding circuitry that fixes the

nominal output common-mode voltage at 1.5 V above the negative

rail. Each part has a resistive divider on the V_OCMinput that sets

the nominal output common-mode voltage to 1.5 V above the

negative rail when no external voltage is applied. The divider

consists of a 8.75 kΩ resistor to V_S+and a 3.75 kΩ resistor to V_S−,

forming a Thevenin equivalent load of 2.6 kΩ to 30% of the

voltage across the supplies. In the single 5 V supply case, the

Thevenin load voltage is 30% of 5 V above 0 V, or 1.5 V.

The receivers used with the AD8141 and AD8142, such as the

AD8145, AD8143, AD8123, and AD8128, generally operate

with split supplies, ranging from 5 V to 12 V. The split supply

arrangement results in a receiver input common-mode range

that is centered at 0 V relative to the local ground reference and

ranges to within a volt or two from each rail. Ground potential

differences normally exist between the driver end and the receiver

end, and these differences cause the relative common-mode

voltages between the driver and receiver to shift. See Figure 43

for an example.

DRIVER

AD8141/AD8142

49.9Ω

–

+

100Ω

UTP

V

100Ω

OCM

49.9Ω

–

+

O, CM

+

R, CM

V

–

+

V

SHIFT

Figure 43. End-to-End Common-Mode Shifts due to Ground Shifts

Rev. 0 | Page 19 of 24

AD8141/AD8142

AD8142 SIGNAL LEVELS ON VARIOUS SUPPLIES

Figure 44 and Figure 45 illustrate the key video signal levels

seen in typical applications operating on a single +5 V supply

and 2.5 V supplies; common-mode sync pulses are omitted

from the circuit drawing for clarity but are shown in a separate

waveform drawing of the signals directly at the AD8142 outputs,

shown just below the associated circuit drawing. The sync pulses

are common-mode, that is, they move in the same direction on

each output polarity. In Figure 44 and Figure 45, this means that the

H_SYNCpulses are either both green or both blue for the red and

black video signals.

The disable pin is a binary input that controls the state of the

AD8141/AD8142 outputs. Its binary input levels are compatible

with most TTL and CMOS families (see Table 1 for the logic levels).

The AD8141/AD8142output is disabled when the disable input

is driven to its high state, and the AD8141/AD8142operates in

its normal fashion when the disable input is driven to its low state.

An unavoidable common-mode glitch occurs at the outputs

when switching between disabled and enabled states and vice

versa. The glitch lasts for a few tens of nanoseconds and is

on the order of 2 V or 3 V. If the disable feature is used, it is

recommended that common-mode protection be used on the

receiver (see the AD8143 data sheet for a detailed description of

common-mode protection)

DISABLE FEATURE

When asserted, the disable feature minimizes quiescent current

consumption and provides a high-Z output. It offers a convenient

means to connect two driver outputs together in parallel to form a

tristate multiplexed application. The disable feature can also be

used to minimize quiescent current drawn when a particular

device is not being used.

AD8142 KEY SIGNAL LEVELS ON SINGLE +5V SUPPLY

+5V

0.7V

0V

1.5V

0.8V

AD8142

2kΩ

1kΩ

49.9Ω

75Ω

+

100Ω

UTP

100Ω

0.7V

1.5V

80.6Ω

VIDEO

SOURCE

–

38.3Ω

2kΩ

2.2V

1.5V

0.76V

0.52V

AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE H

SYNC

PULSES

0.5V

2.2V

1.5V

0.8V

1.4V

Figure 44. AD8142 Key Signal Levels on Single 5 V Supply; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with H_SYNCPulses

Rev. 0 | Page 20 of 24

AD8141/AD8142

AD8142 KEY SIGNAL LEVELS ON SINGLE ±2.5V SUPPLIES

+2.5V

0.7V

0V

–1.0V

AD8142

2kΩ

–1.7V

1kΩ

49.9Ω

75Ω

+

–

100Ω

UTP

100Ω

0.7V

–1.0V

80.6Ω

VIDEO

SOURCE

38.3Ω

2kΩ

–0.3V

–1.0V

–2.5V

–0.10V

–0.34V

AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE H

SYNC

PULSES

0.5V

–0.3V

–1.0V

–1.7V

1.4V

Figure 45. AD8142 Key Signal Levels on 2.5 V Supplies; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with H_SYNCPulses

horizontal sync signals as weighted sums and differences of the

DRIVING MULTIPLE OUTPUTS

output common-mode signals. The RGB color signals are each

The AD8141/AD8142 can drive four parallel UTP cables (50 Ω

transmitted differentially over separate physical channels. The

differential load) with only 1.5% reduction in output swing (see

fact that the differential and common-mode signals are orthogonal

Figure 46). As is expected, driving fewer parallel cables results in

allows the RGB color and sync signals to be separated at the

less output swing reduction.

channel’s receiver.

49.9Ω

100Ω

49.9Ω UTP

Cat-5 type cable contains four balanced twisted-pair physical

100Ω

AD8141/AD8142

channels that can support both differential and common-mode

signals. Transmitting typical computer monitor video over this

cable can be accomplished by using three of the twisted pairs for

49.9Ω

100Ω

+

V

100Ω

49.9Ω UTP

OCM

the RGB and sync signals. Each color is transmitted differentially,

one on each of the three pairs. The encoded sync signals are

transmitted among the common-mode signals of each of the

three pairs. To minimize EMI from the sync signals, the common-

mode signals on each of the three pairs produced by the sync

encoding scheme induce electric and magnetic fields that, for

the most part, cancel each other. A conceptual block diagram

of the sync encoding scheme is presented in Figure 47. Because

the AD8142 has the sync encoding scheme implemented internally,

the user simply applies the horizontal and vertical sync signals

directly to the appropriate inputs. As described in the Theory of

Operation section, the AD8142 accepts ground-referenced logic-

level sync pulses (see Table 1 for the exact levels). In many cases,

the sync pulses can be applied directly from video card VGA

connector outputs.

–

49.9Ω

100Ω

49.9Ω UTP

49.9Ω

100Ω

49.9Ω UTP

Figure 46. Driving Four UTP Cables in Parallel

VIDEO SYNC-ON-COMMON-MODE (AD8142)

In computer video applications, the horizontal and vertical sync

signals are most often separate from the video information signals.

For example, in typical computer monitor applications, the red,

green, and blue (RGB) color signals are transmitted over separate

cables, as are the vertical and horizontal sync signals. When

transmitting these types of video signals over long distances

on UTP cable, it is desirable to reduce the required number of

physical channels. One way to do this is to encode the vertical and

Rev. 0 | Page 21 of 24

AD8141/AD8142

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

17.5

12.5

SYNC LEVEL = 0.5V

2kΩ

G

CM

AD8142

1kΩ

+IN R

–OUT R

+OUT R

+

V

R

OCM

R

B

CM

–

–IN R

V

2kΩ

SYNC

7.5

H

SYNC

H

V

SYNC

2kΩ

2.5

SYNC LEVEL

+IN G

1kΩ

–OUT G

+OUT G

+

V

G

OCM

×2

–2.5

–

–IN G

0

40

80

120 160 200 240 280 320 360 400

2kΩ

TIME (ns)

Figure 48. AD8142 Sync-On-Common-Mode Signals in Single 5 V Application

1kΩ

LAYOUT AND POWER SUPPLY DECOUPLING

CONSIDERATIONS

–OUT B

+OUT B

+IN B

–IN B

+

V

B

OCM

–

When designing with the AD8141 and AD8142, adhere to

standard high speed printed circuit board (PCB) layout practices.

A solid ground plane is recommended and good wideband power

supply decoupling networks should be placed as close as possible

to the supply pins. Small surface-mount ceramic capacitors are

recommended for these networks, and tantalum capacitors are

recommended for bulk supply decoupling.

2kΩ

DIS

V

WEIGHTING EQUATIONS ON +5V SUPPLY:

OCM

K

2

RED V

=

(V

– H

) + 1.5V

OCM

SYNC

K

2

GREEN V

=

(–2V

) + 1.5V

OCM

SYNC

K

2

BLUE V

=

(V

+ H

) + 1.5V

OCM

SYNC

AMPLIFIER-TO-AMPLIFIER ISOLATION

Figure 47. AD8142 Conceptual Sync-On-Common-Mode Encoding Scheme

The least amount of isolation between the three AD8142 amplifiers

exists between the green and red channels (Amplifier A and

Amplifier B for the AD8141). This is, therefore, viewed as the

worst-case isolation, which is reflected in Table 1 and the

Theory of Operation section.

The transmitted common-mode sync signal magnitudes are

scaled by applying a dc voltage to the SYNC LEVEL input,

referenced to the negative supply. The difference between the

voltage applied to the SYNC LEVEL input and the negative supply

sets the peak deviation of the encoded sync signals about the

midsupply common-mode voltage. For example, with the SYNC

LEVEL input set at V_S−+ 500 mV, the deviation of the encoded

sync pulses about the nominal midsupply common-mode voltage

is nominally 500 mV. The equations in Figure 47 describe how

the V_SYNCand H_SYNCsignals are encoded on each color’s midsupply

common-mode signal. In these equations, the weights of the V_SYNC

and H_SYNCsignals are 1 (that is, +1 for high, −1 for low), and the

constant, K, is equal to the peak deviation of the encoded sync

signals.

EXPOSED PADDLE (EPAD)

The 24-lead LFCSP package has an exposed paddle on the

underside of its body. To achieve the specified thermal resistance, it

must have a good thermal connection to one of the PCB planes.

The exposed paddle must be soldered to a pad on top of the board

that is connected with several thermal vias to a ground plane.

Figure 48 shows how the sync signals appear on each common-

mode voltage in a single 5 V supply application when the voltage

applied to the SYNC LEVEL input is set to V_S−+ 500 mV.

Although the typical setting for the SYNC LEVEL voltage is

500 mV above the negative supply, it can be increased, if

necessary, in extremely noisy environments. Increasing the

SYNC LEVEL voltage too much has the potential to produce

excessive EMI.

Rev. 0 | Page 22 of 24

AD8141/AD8142

TYPICAL AD8142 5 V APPLICATION CIRCUIT

Figure 49 illustrates a typical AD8142 application circuit on a single 5 V supply.

BLUE VIDEO IN

+5V

80.6Ω

17.8kΩ

38.3Ω

0.01µF

2kΩ

49.9Ω

–

+

+5V

0.01µF

DIFFERENTIAL BLUE VIDEO OUT

18 17 16 15 14 13

AD8142

49.9Ω

H

V

19

20

21

22

23

24

12

11

10

9

SYNC

B

SYNC

49.9Ω

×2

80.6Ω

38.3Ω

–

+

G

DIFFERENTIAL GREEN VIDEO OUT

DIFFERENTIAL RED VIDEO OUT

GREEN VIDEO IN

8

49.9Ω

R

7

+

+5V

0.01µF

1

2

3

4

5

6

49.9Ω

–

RED VIDEO IN

DISABLE

80.6Ω

38.3Ω

Figure 49. Typical AD8142 Application Circuit on a Single 5 V Supply

Rev. 0 | Page 23 of 24

AD8141/AD8142

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

19

24

0.50

BSC

18

1

2.65

2.50 SQ

2.45

EXPOSED

PAD

13

12

BOTTOM VIEW

6

7

0.50

0.40

0.30

0.25 MIN

TOP VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 50. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-24-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Package

−40°C to +85°C

Package Description

24-Lead LFCSP_WQ

Evaluation Board

Package Option

CP-24-7

AD8141ACPZ-R2

AD8141ACPZ-RL

AD8141ACPZ-R7

AD8142ACPZ-R2

AD8142ACPZ-RL

AD8142ACPZ-R7

AD8142-EVALZ

CP-24-7

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09461-0-7/11(0)

Rev. 0 | Page 24 of 24


型号：	AD8141ACPZ-R2
厂家：	ADI
描述：	Low Cost, Triple Differential Drivers 低成本，三差分驱动器线路驱动器或接收器驱动程序和接口接口集成电路
文件：	总24页 (文件大小：451K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8141ACPZ-R2 [ADI]

相关型号：

AD8141ACPZ-R7

AD8141ACPZ-RL

AD8142

AD8142-EVALZ

AD8142ACPZ-R2

AD8142ACPZ-R7

AD8142ACPZ-RL

AD8143

AD8143-EVALZ

AD8143ACPZ-R2

AD8143ACPZ-REEL

AD8143ACPZ-REEL7