AD815ARB-24-REEL [ADI]
High Output Current Differential Driver; 高输出电流差分驱动器
| 型号： | AD815ARB-24-REEL |
| 厂家： | 
ADI |
| 描述： | High Output Current Differential Driver |
| 文件： | 总16页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Output Current
Differential Driver
a
AD815
FUNCTIONAL BLOCK DIAGRAM
FEATURES
15-Lead Through-Hole SIP (Y) and Surface-Mount
DDPAK(VR)
Flexible Configuration
Differential Input and Output Driver
or Two Single-Ended Drivers
High Output Power
15
14
13
12
11
10
9
NC
NC
Power Package
NC
26 dBm Differential Line Drive for ADSL Application
40 V p-p Differential Output Voltage, RL = 50 ⍀
500 mA Minimum Output Drive/Amp, RL = 5 ⍀
Thermally Enhanced SOIC
400 mA Minimum Output Drive/Amp, RL = 10 ⍀
Low Distortion
–66 dB @ 1 MHz THD, RL = 200 ⍀, VOUT = 40 V p-p
0.05% and 0.45؇ Differential Gain and Phase, RL = 25 ⍀
(6 Back-Terminated Video Loads)
High Speed
TAB IS
NC
+V
S
+IN2
–IN2
OUT2
+V
S
8
AD815
7
–V
S
6
OUT1
–IN1
+IN1
NC
5
4
3
2
1
NC
NC
120 MHz Bandwidth (–3 dB)
900 V/s Differential Slew Rate
70 ns Settling Time to 0.1%
NC = NO CONNECT
REFER TO PAGE 3 FOR 24-LEAD SOIC PACKAGE
Thermal Shutdown
coupling transformer with a greater than 1:1 turns ratio. The
low harmonic distortion of –66 dB @ 1 MHz into 200 Ω
combined with the wide bandwidth and high current drive make
the differential driver ideal for communication applications such
as subscriber line interfaces for ADSL, HDSL and VDSL.
APPLICATIONS
ADSL, HDSL and VDSL Line Interface Driver
Coil or Transformer Driver
CRT Convergence and Astigmatism Adjustment
Video Distribution Amp
Twisted Pair Cable Driver
The AD815 differential slew rate of 900 V/µs and high load drive
are suitable for fast dynamic control of coils or transformers,
and the video performance of 0.05% and 0.45° differential gain
and phase into a load of 25 Ω enable up to 12 back-terminated
loads to be driven.
PRODUCT DESCRIPTION
The AD815 consists of two high speed amplifiers capable of
supplying a minimum of 500 mA. They are typically configured
as a differential driver enabling an output signal of 40 V p-p on
±15 V supplies. This can be increased further with the use of a
Three package styles are available, and all work over the
industrial temperature range (–40°C to +85°C). Maximum
output power is achieved with the power package available for
through-hole mounting (Y) and surface-mounting (VR). The
24-lead SOIC (RB) is capable of driving 26 dBm for full rate
ADSL with proper heat sinking.
–40
V
= ؎15V
S
G = +10
–50
–60
V
= 40V p-p
OUT
+15V
1/2
AD815
100⍀
R
= 15⍀
1
–70
AMP1
R
= 50⍀
L
–80
499⍀
(DIFFERENTIAL)
R
120⍀
R
= 200⍀
V
=
V =
D
40Vp-p
L
L
IN
V
=
OUT
G = +10
–90
110⍀
(DIFFERENTIAL)
4Vp-p
40Vp-p
499⍀
–100
R
= 15⍀
2
AMP2
–15V
–110
100⍀
1:2
TRANSFORMER
1/2
AD815
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Total Harmonic Distortion vs. Frequency
Subscriber Line Differential Driver
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD815–SPECIFICATIONS
(@ TA = +25؇C, VS = ؎15 V dc, RFB = 1 k⍀ and RLOAD = 100 ⍀ unless otherwise noted)
AD815A
Model
Conditions
VS
Min
Typ Max Units
DYNAMIC PERFORMANCE
Small Signal Bandwidth (–3 dB)
G = +1
G = +1
G = +2
G = +2
±15
±5
±15
±5
±15
±15
100
90
120
110
40
10
900
70
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth (0.1 dB)
Differential Slew Rate
Settling Time to 0.1%
V
OUT = 20 V p-p, G = +2
800
10 V Step, G = +2
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
f = 1 MHz, RLOAD = 200 Ω, VOUT = 40 V p-p ±15
–66
1.85
1.8
19
0.05
0.45
dBc
f = 10 kHz, G = +2 (Single Ended)
f = 10 kHz, G = +2
f = 10 kHz, G = +2
NTSC, G = +2, RLOAD = 25 Ω
NTSC, G = +2, RLOAD = 25 Ω
±5, ±15
nV/√Hz
pA/√Hz
pA/√Hz
%
Input Current Noise (+IIN
)
±5, ±15
±5, ±15
±15
Input Current Noise (–IIN
Differential Gain Error
Differential Phase Error
)
±15
Degrees
DC PERFORMANCE
Input Offset Voltage
±5
±15
5
10
8
15
30
mV
mV
mV
µV/°C
mV
mV
mV
µV/°C
µA
µA
µA
µA
µA
TMIN – TMAX
Input Offset Voltage Drift
Differential Offset Voltage
20
0.5
0.5
±5
±15
2
4
5
TMIN – TMAX
Differential Offset Voltage Drift
–Input Bias Current
10
10
±5, ±15
±5, ±15
±5, ±15
±5, ±15
90
150
5
5
75
100
TMIN – TMAX
TMIN – TMAX
TMIN – TMAX
TMIN – TMAX
+Input Bias Current
2
Differential Input Bias Current
Open-Loop Transresistance
10
5.0
µA
MΩ
MΩ
1.0
0.5
INPUT CHARACTERISTICS
Differential Input Resistance
+Input
–Input
±15
7
15
MΩ
Ω
Differential Input Capacitance
Input Common-Mode Voltage Range
±15
±15
±5
±5, ±15
±5, ±15
1.4
13.5
3.5
65
pF
±V
±V
dB
dB
Common-Mode Rejection Ratio
Differential Common-Mode Rejection Ratio TMIN – TMAX
TMIN – TMAX
57
80
100
OUTPUT CHARACTERISTICS
Voltage Swing
Single Ended, RLOAD = 25 Ω
±15
±5
±15
11.0
1.1
21
11.7
1.8
23
±V
±V
±V
±V
Differential, RLOAD = 50 Ω
MIN – TMAX
T
±15
22.5
24.5
Output Current1, 2
VR, Y
RLOAD = 5 Ω
±15
±5
±15
±15
±15
500
350
400
750
400
500
1.0
13
mA
mA
mA
A
RB-24
Short Circuit Current
Output Resistance
RLOAD = 10 Ω
Ω
MATCHING CHARACTERISTICS
Crosstalk
f = 1 MHz
±15
–65
dB
POWER SUPPLY
Operating Range3
Quiescent Current
TMIN – TMAX
±18
30
40
40
55
V
±5
±15
±5
±15
±5, ±15
23
30
mA
mA
mA
mA
dB
TMIN – TMAX
TMIN – TMAX
Power Supply Rejection Ratio
NOTES
–55
–66
1Output current is limited in the 24-lead SOIC package to the maximum power dissipation. See absolute maximum ratings and derating curves.
2See Figure 12 for bandwidth, gain, output drive recommended operation range.
3Observe derating curves for maximum junction temperature.
Specifications subject to change without notice.
–2–
REV. B
AD815
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Total
The maximum power that can be safely dissipated by the AD815
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for the plastic encapsulated
parts is determined by the glass transition temperature of the
plastic, about 150°C. Exceeding this limit temporarily may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.
Internal Power Dissipation2
Plastic (Y and VR) . . 3.05 Watts (Observe Derating Curves)
Small Outline (RB) . . 2.4 Watts (Observe Derating Curves)
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Can Only Short to Ground
Storage Temperature Range
Y, VR and RB Package . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD815A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C
The AD815 has thermal shutdown protection, which guarantees
that the maximum junction temperature of the die remains below a
safe level, even when the output is shorted to ground. Shorting
the output to either power supply will result in device failure.
To ensure proper operation, it is important to observe the
derating curves and refer to the section on power considerations.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
It must also be noted that in high (noninverting) gain configurations
(with low values of gain resistor), a high level of input overdrive
can result in a large input error current, which may result in a
significant power dissipation in the input stage. This power
must be included when computing the junction temperature rise
due to total internal power.
2Specification is for device in free air with 0 ft/min air flow: 15-Lead Through-Hole
and Surface Mount: θJA = 41°C/W; 24-Lead Surface Mount: θJA = 52°C/W.
PIN CONFIGURATION
24-Lead Thermally-Enhanced SOIC (RB-24)
14
T
= 150؇C
J
13
12
11
θJA = 16؇C/W
1
2
24
23
22
21
20
19
18
17
16
NC
NC
NC
NC
NC
NC
NC
NC
SOLDERED DOWN TO
COPPER HEAT SINK
(STILL AIR = 0FT/MIN)
10
9
3
AD815 AVR, AY
8
4
7
6
θJA = 41؇C/W
(STILL AIR = 0FT/MIN)
5
AD815
TOP VIEW
THERMAL
HEAT TABS
THERMAL
HEAT TABS
6
NO HEAT SINK
5
4
(Not to Scale)
7
AD815 AVR, AY
+V
*
+V
*
S
S
8
3
θJA = 52؇C/W
(STILL AIR = 0 FT/MIN)
NO HEAT SINK
+IN1
–IN1
9
+IN2
2
1
AD815ARB-24
10
15 –IN2
0
OUT1 11
–V
14 OUT2
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
12
13 +V
S
S
AMBIENT TEMPERATURE – ؇C
NC = NO CONNECT
*HEAT TABS ARE CONNECTED TO THE POSITIVE SUPPLY.
Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
AD815ARB-24
AD815ARB-24-REEL
AD815AVR
AD815AY
AD815AYS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Thermally Enhanced SOIC
24-Lead Thermally Enhanced SOIC
15-Lead Surface Mount DDPAK
15-Lead Through-Hole SIP with Staggered Leads and 90° Lead Form
15-Lead Through-Hole SIP with Staggered Leads and Straight Lead Form
Evaluation Board
RB-24
RB-24
VR-15
Y-15
YS-15
AD815-EB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD815 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD815–Typical Performance Characteristics
20
36
34
32
30
V
= ؎15V
= ؎5V
80
S
15
28
26
10
5
V
S
24
22
20
18
0
0
5
10
15
20
–40
–20
0
20
40
60
100
SUPPLY VOLTAGE – ؎Volts
JUNCTION TEMPERATURE – ؇C
Figure 1. Input Common-Mode Voltage Range vs. Supply
Voltage
Figure 4. Total Supply Current vs. Temperature
80
60
33
40
30
T
= +25؇C
A
30
27
24
21
18
NO LOAD
40
20
20
10
R = 50⍀
L
(DIFFERENTIAL)
= 25⍀
R
L
(SINGLE-ENDED)
0
0
20
0
2
4
6
8
10
12
14
16
0
5
10
15
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎Volts
Figure 2. Output Voltage Swing vs. Supply Voltage
Figure 5. Total Supply Current vs. Supply Voltage
60
50
30
25
20
10
SIDE A, B
V
= ؎15V
S
+I
B
0
–10
–20
V
= ؎15V, ؎5V
S
40
30
20
10
0
V
= ؎5V
S
–30
–40
–50
–60
–70
SIDE B
–I
15
10
B
SIDE A
V
= ؎5V
S
SIDE B
SIDE A
V
5
0
–I
B
= ؎15V
S
–80
–40
–20
0
20
40
60
80
100
10
100
1k
10k
LOAD RESISTANCE – (Differential – ⍀) (Single-Ended – ⍀/2)
JUNCTION TEMPERATURE – ؇C
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 6. Input Bias Current vs. Temperature
–4–
REV. B
AD815
80
0
T
= 25؇C
A
60
40
20
0
–2
–4
V
=
S
؎15V
V
=
V
= ؎5V
S
S
؎10V
–6
V
=
S
؎5V
–8
V
IN
1/2
f = 0.1Hz
AD815
100⍀
V
–20
OUT
–10
–12
–14
49.9⍀
V
= ؎15V
S
R =
L
5⍀
–40
–60
1k⍀
1k⍀
0
LOAD CURRENT – Amps
–2.0 –1.6 –1.2 –0.8 –0.4
0.4
0.8 1.2 1.6
2.0
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE – ؇C
Figure 7. Input Offset Voltage vs. Temperature
Figure 10. Thermal Nonlinearity vs. Output Current Drive
750
V
= ؎15V
S
100
10
700
650
600
550
SOURCE
V
= ؎5V
S
V
= ؎15V
1
S
SINK
0.1
500
450
0.01
–60 –40 –20
0
20
40
60
80
100 120 140
30k
100k 300k
1M
3M
10M
30M 100M 300M
JUNCTION TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 8. Short Circuit Current vs. Temperature
Figure 11. Closed-Loop Output Resistance vs. Frequency
15
T
= 25؇C
A
V
= ؎10V
40
S
T
R
= 25؇C
= 25⍀
A
V
= ±15V
S
10
5
L
V
= ؎5V
V
= ؎15V
S
R
= 100⍀
S
L
30
20
R
R
= 50⍀
= 25⍀
L
0
V
IN
1/2
f = 0.1Hz
AD815
100⍀
–5
–10
–15
V
L
OUT
49.9⍀
10
0
R =
L
25⍀
1k⍀
1k⍀
R
= 1⍀
L
0
2
4
6
8
10
12
14
–20 –16 –12
–8
–4
V
0
4
8
12
16
20
FREQUENCY – MHz
– Volts
OUT
Figure 9. Gain Nonlinearity vs. Output Voltage
Figure 12. Large Signal Frequency Response
REV. B
–5–
AD815
100
100
120
110
100
90
TRANSIMPEDANCE
INVERTING INPUT
CURRENT NOISE
100
500
0
80
PHASE
10
10
70
–50
–100
–150
–200
–250
60
NONINVERTING INPUT
CURRENT NOISE
50
40
30
INPUT VOLTAGE
NOISE
1
100k
1
10
100
1k
10k
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
FREQUENCY – Hz
Figure 13. Input Current and Voltage Noise vs. Frequency
Figure 16. Open-Loop Transimpedance vs. Frequency
90
80
–40
V
= ؎15V
S
G = +10
–50
–60
V
= ؎15V
V
= 40V p-p
S
OUT
70
60
SIDE B
SIDE A
–70
50
40
30
20
10
562⍀
R
= 50⍀
L
–80
(DIFFERENTIAL)
562⍀
562⍀
V
V
OUT
IN
R
= 200⍀
L
–90
(DIFFERENTIAL)
1/2
AD815
562⍀
–100
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 14. Common-Mode Rejection vs. Frequency
Figure 17. Total Harmonic Distortion vs. Frequency
0
10
8
–10
–20
V
= ؎15V
S
0.1%
1%
G = +2
= 100⍀
6
R
L
GAIN = +2
–30
–40
4
2
0
V
= ؎15V
S
–PSRR
–50
–60
–70
+PSRR
–2
–4
–80
–90
–6
1%
0.1%
–8
–100
–10
0.01
0.1
1
10
100
300
0
20
40
60
70
80
100
FREQUENCY – MHz
SETTLING TIME – ns
Figure 15. Power Supply Rejection vs. Frequency
Figure 18. Output Swing and Error vs. Settling Time
–6–
REV. B
AD815
700
1400
5
4
3
2
1
0
G = +10
G = +2
600
500
400
300
200
100
0
1200
1000
800
600
400
200
0
SIDE B
SIDE A
SIDE A
+T
Z
–T
Z
SIDE B
0
5
10
15
20
25
–40
–20
0
20
40
60
80
100
OUTPUT STEP SIZE – V p-p
JUNCTION TEMPERATURE – ؇C
Figure 19. Slew Rate vs. Output Step Size
Figure 22. Open-Loop Transresistance vs. Temperature
–85
–80
–75
–70
–65
–60
15
V
= ؎15V
S
V
= ؎15V
S
SIDE B
SIDE A
R
= 150⍀
L
14
13
12
11
10
+PSRR
+V
OUT
| –V
|
OUT
+V
OUT
R
= 25⍀
L
SIDE A
SIDE B
| –V
|
OUT
–PSRR
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 20. PSRR vs. Temperature
Figure 23. Single-Ended Output Swing vs. Temperature
27
26
–74
–73
–72
–71
V
R
= ؎15V
= 50⍀
S
L
25
24
–V
+V
OUT
–70
–69
–68
–67
–66
OUT
–CMRR
+CMRR
23
22
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE – ؇C
JUNCTION TEMPERATURE – ؇C
Figure 24. Differential Output Swing vs. Temperature
Figure 21. CMRR vs. Temperature
REV. B
–7–
AD815
1
6 BACK TERMINATED LOADS (25⍀)
؎15V
؎15V
0.04
0.03
0.02
0.01
0.00
0.5
0.4
0.3
0
؎5V
PHASE
G = +2
F
NTSC
0.1
0
–1
R
= 1k⍀ 0.2
0.1
0.0
–0.1
–0.2
–0.3
–2
–3
–0.01
–0.02
–0.03
–0.04
A
B
GAIN
–0.1
A
–0.2
–0.3
–0.4
–4
–5
–6
1
2
3
4
5
6
7
8
9
10 11
B
2 BACK TERMINATED LOADS (75⍀)
V
IN
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.010
0.005
0.000
–0.005
–0.010
–0.015
100⍀
V
OUT
PHASE
GAIN
؎5V
GAIN
49.9⍀
499⍀
G = +2
100⍀
–7
–8
–0.5
–0.6
R
= 1k⍀
499⍀
F
NTSC
–0.020
PHASE
–0.025
–0.030
–0.02
–0.04
–9
300
–0.7
0.1
1
10
FREQUENCY – MHz
100
1
2
3
4
5
6
7
8
9
10 11
Figure 25. Differential Gain and Differential Phase
(per Amplifier)
Figure 28. Bandwidth vs. Frequency, G = +2
–10
1
V
= ؎15V
S
G = +2
–20
–30
0
–1
–2
R
= 499⍀
F
SIDE A
V
= ؎15V, ؎5V
= 400mVrms
= 100⍀
SIDE B
S
V
IN
–40
–50
R
L
SIDE B
SIDE A
–60
–70
–80
–3
–4
–5
–6
V
IN
100⍀
V
OUT
49.9⍀
124⍀ 499⍀
100⍀
–90
–100
–110
–7
0.1
0.03
0.1
1
10
100
300
1
10
100
300
FREQUENCY – MHz
FREQUENCY – MHz
Figure 26. Output-to-Output Crosstalk vs. Frequency
Figure 29. –3 dB Bandwidth vs. Frequency, G = +5
2
V
V
= ؎15V
S
1
0
= 0 dBm
SIDE B
IN
100
90
SIDE A
–1
–2
–3
V
IN
100⍀
V
OUT
–4
–5
49.9⍀
10
100⍀
562⍀
0%
–6
–7
–9
5V
1s
0.1
1
10
100
300
FREQUENCY – MHz
Figure 27. –3 dB Bandwidth vs. Frequency, G = +1
Figure 30. 40 V p-p Differential Sine Wave, RL = 50 Ω,
f = 100 kHz
–8–
REV. B
AD815
R
562⍀
F
10F
0.1F
10F
0.1F
+15V
+15V
0.1F
R
S
8
1/2 AD815
7
8
1/2 AD815
100⍀
50⍀
100⍀
0.1F
10F
R
= 100⍀
V
IN
R
= 100⍀
V
L
L
IN
7
PULSE
GENERATOR
PULSE
GENERATOR
50⍀
10F
–15V
–15V
T
/T = 250ps
F
T
/T = 250ps
F
R
R
Figure 35. Test Circuit, Gain = 1 + RF /RS
Figure 31. Test Circuit, Gain = +1
SIDE A
G = +1
G = +5
R
R
R
= 562⍀
= 100⍀
= 140⍀
R
R
= 698⍀
= 100⍀
F
L
S
F
L
SIDE A
SIDE B
SIDE B
5V
100mV
100ns
20ns
Figure 36. 20 V Step Response, G = +5
Figure 32. 500 mV Step Response, G = +1
G = +1
562⍀
R
R
= 562⍀
= 100⍀
F
L
SIDE A
SIDE B
10F
+15V
0.1F
562⍀
8
V
IN
PULSE
GENERATOR
1/2 AD815
55⍀
100⍀
0.1F
R
= 100⍀
L
7
T
/T = 250ps
F
R
10F
–15V
1V
20ns
Figure 33. 4 V Step Response, G = +1
Figure 37. Test Circuit, Gain = –1
SIDE A
G = –1
SIDE A
G = +1
R
R
= 562⍀
= 100⍀
R
R
= 562⍀
= 100⍀
F
L
F
L
SIDE B
SIDE B
100mV
2V
20ns
50ns
Figure 34. 10 V Step Response, G = +1
Figure 38. 500 mV Step Response, G = –1
REV. B
–9–
AD815
Choice of Feedback and Gain Resistors
G = –1
The fine scale gain flatness will, to some extent, vary with
feedback resistance. It therefore is recommended that once
optimum resistor values have been determined, 1% tolerance
values should be used if it is desired to maintain flatness over
a wide range of production lots. Table I shows optimum values
for several useful configurations. These should be used as
starting point in any application.
R
R
= 562⍀
= 100⍀
F
L
SIDE A
SIDE B
Table I. Resistor Values
RF (⍀) RG (⍀)
1V
20ns
G = +1
562
499
499
499
ϱ
–1
+2
+5
499
499
125
110
Figure 39. 4 V Step Response, G = –1
THEORY OF OPERATION
+10 1 k
The AD815 is a dual current feedback amplifier with high
(500 mA) output current capability. Being a current feedback
amplifier, the AD815’s open-loop behavior is expressed
as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop
transimpedance behaves just as the open-loop voltage gain
of a voltage feedback amplifier, that is, it has a large dc value
and decreases at roughly 6 dB/octave in frequency.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling.
Since RIN is proportional to 1/gM, the equivalent voltage gain is
just TZ × gM, where the gM in question is the transconductance
of the input stage. Using this amplifier as a follower with gain,
Figure 40, basic analysis yields the following result:
POWER SUPPLY BYPASSING
TZ
S
( )
VO
VIN
Adequate power supply bypassing can be critical when optimizing
the performance of a high frequency circuit. Inductance in the
power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
10.0 µF and 0.1 µF is recommended. Under some low frequency
applications, a bypass capacitance of greater than 10 µF may be
necessary. Due to the large load currents delivered by the
AD815, special consideration must be given to careful bypassing.
The ground returns on both supply bypass capacitors as well as
signal common must be “star” connected as shown in Figure 41.
= G ×
TZ S + G × R + RF
( )
IN
where:
RF
G = 1 +
RG
IN = 1/gM ≈ 25 Ω
R
R
F
R
G
R
IN
V
OUT
R
N
+V
S
V
IN
+IN
+OUT
R
F
Figure 40. Current Feedback Amplifier Operation
R
G
Recognizing that G × RIN << RF for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G).
R
F
(OPTIONAL)
–OUT
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice
parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop, so picking an optimum value for RF
can be difficult.
–IN
–V
S
Figure 41. Signal Ground Connected in “Star”
Configuration
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
–10–
REV. B
AD815
DC ERRORS AND NOISE
Figure 44 gives the relationship between output voltage swing
into various loads and the power dissipated by the AD815 (PIN).
This data is given for both sine wave and square wave (worst
case) conditions. It should be noted that these graphs are for
mostly resistive (phase < ±10°) loads. When the power dissipation
requirements are known, Equation 1 and the graph on Figure 45
can be used to choose an appropriate heat sinking configuration.
There are three major noise and offset terms to consider in
a current feedback amplifier. For offset errors refer to the
equation below. For noise error the terms are root-sum-squared
to give a net output error. In the circuit below (Figure 42), they
are input offset (VIO) which appears at the output multiplied by
the noise gain of the circuit (1 + RF/RG), noninverting input
current (IBN × RN) also multiplied by the noise gain, and the
inverting input current, which when divided between RF and RG
and subsequently multiplied by the noise gain always appear at
the output as IBI × RF. The input voltage noise of the AD815 is
less than 2 nV/√Hz. At low gains though, the inverting input
current noise times RF is the dominant noise source. Careful
layout and device matching contribute to better offset and
drift specifications for the AD815 compared to many other
current feedback amplifiers. The typical performance curves
in conjunction with the equations below can be used to predict
the performance of the AD815 in any application.
R
= 50⍀
f = 1kHz
L
4
3
2
1
SQUARE WAVE
SINE WAVE
= 100⍀
R
L
R
= 200⍀
L
RF
RG
RF
RG
V
= VIO × 1+
± IBN × RN × 1+
± IBI × RF
OUT
10
20
30
40
V
– Volts p-p
R
F
OUT
Figure 44. Total Power Dissipation vs. Differential Output
Voltage
I
BI
R
G
I
BN
V
OUT
Normally, the AD815 will be soldered directly to a copper pad.
Figure 45 plots θJA against size of copper pad. This data pertains
to copper pads on both sides of G10 epoxy glass board connected
together with a grid of feedthroughs on 5 mm centers.
R
N
Figure 42. Output Offset Voltage
POWER CONSIDERATIONS
This data shows that loads of 100 ohms or less will usually not
require any more than this. This is a feature of the AD815’s
15-lead power SIP package.
The 500 mA drive capability of the AD815 enables it to drive
a 50 Ω load at 40 V p-p when it is configured as a differential
driver. This implies a power dissipation, PIN, of nearly 5 watts.
To ensure reliability, the junction temperature of the AD815
should be maintained at less than 175°C. For this reason,
the AD815 will require some form of heat sinking in most
applications. The thermal diagram of Figure 43 gives the
basic relationship between junction temperature (TJ) and
various components of θJA.
An important component of θJA is the thermal resistance of the
package to heatsink. The data given is for a direct soldered
connection of package to copper pad. The use of heatsink
grease either with or without an insulating washer will increase
this number. Several options now exist for dry thermal connec-
tions. These are available from Bergquist as part # SP600-90.
Consult with the manufacturer of these products for details of
their application.
35
Equation 1
T
J
= TA + P θJA
IN
T
J
θ
A
(JUNCTION TO
DIE MOUNT)
30
AD815AVR, AY (θ = 2؇C/W)
JC
25
20
θ B (DIE MOUNT
TO CASE)
T
A
θA + θ B = θ JC
CASE
θ JC
θ CA
T
J
15
10
T
A
P
IN
θ JA
WHERE:
0
0.5k
1k
1.5k
2k
2.5k
P
T
= DEVICE DISSIPATION
2
IN
COPPER HEAT SINK AREA (TOP AND BOTTOM) – mm
= AMBIENT TEMPERATURE
A
J
Figure 45. Power Package Thermal Resistance vs. Heat
Sink Area
T
θ
θ
= JUNCTION TEMPERATURE
= THERMAL RESISTANCE – JUNCTION TO CASE
JC
= THERMAL RESISTANCE – CASE TO AMBIENT
CA
Figure 43. A Breakdown of Various Package Thermal
Resistances
REV. B
–11–
AD815
Other Power Considerations
resistor should be placed in series with each output. See Figure
There are additional power considerations applicable to the
AD815. First, as with many current feedback amplifiers, there is an
increase in supply current when delivering a large peak-to-peak
voltage to a resistive load at high frequencies. This behavior is
affected by the load present at the amplifier’s output. Figure 12
summarizes the full power response capabilities of the AD815.
These curves apply to the differential driver applications (e.g.,
Figure 49 or Figure 53). In Figure 12, maximum continuous
peak-to-peak output voltage is plotted vs. frequency for various
resistive loads. Exceeding this value on a continuous basis can
damage the AD815.
48. This circuit can deliver 800 mA into loads of up to 12.5 Ω.
499⍀
499⍀
+15V
0.1F
10F
8
5
4
1⍀
1/2
AD815
6
100⍀
499⍀
50⍀
499⍀
R
L
The AD815 is equipped with a thermal shutdown circuit. This
circuit ensures that the temperature of the AD815 die remains
below a safe level. In normal operation, the circuit shuts down
the AD815 at approximately 180°C and allows the circuit to
turn back on at approximately 140°C. This built-in hysteresis
means that a sustained thermal overload will cycle between
power-on and power-off conditions. The thermal cycling
typically occurs at a rate of 1 ms to several seconds, depending
on the power dissipation and the thermal time constants of the
package and heat sinking. Figures 46 and 47 illustrate the
thermal shutdown operation after driving OUT1 to the + rail,
and OUT2 to the – rail, and then short-circuiting to ground
each output of the AD815. The AD815 will not be damaged by
momentary operation in this state, but the overload condition
should be removed.
10 1/2
AD815
1⍀
9
100⍀
11
7
0.1F
10F
–15V
Figure 48. Parallel Operation for High Current Output
Differential Operation
Various circuit configurations can be used for differential
operation of the AD815. If a differential drive signal is avail-
able, the two halves can be used in a classic instrumentation
configuration to provide a circuit with differential input and
output. The circuit in Figure 49 is an illustration of this. With
the resistors shown, the gain of the circuit is 11. The gain can
be changed by changing the value of RG. This circuit, however,
provides no common-mode rejection.
OUT 1
+15V
100
90
0.1F
10F
100⍀
+IN
4
8
OUT 1
1/2
6
AD815
OUT 2
5
R
F
499⍀
10
0%
V
R
G
100⍀
IN
V
R
OUT
L
5V
200s
R
F
499⍀
10 1/2
AD815
OUT 2
Figure 46. OUT2 Shorted to Ground, Square Wave Is
OUT1, RF = 1 kΩ, RG = 222 Ω
9
100⍀
–IN
11
7
10F
0.1F
100
90
–15V
Figure 49. Fully-Differential Operation
Creating Differential Signals
OUT 1
If only a single ended signal is available to drive the AD815 and
a differential output signal is desired, several circuits can be
used to perform the single-ended-to-differential conversion.
OUT 2
10
0%
5V
5ms
One circuit to perform this is to use a dual op amp as a
predriver that is configured as a noninverter and inverter. The
circuit shown in Figure 50 performs this function. It uses an
AD826 dual op amp with the gain of one amplifier set at +1 and
the gain of the other at –1. The 1 kΩ resistor across the input
terminals of the follower makes the noise gain (NG = 1) equal
to the inverter’s. The two outputs then differentially drive the
inputs to the AD815 with no common-mode signal to first order.
Figure 47. OUT1 Shorted to Ground, Square Wave Is
OUT2, RF = 1 kΩ, RG = 222 Ω
Parallel Operation
To increase the drive current to a load, both of the amplifiers
within the AD815 can be connected in parallel. Each amplifier
should be set for the same gain and driven with the same signal.
In order to ensure that the two amplifiers share current, a small
–12–
REV. B
AD815
+15V
8
+15V
8
+15V
0.1F
0.1F
10F
100⍀
4
V
IN
4
5
3
2
8
1/2
AD815
1/2
AD815
6
1/2
AD826
6
AMP 1
1
1k⍀
5
R
F
R
F1
499⍀
1k⍀
402⍀
R
100⍀
G
R
100⍀
G
R
V
L
R
OUT
L
1k⍀
1k⍀
R
F
499⍀
R
499⍀
F2
6
10
11
1/2
10 1/2
1/2
7
AD826
9
9
AD815
100⍀
AMP 2
AD815
4
5
0.1F
7
11
7
10F
0.1F
–15V
–15V
–15V
Figure 50. Differential Driver with Single-Ended
Differential Converter
Figure 52. Direct Single-Ended-to-Differential Conversion
Amp 1 has its + input driven with the input signal, while the
+ input of Amp 2 is grounded. Thus the – input of Amp 2 is
driven to virtual ground potential by its output. Therefore
Amp 1 is configured for a noninverting gain of five, (1 + RF1/RG),
because RG is connected to the virtual ground of Amp 2’s – input.
Another means for creating a differential signal from a single-
ended signal is to use a transformer with a center-tapped
secondary. The center tap of the transformer is grounded and
the two secondary windings are connected to obtain opposite
polarity signals to the two inputs of the AD815 amplifiers. The
bias currents for the AD815 inputs are provided by the center
tap ground connection through the transformer windings.
When the + input of Amp 1 is driven with a signal, the same
signal appears at the – input of Amp 1. This signal serves as an
input to Amp 2 configured for a gain of –5, (–RF2/RG). Thus the
two outputs move in opposite directions with the same gain and
create a balanced differential signal.
One advantage of using a transformer is its ability to provide
isolation between circuit sections and to provide good common-
mode rejection. The disadvantages are that transformers have
no dc response and can sometimes be large, heavy, and expensive.
This circuit is shown in Figure 51.
This circuit can work at various gains with proper resistor
selection. But in general, in order to change the gain of the
circuit, at least two resistor values will have to be changed. In
addition, the noise gain of the two op amps in this configuration
will always be different by one, so the bandwidths will not match.
+15V
0.1F
10F
A second circuit that has none of the disadvantages mentioned
in the above circuit creates a differential output voltage feedback
op amp out of the pair of current feedback op amps in the AD815.
This circuit, drawn in Figure 53, can be used as a high power
differential line driver, such as required for ADSL (asymmetrical
digital subscriber loop) line driving.
100⍀
4
5
8
1/2
6
AD815
50⍀
1k⍀
50⍀
200⍀
R
L
1k⍀
Each of the AD815’s op amps is configured as a unity gain
follower by the feedback resistors (RA). Each op amp output
also drives the other as a unity gain inverter via the two RBs,
creating a totally symmetrical circuit.
10
11
1/2
9
AD815
100⍀
7
If the + input to Amp 2 is grounded and a small positive signal
is applied to the + input of Amp 1, the output of Amp 1 will be
driven to saturation in the positive direction and the output of
Amp 2 driven to saturation in the negative direction. This is
similar to the way a conventional op amp behaves without any
feedback.
10F
0.1F
–15V
Figure 51. Differential Driver with Transformer Input
Direct Single-Ended-to-Differential Conversion
Two types of circuits can create a differential output signal from
a single-ended input without the use of any other components
than resistors. The first of these is illustrated in Figure 52.
REV. B
–13–
AD815
~20pF
Twelve Channel Video Distribution Amplifier
The high current of the AD815 enables it to drive up to twelve
standard 75 Ω reverse terminated video loads. Figure 54 is a
schematic of such an application.
R
F
499⍀
+15V
V
R
499⍀
I
(OPTIONAL)
50⍀
0.1F
The input video signal is terminated in 75 Ω and applied to the
noninverting inputs of both amplifiers of the AD815. Each
amplifier is configured for a gain of two to compensate for the
divide-by-two feature of each cable termination. Six separate
75 Ω resistors for each amplifier output are used for the cable
back termination. In this manner, all cables are relatively
independent of each other and small disturbances on any cable
will not have an effect on the other cables.
10F
CC
V
4
5
8
IN
1/2
AD815
6
AMP1
R
A
R
B
250
(50⍀)
(OPTIONAL)
499⍀
499⍀
100⍀
R
B
R
A
499⍀
499⍀
When driving six video cables in this fashion, the load seen by
each amplifier output is resistive and is equal to 150 Ω/6 or
25 Ω. The differential gain is 0.05% and the differential phase
10 1/2
50⍀
9
CC
AMP2
AD815
is 0.45°.
11
7
V
+15V
10F
0.1F
0.1F
10F
–15V
499⍀
12
؋
75⍀ Figure 53. Single-Ended-to-Differential Driver
499⍀
If a resistor (RF) is connected from the output of Amp 2 to the
+ input of Amp 1, negative feedback is provided which closes
the loop. An input resistor (RI) will make the circuit look like a
conventional inverting op amp configuration with differential
outputs. The inverting input to this dual output op amp becomes
Pin 4, the positive input of Amp 1.
5
4
8
6
100⍀
12
؋
VIDEO OUT
TO 75⍀
CABLES
VIDEO IN
AD815
75⍀
100⍀
11
10
The gain of this circuit from input to either output will be ± RF/
RI. Or the single-ended-to-differential gain will be 2 × RF/RI.
9
7
The differential outputs can be applied to the primary of a
transformer. If each output can swing ±10 V, the effective swing
on the transformer primary is 40 V p-p. The optional capacitor
can be added to prevent any dc current in the transformer due
to dc offsets at the output of the AD815.
499⍀
499⍀
10F
0.1F
–15V
Figure 54. AD815 Video Distribution Amp Driving
12 Video Cables
C1
B2
B1
B3
+15V
–15V
TP4 TP3
J5
TP2
C2
0.1F
R3
+15V
4
J1
R1
R5
T1
C3
2
8
10F
4
C6
R7
R19
1/2
AD815
6
1
R8
5
U1
1
2
7
5
1
2
R2
R6
R17
R20
J4
R4
J7
R22
3
1
2
C13
R16
3
R15
10
9
6
C9
J2
TP1
–15V
C10
0.1F
8
11
R14
12
3
JP1
J3
R10
R12
C11
11
7
10F
R13
J6
R9
R21
1/2
9
AD815
10
U1
R11
R18
Figure 55. AD815 Evaluation Board Schematic
–14–
REV. B
AD815
Figure 56. AD815 AVR Evaluation Board Assembly Drawing
Figure 58. AD815 AVR Evaluation Board Layout
(Solder Side)
Figure 57. AD815 AVR Evaluation Board Layout
(Component Side)
REV. B
–15–
AD815
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
15-Lead Through-Hole SIP with Staggered Leads and
15-Lead Surface Mount DDPAK
(VR-15)
90؇ Lead Form (Y-15)
0.110
(2.79)
BSC
0.110
(2.79)
BSC
0.063 (1.60)
0.057 (1.45)
0.063 (1.60)
0.057 (1.45)
0.152 (3.86)
0.152 (3.86)
0.148 (3.76)
0.394
(10.007)
0.394
0.148 (3.76)
(10.007)
0.137
(3.479)
TYP
0.137
(3.479)
TYP
0.516
(13.106)
0.671
±0.006
(17.043
±0.152)
SHORT
LEAD
0.666
0.042
(1.066)
TYP
±0.006
(16.916
±0.152)
LONG
LEAD
0.042
(1.066)
TYP
0.080 (2.03)
0.080 (2.03)
1
15
1
15
0.065 (1.65)
2 PLACES
0.065 (1.65)
2 PLACES
8°
0°
PIN 1
0.079 (2.006)
DIA
2 PLACES
PIN 1
0.079 (2.006)
DIA
2 PLACES
0.600 (15.24)
BSC
0.146 (3.70)
0.138 (3.50)
0.024 (0.61)
0.014 (0.36)
0.798 (20.27)
0.024 (0.61)
0.014 (0.36)
0.778 (19.76)
0.798 (20.27)
0.778 (19.76)
0.182 (4.62)
0.172 (4.37)
0.182 (4.62)
0.172 (4.37)
0.209 ±0.010
(5.308 ±0.254)
SEATING
PLANE
0.100 (2.54) 0.031 (0.79)
SEATING
PLANE
BSC
0.024 (0.60)
0.050 0.031 (0.79)
(1.27)
BSC
0.024 (0.60)
0.700 (17.78) BSC
24-Lead Thermally Enhanced SOIC
(RB-24)
15-Lead Through-Hole SIP with Staggered Leads and
Straight Lead Form (YS-15)
0.6141 (15.60)
0.5985 (15.20)
0.110
(2.79)
BSC
0.152 (3.86)
0.148 (3.76)
0.063 (1.60)
0.057 (1.45)
0.394
(10.007)
24
13
0.137
(3.48)
TYP
0.601
±0.010
(15.265
±0.254)
LONG
LEAD
0.627
0.042
(1.07)
TYP
±0.010
(15.926
±0.254)
SHORT
LEAD
1
12
0.710 (18.03)
0.690 (17.53)
PIN 1
0.1043 (2.65)
0.0291 (0.74)
0.0098 (0.25)
1
15
0.080 (2.03)
x 45°
0.0926 (2.35)
0.065 (1.65)
2 PLACES
0.176 (4.47)
0.150 (3.81)
0.024 (0.61)
0.014 (0.36)
PIN 1
0.079
(2.007) DIA
2 PLACES
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.700 (17.78) BSC
0.0500
(1.27)
BSC
0.0201 (0.51)
0.0130 (0.33)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.200
(5.08)
BSC
0.169
(4.29)
BSC
0.798 (20.27)
0.778 (19.76)
0.182 (4.62)
0.172 (4.37)
SEATING
PLANE
0.050 (1.27)
BSC
0.031 (0.79)
0.024 (0.60)
–16–
REV. B
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