AD8174AR-REEL [ADI]
250 MHz, 10 ns Switching Multiplexers w/Amplifier; 250兆赫， 10 ns开关多路复用器瓦特/放大器
| 型号： | AD8174AR-REEL |
| 厂家： | 
ADI |
| 描述： | 250 MHz, 10 ns Switching Multiplexers w/Amplifier |
| 文件： | 总16页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 MHz, 10 ns Switching
Multiplexers w/Amplifier
a
AD8170/AD8174
FUNCTIONAL BLOCK DIAGRAM
AD8170
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
Internal Current Feedback Output Amplifier
High Output Drive: 50 mA
Flexible Gain Setting via External Resistor(s)
High Speed
SELECT
1
2
3
4
8
7
6
5
V
OUT
–V
+V
GND
IN
–V
S
S
IN1
IN0
+1
+1
250 MHz Bandwidth, G = +2
1000 V/s Slew Rate
Fast Settling Time of 15 ns to 0.1%
Low Power: < 10 mA
Excellent Video Specifications (RL = 150 ⍀, G = +2)
Gain Flatness of 0.1 dB Beyond 80 MHz
0.02% Differential Gain Error
AD8174
+1
+V
14
13
12
1
2
3
4
IN0
GND
IN1
S
V
OUT
–V
IN
+1
+1
+1
2
GND
IN2
11 SD
0.05؇ Differential Phase Error
Low Crosstalk of –78 dB @ 5 MHz
High Disable Isolation of –88 dB @ 5 MHz
High Shutdown Isolation of –92 dB @ 5 MHz
Low Cost
ENABLE
10
9
5
6
7
A1
A0
–V
S
8
IN3
2
Fast Output Disable Feature for Connecting Multiple
Devices (AD8174 Only)
Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only)
APPLICATIONS
The AD8174 offers a high speed disable feature allowing the
output to be put into a high impedance state for cascading
stages so that the off channels do not load the output bus.
Additionally, the AD8174 can be shut down (SD) when not in
use to minimize power consumption (IS = 1.5 mA). These
products will be offered in 8-lead and 14-lead PDIP and SOIC
packages.
Pixel Switching for “Picture-In-Picture”
LCD and Plasma Displays
Video Routers
PRODUCT DESCRIPTION
The AD8170(2:1) and AD8174(4:1) are very high speed
buffered multiplexers. These multiplexers offer an internal
current feedback output amplifier whose gain can be pro-
grammed via external resistors and is capable of delivering 50
mA of output current. They offer –3 dB signal bandwidth of
250 MHz and slew rate of greater than 1000 V/µs. Additionally,
the AD8170 and AD8174 have excellent video specifications
with low differential gain and differential phase error of 0.02%
and 0.05° and 0.1 dB flatness out to 80 MHz. With a low 78
dB of crosstalk and better than 88 dB isolation, these devices are
useful in many high speed applications. These are low power
devices consuming only 9.7 mA from a ±5 V supply.
0
V
= 50mV rms
IN
G = +2
–1
–2
–3
–4
–5
–6
–7
–8
–9
R
R
R
= 499Ω (AD8170R)
F
F
L
= 549Ω (AD8174R)
= 100Ω
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
1M
10M
100M
1G
FREQUENCY – Hz
Figure 1. Small Signal Frequency Response
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
(@ TA = +25؇C, VS = ؎5 V, RL = 150 ⍀, G = +2, RF = 499 ⍀
(AD8170R), RF = 549 ⍀ (AD8174R) unless otherwise noted)
AD8170/AD8174–SPECIFICATIONS
AD8170A/AD8174A
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
Switching Time1
Channel-to-Channel
50% Logic to 10% Output Settling
50% Logic to 90% Output Settling
50% Logic to 99.9% Output Settling
ENABLE to Channel ON Time2 (AD8174R)
50% Logic to 90% Output Settling
ENABLE to Channel OFF Time2 (AD8174R)
50% Logic to 90% Output Settling
Shutdown to Channel ON Time3 (AD8174R)
50% Logic to 90% Output Settling
Shutdown to Channel OFF Time3 (AD8174R)
50% Logic to 90% Output Settling
Channel Switching Transient (Glitch)4
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
7.5
9.1
25
ns
ns
ns
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
17
ns
ns
ns
120
20
IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V
All Inputs Grounded
115
138 /104
ns
mV p-p
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
SELECT, A0, A1, ENABLE, SD Inputs, TMIN–TMAX
SELECT, A0, A1, ENABLE, SD Inputs, TMIN–TMAX
SELECT, A0, A1 Inputs, TMIN–TMAX
ENABLE, SD Inputs, TMIN–TMAX
SELECT, A0, A1 Inputs, TMIN–TMAX
2.0
V
V
nA
µA
µA
nA
0.8
300
5
5
300
Logic “1” Input Current
50
1
3
Logic “0” Input Current
ENABLE, SD Inputs, TMIN–TMAX
30
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)5
–3 dB Bandwidth (Large Signal)5
0.1 dB Bandwidth5
VO = 50 mV rms, RL = 100 Ω
VO = 1 V rms, RL = 100 Ω
VO = 50 mV rms, RF = 499 Ω (AD8170R), RL = 100 Ω
250
100
MHz
MHz
VO = 50 mV rms, RF = 549 Ω (AD8174R), RL = 100 Ω
85
MHz
ns
V/µs
ns
Rise and Fall Time (10% to 90%)
Slew Rate
Settling Time to 0.1%
2 V Step
2 V Step
2 V Step
1.6
1000
15
DISTORTION/NOISE PERFORMANCE
Differential Gain
Differential Phase
ƒ = 3.58 MHz
ƒ = 3.58 MHz
0.02
0.05
–80
–65
–78
–63
–88
–72
–92
–77
10
%
Degrees
dB
dB
dB
dB
dB
dB
dB
All Hostile Crosstalk6
All Hostile Crosstalk6
Disable Isolation7
AD8170R ƒ = 5 MHz, RL = 100 Ω
ƒ = 30 MHz, RL = 100 Ω
AD8174R ƒ = 5 MHz, RL = 100 Ω
ƒ = 30 MHz, RL = 100 Ω
AD8174R ƒ = 5 MHz, RL = 100 Ω
ƒ = 30 MHz, RL = 100 Ω
AD8174R ƒ = 5 MHz, RL = 100 Ω
ƒ = 30 MHz, RL = 100 Ω
Shutdown Isolation8
dB
Input Voltage Noise
ƒ = 10 kHz to 30 MHz
ƒ = 10 kHz to 30 MHz
ƒ = 10 kHz to 30 MHz
ƒC = 10 MHz, VO = 2 V p-p, RL = 150 Ω
nV/√Hz
pA/√Hz
pA/√Hz
dBc
dBc
+Input Current Noise
–Input Current Noise
Total Harmonic Distortion
1.6
8.5
–60
–72
ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kΩ
DC/TRANSFER CHARACTERISTICS
Transresistance
400
2000
600
6000
0.4
kΩ
V/V
%
Open-Loop Voltage Gain
Gain Accuracy9
G = +1, RF = 1 kΩ
Gain Matching
Input Offset Voltage
Channel-to-Channel
0.05
5
%
9
12
5
mV
mV
mV
µV/°C
µA
µA
µA
µA
TMIN to TMAX
Channel-to-Channel
Input Offset Voltage Matching
Input Offset Voltage Drift
Input Bias Current
1.5
11
7
(+) Switch Input
TMIN to TMAX
(–) Buffer Input
15
15
10
14
3
TMIN to TMAX
Input Bias Current Drift
(+) Switch and (–) Buffer Input
20
nA/°C
REV. 0
–2–
AD8170/AD8174
AD8170A/AD8174A
Parameter
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Input Resistance
(+) Switch Input
(–) Buffer Input
Channel Enabled (R Package)
Channel Disabled (R Package)
1.7
100
1.1
1.1
±3.3
56
MΩ
Ω
pF
pF
V
Input Capacitance
Input Voltage Range
Input Common-Mode Rejection Ratio
+CMRR, ∆VCM = 1 V
–CMRR, ∆VCM = 1 V
51
50
dB
dB
52
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 1 kΩ, TMIN–TMAX
RL = 150 Ω, TMIN–TMAX
RL = 10 Ω
±4.0
±3.5
±4.26
±4.0
50
180
10
V
V
Output Current
Short Circuit Current
Output Resistance
mA
mA
mΩ
MΩ
pF
Enabled
Disabled (AD8174)
Disabled (AD8174)
10
7.5
Output Capacitance
POWER SUPPLY
Operating Range
±4
58
55
52
50
±6
V
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Quiescent Current
+PSRR
–PSRR
+VS = +4.5 V to +5.5 V, –VS = –5 V
TMIN–TMAX
–VS = –4.5 V to –5.5 V, +VS= +5 V
TMIN–TMAX
All Channels “ON”, TMIN–TMAX
AD8174 Disabled, TMIN–TMAX
AD8174 Shutdown, TMIN–TMAX
66
58
dB
dB
dB
dB
mA
mA
mA
8.7/9.7
4.1
1.5
11/13
5
2.5
OPERATING TEMPERATURE RANGE
NOTES
–40
+85
°C
1Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is
driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transi-
tion from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa.
2AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆tOFF is the disable time, ∆tON is the enable time.
3AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Figure 6, ∆tOFF is the shutdown assert time, ∆tON is the shutdown
release time.
4All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT
(A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane.
5Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best
compromise between a wide and a flat frequency response.
6Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2).
Drive all other inputs with VIN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100 Ω (see Figure 13).
7AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.354 V rms. Out-
put is monitored at f = 5 MHz and 30 MHz; RL = 100 Ω. In this mode, the output impedance of the disabled mux is very high (typ 10 MΩ), and the signal couples
across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r OUT ഡ 10 MΩ, in a gain of +2
(RF = RG = 549 Ω), rOUT = 1.1 kΩ (see Figure 14).
8AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is moni-
tored at f = 5 MHz and 30 MHz; RL = 100 Ω. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance.
9For Gain Accuracy expression, refer to Equation 4.
Specifications subject to change without notice.
Table II. AD8174 Truth Table
Table I. AD8170 Truth Table
A0
A1
ENABLE
SD
VOUT
SELECT
VOUT
0
1
IN0
IN1
0
1
0
1
X
X
0
0
1
1
X
X
0
0
0
0
1
X
0
0
0
0
0
1
IN0
IN1
IN2
IN3
HIGH Z, IS = 4.1 mA
HIGH Z, IS = 1.5 mA
REV. 0
–3–
AD8170/AD8174
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
The maximum power that can be safely dissipated by the
AD8170 and AD8174 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately +150°C.
Exceeding this limit temporarily may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of +175°C
for an extended period can result in device failure.
Internal Power Dissipation2
AD8170 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts
AD8170 8-Lead Small Outline (R) . . . . . . . . . . . 0.9 Watts
AD8174 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts
AD8174 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range
N & R Packages . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C
While the AD8170 and AD8174 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves shown in Figures 2 and 3.
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Specification is for device in free air: 8-Pin Plastic Package: θJA = 90°C/Watt;
8-Pin SOIC Package: θJA = 160°C/Watt; 14-Pin Plastic Package: θJA = 90°C/Watt
2.0
8-PIN MINI-DIP PACKAGE
T
= +150°C
J
14-Pin SOIC Package: θJA = 120°C/Watt, where PD = (TJ–TA)/θJA
.
1.5
1.0
0.5
0
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD8170AN
AD8170AR
–40°C to +85°C 8-Pin Plastic DIP
–40°C to +85°C 8-Pin SOIC
N-8
8-PIN SOIC PACKAGE
SO-8
SO-8
N-14
AD8170AR-REEL –40°C to +85°C Reel 8-Pin SOIC
AD8174AN
AD8174AR
–40°C to +85°C 14-Pin Plastic DIP
–40°C to +85°C 14-Pin Narrow SOIC R-14
R-14
AD8174AR-REEL –40°C to +85°C Reel 14-Pin SOIC
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AD8170-EB
AD8174-EB
Evaluation Board For AD8170R
Evaluation Board For AD8174R
AMBIENT TEMPERATURE –
°
C
Figure 2. AD8170 Maximum Power Dissipation vs.
Temperature
2.5
T
= +150°C
J
2.0
1.5
1.0
0.5
14-PIN DIP PACKAGE
14-PIN SOIC
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – °C
Figure 3. AD8174 Maximum Power Dissipation vs.
Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8170/AD8174 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–4–
Typical Performance Characteristics – AD8170/AD8174
OUTPUT (AD8170R)
SEL SWITCHING
∆t
RISE
= 7.5ns
∆t
FALL
= 9.1ns
R
= 549⍀
G = +2
F
R
= 499⍀
(AD8174R)
R = 100⍀
L
F
DUT
OUT
OUTPUT
(AD8170R)
IN0, IN2 =
+0.5V
IN1, IN3 =
+0.5V
G = +2
A0 SWITCHING
A1 SWITCHING
OUTPUT
(AD8174R)
R
= R = 499⍀
F
L
G
R
= 100⍀
SELECT
PULSE
0 TO +5V
SEL, A0, A1
PULSE
0 TO +5V
5ns/DIV
10ns/DIV
Figure 4. Channel Switching Characteristics
Figure 7. Switching Transient (Glitch) Response
4
AD8174R
INØ = +0.5VDC
G = +2
G = +2
3
2
R
R
= R = 1kΩ
= 150Ω
F
L
G
R
R
= 549⍀
= 100⍀
F
L
OUTPUT
1
0
∆t
= 120ns
OFF
–1
–2
–3
–4
∆t
ON
= 17ns
ENABLE PULSE
0 TO +5V
(5nsec EDGES)
50ns/DIV
–3
–2
–1
0
1
2
3
V
– Volts
IN
Figure 5. Enable and Disable Switching Characteristics
Figure 8. Output Voltage vs. Input Voltage, G = +2
9
9
6
3
V
V
= 1.0V rms
IN
G = +2
0
R
R
= 549Ω
= 100Ω
F
L
AD8174R
OUTPUT
–3
= 0.5V rms
INØ = +0.5VDC
G = +2
IN
IN
IN
IN
–6
0
–3
R
R
= 549⍀
= 100⍀
F
L
–9
V
V
V
= 0.25V rms
= 125mV rms
= 625mV rms
–12
–15
–18
–21
–24
–27
–6
∆t
ON
= 20ns
–9
∆t
= 115ns
–12
–15
–18
–21
OFF
SHUTDOWN PULSE
0 TO +5V
(5nsec EDGES)
1M
10M
100M
1G
50ns/DIV
FREQUENCY – Hz
Figure 6. Shutdown Switching Characteristics
Figure 9. Large Signal Frequency Response
REV. 0
–5–
AD8170/AD8174
–10
V
= +0.707V rms
G = +2
IN
G = +2
–20
–30
R
R
R
= 499⍀ (AD8170R)
= 549⍀ (AD8174R)
= 100⍀
F
F
R
R
R
= 499Ω (AD8170R)
= 549Ω (AD8174R)
= 100Ω
F
F
L
L
–40
–50
AD8170R
–60
–70
AD8174R
–80
–90
–100
–110
20ns/DIV
0.1
1M
10M
FREQUENCY – Hz
100M
1G
Figure 10. Small Signal Pulse Response
Figure 13. All-Hostile Crosstalk vs. Frequency
–20
V
= 4V p-p
V
= +0.354V rms
OUT
G = +2
IN
G = +2
–30
–40
R
R
R
= 499⍀
R
R
= 549Ω
F
F
L
F
L
(AD8170R)
= 549⍀
(AD8174R)
= 100⍀
= 100Ω
–50
ENABLE = LOGIC 1
SD = LOGIC 0
–60
–70
–80
–90
SD = LOGIC 1
ENABLE = LOGIC 0
DISABLE ISOLATION
–100
–110
–120
SHUTDOWN ISOLATION
10ns/DIV
0.03
0.1
1
10
100
500
FREQUENCY – MHz
Figure 11. Large Signal Transient Response
Figure 14. AD8174R Disable and Shutdown Isolation
vs. Frequency
100
100
0.04
0.03
0.02
0.01
G = +2
0.00
–0.01
–0.02
–0.03
–0.04
R
R
R
= 150Ω
= 499Ω (AD8170R)
= 549Ω (AD8174R)
L
F
F
1
2
3
4
5
6
7
8
9
10
11
V
NOISE
IRE
10
10
0.05
0.04
0.03
0.02
0.01
0.00
INVERTING INPUT I
–0.01
–0.02
–0.03
SWITCHING INPUT I
1
2
3
4
5
6
7
8
9
10
11
IRE
1
10
1
1M
100
1k
10k
100k
FREQUENCY – Hz
Figure 12. Differential Gain and Phase Error
Figure 15. Noise vs. Frequency
REV. 0
–6–
AD8170/AD8174
–30
–40
–50
–60
V
= 2V p-p
OUT
G = +2
0
C
= 20pF
L
V
= 2V p-p
R
R
R
= 499Ω (AD8170R)
= 549Ω (AD8174R)
= 100Ω
OUT
G = +2
F
F
L
–1
–2
–3
–4
–5
–6
–7
–8
–9
R
R
= 1kΩ
C
= 0
F
L
= 20Ω
S(OUT)
C
= 300pF
L
–70
–80
+0.1
0
C
=
L
2ND HARMONIC
C
= 50pF
100pF
L
–90
–100
–110
–120
–0.1
–0.2
–0.3
–0.4
C
50pF
=
L
C
L
=
C
= 300pF
L
100pF
3RD HARMONIC
*WORST CHANNEL
0.5
1
10
FREQUENCY – MHz
100
1M
10M
100M
1G
FREQUENCY – Hz
Figure 16. Harmonic Distortion vs. Frequency
Figure 19. Frequency Response vs. Capacitive Load, G = +2
1M
ENABLED
V
= +0.221V rms
IN
G = +2
(OR DISABLED)
INPUT
IMPEDANCE
0
316k
100k
31.6k
10k
R
R
= 499Ω (AD8170R)
V
= 50mV rms
F
F
IN
G = +2
–1
–2
–3
–4
–5
–6
–7
–8
–9
= 549Ω (AD8174R)
R
R
R
= 499Ω (AD8170R)
DISABLED
F
F
L
(OR SHUTDOWN)
OUTPUT IMPEDANCE
(G = +1)
= 549Ω (AD8174R)
= 100Ω
ENABLE,
SD = LOGIC 1;
G = +1
0.1
0
3.16k
1k
ENABLE, SD = LOGIC 1; G = +2
–0.1
DISABLED (OR SHUTDOWN)
OUTPUT IMPEDANCE (G= +2)
316
–0.2
–0.3
–0.4
–0.5
100
ENABLED OUTPUT IMPEDANCE (G = +2)
31.6
10
ENABLE, SD = LOGIC 0, R
= 50Ω
S(OUT)
0.03
1M
10M
100M
1G
0.1
1
10
100
500
FREQUENCY – MHz
FREQUENCY – Hz
Figure 17. Input & Output Impedance vs. Frequency
Figure 20. Small Signal Frequency Response
0
1M
100k
10k
1k
180
135
90
V
= 200mV rms
IN
G = +2
–10
–20
–30
–40
–50
–60
–70
–80
R
R
R
= 499Ω (AD8170R)
F
F
L
= 549Ω (AD8174R)
= 100Ω
TRANSIMPEDANCE
PHASE
–PSRR
45
+PSRR
0
100
–45
1G
10
1k
0.03
0.1
1
10
100
500
10k
100k
1M
10M
100M
FREQUENCY – MHz
FREQUENCY – Hz
Figure 18. Power Supply Rejection vs. Frequency
Figure 21. Open-Loop Transresistance and Phase
vs. Frequency
REV. 0
–7–
AD8170/AD8174
THEORY OF OPERATION
General
Bringing SD high shuts off the supply current for all the switches,
that some of the logic control circuitry and the amplifier,
reducing the quiescent current drain to 1.5 mA. If the
ENABLE and SD functions are not to be used, those respective
pins must be tied to ground for proper operation. Any unused
channel input should also be tied to ground.
The AD8170/AD8174 multiplexers integrate wideband analog
switches with a high speed current feedback amplifier. The
input switches are complementary bipolar follower stages that
are turned on and off by using a current steering technique that
attains switch times of less than 10 ns and ensures low switching
transients. The 250 MHz current feedback amplifier provides
up to 50 mA of drive current. Overall gain and frequency
response are set by external resistors for maximum versatility.
The AD8170 has two switches driving an amplifier to form a 2:1
multiplexer. No disable or shutdown functions are provided.
DC Performance and Noise Considerations
Figure 23 shows the different contributors to total output offset
and noise. Total expected output offset can be calculated using
Equation 1 below:
Figure 22 is a block diagram of the multiplexer signal chain,
with a simplified schematic of an input switch. When the
channel is on (i.e., VONB more positive than VREFB, VONT more
negative than VREFT), I2 flows through Q1 and Q2, and I3 flows
through Q3 and Q4. This biases up Q5 through Q8 to form the
unity gain follower. I1 and I4 (the “off” currents) are steered,
either to another switch or to the power supply. When the
channel turns off, I2 and I3 are steered away while I1 switches
over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts
from ground reference) and I4 switches over to pull the base of
Q5 down to VCLB – 1 VBE (about –2.7 volts away from ground
reference). Clamping the bases of the reverse biased output
transistors to a low impedance point greatly improves isolation
performance.
RF
RG
−
VOS out =
I
+ × RS +V
1+
+ I × RF
(
)
(
[
)
(
)
B
OS
B
]
(1)
SWITCH
R
BUFFER
S
V
IN
+
+
I
/I
en
B
R
F
V
/V
OS en
V
OUT
R
–
–
G
I
/I
en
B
The AD8174 has four switches with outputs wired together and
driving the positive input of a current feedback amplifier to form
a 4:1 multiplexer. It is designed so that only one channel is on
at a time. By bringing ENABLE high, the supply current for the
amplifier is shut off. This turns the output of the amplifier into
a high impedance, allowing the AD8174 to be used in larger
arrays. In practice, the disabled output impedance of the mux
will be determined by the amplifier’s feedback network.
Figure 23. DC Errors for Buffered Multiplexer
Equations 2 and 3 below can be used to predict the output
voltage noise of the multiplexer for different choices of gains
and external resistors. The different contributions to output
noise are root-sum-squared to calculate total output noise
spectral density in Equation 2. As there is no peaking in the
multiplier’s noise characteristic, the total peak-to-peak output
noise will be accurately predicted using Equation 3.
2
2
2
2
V EN
nV / Hz
=
I
EN
+ × RS 2 + V EN
1+
+ IEN– × RF 2 +4KT RF + RS 1+
+ RG
RF
RG
RF
RG
RF
RG
(OUT )
(
)
(
)
(
)
(
)
(2)
(3)
VEN p−p =VEN
×
f
−3dB ×6.2×1. 26
IN0
IN1
IN2
VOUT
VFB
I1
I3
I6
VREFT
VOFFT
IN3
VONT
VREFT
Q5
Q6
Q3
Q4
Q1
VCLB
Q7
Q8
Q2
VCLT
VOFFB
VONB
VREFB
VREFB
I4
I2
Figure 22. Block Diagram and Simplified Schematic of the AD8170
–8–
REV. 0
AD8170/AD8174
Equation 4 can be used to calculate expected gain error due to
the current feedback amplifier’s finite transimpedance and
common mode rejection. For low gains and recommended
feedback resistors, this will be typically less than 0.4%. For
most applications with gain greater than 1, the dominant source
of gain error will most likely be the ratio-match of the external
resistors. All of the dominant contributors to gain error are
associated with the buffer amplifier and external resistors.
These do not change as different channels are selected, so
channel-to-channel gain match of less than 0.05% is easily
attained.
ACL = Closed Loop Gain
CT = Transcapacitance Х 0.8 pF
RF = Feedback Resistor
G = Ideal Closed Loop Gain
GN = (1 + RF/RG) = Noise Gain
RIN = Inverting Terminal Input Resistance 100 Ω
The –3 dB bandwidth is determined from this model as:
1
f –3dB
2π CT R +G RIN
(
)
F
N
This model is typically good to within 15%.
Table III. Recommended Component Values
RF
RG
RT
G = 1+
1−CMRR
[
]
RF
RG
(4)
RT + RIN 1+
+ RF
Small Signal
OUT = 50 mV rms VOUT = 0.707 V rms
Gain RF (⍀) RG (⍀) –3 dB BW (MHz) –3 dB BW (MHz)
Large Signal
V
↑
↑
Ideal Gain
Error Terms
AD8170R +1
+2
1 k
—
710
250
50
270
290
55
RT = Amplifier Transresistance = 600 kΩ
IN = Amplifier Input Resistance 100 Ω
CMRR = Amplifier Common-Mode Rejection –52 dB
499
499
54.9
26.3
R
+10 499
+20 499
27
27
AD8174R +1
+2
1 k
—
780
235
50
270
280
55
Choice of External Resistors
549
549
54.9
26.3
The gain and bandwidth of the multiplexer are determined by
the closed-loop gain and bandwidth of the onboard current
feedback amplifier. These both may be customized by the
external resistor feedback network. Table III shows typical
bandwidths at some common closed loop gains for given
feedback and gain resistors (RF and RG, respectively).
+10 499
+20 499
27
27
Capacitive Load
The general rule for current feedback amplifiers is that the
higher the load capacitance, the higher the feedback resistor
required for stable operation. For the best combination of wide
bandwidth and clean pulse response, a small output resistor is
also recommended, as shown in Figure 24. Table IV contains
values of feedback and series resistors that result in the best
pulse response for a given load capacitance.
The choice of RF is not critical unless the widest and flattest
frequency response must be maintained. The resistors recom-
mended in the table result in the widest 0.1 dB bandwidth with
the least peaking. 1% resistors are recommended for applications
requiring the best control of bandwidth. Packaging parasitics vary
between DIP and SOIC packages, which may result in a slightly
different resistor value for optimum frequency performance.
Wider bandwidths than those listed in the table can be attained
by reducing RF at the expense of increased peaking.
R
F
10µF
+V
S
R
G
0.1µF
R
To estimate the –3 dB bandwidth for feedback resistors not
listed in Table III, the following single-pole model for the
current feedback amplifier may be used:
S(OUT)
V
BUFFER
OUT
(TO FET PROBE)
0.1µF
C
V
L
IN
R
50Ω
T
SWITCH
–V
S
G
10µF
ACL
=
1+sCT R +G RIN
(
)
F
N
Figure 24. Circuit for Driving a Capacitive Load
Table IV. Recommended Feedback and Series Resistors and Bandwidth vs. Capacitive Load and Gain
G = +1
G = +2
VOUT = 2 V p-p
RSOUT –3 dB BW
G = +3
VOUT = 2 V p-p
RSOUT –3 dB BW
G ը +4
V
OUT = 2 V p-p
CL
RF
RSOUT
–3 dB BW
(MHz)
RF
(⍀)
RF
(⍀)
RF
RSOUT
(pF) (⍀)
(⍀)
(⍀)
(MHz)
(⍀)
(MHz)
(⍀)
(⍀)
20
50
100
300
1 k
1 k
2k
50
30
20
20
149
104
73
1 k
1 k
1 k
1 k
20
15
15
15
174
117
80
499
1 k
1 k
1 k
25
15
15
15
170
98
71
499
499
499
499
20
20
15
15
2k
27
34
33
REV. 0
–9–
AD8170/AD8174
Signal traces should be as short as possible. Stripline or
microstrip techniques should be used for long signal traces
(longer than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end using surface mount components.
V
= 2V p-p
OUT
G = +2
R
R
= 499⍀ (AD8170R)
F
F
L
= 549⍀ (AD8174R)
C
R
= 300PF
= 15⍀
S(OUT)
OUTPUT
Careful layout is imperative to minimize crosstalk. Guards
(ground or supply traces) must be run between all signal traces
to limit direct capacitive coupling. Input and output signal lines
should fan out away from the mux as much as possible. If
multiple signal layers are available, a buried stripline structure
having ground plane above, below, and between signal traces
will have the best crosstalk performance.
V
= ±1V
OUT
INPUT
V
= ±0.5V
IN
20ns/DIV
Return currents flowing through termination resistors can also
increase crosstalk if these currents flow in sections of the finite-
impedance ground circuit that is shared between more than one
input or output. Minimizing the inductance and resistance of the
ground plane can reduce this effect, but further care should be
taken in positioning the terminations. Terminating cables directly
at the connectors will minimize the return current flowing on the
board, but the signal trace between the connector and the mux will
look like an open stub and will degrade the frequency response.
Moving the termination resistors close to the input pins will
improve the frequency response, but the terminations from
neighboring inputs should not have a common ground return.
Figure 25. Pulse Response Driving a Large Load
Capacitor, CL = 300 pF
Overload Behavior and Recovery
There are three important overload conditions: input voltage
overdrive, output voltage overdrive and current overload at the
amplifier’s negative feedback input.
At a gain of 1, recovery from driving the input voltages beyond
the voltage range of the input switches is very quick, typically
less than 30 ns. Recovery from output overdrive is somewhat
slower and depends on how much the output is overdriven.
Recovery from 15% overdrive is under 60 ns. 50% overdrive
produces recovery times of about 85 ns.
APPLICATIONS
8-to-1 Video Multiplexer
Input overdrive in a high gain application can result in a large
current flow in the input stage. This current is internally limited
to 40 mA. The effect on total power dissipation should be taken
into account.
Two AD8174 4-to-1 multiplexers can be combined with a single
digital inverter to yield an 8-to-1 multiplexer as shown in Figure
26. The ENABLE control pin allows the two op amp outputs to
be connected together directly. Taking the ENABLE pin high
shuts off the supply current to the output op amp and places the
op amp’s output and inverting input (Pin 12, –VIN) in high
impedance states.
LAYOUT CONSIDERATIONS:
Realizing the high speed performance attainable with the
AD8170 and AD8174 requires careful attention to board layout
and component selection. Proper RF design techniques and low
parasitic component selection are mandatory.
The two least significant bits (LSBs) of the address lines
connect directly to the A0 and A1 inputs of both AD8174
devices. The third address line connects directly to the
ENABLE input on one device and is inverted before being
applied to the ENABLE input on the second device. As a
result, when one device is enabled, the second device presents a
high impedance. The op amp of the enabled device must
however drive both feedback networks ((549 Ω + 549 Ω)/2).
Wire wrap boards, prototype boards, and sockets are not
recommended because of their high parasitic inductance and
capacitance. Instead, surface-mount components should be
soldered directly to a printed circuit board (PCB). The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near input and output pins to reduce stray capacitance.
The gain of this multiplexer has been set to +2 in this example.
This gives an overall gain of +1 when back terminated lines are
used. In applications where switching and settling times are
critical, the digital control pins (A0, A1 and ENABLE) should
also be appropriately terminated (with either 50 Ω or 75 Ω).
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/4 inch of each power pin. An additional large
(4.7 µF–10 µF) tantalum capacitor should be connected in
parallel with each of the smaller capacitors for low impedance
supply bypassing over a broad range of frequencies.
REV. 0
–10–
AD8170/AD8174
+
IN0
IN1
IN2
10µF
+5V
AD8174
0.1µF
75Ω
+V
1
2
3
4
+1
14
13
12
11
10
9
R
75Ω
S
BT
GND
+1
V
OUT
75Ω
549Ω
549Ω
SD
2
GND
+1
+5V
75Ω
ENABLE
0.1µF
+
5
6
7
A2
A1
A0
R *
T
A1
–V
S
–5V
A0
8
+1
10µF
2
IN3
R *
T
75Ω
R *
T
+
IN4
IN5
IN6
10µF
+5V
AD8174
0.1µF
75Ω
+V
1
2
3
4
5
6
7
+1
14
13
12
11
10
9
S
GND
+1
75Ω
549Ω
549Ω
SD
2
GND
+1
+5V
75Ω
ENABLE
0.1µF
+
A1
–V
S
–5V
A0
8
+1
10µF
2
IN7
*OPTIONAL
75Ω
Figure 26. 8-to-1 Multiplexer
phase is used for switching and settling to the next channel.
Assuming a 50% duty cycle, the signal chain must settle within
25 ns. With a settling time to 0.1% of 15 ns, the multiplexer
easily satisfies this criterion.
Color Document Scanner
Charge Coupled Devices (CCDs) find widespread use in
scanner applications. A monochrome CCD delivers a serial
stream of voltage levels, each level being proportional to the
light shining on that cell. In the case of the color image scanner
shown, there are three output streams, representing red, green
and blue. Interlaced with the stream of voltage levels is a voltage
representing the reset level (or black level) of each cell. A
Correlated Double Sampler (CDS) subtracts these two voltages
from each other in order to eliminate the relatively large offsets
which are common with CCDs.
In the example shown, the fourth (spare) channel of the
AD8174 is used to measure a reference voltage. This voltage
would probably be measured less frequently than the R, G and
B signals. Multiplexing a reference voltage offers the advantage
that any temperature drift effects caused by the multiplexer will
equally impact the reference voltage and the to-be-measured
signals. If the fourth channel is unused, it is good design
practice to tie the input permanently to ground.
The next step in the data acquisition process involves digitizing
the three signal streams. Assuming that the analog to digital
converter chosen has a fast enough sample rate, multiplexing the
three streams into a single ADC is generally more economic
than using one ADC per channel. In the example shown, the
AD8174 is used to multiplex the red, green and blue channels
into the AD876, an 8- or 10-bit 20 MSPS ADC. Because of its
high bandwidth, the AD8174 is capable of driving the switched
capacitor input stage of the AD876 without additional buffering.
In addition to the bandwidth, it is necessary to consider the
settling time of the multiplexer. In this case, the ADC has a
sample rate of 20 MHz which corresponds to a sampling
period of 50 ns. Typically, one phase of the sampling clock is
used for conversion (i.e., all levels are held steady) and the other
CONTROL AND TIMING
A0 A1 SD
IN0
ENABLE
R
G
CDS
CDS
AD8174
IN1
AD876
8/10-BIT
20MSPS
A/D
CCD
V
OUT
B
1kΩ
(G = +1)
CDS
IN2
IN3
–V
IN
REFERENCE
Figure 27. Color Document Scanner
REV. 0
–11–
AD8170/AD8174
EVALUATION BOARD
Both evaluation boards ship with 75 Ω termination resistors on
their analog inputs and analog outputs. To use the evaluation
board in nonvideo applications where 50 Ω termination is more
popular, these resistors can be replaced with 50 Ω values. The
digital control pins are terminated with 50 Ω resistors to allow
easy connection to laboratory equipment.
Evaluation boards for the AD8170 and AD8174 are available
that have been carefully laid out and tested to demonstrate the
specified high speed performance of the devices. Figure 28 and
Figure 32 show the schematics of the AD8170 and AD8174
evaluation boards respectively. For ordering information, please
refer to the Ordering Guide.
The gain of the output current feedback op amp on both boards
has been set to +2. For other gains the two gain resistors can be
easily replaced. Refer to Table III for appropriate values at gains
other than +2.
Figure 29 shows the silkscreen of the component side of the
solder side of the AD8170 evaluation board. Figures 30 and 31
show the layout of the component side and solder side respec-
tively. The silkscreens and layout of the AD8174 evaluation
board are shown in Figures 33, 34, 35 and 36.
For connection to external instruments, side-launched SMA
type connectors are provided. Space is also provided on the
board for the installation of SMB of SMC type connectors.
R6
75Ω
V
OUT
SELECT
R1
R5
AD8170
549Ω
1
2
3
4
8
7
6
5
50Ω
C1
C3
GND
R4
549Ω
10µF
10µF
+
+
–VS
+1
–V
+V
S
+V
+1
S
S
C4
0.1µF
C2
0.1µF
IN0
IN1
R2
75Ω
R3
75Ω
Figure 28. AD8170 Evaluation Board
Figure 29. AD8170 Component Side Silkscreen
Figure 31. AD8170 Board Layout (Solder Side)
Figure 30. AD8170 Board Layout (Component Side)
REV. 0
–12–
AD8170/AD8174
C3
IN0
IN1
10µF
C4
0.1µF
R1
AD8174
75Ω
+V
1
2
3
4
+1
14
13
12
11
S
+V
S
R11
75Ω
GND
+1
V
OUT
R2
R10
549Ω
75Ω
IN2
2
R9
549Ω
GND
+1
R3
75Ω
C1
10µF
5
6
7
10
9
+
SD
–V
S
–V
S
R8
50Ω
+1
8
C2
0.1µF
2
ENABLE
IN3
A0
A1
R7
50Ω
R4
75Ω
R5
50Ω
R6
50Ω
Figure 32. AD8174 Evaluation Board
Figure 33. AD8174 Component Side Silkscreen
Figure 35. AD8174 Solder Side Silkscreen
Figure 34. AD8174 Board Layout (Component Side)
Figure 36. AD8174 Board Layout (Solder Side)
REV. 0
–13–
AD8170/AD8174
3. Input termination resistor placement on the evaluation board
is critical to reducing crosstalk. Each termination resistor is
oriented so that ground return currents flow counterclock-
wise to a ground plane “island.” Although the direction of
this ground current flow is arbitrary, it is important that no
two input or output termination resistors share a connection
to the same ground “island.”
NOTES
1. AD8170R/AD8174R Evaluation Board inputs are configured
with 50 Ω impedance striplines. This FR4 board type has the
following stripline dimensions: 60-mil width, 12-mil gap
between center conductor and outside ground plane “is-
lands,” and 62-mil board thickness.
2. Several types of SMA connectors can be mounted on this
board: the side-mount type, which can be easily installed at
the edges of the board; and the top-mount type, which is
placed on top. When using the top-mount SMA connector, it
is recommended that the stripline on the outside 1/8" of the
board edge be removed with an X-Acto blade as this unused
stripline acts as an open stub, which could degrade the small-
signal frequency response of the mux.
REV. 0
–14–
AD8170/AD8174
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
8-Lead Plastic DIP
(N-8)
(N-14)
0.795 (20.19)
0.725 (18.42)
0.430 (10.92)
0.348 (8.84)
14
1
8
8
5
4
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
7
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
0.195 (4.95)
0.115 (2.93)
MAX
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 0.070 (1.77)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
(2.54)
BSC
0.045 (1.15)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
14-Lead SOIC
(R-14)
8-Lead Plastic SOIC
(SO-8)
0.3444 (8.75)
0.3367 (8.55)
0.1968 (5.00)
0.1890 (4.80)
14
8
7
8
1
5
4
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
x 45°
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
REV. 0
–15–
–16–
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